Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device in which the number of times of forming epitaxial layers can be reduced.SOLUTION: In a silicon carbide semiconductor device MOSFET 100, a silicon carbide substrate 10 has a drift region 11 having a first conductivity type, a body region 12 having a second conductivity type, and a source region 13 having the first conductivity type. A gate trench 5 reaching the drift region is provided on a first principal surface 1 of the silicon carbide substrate. The silicon carbide substrate has: a first contact region 18 connected to the body region and having the second conductivity type; a first region 15 overlapping the first contact region 18; a first electric field relaxation region 17 connected to the body region and having the second conductivity type; a second electric field relaxation region 31 surrounding the first region and having the second conductivity type; and a third electric field relaxation region 16 provided between the gate trench and a second principal surface 2 and having the second conductivity type. The peak depth of an effective concentration of a second conductivity type impurities in the third electric field relaxation region with the first principal surface as a reference is 1.0 μm or less.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to silicon carbide semiconductor devices. [Background technology]

[0002] BACKGROUND ART As one of silicon carbide semiconductor devices, a MOS type field effect transistor (Metal Oxide Semiconductor Field Effect Transistor: MOSFET) having a gate trench penetrating a source region and a body region has been disclosed (for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-41990 [Patent Document 2] Japanese Patent Application Laid-Open No. 2017-139441 Summary of the Invention [Problem to be solved by the invention]

[0004] In order to manufacture a conventional silicon carbide semiconductor device, it is necessary to form epitaxial layers multiple times on a silicon carbide single crystal substrate. In order to reduce costs, it is desirable to reduce the number of times that epitaxial layers are formed.

[0005] An object of the present disclosure is to provide a silicon carbide semiconductor device that can reduce the number of times epitaxial layers are formed. [Means for solving the problem]

[0006] A silicon carbide semiconductor device according to the present disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be spaced from the drift region and having the first conductivity type, the first main surface being provided with a gate trench defined by a side surface extending through the source region and the body region to reach the drift region, and a bottom surface continuous with the side surface, the silicon carbide substrate sandwiching the source region between the side surface and the silicon carbide substrate, and a source region connected to the body region and having the second conductivity type a first contact region having a first conductivity type, a first region overlapping the first contact region when viewed in a plane from a direction perpendicular to the first main surface, a first electric field relaxation region provided on the second main surface side of the body region, connected to the body region, and having the second conductivity type; a second electric field relaxation region having the second conductivity type, surrounding the first region when viewed in a plane from a direction perpendicular to the first main surface, and provided on the second main surface side of the first electric field relaxation region; and a third electric field relaxation region having the second conductivity type, provided between the gate trench and the second main surface, wherein a peak depth of the effective concentration of the second conductivity type impurity in the third electric field relaxation region is 1.0 μm or less, based on the first main surface. [Effects of the Invention]

[0007] According to the present disclosure, the number of times epitaxial layers are formed can be reduced. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view (part 1) showing the configuration of a silicon carbide semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view (part 2) showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a cross-sectional view (part 3) showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 4]FIG. 4 is a cross-sectional view (part 4) showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 5] FIG. 5 is a diagram showing the configuration of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 1) illustrating a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 2) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 3) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 4) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 5) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 6) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 12] FIG. 12 is a cross-sectional view (part 7) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 8) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 14] FIG. 14 is a ninth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 15] FIG. 15 is a cross-sectional view (part 10) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 16] FIG. 16 is a cross-sectional view (part 11) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 17] FIG. 17 is a twelfth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 18] FIG. 18 is a thirteenth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 19] FIG. 19 is a fourteenth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 20] FIG. 20 is a cross-sectional view (part 15) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 21] FIG. 21 is a sixteenth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 22] FIG. 22 is a cross-sectional view (part 17) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 23] FIG. 23 is a cross-sectional view (part 18) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 24] FIG. 24 is a schematic diagram showing the positional relationship between the connection region, the second electric field relaxation region, the third electric field relaxation region, the first contact region, and the second contact region. [Figure 25] FIG. 25 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to a modification of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments for carrying out the invention are described below.

[0010] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements will be given the same symbols, and the same description will not be repeated. In the crystallographic descriptions in this specification, individual directions are represented by [], collective directions by <>, individual planes by (), and collective planes by {}. Furthermore, negative indices in crystallography are usually represented by placing a "-" (bar) above the number, but in this specification, a negative sign is placed before the number.

[0011] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region to be separated from the drift region and having the first conductivity type, the first main surface having a gate trench defined by a side surface penetrating the source region and the body region to reach the drift region and a bottom surface continuous with the side surface, the silicon carbide substrate sandwiching the source region between the side surface and the gate trench, and connecting to the body region and the second conductive type. a first contact region having a second conductivity type, and a first region overlapping with the first contact region when viewed in a plane from a direction perpendicular to the first main surface; a first electric field relaxation region having the second conductivity type, which is provided on the second main surface side of the body region and connected to the body region; a second electric field relaxation region having the second conductivity type, which surrounds the first region when viewed in a plane from a direction perpendicular to the first main surface and is provided on the second main surface side of the first electric field relaxation region; and a third electric field relaxation region having the second conductivity type, which is provided between the gate trench and the second main surface;

[0012] The peak depth of the effective concentration of the second conductivity type impurity in the first electric field buffer region is 1.0 μm or less with respect to the first main surface. Therefore, the source region, body region, drift region, and first electric field buffer region can be appropriately formed without forming epitaxial layers multiple times. Furthermore, when viewed in a plan view perpendicular to the first main surface, the first electric field buffer region has a first region that overlaps with the first contact region, and the second electric field buffer region surrounds the first region. Therefore, even if the first contact region contains many crystal defects, drain leakage via these crystal defects can be suppressed.

[0013] [2] In [1], the second electric field buffer region and the third electric field buffer region may be connected in a direction parallel to the first main surface, in which case the second electric field buffer region and the third electric field buffer region are at the same potential, making it easier to suppress drain leakage.

[0014] [3] In [1] or [2], a connection region may be provided that is connected to the first electric field relaxation region and the second electric field relaxation region and electrically connects the first electric field relaxation region and the second electric field relaxation region. In this case, the first electric field relaxation region and the second electric field relaxation region are set to the same potential, which makes it easier to suppress drain leakage.

[0015] [4] In any of [1] to [3], the second electric field buffer regions may be periodically arranged in the longitudinal direction of the gate trench, which makes it easy to suppress drain leakage while sufficiently securing a current path for on-current.

[0016] [5] In [4], the drift region may have a second region between the second electric field buffer regions adjacent in the longitudinal direction, and a first length of the second electric field buffer region in the longitudinal direction may be equal to or shorter than a second length of the second region. In this case, a current path for an on-current is easily secured.

[0017] [6] In [5], the first length may be 20% to 40% of the sum of the first length and the second length, which makes it particularly easy to ensure a current path for on-current and suppress drain leakage.

[0018] [7] In any of [1] to [6], the third electric field buffer region may have a third region located closer to the second major surface than the bottom surface and a fourth region protruding from the third region toward the first major surface, and a part of the drift region may be located between the fourth region and the body region. In this case, even if a high drain voltage is applied during off-state, penetration of an electric field into the body region is suppressed, and drain leakage is easily suppressed.

[0019] [8] In any of [1] to [7], the silicon carbide substrate may have a second contact region provided between the source region and the first contact region, connected to the source region, and having the first conductivity type, the second contact region being thicker than the source region, which makes it easier to form an ohmic contact between a source electrode and the contact region.

[0020] [9] In any of [1] to [8], the side surface of the gate trench may include a {0-33-8} plane. By including the {0-33-8} plane on the side surface, good mobility can be obtained on the side surface of the gate trench, and channel resistance can be reduced.

[0021] [Embodiments of the present disclosure] An embodiment of the present disclosure relates to a so-called vertical MOSFET (silicon carbide semiconductor device). FIGS. 1 to 4 are cross-sectional views showing the configuration of a silicon carbide semiconductor device according to an embodiment. FIG. 5 is a diagram showing the configuration of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to an embodiment. FIG. 1 corresponds to a cross-sectional view taken along line II in FIG. 5. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. 5. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG. 5. FIG. 4 corresponds to a cross-sectional view taken along line IV-IV in FIG. 5.

[0022] 1 to 5 , a MOSFET 100 according to this embodiment mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, a barrier metal film 84, and a passivation film 85. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has n-type conductivity (first conductivity type).

[0023] The first main surface 1 is a {0001} plane or a plane inclined at an off angle of 8° or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a plane inclined at an off angle of 8° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

[0024] The silicon carbide epitaxial layer 40 mainly has a drift region 11, a body region 12, a source region 13, a current spreading region 14, a third electric field relaxation region 16, a first electric field relaxation region 17, a first contact region 18, a second contact region 19, a second electric field relaxation region 31, and a connection region 32.

[0025] The drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. The drift region 11 mainly includes, for example, a fifth region 11C, a second region 11D, and a sixth region 11E.

[0026] The current spreading region 14 is provided on the drift region 11. The current spreading region 14 contains n-type impurities such as phosphorus and has n-type conductivity. The current spreading region 14 is located between the body region 12 and the fifth region 11C in a direction perpendicular to the second main surface 2. The current spreading region 14 is in contact with the body region 12 and the fifth region 11C. The current spreading region 14 is located closer to the second main surface 2 than the body region 12. The current spreading region 14 is located closer to the first main surface 1 than the fifth region 11C. The current spreading region 14 is also in contact with the side surface 3. The peak value of the effective concentration of the n-type impurity in the current spreading region 14 is preferably 5×10 17 cm -3 The peak value of the effective concentration of the n-type impurity in the current spreading region 14 is preferably 2×10 17 cm -3 The current spreading region 14 constitutes a part of the drift region.

[0027] The body region 12 is provided on the current diffusion region 14. The body region 12 contains p-type impurities such as aluminum (Al) and has p-type conductivity (second conductivity type). The body region 12 is located between the source region 13 and the current diffusion region 14 in a direction perpendicular to the second main surface 2. The body region 12 is in contact with the source region 13 and the current diffusion region 14. The body region 12 is located closer to the second main surface 2 than the source region 13. The body region 12 is located closer to the first main surface 1 than the current diffusion region 14. The body region 12 is also in contact with the side surface 3. The body region 12 has a bottom surface 94 that is connected to the side surface 3. The bottom surface 94 is in contact with the top surface of the current diffusion region 14. A depth D2 of the bottom surface 94 from the first main surface 1 is, for example, 0.2 μm or more and 0.5 μm or less. The effective concentration of the p-type impurity in the body region 12 is, for example, 5×10 17 cm -3 5x10 or more 18 cm -3 The peak value of the effective concentration of the p-type impurity in the body region 12 is preferably 2×10 18 cm -3That's all. The short channel effect (punch-through) can occur when a depletion layer spreads from the pn junction region into the channel region, causing the entire channel region to become a depletion layer. By increasing the effective concentration of p-type impurities in the body region 12, the spread of the depletion layer formed in the channel region can be reduced.

[0028] The source region 13 is on the body region 12 in a direction perpendicular to the second main surface 2. The source region 13 is in contact with the body region 12. The source region 13 is provided on the body region 12 so as to be separated from the current spreading region 14 by the body region 12. The source region 13 is closer to the first main surface 1 than the body region 12. The source region 13 is also in contact with the side surface 3. The source region 13 has a lower end surface 97 connected to the side surface 3. The lower end surface 97 is in contact with the upper end surface of the body region 12. The source region 13 has a first thickness T1. The first thickness T1 is, for example, not less than 0.1 μm and not more than 0.3 μm. The source region 13 is covered with a gate insulating film 81. The source region 13 is in direct contact with the gate insulating film 81. The source region 13 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. The source region 13 constitutes the first main surface 1. The effective concentration of the n-type impurities in the source region 13 is, for example, 5×10 18 cm -3 5x10 or more 19 cm -3 The effective concentration of n-type impurities in the first main surface 1 of the source region 13 is preferably 1×10 19 cm -3 That's all.

[0029] The second contact region 19 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. The second contact region 19 sandwiches the source region 13 between itself and the side surface 3. That is, the source region 13 is located between the side surface 3 and the second contact region 19 in a direction parallel to the first major surface 1. The second contact region 19 is located farther from the gate trench 5 than the source region 13. The second contact region 19 connects to the source region 13. The second contact region 19 constitutes the first major surface 1. A lower end surface 96 of the second contact region 19 is located closer to the second major surface 2 than a lower end surface 97 of the source region 13. The second contact region 19 is thicker than the source region 13. The second contact region 19 has a second thickness T2 greater than the first thickness T1. The second thickness T2 may be 1.1 to 5.0 times the first thickness T1. The second thickness T2 is, for example, 0.2 μm or greater. The second thickness T2 may be 0.2 μm or more and 0.5 μm or less. The effective concentration of n-type impurities in the second contact region 19 may be approximately the same as the effective concentration of n-type impurities in the source region 13. The effective concentration of n-type impurities in the second contact region 19 may be, for example, 5×10 18 cm -3 5x10 or more 19 cm -3 The second contact region 19 is an example of a contact region having the first conductivity type.

[0030] The first contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The effective concentration of the p-type impurities in the first contact region 18 is higher than the effective concentration of the p-type impurities in the body region 12, for example. The first contact region 18 penetrates the second contact region 19 and contacts the body region 12. The first contact region 18 constitutes the first main surface 1. The effective concentration of the p-type impurities in the first contact region 18 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0031] The first major surface 1 is provided with a gate trench 5 defined by a side surface 3 and a bottom surface 4. The side surface 3 penetrates the source region 13, the body region 12, the current spreading region 14, and the drift region 11 to reach the third electric field relaxation region 16. The bottom surface 4 is continuous with the side surface 3. The bottom surface 4 is located in the third electric field relaxation region 16. The bottom surface 4 is, for example, a plane parallel to the second major surface 2. The angle θ1 of the side surface 3 with respect to a plane including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility. The gate trench 5 extends, for example, in a stripe shape along a first direction parallel to the first major surface 1. When viewed from above in a direction perpendicular to the first main surface 1, a plurality of gate trenches 5 are provided at regular intervals in a second direction perpendicular to the first direction. The plurality of gate trenches 5 may be provided in an array, for example.

[0032] The third electric field relaxation region 16 contains p-type impurities such as aluminum and has p-type conductivity. The third electric field relaxation region 16 is located between the current spreading region 14 and the second major surface 2. When viewed in a plan view perpendicular to the first major surface 1, the third electric field relaxation region 16 includes a portion overlapping with the gate trench 5. For example, the third electric field relaxation region 16 is located between the bottom surface 4 of the gate trench 5 and the second major surface 2, and the upper end surface of the third electric field relaxation region 16 includes, for example, the bottom surface 4 of the gate trench 5. A portion of the upper end surface of the third electric field relaxation region 16 faces a portion of the lower end surface of the current spreading region 14. When viewed in a plan view perpendicular to the first major surface 1, the third electric field relaxation region 16 has a side end surface 92 located farther from the gate trench 5 than a first position 91 where the current spreading region 14, the body region 12, and the side surface 3 contact each other. The third electric field relaxation region 16 may be electrically connected to a source electrode 60. The effective concentration of the p-type impurity in the third electric field buffer region 16 is, for example, 5×10 17 cm -3 5x10 or more 18 cm -3The peak depth D1 of the effective concentration of p-type impurities in the third electric field buffer region 16, based on the first main surface 1, is, for example, 1.0 μm or less. The peak depth D1 may be 0.8 μm or more and 1.0 μm or less. The thickness of the third electric field buffer region 16 in the direction perpendicular to the first main surface 1 may be 0.4 μm or more and 0.6 μm or less.

[0033] The third electric field relaxation region 16 includes a third region 16A and a fourth region 16B. The third region 16A is located closer to the second main surface 2 than the bottom surface 4 of the gate trench 5. The fourth region 16B protrudes from the third region 16A toward the first main surface 1. When viewed in a plan view from a direction perpendicular to the first main surface 1, the fourth region 16B is located between the first position 91 and the side end surface 92. The lower end surface of the current diffusion region 14 includes a recessed portion toward the first main surface 1, following the fourth region 16B. The fourth region 16B may be provided, for example, near a portion of the side end surface 92 that contacts the second region 11D of the drift region 11, but may not be provided near a portion of the side end surface 92 that contacts the second electric field relaxation region 31 (see FIG. 24 ).

[0034] The first electric field relief region 17 contains p-type impurities such as aluminum and has p-type conductivity. The first electric field relief region 17 sandwiches the body region 12 between itself and the side surface 3. That is, the body region 12 is located between the side surface 3 and the first electric field relief region 17 in a direction parallel to the first main surface 1. The first electric field relief region 17 is located farther from the gate trench 5 than the body region 12. The first electric field relief region 17 is connected to the body region 12. The first electric field relief region 17 is located closer to the second main surface 2 than the first contact region 18 and the second contact region 19. The first electric field relief region 17 has a first region 15 that overlaps with the first contact region 18 when viewed in a plan view perpendicular to the first main surface 1. The first electric field relief region 17 may also overlap with the second contact region 19 when viewed in a plan view perpendicular to the first main surface 1.

[0035] A lower end surface 93 of the first electric field relaxation region 17 is located closer to the second main surface 2 than a lower end surface 94 of the body region 12. In other words, a depth D3 of the lower end surface 93 with respect to the first main surface 1 is greater than a depth D2 of the lower end surface 94. The lower end surface 93 of the first electric field relaxation region 17 is located closer to the first main surface 1 than an upper end surface 95 of the third region 16A of the third electric field relaxation region 16. In other words, the lower end surface 93 of the first electric field relaxation region 17 is located closer to the first main surface 1 than the bottom surface 4 of the gate trench 5. The first electric field relaxation region 17 may penetrate the current spreading region 14. The effective concentration of p-type impurities in the first electric field relaxation region 17 is preferably 1×10 18 cm -3 Over 2×10 19 cm -3 This is to obtain a good breakdown voltage and short circuit resistance. In addition, the effective concentration of the p-type impurity in the first electric field buffer region 17 is 1×10 18 cm -3 Over 2×10 19 cm -3 If it is equal to or less than this, the current diffusion region 14 can be easily secured.

[0036] The fifth region 11C of the drift region 11 is located between the current diffusion region 14 and the third electric field buffer region 16. The fifth region 11C is in contact with the current diffusion region 14 and the third electric field buffer region 16. The fifth region 11C is located closer to the second main surface 2 than the current diffusion region 14. The fifth region 11C is located closer to the first main surface 1 than the third electric field buffer region 16. The effective concentration of n-type impurities in the fifth region 11C is, for example, 5×10 15 cm -3 5x10 or more 16 cm -3 The following is the result.

[0037] The second region 11D is located closer to the second major surface 2 than the fifth region 11C. The second region 11D is continuous with the fifth region 11C. The second region 11D is in contact with the third electric field buffer region 16 in a direction parallel to the second major surface 2. The second region 11D and the third electric field buffer region 16 may be located on the same plane parallel to the second major surface 2. The effective concentration of n-type impurities in the second region 11D may be higher than the effective concentration of n-type impurities in the fifth region 11C. The effective concentration of n-type impurities in the second region 11D is, for example, 5×10 16cm -3 5x10 or more 17 cm -3 The following is the result.

[0038] The sixth region 11E is located closer to the second main surface 2 than the second region 11D. The sixth region 11E is continuous with the second region 11D. The sixth region 11E is in contact with the third electric field relaxation region 16. The sixth region 11E is located closer to the second main surface 2 than the third electric field relaxation region 16. The sixth region 11E may be located between the second region 11D and the silicon carbide single crystal substrate 50. The sixth region 11E may be continuous with the silicon carbide single crystal substrate 50. The effective concentration of n-type impurities in the sixth region 11E may be lower than the effective concentration of n-type impurities in the second region 11D. The effective concentration of n-type impurities in the sixth region 11E is, for example, 5×10 15 cm -3 5x10 or more 16 cm -3 The following is the result.

[0039] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the third electric field reduction region 16 at the bottom surface 4. The gate insulating film 81 contacts each of the source region 13, the body region 12, the current diffusion region 14, and the fifth region 11C at the side surface 3. The gate insulating film 81 may also contact the source region 13 at the first main surface 1.

[0040] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. A portion of the gate electrode 82 may be disposed on the first main surface 1.

[0041] The interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 from the source electrode 60. A part of the interlayer insulating film 83 may be provided inside the gate trench 5.

[0042] Contact holes 86 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals in the second direction. The contact holes 86 are provided so that the gate trench 5 is located between adjacent contact holes 86 in the second direction when viewed in a plan view from a direction perpendicular to the first main surface 1. The contact holes 86 extend in the first direction. The source region 13, the first contact region 18, and the second contact region 19 are exposed from the interlayer insulating film 83 and the gate insulating film 81 through the contact holes 86. The first contact regions 18 do not need to be arranged over the entire area in the first direction (the longitudinal direction of the gate trench 5), and may be arranged periodically, for example, as shown in FIGS. 4 and 5 .

[0043] The second electric field relaxation region 31 contains p-type impurities such as aluminum and has p-type conductivity. The second electric field relaxation region 31 is located closer to the second main surface 2 than the first electric field relaxation region 17. The second electric field relaxation region 31 is located between adjacent third electric field relaxation regions 16 in the second direction and is in contact with both of these adjacent third electric field relaxation regions 16 in the second direction. The second electric field relaxation region 31 and the third electric field relaxation region 16 may be located on the same plane parallel to the second main surface 2. The second electric field relaxation region 31 is periodically arranged in the first direction. For example, the second electric field relaxation region 31 is arranged with the same period as the first contact regions 18 in the first direction. The second electric field relaxation region 31 surrounds the first region 15 when viewed in a plan view perpendicular to the first main surface 1. The effective concentration of the p-type impurity in the second electric field relaxation region 31 may be approximately the same as the effective concentration of the p-type impurity in the third electric field relaxation region 16. The effective concentration of the p-type impurity in the second electric field buffer region 31 is, for example, 1×10 17 cm -3 5x10 or more 18 cm-3 The following is the result.

[0044] The connection region 32 contains p-type impurities such as aluminum and has p-type conductivity. The connection region 32 is located between the second electric field relief region 31 and the first electric field relief region 17 in the direction perpendicular to the second main surface 2 and is in contact with the second electric field relief region 31 and the first electric field relief region 17. The connection region 32 is located on the second main surface 2 side of the first electric field relief region 17. The connection region 32 is located on the first main surface 1 side of the second electric field relief region 31. The connection regions 32 are periodically arranged in the first direction, similar to the second electric field relief region 31. The connection regions 32 are periodically arranged in the first direction as the second electric field relief region 31. When viewed in a plan view in a direction perpendicular to the first main surface 1, two edges of the connection region 32 may be located between two edges of the first contact region 18 in the first direction. When viewed in a plan view in a direction perpendicular to the first main surface 1, two edges of the connection region 32 may overlap two edges of the second contact region 19 in the second direction. The effective concentration of the p-type impurity in the connection region 32 is, for example, 1×10 17 cm -3 5x10 or more 18 cm -3 The following is the result.

[0045] The first contact region 18 is in contact with the body region 12, the body region 12 is in contact with the first electric field relief region 17, the first electric field relief region 17 is in contact with the connection region 32, the connection region 32 is in contact with the second electric field relief region 31, and the connection region 32 is in contact with the third electric field relief region 16. In this way, the third electric field relief region 16 is electrically connected to the first contact region 18.

[0046] The barrier metal film 84 covers the upper surface and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is in contact with both the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

[0047] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 includes a contact electrode 61 and a source wiring 62. The contact electrode 61 may be in contact with the source region 13, the first contact region 18, and the second contact region 19 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing, for example, titanium, aluminum, and silicon. The contact electrode 61 is in ohmic contact with the second contact region 19. The contact electrode 61 may be in ohmic contact with the first contact region 18. The source wiring 62 covers the upper surface and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with each of the barrier metal film 84 and the contact electrode 61. The source wiring 62 is made of a material containing, for example, aluminum.

[0048] The passivation film 85 covers the upper surface of the source wiring 62. The passivation film 85 is in contact with the source wiring 62. The passivation film 85 is made of a material containing, for example, polyimide.

[0049] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing nickel silicide, for example. The drain electrode 70 may also be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 is in ohmic contact with the silicon carbide single crystal substrate 50.

[0050] In the direction perpendicular to the second main surface 2, the top surface of the third electric field relaxation region 16 may be spaced apart from the bottom surface 4. In this case, for example, the bottom surface 4 may be located in the drift region 11, and the side surface 3 may extend through the source region 13, the body region 12, and the current spreading region 14 to reach the drift region 11. For example, a fifth region 11C may be present between the top surface of the third electric field relaxation region 16 and the bottom surface 4.

[0051] A buffer layer containing n-type impurities such as nitrogen and having n-type conductivity may be provided between silicon carbide single crystal substrate 50 and sixth region 11E. The effective concentration of the n-type impurity in the buffer layer may be higher than the effective concentration of the n-type impurity in sixth region 11E.

[0052] In the present disclosure, the effective concentration of p-type impurities is the difference between the concentration of p-type impurities and the concentration of n-type impurities, and the effective concentration of n-type impurities is the difference between the concentration of n-type impurities and the concentration of p-type impurities. The effective concentrations can be measured, for example, by the following steps 1 to 4.

[0053] (Step 1) The surface of the semiconductor device is observed to identify the element region.

[0054] (Step 2) The semiconductor device is processed so that the cross section of the semiconductor region appears as shown in Fig. 2. For example, a focused ion beam (FIB) device is used to process the cross section of the semiconductor device.

[0055] (Step 3) Using a scanning electron microscope (SEM), determine whether the conductivity type of the impurity-implanted region is p-type or n-type. For example, when SEM observation is performed under conditions of an accelerating voltage of 3 kV and a magnification of 10,000 times, the bright regions are p-type regions and the dark regions are n-type regions.

[0056] (Step 4) The impurity concentrations of the p-type and n-type regions in the cross section are measured using a scanning spreading resistance microscope (SSRM). The concentration in the p-type region is the effective concentration of p-type impurities, and the concentration in the n-type region is the effective concentration of n-type impurities.

[0057] Next, a method for manufacturing the MOSFET 100 according to the embodiment will be described. FIGS. 6 to 23 are cross-sectional views illustrating a method for manufacturing the MOSFET 100 according to the embodiment. Like FIG. 1, FIGS. 6 to 8, 10 to 12, 15 to 16, and 18 to 23 correspond to cross-sectional views taken along line II in FIG. 5. Like FIG. 2, FIGS. 9, 13, and 17 correspond to cross-sectional views taken along line II-II in FIG. 5. Like FIG. 4, FIG. 14 corresponds to a cross-sectional view taken along line IV-IV in FIG. 5.

[0058] First, as shown in Fig. 6, a silicon carbide single crystal substrate 50 is prepared. For example, a silicon carbide ingot (not shown) manufactured by sublimation is sliced ​​to prepare the silicon carbide single crystal substrate 50. A buffer layer (not shown) may be formed on the silicon carbide single crystal substrate 50. The buffer layer may be formed by chemical vapor deposition (CVD) using, for example, a mixed gas of silane (SiH4) and propane (C3H8) as a source gas and hydrogen (H2) as a carrier gas. During epitaxial growth of the buffer layer, an n-type impurity such as nitrogen may be introduced into the buffer layer.

[0059] Next, as also shown in FIG. 6, epitaxial layer 21 is formed. For example, epitaxial layer 21 is formed on silicon carbide single crystal substrate 50 by a CVD method using a mixed gas of silane and propane as a source gas and hydrogen as a carrier gas. During epitaxial growth, n-type impurities such as nitrogen are introduced into epitaxial layer 21. Epitaxial layer 21 has n-type conductivity. The effective concentration of the n-type impurity in epitaxial layer 21 may be lower than the effective concentration of the n-type impurity in the buffer layer.

[0060] 7, a mask layer 150 having openings 151 is formed on the regions where the third electric field buffer region 16 and the second electric field buffer region 31 are to be formed. The mask layer 150 is made of a material containing, for example, silicon dioxide. In forming the mask layer 150, after forming a silicon dioxide film, the silicon dioxide film is etched using a photoresist mask. This etching is performed under conditions such that the opening area at the bottom of the opening 151 is smaller than at the top.

[0061] 8 and 9, p-type impurity ions capable of imparting p-type conductivity, such as aluminum ions, are implanted into the epitaxial layer 21. This forms the third electric field buffer region 16 and the second electric field buffer region 31. The third electric field buffer region 16 and the second electric field buffer region 31 are each formed inside the epitaxial layer 21 so as not to be exposed on the surface of the epitaxial layer 21. The third electric field buffer region 16 and the second electric field buffer region 31 may be formed simultaneously or separately. The implantation energy of the p-type impurity ions when forming the third electric field buffer region 16 and the second electric field buffer region 31 may be 700 keV or more and 1200 keV or less. The peak depth of the effective concentration of the p-type impurity in the third electric field buffer region 16 and the second electric field buffer region 31, based on the first main surface 1, may be, for example, 0.8 μm or more and 1.0 μm or less.

[0062] The opening area of ​​the opening 151 in the mask layer 150 used to form the third electric field buffer region 16 and the second electric field buffer region 31 is smaller at the lower end than at the upper end. Therefore, the third electric field buffer region 16 is likely to be formed shallower on the sidewall surface of the opening 151 closer to the second main surface 2 than at the center of the opening 151, and is formed to include a third region 16A and a fourth region 16B.

[0063] Next, as shown in FIG. 10, the body region 12 is formed. For example, p-type impurity ions, such as aluminum ions, capable of imparting p-type conductivity are implanted into the entire surface of the epitaxial layer 21. This forms the body region 12. The implantation energy of the p-type impurity ions when forming the body region 12 may be 200 keV or more and 400 keV or less. The thickness of the body region 12 is, for example, 0.2 μm or more and 0.5 μm or less.

[0064] 11, the current spreading region 14 is formed. For example, n-type impurity ions, such as phosphorus ions, capable of imparting n-type conductivity are implanted into the entire surface of the epitaxial layer 21. This forms the current spreading region 14. The implantation energy of the n-type impurity ions when forming the current spreading region 14 may be set to 300 keV or more and 800 keV or less.

[0065] 12, the source region 13 is formed. For example, n-type impurity ions such as phosphorus ions capable of imparting n-type conductivity are implanted into the entire surface of the epitaxial layer 21. This forms the source region 13. The implantation energy of the n-type impurity ions when forming the source region 13 may be 50 keV or more and 150 keV or less. The thickness of the source region 13 is, for example, 0.1 μm or more and 0.3 μm or less.

[0066] Next, as shown in FIGS. 13, 14, and 24, the connection region 32 is formed. For example, a mask layer (not shown) having an opening is formed over the region where the connection region 32 is to be formed. Next, p-type impurity ions capable of imparting p-type conductivity, such as aluminum ions, are implanted into the drift region 11. This forms the connection region 32. The implantation energy of the p-type impurity ions when forming the connection region 32 may be 400 keV or more and 900 keV or less. FIG. 24 is a schematic diagram showing the positional relationship between the connection region 32, the second electric field buffer region 31, the third electric field buffer region 16, the first contact region 18, and the second contact region 19. FIG. 13 corresponds to a cross-sectional view taken along line XIII-XIII in FIG. 24. FIG. 14 corresponds to a cross-sectional view taken along line XIV-XIV in FIG. 24.

[0067] 15, first electric field buffer region 17 is formed. For example, a mask layer (not shown) having an opening is formed on the region where first electric field buffer region 17 is to be formed. Next, p-type impurity ions capable of imparting p-type conductivity, such as aluminum ions, are implanted into epitaxial layer 21. This forms first electric field buffer region 17. The implantation energy of p-type impurity ions when forming first electric field buffer region 17 may be set to 300 keV or more and 800 keV or less.

[0068] 16, the second contact region 19 is formed. For example, a mask layer (not shown) having an opening on the region where the second contact region 19 is to be formed is formed. Next, n-type impurity ions capable of imparting n-type conductivity, such as phosphorus ions, are implanted into the epitaxial layer 21. This forms the second contact region 19. The implantation energy of the n-type impurity ions when forming the second contact region 19 may be set to 100 keV or more and 300 keV or less. The mask layer used to form the first electric field reduction region 17 may be used directly to form the second contact region 19.

[0069] 17, first contact region 18 is formed. For example, a mask layer (not shown) having an opening is formed on the region where first contact region 18 is to be formed. Next, p-type impurity ions capable of imparting p-type conductivity, such as aluminum ions, are implanted into second contact region 19 and body region 12. This forms first contact region 18 in contact with body region 12. The implantation energy of p-type impurity ions when forming first contact region 18 may be 50 keV or more and 300 keV or less. The drift region 11 is formed from a portion of epitaxial layer 21 into which impurity ions have not been implanted after formation of epitaxial layer 21.

[0070] Next, activation annealing is performed to activate the impurity ions implanted into the silicon carbide substrate 10. The temperature of the activation annealing is preferably 1500°C or higher and 1900°C or lower, for example, about 1700°C. The time of the activation annealing is, for example, about 30 minutes. The atmosphere for the activation annealing is preferably an inert gas atmosphere, for example, an argon (Ar) atmosphere.

[0071] Next, as shown in FIG. 18 , a gate trench 5 is formed. For example, a mask layer (not shown) having an opening at a position where the gate trench 5 is to be formed is formed on the first main surface 1. Using the mask layer, a portion of the source region 13, a portion of the body region 12, a portion of the current diffusion region 14, and a portion of the drift region 11 are removed by etching. The etching method may be, for example, reactive ion etching, particularly inductively coupled plasma reactive ion etching. Specifically, for example, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF) or a mixed gas of SF and oxygen (O) as a reactive gas may be used. By etching, a recess (not shown) having a side portion substantially perpendicular to the first main surface 1 and a bottom portion that is continuous with the side portion and substantially parallel to the first main surface 1 is formed in the region where the gate trench 5 is to be formed.

[0072] Next, thermal etching is performed on the recesses. Thermal etching can be performed, for example, by heating the mask layer formed on the first main surface 1 in an atmosphere containing a reactive gas having at least one type of halogen atom. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere includes, for example, chlorine (Cl2), boron trichloride (BCl3), SF6, or carbon tetrafluoride (CF4). For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as the reactive gas, and setting the heat treatment temperature to, for example, 800°C or higher and 900°C or lower. The reactive gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. Examples of the carrier gas that can be used include nitrogen gas, argon gas, and helium gas.

[0073] By the thermal etching, a gate trench 5 is formed in the first main surface 1 of the silicon carbide substrate 10. The gate trench 5 is defined by a side surface 3 and a bottom surface 4. The side surface 3 is composed of a source region 13, a body region 12, a current diffusion region 14, and a drift region 11. The bottom surface 4 is composed of a third electric field reduction region 16. An angle θ1 between the side surface 3 and a plane including the bottom surface 4 is, for example, not less than 45° and not more than 65°. Next, the mask layer is removed from the first main surface 1.

[0074] Next, as shown in FIG. 19 , a gate insulating film 81 is formed. For example, by thermally oxidizing the silicon carbide substrate 10, the gate insulating film 81 is formed in contact with the source region 13, the body region 12, the current diffusion region 14, the drift region 11, the third electric field relaxation region 16, the first contact region 18, and the second contact region 19. Specifically, the silicon carbide substrate 10 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300° C. or higher and 1400° C. or lower. This forms the gate insulating film 81 in contact with the first main surface 1, the side surface 3, and the bottom surface 4. Note that, when the gate insulating film 81 is formed by thermal oxidation, strictly speaking, a portion of the silicon carbide substrate 10 is incorporated into the gate insulating film 81. Therefore, in the subsequent processing, it is assumed that the first main surface 1, the side surface 3, and the bottom surface 4 have moved slightly to the interface between the gate insulating film 81 and the silicon carbide substrate 10 after thermal oxidation.

[0075] Next, the silicon carbide substrate 10 may be subjected to a heat treatment (NO annealing) in a nitric oxide (NO) gas atmosphere. In the NO annealing, the silicon carbide substrate 10 is maintained, for example, under conditions of 1100°C or higher and 1400°C or lower for about one hour. This introduces nitrogen atoms into the interface region between the gate insulating film 81 and the body region 12. As a result, the formation of interface states in the interface region is suppressed, thereby improving channel mobility.

[0076] After the NO annealing, Ar annealing may be performed using argon (Ar) as the atmospheric gas. The heating temperature of the Ar annealing is, for example, equal to or higher than the heating temperature of the NO annealing. The Ar annealing time is, for example, about one hour. This further suppresses the formation of interface states in the interface region between the gate insulating film 81 and the body region 12. Note that, instead of Ar gas, other inert gases such as nitrogen gas may be used as the atmospheric gas.

[0077] 20 , a gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed by, for example, a low pressure chemical vapor deposition (LP-CVD) method. The gate electrode 82 is formed to face each of the source region 13, the body region 12, the current diffusion region 14, and the drift region 11.

[0078] Next, as shown in FIG. 21 , an interlayer insulating film 83 is formed. Specifically, the interlayer insulating film 83 is formed so as to cover the gate electrode 82 and to be in contact with the gate insulating film 81. The interlayer insulating film 83 is formed by, for example, a CVD method. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. A part of the interlayer insulating film 83 may be formed inside the gate trench 5.

[0079] 22 , contact holes 86 are formed in the interlayer insulating film 83 and the gate insulating film 81. The first contact region 18 and the second contact region 19 are exposed from the interlayer insulating film 83 and the gate insulating film 81 through the contact holes 86. The source region 13 is preferably left covered with the gate insulating film 81 and the interlayer insulating film 83.

[0080] Next, as shown in FIG. 23 , a barrier metal film 84, a contact electrode 61, and a drain electrode 70 are formed. For example, the barrier metal film 84 is formed to cover the upper surface and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. When viewed from a plane perpendicular to the first main surface 1, the source region 13 is preferably located inside the side end surface of the barrier metal film 84. The barrier metal film 84 is made of a material containing, for example, titanium nitride. The barrier metal film 84 is formed by, for example, sputtering film formation and reactive ion etching (RIE). Next, a metal film (not shown) for the contact electrode 61 is formed on the first main surface 1, the metal film being in contact with the first contact region 18 and the second contact region 19. The metal film for the contact electrode 61 is formed by, for example, sputtering. The metal film for the contact electrode 61 is made of, for example, a material containing nickel. Next, a metal film (not shown) for the drain electrode 70 is formed on the second main surface 2, the drain electrode 70 being in contact with the silicon carbide single crystal substrate 50. The metal film for the drain electrode 70 is formed by, for example, sputtering, and is made of, for example, a material containing nickel.

[0081] Next, alloying annealing is performed. The metal film for contact electrode 61 and the metal film for drain electrode 70 are maintained at a temperature of, for example, 900°C or higher and 1100°C or lower for about 5 minutes. As a result, at least a portion of the metal film for contact electrode 61 and at least a portion of the metal film for drain electrode 70 react with silicon contained in silicon carbide substrate 10 and are silicided. As a result, contact electrode 61 making an ohmic junction with second contact region 19 and drain electrode 70 making an ohmic junction with silicon carbide single crystal substrate 50 are formed. When viewed in a plan view from a direction perpendicular to first main surface 1, if source region 13 is located inside the side end faces of barrier metal film 84, contact electrode 61 is formed so that the side end faces of contact electrode 61 are farther from gate trench 5 than the boundary surface between source region 13 and second contact region 19. Although a part of the second contact region 19 is consumed in the silicidation, the source region 13 is not consumed because it is covered with the gate insulating film 81 and the interlayer insulating film 83. The contact electrode 61 may form an ohmic junction with the first contact region 18. The contact electrode 61 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 may be made of a material containing titanium, aluminum, and silicon.

[0082] Next, the source wiring 62 is formed. Specifically, the source wiring 62 is formed to cover the contact electrode 61 and the barrier metal film 84. The source wiring 62 is formed by film formation using a sputtering method and RIE, for example. The source wiring 62 is made of a material containing aluminum, for example. In this way, the source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.

[0083] Next, the passivation film 85 is formed. Specifically, the passivation film 85 is formed to cover the source wiring 62. The passivation film 85 is made of a material containing polyimide, for example. The passivation film 85 is formed by, for example, a coating method.

[0084] In this way, the MOSFET 100 according to the embodiment is completed.

[0085] Next, the effects of the MOSFET according to this embodiment will be described.

[0086] In the MOSFET 100 according to this embodiment, the peak depth of the effective concentration of p-type impurities in the third electric field buffer region 16 is 1.0 μm or less, based on the first main surface 1. Therefore, the source region 13, the body region 12, the current spreading region 14, the drift region 11, and the third electric field buffer region 16 can be appropriately formed by ion implantation without forming epitaxial layers multiple times. Furthermore, when viewed in a plan view perpendicular to the first main surface 1, the first electric field buffer region 17 has the first region 15 overlapping with the first contact region 18, and the second electric field buffer region 31 surrounds the first region 15. Therefore, even if the first contact region 18 contains many crystal defects due to high-concentration ion implantation or the like, drain leakage via these crystal defects can be suppressed.

[0087] When the peak depth D1 is small, unlike the above-described manufacturing method, regrowth of an epitaxial layer is not required after the formation of the third electric field buffer region 16. This reduces the cost associated with regrowth of an epitaxial layer. Furthermore, high-energy ion implantation is not required when forming the third electric field buffer region 16. This avoids the increase in cost associated with high-energy ion implantation.

[0088] Furthermore, the smaller the first thickness T1 of the source region 13, the more the drain current during a short circuit is reduced, improving the short circuit resistance. On the other hand, because the second thickness T2 of the second contact region 19 is greater than the first thickness T1, even if part of the second contact region 19 is consumed when the contact electrode 61 is formed, it is easy to form an ohmic junction between the source electrode 60 including the contact electrode 61 and the second contact region 19.

[0089] The third electric field relaxation region 16 and the body region 12 are electrically connected to each other via the second electric field relaxation region 31, the connection region 32, and the first electric field relaxation region 17. This makes it easy to suppress drain leakage by keeping the third electric field relaxation region 16 and the body region 12 at the same potential. Furthermore, the second electric field relaxation region 31 and the connection region 32 are periodically arranged in the first direction. This makes it easy to suppress drain leakage while sufficiently ensuring a current path for on-current.

[0090] In addition, in the first direction, the first length L1 of the second electric field reduction region 31 is preferably equal to or shorter than the second length L2 of the second region 11D of the drift region 11. This is because it is easy to ensure a current path for the on-current. Furthermore, the first length L1 is preferably 20% to 40% of the sum of the first length L1 and the second length L2, and more preferably 25% to 35%. This is because it is particularly easy to achieve both ensuring a current path for the on-current and suppressing drain leakage.

[0091] In this embodiment, the third electric field reduction region 16 includes the fourth region 16B. Therefore, even if a high drain voltage is applied during off-state, penetration of an electric field into the body region 12 is suppressed, and drain leakage is easily suppressed.

[0092] The lower end surface 93 of the first electric field relaxation region 17 may be located closer to the first main surface 1 than the upper end surface 95 of the third region 16A of the third electric field relaxation region 16. As a result, the current spreading region 14 and the fifth region 11C of the drift region 11 are sandwiched between the fourth region 16B of the third electric field relaxation region 16 and the first electric field relaxation region 17, which makes it easier to suppress drain leakage.

[0093] The third electric field relaxation region 16 and the first electric field relaxation region 17 are electrically connected to each other via the second electric field relaxation region 31 and the connection region 32. This makes it easy to keep the third electric field relaxation region 16 and the first electric field relaxation region 17 at the same potential and suppress drain leakage.

[0094] Furthermore, by increasing the effective concentration of n-type impurities in the current diffusion region 14, an increase in on-resistance can be suppressed even if the fourth region 16B is provided.

[0095] [Variations] Next, a modified example of the embodiment will be described. The modified example differs from the embodiment mainly in the shape of the gate trench. Fig. 25 is a cross-sectional view showing the configuration of a MOSFET (silicon carbide semiconductor device) according to the modified example of the embodiment. Fig. 25 shows a cross section similar to the cross section taken along line II in Fig. 5.

[0096] 25, in a MOSFET 200 according to the modification, the gate trench 5 is a vertical trench. That is, the angle θ1 of the side surface 3 with respect to a plane including the bottom surface 4 may be 90°. The other configurations are the same as those of the embodiment.

[0097] Even with such a modification, the same effects as those of the embodiment can be obtained.

[0098] In the above embodiments and reference examples, n-type is the first conductivity type and p-type is the second conductivity type. However, p-type may be the first conductivity type and n-type may be the second conductivity type. In the above embodiments and reference examples, MOSFETs are used as examples of silicon carbide semiconductor devices. However, the silicon carbide semiconductor device may be, for example, an insulated gate bipolar transistor (IGBT). The effective concentrations of p-type impurities and n-type impurities in each impurity region can be measured by, for example, a scanning capacitance microscope (SCM) method or a secondary ion mass spectrometry (SIMS) method. The position of the boundary between the p-type region and the n-type region (i.e., the pn junction interface) can be identified by, for example, the SCM method or the SIMS method. The distribution of the effective concentration of majority carriers in the current spreading region can be determined based on the distribution of the thickness of the depletion layer generated by the pn junction between the current spreading region and the body region, without measuring the effective concentration. The thickness of the depletion layer can be determined by, for example, the SCM method or the SIMS method.

[0099] The gate trenches may extend in a honeycomb pattern or may be scattered in an island pattern.

[0100] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0101] 1 First main surface 2 Second main surface 3. Aspects 4 Bottom 5 Gate trench 10 Silicon carbide substrate 11 Drift Region 11C 5th area 11D 2nd area 11E 6th area 12 Body Region 13 Source Region 14 Current spreading region 15 First area 16 Third electric field relaxation region 16A 3rd area 16B 4th area 17 First electric field relaxation region 18 First contact area 19 Second contact area 21 Epitaxial layer 31 Second electric field relaxation region 32 Connection Area 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 70 drain electrode 81 Gate insulating film 82 gate electrode 83 Interlayer insulating film 84 Barrier metal film 85 Passivation Film 86 Contact Hole 91 1st position 92 Side end face 93, 94, 96, 97 Lower end surface 95 Upper end surface 100, 200 MOSFETs 150 mask layers 151 Opening

Claims

1. a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface; The silicon carbide substrate is a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; a source region having the first conductivity type and provided on the body region so as to be separated from the drift region; and a gate trench is provided in the first main surface, the gate trench being defined by a side surface that penetrates the source region and the body region to reach the drift region and a bottom surface that is continuous with the side surface; The silicon carbide substrate is a first contact region having the second conductivity type, the first contact region being connected to the body region and sandwiching the source region between the first contact region and the side surface; a first electric field relief region having the second conductivity type, the first region overlapping the first contact region when viewed in a plan view from a direction perpendicular to the first main surface, the first electric field relief region being provided on the second main surface side of the body region, connected to the body region; a second electric field buffer region having the second conductivity type and provided closer to the second main surface than the first electric field buffer region; a third electric field reduction region having the second conductivity type, the third electric field reduction region being provided between the gate trench and the second main surface; and the first region is surrounded by the outline of the second electric field buffer region when viewed in a plan view from a direction perpendicular to the first main surface, a peak depth of the effective concentration of the second conductivity type impurity in the third electric field relaxation region with respect to the first main surface being 1.0 μm or less; the second electric field relaxation regions are periodically arranged in the longitudinal direction of the gate trench, the drift region has a second region between the second electric field buffer regions adjacent to each other in the longitudinal direction, a first length of the second electric field relaxation region in the longitudinal direction that is equal to or less than a second length of the second region;

2. The silicon carbide semiconductor device according to claim 1 , wherein said first length is equal to or greater than 20% and equal to or less than 40% of the sum of said first length and said second length.

3. The third electric field relaxation region is a third region located closer to the second main surface than the bottom surface; a fourth region protruding from the third region toward the first main surface; and The silicon carbide semiconductor device according to claim 1 , wherein a portion of the drift region is located between the fourth region and the body region.

4. A silicon carbide substrate having a first main surface and a second main surface opposite the first main surface, The silicon carbide substrate is a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; a source region having the first conductivity type and provided on the body region so as to be separated from the drift region; and a gate trench is provided in the first main surface, the gate trench being defined by a side surface that penetrates the source region and the body region to reach the drift region and a bottom surface that is continuous with the side surface; The silicon carbide substrate is a first contact region having the second conductivity type, the first contact region being connected to the body region and sandwiching the source region between the first contact region and the side surface; a first electric field relief region having the second conductivity type, the first region overlapping the first contact region when viewed in a plan view from a direction perpendicular to the first main surface, the first electric field relief region being provided on the second main surface side of the body region, connected to the body region; a second electric field buffer region having the second conductivity type and provided closer to the second main surface than the first electric field buffer region; a third electric field reduction region having the second conductivity type, the third electric field reduction region being provided between the gate trench and the second main surface; and the first region is surrounded by the outline of the second electric field buffer region when viewed in a plan view from a direction perpendicular to the first main surface, a peak depth of the effective concentration of the second conductivity type impurity in the third electric field relaxation region with respect to the first main surface being 1.0 μm or less; The third electric field relaxation region is a third region located closer to the second main surface than the bottom surface; a fourth region protruding from the third region toward the first main surface; and a silicon carbide semiconductor device in which a portion of the drift region is located between the fourth region and the body region;

5. The silicon carbide semiconductor device according to claim 4 , wherein the second electric field relaxation regions are periodically arranged in a longitudinal direction of the gate trench.

6. The silicon carbide semiconductor device according to claim 1 , wherein the second electric field buffer region and the third electric field buffer region are connected in a direction parallel to the first main surface.

7. 7 . The silicon carbide semiconductor device according to claim 1 , further comprising a connection region that is connected to the first electric field relaxation region and the second electric field relaxation region and electrically connects the first electric field relaxation region and the second electric field relaxation region.

8. the silicon carbide substrate has a second contact region provided between the source region and the first contact region, connected to the source region, and having the first conductivity type; The silicon carbide semiconductor device according to claim 1 , wherein the second contact region is thicker than the source region.

9. 9. The silicon carbide semiconductor device according to claim 1, wherein the side surface of the gate trench includes a {0-33-8} plane.

Images