Optical transmitter and method for controlling optical transmitter

Abstract

This optical transmitter comprises a control unit for generating a multi-level amplitude modulation signal on the basis of binary transmission data, a drive unit for generating a drive signal in accordance with the multi-level amplitude modulation signal, and a light emitting unit for generating an optical signal in accordance with the drive signal. The control unit selects a first coding scheme or a second coding scheme in accordance with a switching signal. The control unit, using the selected coding scheme, generates a multi-level amplitude modulation signal by converting an M-bit (M is an integer of 2 or more) bit string included in the transmission data into a pulse signal of 2M logic levels. The control unit sets a voltage value of 2M logic levels in accordance with the selected coding scheme.

Description

[Technical Field]

[0001] The present disclosure relates to an optical transmitter and a method for controlling an optical transmitter. [Background technology]

[0002] In recent years, with the spread of smartphones and cloud computing, communication capacity has been steadily increasing. To achieve this increase in communication capacity, multi-level modulation methods such as PAM4 (4-level Pulse Amplitude Modulation) are sometimes adopted instead of binary modulation methods such as NRZ (Non-Return to Zero). In optical transmission using such multi-level modulation methods, noise may be mixed into the optical signal, making it difficult for optical receivers to accurately determine the level.

[0003] Patent Document 1 describes an optical transmitter that sets each level so that the greater the extinction ratio of a multi-level modulated optical signal, the greater the interval between two adjacent levels, in order to equalize the S / N (Signal to Noise) ratio at each level. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-113386 Summary of the Invention [Problem to be solved by the invention]

[0005] For example, in PAM4, two bits of data are assigned to each level. When an optical receiver receives a PAM4 signal, it performs level determination to decode the two bits of data and transmits each bit to the host device via a different lane. At this time, if the PAM4 signal is misjudged as a level adjacent to the original level, an error occurs in at least one of the two bits (lanes). The lane in which the error occurs differs depending on which logical level the misjudgment occurs between. When a misjudgment occurs between two adjacent logical levels, the probability that an error will occur in a lane (error occurrence probability) differs depending on the encoding method. For example, when the encoding method is Gray code, the error occurrence probability in the lane corresponding to the first bit is two-thirds, and the error occurrence probability in the lane corresponding to the second bit is 1 / 3. occurrence The probability is 1 in 3. Therefore, in the optical transmitter described in Patent Document 1, although the S / N ratio of each level can be made uniform, there is a risk that the receiving sensitivity (bit error rate) between the two lanes will become uneven.

[0006] The present disclosure describes an optical transmitter that can reduce the difference in receiving sensitivity between lanes, and a method for controlling the optical transmitter. [Means for solving the problem]

[0007] An optical transmitter according to one aspect of the present disclosure is an optical transmitter that outputs a multi-level amplitude modulated optical signal. This optical transmitter includes a control unit that generates a multi-level amplitude modulated signal based on binary transmission data, a drive unit that generates a drive signal in response to the multi-level amplitude modulated signal, and a light emitting unit that generates an optical signal in response to the drive signal. The control unit selects either a first encoding method or a second encoding method in response to a switching signal. The control unit encodes an M-bit bit string included in the transmission data into binary bits using the selected encoding method. M The control unit converts the digital signal into a pulse signal of two logic levels to generate a multi-level amplitude modulation signal. M Sets the voltage values ​​of logic levels, where M is an integer equal to or greater than 2. [Effects of the Invention]

[0008] According to the present disclosure, the difference in reception sensitivity between lanes can be reduced. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating a schematic configuration of an optical transceiver including an optical transmitter according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating an example of an eye pattern of a PAM4 signal. [Figure 3] FIG. 3 is a diagram for explaining the values ​​of each lane in the binary code and the Gray code. [Figure 4] FIG. 4 is a diagram for explaining four-level pulse amplitude modulation performed by the DSP (Digital Signal Processor) shown in FIG. [Figure 5] FIG. 5 is a diagram showing lanes in which an error occurs when an erroneous determination occurs between logic levels. [Figure 6] FIG. 6 is a diagram showing combinations of voltage values ​​for each logic level. [Figure 7] FIG. 7 is a diagram showing the bit error rate when the voltage values ​​shown in FIG. 6 are used. [Figure 8] FIG. 8 is a diagram showing linearity when the voltage values ​​shown in FIG. 6 are used. [Figure 9] FIG. 9 is a diagram showing SECQ (Stressed Eye Closure for PAM4) when the voltage values ​​shown in FIG. 6 are used. [Figure 10] FIG. 10 is a flowchart showing the setting process performed by the optical transceiver shown in FIG. [Figure 11] FIG. 11 is a flowchart illustrating a transmission control process performed by the optical transceiver shown in FIG. [Figure 12] FIG. 12 is a flowchart illustrating a reception control process performed by the optical transceiver shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0011] An optical transmitter according to one aspect of the present disclosure is an optical transmitter that outputs a multi-level amplitude modulated optical signal. This optical transmitter includes a control unit that generates a multi-level amplitude modulated signal based on binary transmission data, a drive unit that generates a drive signal in response to the multi-level amplitude modulated signal, and a light emitting unit that generates an optical signal in response to the drive signal. The control unit selects either a first encoding method or a second encoding method in response to a switching signal. The control unit encodes an M-bit bit string included in the transmission data into binary bits using the selected encoding method. M The control unit converts the digital signal into a pulse signal of two logic levels to generate a multi-level amplitude modulation signal. M Sets the voltage values ​​of logic levels, where M is an integer equal to or greater than 2.

[0012] In this optical transmitter, the bit string of M bits included in the transmitted data is 2 M The optical receiver generates a multi-level amplitude modulated signal by converting the optical signal into a pulse signal of five logic levels, generates a drive signal in response to the multi-level amplitude modulated signal, and generates an optical signal in response to the drive signal. modulation The multi-level amplitude modulation signal is converted into a signal, the multi-level amplitude modulation signal is decoded into a bit string of M bits, and the M bits can be transmitted in different lanes. M Voltage values ​​of the M logic levels are set. For example, by setting the voltage values ​​of each logic level according to the probability of error occurrence between the lanes, the difference in bit error rate between the M lanes can be reduced. As a result, it is possible to reduce the difference in receiving sensitivity between the lanes. Furthermore, two encoding methods can be used without increasing the difference in receiving sensitivity between the lanes.

[0013] The control unit performs 2-bit multiplication so that the bit error rates of the first bit to the Mth bit included in the M bits are equal to each other. M In the optical receiver, the optical signal may be multi-level amplitude. modulation The multi-level amplitude modulation signal is decoded into an M-bit bit string, and the M bits can be transmitted on different lanes. In this case, in the above configuration, the 2-bit error rate is set so that the bit error rates of the first bit to the M-th bit are equal to each other. M Since the voltage values ​​of the logic levels are set, the difference in bit error rate among the M lanes is reduced, and therefore it is possible to reduce the difference in receiving sensitivity among the lanes.

[0014] The control unit is M The error probability is the probability that an error occurs in each bit of the bit string when a misjudgment occurs between two adjacent logic levels among the logic levels. M The voltage value of each logic level may be set. When the voltage difference between two adjacent logic levels is large, the possibility of an erroneous decision occurring between those two logic levels decreases. For example, by increasing the voltage difference between two logic levels at which a bit with a high error probability changes, the bit error rate of that bit is reduced. In this way, the voltage difference between two logic levels can be set according to the error probability. M By setting the voltage values ​​of the logic levels, it is possible to reduce the difference in reception sensitivity between lanes.

[0015] The control unit adjusts the voltage difference between two logic levels at which the first bit changes to be greater than the voltage difference between two other logic levels at which the second bit changes, when the probability of an error occurring in a first bit of the bit string is higher than the probability of an error occurring in a second bit of the bit string. MThe voltage values ​​of the logic levels may be set. Increasing the voltage difference between two adjacent logic levels reduces the possibility of erroneous determination between those two logic levels. Therefore, by making the voltage difference between the two logic levels at which the first bit changes larger than the voltage difference between the other two logic levels at which the second bit changes, the difference between the bit error rate of the first bit and the bit error rate of the second bit is reduced. As a result, it is possible to reduce the difference in reception sensitivity between the lanes.

[0016] The first encoding method may be a Gray code. M The logic levels may include a first logic level which is the smallest, a second logic level which is the second smallest, and a third logic level which is the third smallest. The control unit controls the two logic levels so that a voltage difference between the first logic level and the second logic level when the first encoding method is selected is larger than a voltage difference between the second logic level and the third logic level. M In the Gray code, bits that change between the first and second logic levels change more frequently (number of times) between two adjacent logic levels than bits that change between the second and third logic levels. Therefore, when the voltage difference between the first and second logic levels is the same as the voltage difference between the second and third logic levels, the bit error rate of bits that change between the first and second logic levels is higher than the bit error rate of bits that change between the second and third logic levels. In contrast, with the above configuration, the possibility of erroneous determination between the first and second logic levels can be reduced more than the possibility of erroneous determination between the second and third logic levels. Therefore, it is possible to reduce the difference between the bit error rate of bits that change between the first and second logic levels and the bit error rate of bits that change between the second and third logic levels. As a result, it is possible to reduce the difference in reception sensitivity between lanes.

[0017] The first encoding method may be a Gray code, and the second encoding method may be a binary code, in which case an optical transmitter compliant with IEEE (Institute of Electrical and Electronics Engineers) P802.3bs can be provided.

[0018] 2 M The logic levels may include a first logic level which is the smallest, a second logic level which is the second smallest, and a third logic level which is the third smallest. The control unit controls the two logic levels so that a voltage difference between the second logic level and the third logic level when the first encoding method is selected is smaller than a voltage difference between the second logic level and the third logic level when the second encoding method is selected. M Voltage values ​​for the logic levels may be set.

[0019] In a binary code, when the voltage difference between the first logic level and the second logic level is the same as the voltage difference between the second logic level and the third logic level, the bit error rates of the first to Mth bits included in the bit string can be uniform. In a Gray code, bits that change between the first logic level and the second logic level change more frequently (number of times) between two adjacent logic levels than bits that change between the second logic level and the third logic level. Therefore, in a Gray code, when the voltage difference between the first logic level and the second logic level is the same as the voltage difference between the second logic level and the third logic level, the bit error rate of bits that change between the first logic level and the second logic level is higher than the bit error rate of bits that change between the second logic level and the third logic level. In contrast, with the above configuration, when a Gray code is selected as the encoding method, the possibility of erroneous determination between the first logic level and the second logic level can be reduced more than the possibility of erroneous determination between the second logic level and the third logic level. Therefore, it is possible to reduce the difference between the bit error rate of bits that change between the first and second logic levels and the bit error rate of bits that change between the second and third logic levels, which in turn reduces the difference in reception sensitivity between lanes when Gray code is selected as the encoding method.

[0020] A control method for an optical transmitter according to another aspect of the present disclosure is a control method for an optical transmitter that outputs a multi-level amplitude modulated optical signal. This control method includes the steps of generating a multi-level amplitude modulated signal based on binary transmission data, generating a drive signal in response to the multi-level amplitude modulated signal, and generating an optical signal in response to the drive signal. In the step of generating the multi-level amplitude modulated signal, either a first encoding method or a second encoding method is selected in response to a switching signal, and a bit string of M bits included in the transmission data is encoded into binary bits using the selected encoding method. M By converting the input signal into a pulse signal with 2 logic levels, a multi-level amplitude modulation signal is generated. MThe voltage values ​​of the logic levels are set according to the selected encoding method, where M is an integer equal to or greater than 2.

[0021] In this optical transmitter control method, the bit string of M bits included in the transmission data is 2 M The optical receiver generates a multi-level amplitude modulated signal by converting the optical signal into a pulse signal of five logic levels, generates a drive signal in response to the multi-level amplitude modulated signal, and generates an optical signal in response to the drive signal. modulation The multi-level amplitude modulation signal is converted into a signal, the multi-level amplitude modulation signal is decoded into a bit string of M bits, and the M bits can be transmitted in different lanes. M Voltage values ​​of the M logic levels are set. For example, by setting the voltage values ​​of each logic level according to the probability of error occurrence between the lanes, the difference in bit error rate between the M lanes can be reduced. As a result, it is possible to reduce the difference in receiving sensitivity between the lanes. Furthermore, two encoding methods can be used without increasing the difference in receiving sensitivity between the lanes.

[0022] [Details of the embodiments of the present disclosure] Specific examples of optical transmitters and optical transmitter control methods according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0023] Fig. 1 is a diagram illustrating a schematic configuration of an optical transceiver including an optical transmitter according to an embodiment. Fig. 2 is a diagram illustrating an example of an eye pattern of a PAM4 signal. Fig. 3 is a diagram illustrating values ​​of each lane in a binary code and a Gray code. Fig. 4 is a diagram illustrating four-level pulse amplitude modulation performed by the DSP illustrated in Fig. 1.

[0024] The optical transceiver 1 (optical transmitter) shown in FIG. 1 is an optical transceiver that realizes, for example, 53 Gbps transmission and complies with the QSFP (Quad Small Form-factor Pluggable) 28 standard. The optical transceiver 1 is communicatively connected to another optical transceiver via an optical fiber cable. The optical transceiver 1 transmits a multi-level amplitude modulated optical signal to the other optical transceiver and receives a multi-level amplitude modulated optical signal from the other optical transceiver. In this embodiment, PAM4 (4-level Pulse Amplitude Modulation) is used as the multi-level amplitude modulation. The optical transceiver 1 is communicatively connected to a host device 2.

[0025] The host device 2 is a higher-level device that monitors and controls the optical transceiver 1. The host device 2 includes a host board 21 for communicating with the optical transceiver 1. The host board 21 transmits transmission data to the optical transceiver 1 via lanes Tx1 and Tx2, which are transmission channels. The host board 21 receives reception data from the optical transceiver 1 via lanes Rx1 and Rx2, which are reception channels. The transmission data transmitted via lanes Tx1 and Tx2 and the reception data transmitted via lanes Rx1 and Rx2 are binary-modulated electrical signals. For example, NRZ (Non-Return to Zero) is used as the binary modulation method.

[0026] Specifically, the host board 21 transmits transmission data by synchronizing one bit at a time using lanes Tx1 and Tx2. The host board 21 receives reception data from the optical transceiver 1 by synchronizing one bit at a time using lanes Rx1 and Rx2, which are reception channels. Each lane (lanes Tx1, Tx2, Rx1, Rx2) transmits data at a transmission speed of 26.5 Gbps. To achieve transmission of 400 Gbps, eight sets of lanes Tx1, Tx2, Rx1, Rx2 may be provided. The host board 21 transmits a switching signal to the optical transceiver 1 by serial communication. The switching signal is a signal indicating whether or not to use Gray code. An example of serial communication is 2C (Inter-Integrated Circuit), and MDIO (Management Data Input / Output).

[0027] The optical transceiver 1 includes a DSP 11 (control unit), a drive circuit 12 (drive unit), a TOSA (Transmitter Optical Sub-Assembly) 13 (light emitting unit), a bias circuit 14, a ROSA (Receiver Optical Sub-Assembly) 15, and a CPU (Central Processing Unit) 16.

[0028] The DSP 11 is a device that performs signal processing. The DSP 11 generates a PAM4 signal (multiple amplitude modulation signal), which is an electrical signal, based on transmission data received from the host device 2. The PAM4 signal is transmitted at, for example, 26.5 Gbaud. As shown in FIG. 2, the PAM4 signal has four logic levels (voltage levels): Level-0, Level-1, Level-2, and Level-3. The logic levels are sometimes referred to as symbols. Level-0 to Level-3 increase in the order of Level-0, Level-1, Level-2, and Level-3. That is, Level-0 is the smallest logic level, Level-1 is the second smallest logic level, Level-2 is the third smallest logic level, and Level-3 is the largest logic level.

[0029] The DSP 11 converts two lanes of transmission data into one lane of PAM4 signals using a predetermined encoding method. In this embodiment, the DSP 11 can use Gray code (first encoding method) and binary code (second encoding method) as encoding methods. The CPU 16 sets whether to use Gray code or binary code as the encoding method. The DSP 11 selects either Gray code or binary code as the encoding method in accordance with a switching signal output from the host board 21. The Gray code is an encoding method in which the Hamming distance between codes (bit strings) assigned to adjacent symbols is 1. The DSP 11 converts the data into pulses of one of the logic levels Level-0, Level-1, Level-2, and Level-3 in accordance with the combination (B2, B1) of bit B2 of lane Tx2 and bit B1 of lane Tx1 simultaneously received from the host board 21.

[0030] A case where a binary code is selected as the encoding method will be described. As shown in Figures 3 and 4, DSP11 generates a Level-0 pulse when the combination (B2, B1) is (0,0). DSP11 generates a Level-1 pulse when the combination (B2, B1) is (0,1). DSP11 generates a Level-2 pulse when the combination (B2, B1) is (1,0). DSP11 generates a Level-3 pulse when the combination (B2, B1) is (1,1).

[0031] A case will be described where Gray code is selected as the encoding method. As shown in Fig. 3, DSP11 generates a Level-0 pulse when the combination (B2, B1) is (0,0). DSP11 generates a Level-1 pulse when the combination (B2, B1) is (0,1). DSP11 generates a Level-2 pulse when the combination (B2, B1) is (1,1). DSP11 generates a Level-3 pulse when the combination (B2, B1) is (1,0).

[0032] The DSP 11 generates a PAM4 signal by performing the above conversion every time it receives one bit from each lane. The DSP 11 outputs the PAM4 signal to the driver circuit 12. The CPU 16 sets, in a register of the DSP 11, a voltage value (output amplitude) for each logic level according to the selected encoding method. The DSP 11 generates a pulse having an amplitude of the voltage value set in the register.

[0033] The DSP 11 generates received data based on the PAM4 signal, which is an electrical signal received from the ROSA 15. Specifically, the DSP 11 converts a one-lane PAM4 signal into two-lane received data using a predetermined encoding method. As described above, in this embodiment, the DSP 11 can use Gray code and binary code as encoding methods. The DSP 11 determines the logic level for each symbol (pulse) of the PAM4 signal received from the ROSA 15 and generates a combination (B2, B1) of bit B2 of lane Rx2 and bit B1 of lane Rx1 according to the logic level. The DSP 11 compares the voltage value of the symbol with a preset threshold voltage to determine which logic level the symbol is at.

[0034] A case will be described where a binary code is selected as the encoding method. As shown in Fig. 3, when the logic level is Level-0, the DSP 11 generates (0,0) as the combination (B2,B1). When the logic level is Level-1, the DSP 11 generates (0,1) as the combination (B2,B1). When the logic level is Level-2, the DSP 11 generates (1,0) as the combination (B2,B1). When the logic level is Level-3, the DSP 11 generates (1,1) as the combination (B2,B1).

[0035] A case will be described where Gray code is selected as the encoding method. As shown in Fig. 3, when the logic level is Level-0, the DSP 11 generates (0,0) as the combination (B2,B1). When the logic level is Level-1, the DSP 11 generates (0,1) as the combination (B2,B1). When the logic level is Level-2, the DSP 11 generates (1,1) as the combination (B2,B1). When the logic level is Level-3, the DSP 11 generates (1,0) as the combination (B2,B1).

[0036] The DSP11 transmits bit B1 to the host device 2 via lane Rx1, and transmits bit B2 to the host device 2 via lane Rx2. The DSP11 synchronizes the transmission of bit B1 with the transmission of bit B2.

[0037] The driver circuit 12 is a circuit that drives the laser diode included in the TOSA 13. The driver circuit 12 generates a driver signal, which is an electrical signal, in response to the PAM4 signal and outputs the driver signal to the TOSA 13. The driver circuit 12 may be built into the TOSA 13.

[0038] The TOSA 13 is an optical transmission module that generates an optical signal in response to a drive signal and transmits the optical signal to another optical transceiver via an optical fiber cable. The TOSA 13 includes a laser diode, which is a light-emitting element for generating the optical signal. The laser diode is driven by the drive signal and outputs the optical signal in response to the drive signal. Examples of laser diodes include a directly modulated laser diode (DML) and an electro-absorption modulator integrated with distributed feedback laser diode (EML). Here, we will explain the use of an EML as an example. The EML includes a laser diode and an electro-absorption modulator (EA). A direct current is supplied to the anode of the laser diode, and the laser diode generates continuous wave (CW) light. The EA modulator modulates the CW light based on the drive signal.

[0039] The bias circuit 14 is a circuit that applies a DC (Direct Current) bias voltage to the EA modulator included in the TOSA 13 for waveform adjustment. The bias circuit 14 adjusts the DC bias voltage based on a control signal output from the CPU 16. When a DML is used as the laser diode of the TOSA 13, the bias circuit 14 adjusts the bias current supplied to the DML based on the control signal output from the CPU 16 for waveform adjustment.

[0040] The ROSA 15 is an optical receiver module that receives an optical signal from a TOSA of another optical transceiver via an optical fiber cable and converts the optical signal into a PAM4 signal, which is an electrical signal. The optical signal is a 26.5 Gbaud PAM4 optical signal. The ROSA 15 includes an opto-electrical conversion element for converting the optical signal into an electrical signal, and an amplifier. Examples of the opto-electrical conversion element include a PIN-PD (Photo Diode) and an APD (Avalanche Photo Diode). The amplifier is a circuit that generates a PAM4 signal by amplifying the electrical signal output from the opto-electrical conversion element. The amplifier is, for example, a linear TIA (Transimpedance Amplifier).

[0041] The CPU 16 controls the entire optical transceiver 1. The CPU 16 performs settings according to the encoding method. The CPU 16 receives a switching signal from the host board 21 and sets the DSP 11 to the encoding method corresponding to the switching signal and the voltage values ​​of each logic level corresponding to the selected encoding method. The voltage values ​​of each logic level are predetermined for each encoding method and stored in a memory (not shown). The CPU 16 reads the voltage values ​​corresponding to the selected encoding method from the memory and sets the read voltage values. Specifically, if the switching signal indicates that Gray code is to be used, the CPU 16 sets the DSP 11 to Gray code as the encoding method, reads the voltage values ​​of each logic level corresponding to the Gray code from the memory, and sets them in the DSP 11. If the switching signal indicates that Gray code is not to be used, the CPU 16 sets the DSP 11 to binary code as the encoding method, and reads the voltage values ​​of each logic level corresponding to the binary code from the memory and sets them in the DSP 11.

[0042] Next, a method for determining the optimum voltage value for each logical level according to the encoding method will be described. FIG. 5 is a diagram showing lanes in which an error occurs when a misjudgment occurs between logical levels. FIG. 6 is a diagram showing combinations of voltage values ​​for each logical level. FIG. 7 is a diagram showing the bit error rate when the voltage values ​​shown in FIG. 6 are used. FIG. 8 is a diagram showing linearity when the voltage values ​​shown in FIG. 6 are used. FIG. 9 is a diagram showing SECQ when the voltage values ​​shown in FIG. 6 are used.

[0043] As described above, the optical transceiver 1 transmits a quaternary pulse amplitude modulated optical signal to another optical transceiver. light When the transceiver receives an optical signal, it converts the optical signal into an electrical signal using an opto-electrical conversion element, and then amplifies the electrical signal using an amplifier to generate a PAM4 signal. light The transceiver's DSP determines the logic level of each symbol (pulse) of the PAM4 signal. In this case, the DSP may determine that the symbol's logic level is an adjacent logic level to the original logic level. In this case, at least one of bit B2 and bit B1 will have an incorrect value.

[0044] A specific example will be described in which a binary code is selected as the encoding method. As shown in FIG. 3, when the logic level is Level-0, the combination (B2, B1) is (0, 0), and when the logic level is Level-1, the combination (B2, B1) is (0, 1). Therefore, as shown in FIG. 5, in a misjudgment between Level-0 and Level-1, bit B1 will have an incorrect value, causing an error in lane Rx1. Note that a misjudgment between Level-0 and Level-1 occurs when Level-0 is judged to be Level-1, and when Level-1 is judged to be Level-0. Similarly, in a misjudgment between Level-1 and Level-2, both bit B1 and bit B2 will have incorrect values, causing errors in lane Rx1 and lane Rx2. In a misjudgment between Level-2 and Level-3, bit B1 will have an incorrect value, causing an error in lane Rx1.

[0045] A specific example will be described when Gray code is selected as the encoding method. As shown in Fig. 5, in a misjudgment between Level-0 and Level-1, bit B1 will have an incorrect value, causing an error in lane Rx1. In a misjudgment between Level-1 and Level-2, bit B2 will have an incorrect value, causing an error in lane Rx2. In a misjudgment between Level-2 and Level-3, bit B1 will have an incorrect value, causing an error in lane Rx1.

[0046] As mentioned above, the lane in which an error occurs differs depending on which logical level a misjudgment occurs between. For example, assuming that the S / N (Signal to Noise) ratio is constant at each logical level and the number of symbol occurrences is uniform, in a binary code, the probability of an error occurring in bit B2 (lane Rx2) is one-third, and the probability of an error occurring in bit B1 (lane Rx1) is one-third. Note that the error probability of a bit (lane) is the probability that an error will occur in that bit (lane) when a misjudgment occurs between logical levels. Under similar conditions, in a Gray code, the probability of an error occurring in bit B2 (lane Rx2) is one-third, and the probability of an error occurring in bit B1 (lane Rx1) is two-thirds.

[0047] When the voltage difference V(0-1) between the voltage values ​​of Level-0 and Level-1, the voltage difference V(1-2) between the voltage values ​​of Level-1 and Level-2, and the voltage difference V(2-3) between the voltage values ​​of Level-2 and Level-3 are equal, the ratio of the bit error rate of lane Rx1 to the bit error rate of lane Rx2 approximately matches the ratio of the error occurrence probabilities. As the voltage difference between two adjacent logical levels decreases, the possibility of an erroneous determination occurring between those two logical levels increases. Therefore, the bit error rate of each lane can change depending on the voltage difference between two adjacent logical levels.

[0048] Although receiver sensitivity is defined as the sum of the bit error rates of lanes Rx1 and Rx2, in actual use, if the difference in bit error rate (receive sensitivity) between lanes Rx1 and Rx2 becomes large, the host device is more likely to experience RxLOL (Loss of Lock) and Synchronization Loss in the lane with poorer receiver sensitivity. LOL is a state in which the host board's ASIC (Application Specific Integrated Circuit) and PLL (Phase Locked Loop) such as CDR (Clock Data Recovery) cannot lock the signal. Therefore, it is desirable to equalize receiver sensitivity between lanes Rx1 and Rx2.

[0049] Therefore, we measured the bit error rates of lanes Rx1 and Rx2 using the combinations of voltage values ​​for each logic level (combination P1 to combination P7) shown in Figure 6, and selected the optimal combination. The voltage supplied to optical transceiver 1 was set to 3.3 V, the ambient temperature was 35°C, and the extinction ratio of the optical signal was set to 8 dB, and the bit error rate was measured. The voltage supplied to optical transceiver 1 was converted to a voltage suitable for DSP 11 by a DC / DC converter within optical transceiver 1. TOSA 13 and ROSA 15 were connected back-to-back. The optical power (intensity) of the optical signal was set to an arbitrary value.

[0050] Here, the voltage value of each logic level is expressed as a percentage (unit: %) of the voltage value of Level-3, with the voltage value of Level-3 being a fixed value. In other words, the voltage value of Level-3 is 100%. In the combinations shown in FIG. 6, the voltage value of Level-0 is also set to a fixed value (18%). Therefore, the voltage difference V(0-3) between the voltage values ​​of Level-0 and Level-3 is constant. The voltage values ​​of Level-1 and Level-2 are set so that the eye opening between Level-1 and Level-2 decreases as the combination number increases. Therefore, in combination P1, the eye opening between Level-1 and Level-2 is the largest, and in combination P7, the eye opening between Level-1 and Level-2 is the smallest. Note that the voltage values ​​of Level-1 and Level-2 for each combination are set so as to be approximately symmetrical with respect to the line of symmetry between Level-0 and Level-3.

[0051] As shown in Figure 7, when Gray code is selected as the encoding method, as the combination number increases, the bit error rate of lane Rx2 increases and the bit error rate of lane Rx1 decreases. In other words, the smaller the voltage difference V(0-1) and voltage difference V(2-3) are and the larger the voltage difference V(1-2), the smaller the bit error rate of lane Rx2 and the larger the bit error rate of lane Rx1. On the other hand, the larger the voltage difference V(0-1) and voltage difference V(2-3) are and the smaller the voltage difference V(1-2), the larger the bit error rate of lane Rx2 and the smaller the bit error rate of lane Rx1.

[0052] As described above, the error probability of lane Rx2 is smaller than the error probability of lane Rx1, so by making the voltage difference V(1-2) smaller than the voltage difference V(0-1) and the voltage difference V(2-3), the difference between the bit error rate of lane Rx1 and the bit error rate of lane Rx2 is reduced. In the test results of FIG. 7, the bit error rate of lane Rx1 and the bit error rate of lane Rx2 were approximately equal in combination P5. In combination P5, the voltage difference V(1-2) is approximately 3% smaller than the voltage difference V(0-1) and the voltage difference V(2-3). Therefore, when Gray code is selected as the encoding method, receiving sensitivity is optimized by setting the voltage values ​​of combination P5.

[0053] When binary code is selected as the encoding method, the bit error rate of lane Rx1 and the bit error rate of lane Rx2 are approximately equal in combination P4, where the voltage difference V(0-1), voltage difference V(1-2), and voltage difference V(2-3) are approximately equal. Therefore, when binary code is selected as the encoding method, receiving sensitivity is optimized by setting the voltage values ​​of combination P4. Therefore, the voltage value of Level-1 when Gray code is selected is approximately 1% to 4% higher than the voltage value of Level-1 when binary code is selected. The voltage value of Level-2 when Gray code is selected is approximately 1% to 4% lower than the voltage value of Level-2 when binary code is selected.

[0054] The waveform of a PAM4 signal is required to have linearity and SECQ. Linearity is an index of waveform quality and indicates the linearity of the eye pattern. Linearity is a positive value less than 1, and the closer to 1, the more ideal the eye pattern. SECQ is an index of waveform quality and indicates the quality of the waveform before transmission. A smaller SECQ value means less noise. Linearity is required to be greater than 0.75 dB, and SECQ is required to be less than 3.2 dB. As shown in Figures 8 and 9, combinations P1 to P6 satisfy the linearity and SECQ specifications.

[0055] As described above, in order to optimize sensitivity, the voltage values ​​of each logic level are determined in advance by testing for each encoding method, and each voltage value is stored in a memory (not shown). Note that, although the voltage values ​​of Level-0 and Level-3 are fixed in the example shown in Fig. 6, all of the voltage values ​​from Level-0 to Level-3 may be changed.

[0056] Next, various processes performed by the optical transceiver 1 will be described. Fig. 10 is a flowchart showing the setting process performed by the optical transceiver shown in Fig. 1. Fig. 11 is a flowchart showing the transmission control process performed by the optical transceiver shown in Fig. 1. Fig. 12 is a flowchart showing the reception control process performed by the optical transceiver shown in Fig. 1.

[0057] In the setting process shown in FIG. 10, the CPU 16 first determines whether or not it has received a switching signal from the host board 21 (step S11). If the CPU 16 determines that it has not received a switching signal (step S11; NO), it repeats the determination process of step S11 until it receives a switching signal. If the CPU 16 determines that it has received a switching signal (step S11; YES), it reads out from a memory (not shown) voltage values ​​of logic levels corresponding to the encoding method selected by the switching signal. Then, the CPU 16 sets the voltage values ​​of each logic level, along with the encoding method, in a register of the DSP 11 (step S12). In step S12, the CPU 16 may output a control signal to the bias circuit 14 to output a DC bias voltage corresponding to the selected encoding method. Note that if a DML is used as the laser diode of the TOSA 13, the CPU 16 may output a control signal to the bias circuit 14 to output a bias current corresponding to the selected encoding method. This completes the setting process.

[0058] 11, first, the DSP 11 determines whether or not it has received two lanes of transmission data from the host board 21 (step S21). If it determines that it has not received the transmission data (step S21; NO), the DSP 11 repeats the determination process of step S21 until it receives the transmission data. If it determines in step S21 that it has received the transmission data (step S21; YES), the DSP 11 generates a PAM4 signal (step S22).

[0059] In step S22, the DSP 11 converts the transmission data into a PAM4 signal using the encoding method set by the CPU 16. Specifically, the DSP 11 converts (serializes) the transmission data into pulses of any one of the logical levels Level-0, Level-1, Level-2, and Level-3 according to the combination (B2, B1) of bit B2 of lane Tx2 and bit B1 of lane Tx1 simultaneously received from the host board 21. At this time, the DSP 11 generates pulses having a voltage value of the logical level set by the CPU 16. The DSP 11 generates a PAM4 signal by performing the above conversion every time one bit is received from each lane. Then, the DSP 11 sequentially outputs the PAM4 signal to the driver circuit 12.

[0060] Next, when the driver circuit 12 receives the PAM4 signal from the DSP 11, it generates a drive signal in accordance with the PAM4 signal (step S23). Then, the driver circuit 12 outputs the drive signal to the TOSA 13. Next, when the TOSA 13 receives the drive signal from the driver circuit 12, it generates an optical signal in accordance with the drive signal (step S24). In step S24, the laser diode is driven by the drive signal to generate an optical signal. Then, the TOSA 13 transmits the optical signal to another optical transceiver via an optical fiber cable. This completes the transmission control process.

[0061] 12, first, the ROSA 15 determines whether or not it has received an optical signal from another optical transceiver via the optical fiber cable (step S31). If the ROSA 15 determines that it has not received an optical signal (step S31; NO), it repeats the determination process of step S31 until it receives an optical signal. If the ROSA 15 determines in step S31 that it has received an optical signal (step S31; YES), it converts the optical signal into a PAM4 signal (step S32). In step S32, the photoelectric conversion element converts the optical signal into an electrical signal and outputs the electrical signal to the amplifier. Then, the amplifier generates a PAM4 signal by amplifying the electrical signal output from the photoelectric conversion element. Then, the ROSA 15 outputs the PAM4 signal to the DSP 11.

[0062] Next, upon receiving a PAM4 signal from the ROSA 15, the DSP 11 generates received data based on the PAM4 signal (step S33). In step S33, the DSP 11 converts (deserializes) the PAM4 signal into two-lane received data using the encoding method set by the CPU 16. Specifically, the DSP 11 determines the logical level of each symbol of the PAM4 signal by comparing a threshold voltage with the voltage value of the symbol. Then, the DSP 11 generates a combination (B2, B1) of bit B2 of lane Rx2 and bit B1 of lane Rx1 according to the determined logical level. Then, the DSP 11 transmits a pulse indicating bit B1 to the host board 21 via lane Rx1 and transmits a pulse indicating bit B2 to the host board 21 via lane Rx2. This completes the reception control process.

[0063] In the optical transceiver 1 and the control method for the optical transceiver 1 described above, a two-bit bit string (bits B2 and B1) included in transmission data is converted into a pulse signal of one of four logical levels to generate a PAM4 signal, a drive signal is generated in response to the PAM4 signal, and an optical signal is generated in response to the drive signal. In another optical transceiver, an optical signal is converted into a PAM4 signal, the PAM4 signal is decoded into a two-bit bit string (bits B2 and B1), and bits B1 and B2 are transmitted over lanes Rx1 and Rx2, respectively. In the optical transceiver 1, voltage values ​​of four logical levels (Level-0 to Level-3) are set according to the encoding method. For example, by setting the voltage value of each logical level according to the error probability between the lanes, the difference in bit error rate between lanes Rx1 and Rx2 can be reduced. As a result, the difference in receiving sensitivity between lanes Rx1 and Rx2 can be reduced.

[0064] Specifically, the DSP 11 sets the voltage values ​​of Level-0 to Level-3 according to the error probability. As the voltage difference between two adjacent logic levels increases, the possibility of an erroneous determination occurring between those two logic levels decreases. For example, by increasing the voltage difference between two logic levels at which a bit with a high error probability changes, the bit error rate of that bit is reduced. In this way, by setting the voltage values ​​of Level-0 to Level-3 according to the error probability, it is possible to reduce the difference in reception sensitivity between lane Rx1 and lane Rx2.

[0065] IEEE (Institute of Electrical and Electronics Engineers) P802.3bs requires switching between binary code and Gray code to maintain low power consumption and versatility. The DSP 11 selects either Gray code or binary code as the encoding method in response to a switching signal. The DSP 11 sets voltage values ​​from Level-0 to Level-3 according to the selected encoding method. This configuration provides an optical transceiver 1 that complies with IEEE P802.3bs. The voltage values ​​of the logic levels that provide optimal receiver sensitivity when the binary code is selected are different from the voltage values ​​of the logic levels that provide optimal receiver sensitivity when the Gray code is selected. Therefore, setting the optimal voltage value for one of the encoding methods degrades receiver sensitivity for the other encoding method. In contrast, the optical transceiver 1 sets the voltage values ​​of each logic level according to the selected encoding method. Therefore, two encoding methods, Gray code and binary code, can be used without increasing the difference in receiver sensitivity between lane Rx1 and lane Rx2.

[0066] In the Gray code, bit B1 changes between Level-0 and Level-1, and between Level-2 and Level-3. On the other hand, bit B2 changes between Level-1 and Level-2. Therefore, bit B1 changes between two adjacent logic levels more frequently (number of times) than bit B2. Therefore, when the voltage difference V(0-1) and the voltage difference V(2-3) are the same as the voltage difference V(1-2), the bit error rate of bit B1 is higher than that of bit B2. On the other hand, when the Gray code is selected as the encoding method, the voltage difference V(0-1) and the voltage difference V(2-3) are set to be larger than the voltage difference V(1-2). This reduces the possibility of erroneous determination between Level-0 and Level-1 and between Level-2 and Level-3 compared to the possibility of erroneous determination between Level-1 and Level-2. Therefore, it is possible to reduce the difference between the bit error rate of bit B1 and the bit error rate of bit B2. As a result, it is possible to reduce the difference in reception sensitivity between lane Rx1 and lane Rx2.

[0067] In other words, when Gray code is selected as the encoding method, the probability of an error occurring in bit B1 is higher than the probability of an error occurring in bit B2. In this case, DSP11 sets the voltage values ​​from Level-0 to Level-3 so that the voltage difference between the two logic levels at which bit B1 changes (between Level-0 and Level-1, and between Level-2 and Level-3) is greater than the voltage difference between the other two logic levels at which bit B2 changes (between Level-1 and Level-2). This reduces the difference between the bit error rate of bit B1 and the bit error rate of bit B2. As a result, it is possible to reduce the difference in reception sensitivity between lane Rx1 and lane Rx2.

[0068] In a binary code, when the voltage differences V(0-1), V(1-2), and V(2-3) are the same, the bit error rates of bits B1 and B2 can be equalized. Therefore, the DSP 11 sets the voltage values ​​of Level-0 to Level-3 so that the voltage difference V(1-2) when the Gray code is selected as the encoding method is smaller than the voltage difference V(1-2) when the binary code is selected as the encoding method. With this configuration, when the Gray code is selected as the encoding method, the possibility of an erroneous determination between Level-0 and Level-1 and between Level-2 and Level-3 can be reduced more than the possibility of an erroneous determination between Level-1 and Level-2. Therefore, it is possible to reduce the difference between the bit error rate of bit B1 and the bit error rate of bit B2. As a result, it is possible to reduce the difference in receiving sensitivity between lanes Rx1 and Rx2 when the Gray code is selected as the encoding method.

[0069] The DSP 11 sets the voltage values ​​from Level-0 to Level-3 so that the bit error rates of bits B1 and B2 are equal to each other. This reduces the difference in bit error rate between lanes Rx1 and Rx2. This reduces the difference in reception sensitivity between lanes Rx1 and Rx2.

[0070] If a misjudgment occurs between Level-1 and Level-2, it results in a two-bit error in binary code, but a one-bit error in Gray code. Therefore, using Gray code can reduce bit errors in optical transmission.

[0071] The optical transmitter and the method for controlling the optical transmitter according to the present disclosure are not limited to the above-described embodiments.

[0072] The optical transceiver 1 does not necessarily have to include the ROSA 15. In this case, the optical transceiver 1 functions as an optical transmitter.

[0073] The encoding methods that the DSP 11 can use are not limited to Gray code and binary code. The DSP 11 may use another encoding method instead of Gray code. The DSP 11 may use another encoding method instead of binary code. The DSP 11 may be configured to be able to use three or more encoding methods.

[0074] In the above embodiment, the DSP 11 may be able to use only one encoding method, for example, the DSP 11 may use only Gray code or only binary code.

[0075] The drive circuit 12 may have a level shift function. In this case, the CPU 16 may set the voltage values ​​of each logic level in the drive circuit 12.

[0076] As the multi-level amplitude modulation, PAM8, PAM16, etc. may be used. In other words, the DSP 11 encodes a bit string of M bits (M is an integer equal to or greater than 2) contained in the transmission data into 2 bits using a predetermined encoding method. M The DSP 11 generates a multi-level amplitude modulation signal by converting the digital signal into a pulse signal having two logic levels according to the encoding method. M In this case, the DSP 11 also sets the voltage values ​​of the two logic levels according to the probability of an error occurring for each bit included in the bit string. M For example, if the probability of an error occurring in the first bit of the bit string is higher than the probability of an error occurring in the second bit of the bit string, the DSP 11 sets the voltage values ​​of the two logic levels such that the voltage difference between the two logic levels at which the first bit changes is greater than the voltage difference between the other two logic levels at which the second bit changes. M The DSP 11 sets the voltage values ​​of the logic levels so that the bit error rates of the first bit to the Mth bit included in the M bits are equal to each other. M The DSP11 sets the voltage value of each logic level. modulationEven when using PAM4, the voltage values ​​of Level-0 to Level-3 may be set in the same way as in PAM4. [Explanation of symbols]

[0077] 1...Optical transceiver (optical transmitter) 2...Host device 11...DSP (control unit) 12...Drive circuit (drive unit) 13...TOSA (light-emitting part) 14...Bias circuit 15…ROSA 16...CPU 21...Host board B1...bit (1st bit) B2...bit (second bit) Rx1...Lane Rx2…Lane Tx1...lane Tx2…lane

Claims

1. An optical transmitter that outputs a multilevel amplitude modulated optical signal, a control unit that generates a multi-level amplitude modulation signal based on binary transmission data; a driver that generates a drive signal in response to the multi-level amplitude modulation signal; a light emitting unit that generates the optical signal in response to the drive signal; Equipped with the control unit selects either a first encoding method or a second encoding method in response to a switching signal; The control unit converts the M-bit bit string included in the transmission data into two bits using the selected encoding method. Ｍ generating the multi-level amplitude modulated signal by converting the multi-level amplitude modulated signal into a pulse signal of five logic levels; The control unit controls the two Ｍ Set the voltage values ​​of the logic levels, M is an integer of 2 or more, the control unit sets voltage values ​​of the 2 M logic levels according to an error occurrence probability, which is a probability that an error will occur in each bit of the bit string when an erroneous determination occurs between two adjacent logic levels among the 2 M logic levels; An optical transmitter wherein the control unit sets the voltage values ​​of the 2M logical levels so that, when the error probability of a first bit of the bit string is higher than the error probability of a second bit of the bit string, the voltage difference between two logical levels at which the first bit changes is greater than the voltage difference between another two logical levels at which the second bit changes.

2. the first encoding method is a Gray code; 2. Ｍ the logic levels include a first logic level that is the smallest, a second logic level that is the second smallest, and a third logic level that is the third smallest; The control unit controls the second logic level so that a voltage difference between the first logic level and the second logic level when the first encoding method is selected is larger than a voltage difference between the second logic level and the third logic level. Ｍ 2. The optical transmitter of claim 1, wherein voltage values ​​of logic levels are set.

3. An optical transmitter as described in Claim 2, wherein the second encoding method is a binary code.

4. An optical transmitter that outputs a multilevel amplitude modulated optical signal, a control unit that generates a multi-level amplitude modulation signal based on binary transmission data; a driver that generates a drive signal in response to the multi-level amplitude modulation signal; a light emitting unit that generates the optical signal in response to the drive signal; Equipped with the control unit selects either a first encoding method or a second encoding method in response to a switching signal; The control unit converts the M-bit bit string included in the transmission data into two bits using the selected encoding method. Ｍ generating the multi-level amplitude modulated signal by converting the multi-level amplitude modulated signal into a pulse signal of five logic levels; The control unit controls the two Ｍ Set the voltage values ​​of the logic levels, M is an integer of 2 or more, the first encoding method is a Gray code; the second encoding method is a binary code, the 2 M logic levels include a first logic level that is the smallest, a second logic level that is the second smallest, and a third logic level that is the third smallest; An optical transmitter wherein the control unit sets voltage values ​​of the 2M logic levels so that the voltage difference between the second logic level and the third logic level when the first encoding method is selected is smaller than the voltage difference between the second logic level and the third logic level when the second encoding method is selected.

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