Switching element and manufacturing method thereof

Abstract

To suppress formation of a gap below an overhang part of a contact layer.SOLUTION: A switching element includes a semiconductor substrate including a trench on an upper surface, a gate electrode disposed in the trench, an interlayer insulating film covering an upper surface of the gate electrode in the trench, a contact layer provided in contact with the upper surface of the semiconductor substrate, formed of an alloy of a metal and a material of the semiconductor substrate, and having an overhang part extending from the upper surface of the semiconductor substrate over the trench, a filling layer covering an upper surface of the interlayer insulating film and extending from a position in contact with one lower surface of two of the overhang parts disposed on both sides of the trench to a position in contact with the other lower surface, and an electrode layer formed of a conductor of a material different from the contact layer and disposed in contact with an upper surface of the filling layer and an upper surface of the contact layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a switching element and a manufacturing method thereof.

[0002] Patent Document 1 discloses a method for manufacturing a trench-gate switching element. In this manufacturing method, after forming a gate electrode in a trench, an interlayer insulating film is formed on the gate electrode and a semiconductor substrate. Next, the interlayer insulating film is etched back to remove the interlayer insulating film on the semiconductor substrate. The interlayer insulating film is left in the trench. Therefore, the upper surface of the interlayer insulating film is located at the same height as or lower than the upper end of the trench. By forming the interlayer insulating film in this manner, it is possible to form the interlayer insulating film in a self-aligned manner on top of the gate electrode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-252468 Summary of the Invention [Problem to be solved by the invention]

[0004] A known technique is to form a contact layer on the top surface of a semiconductor substrate by alloying a metal with the semiconductor substrate. An electrode layer is formed on the contact layer. By providing the contact layer between the electrode layer and the semiconductor substrate in this way, the electrode layer can be in contact with the semiconductor substrate with low contact resistance.

[0005] When an alloy layer is formed on the top surface of a semiconductor substrate in a case where an interlayer insulating film is disposed in a trench as in Patent Document 1, a portion of the alloy layer grows to protrude from the top surface of the semiconductor substrate toward the top of the trench (i.e., the top of the interlayer insulating film), forming an overhang. A gap exists between the overhang and the interlayer insulating film. If an electrode layer is formed on the contact layer and the top of the interlayer insulating film in a state where a gap exists, the electrode layer is difficult to form in the gap, and it is difficult to fill the gap with the electrode layer. As a result, a void may form below the overhang, deteriorating the reliability of the switching element. This specification proposes a technology for suppressing the formation of a void below the overhang. [Means for solving the problem]

[0006] The switching element of item 1 disclosed in this specification comprises a semiconductor substrate having a trench on its upper surface, a gate electrode disposed in the trench, an interlayer insulating film covering the upper surface of the gate electrode within the trench, a contact layer in contact with the upper surface of the semiconductor substrate and made of an alloy of a metal and the material of the semiconductor substrate, the contact layer having an overhang portion extending from the upper surface of the semiconductor substrate to the top of the trench, a filling layer covering the upper surface of the interlayer insulating film and extending from a position contacting the lower surface of one of the two overhang portions disposed on both sides of the trench to a position contacting the lower surface of the other, and an electrode layer made of a conductor of a material different from the contact layer and in contact with the upper surface of the filling layer and the upper surface of the contact layer.

[0007] The filling layer may be an insulator or a conductor. The filling layer may be made of the same compound as the interlayer insulating film. In this case, the filling layer and the interlayer insulating film may be integrated.

[0008] This switching element has a filler layer disposed above the trench, which extends from the position where it contacts the underside of one of the two overhangs disposed on both sides of the trench to the position where it contacts the underside of the other. By providing a filler layer above the trench to fill the gaps below the overhangs, it is possible to prevent voids from forming below the overhangs. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. [Figure 2] 1 is an enlarged cross-sectional view of a contact layer and a filling layer. [Figure 3] FIG. [Figure 4] 5A to 5C are explanatory diagrams of a method for manufacturing a switching element. [Figure 5] 5A to 5C are explanatory diagrams of a method for manufacturing a switching element. [Figure 6] 5A to 5C are explanatory diagrams of a method for manufacturing a switching element. [Figure 7] 5A to 5C are explanatory diagrams of a method for manufacturing a switching element. [Figure 8] 5A to 5C are explanatory diagrams of a method for manufacturing a switching element. [Figure 9] 5A to 5C are explanatory diagrams of a method for manufacturing a switching element. [Figure 10] 5A to 5C are explanatory diagrams of a method for manufacturing a switching element. [Figure 11] 5A to 5C are explanatory diagrams of a method for manufacturing a switching element. [Figure 12] FIG. 10 is an enlarged cross-sectional view of an overhang portion when an electrode layer is formed without a filling layer. DETAILED DESCRIPTION OF THE INVENTION

[0010] The configuration of the technology disclosed in this specification will be explained below item by item, following item 1 above. (Item 2) the semiconductor substrate includes a substrate material that is at least one of Si (silicon), C (carbon), Ga (gallium), In (indium), N (nitrogen), and O (oxygen); the contact layer is made of an alloy of at least one of Ni (nickel), Mo (molybdenum), Al (aluminum), Ti (titanium), Cu (copper), W (tungsten), Nb (niobium), and Mg (magnesium) and the substrate material; Item 1. The switching element according to item 1. (Item 3) the interlayer insulating film is made of silicon oxide, the filling layer is made of silicon oxide having a density lower than that of the interlayer insulating film; Item 3. The switching element according to item 1 or 2. (Item 4) 4. The switching element according to item 3, wherein the filling layer is made of silicon oxide containing B (boron) and P (phosphorus). (Item 5) 5. The switching element according to any one of items 1 to 4, wherein the thickness of the filling layer is greater than the distance between the tip of the overhanging portion and the lower end of the overhanging portion in the thickness direction of the semiconductor substrate and is smaller than the distance between the upper end of the contact layer and the lower end of the contact layer in the thickness direction. (Item 6) A method for manufacturing a switching element, comprising: forming a gate electrode within a trench in a semiconductor substrate having a trench on an upper surface thereof; forming an interlayer insulating film covering an upper surface of the gate electrode in the trench so that the upper surface of the interlayer insulating film is positioned at the same height as or lower than an upper end of the trench; forming a metal layer covering the upper surface of the semiconductor substrate and the upper surface of the interlayer insulating film; a step of forming a contact layer at an interface between the semiconductor substrate and the metal layer by heating the semiconductor substrate, in which the semiconductor substrate and the metal layer are alloyed, and an overhang portion extending from the top surface of the semiconductor substrate to an upper portion of the trench is formed as a part of the contact layer; a step of removing a portion of the metal layer that has not been alloyed, the step of removing the metal layer on the interlayer insulating film to form a gap between a lower surface of the overhang portion and an upper surface of the interlayer insulating film; forming a filling layer covering the upper surface of the interlayer insulating film, the filling layer being formed so that the two gaps disposed on both sides of the trench are filled with the filling layer and the upper surface of the contact layer is exposed from the interlayer insulating film; forming an electrode layer made of a conductor of a material different from that of the contact layer, the electrode layer being in contact with an upper surface of the filling layer and an upper surface of the contact layer; The manufacturing method has the following features.

[0011] According to the configuration of item 2 above, the contact layer can be brought into contact with the semiconductor substrate with low contact resistance.

[0012] According to the above items 3 and 4, the gap below the overhang portion can be suitably filled with silicon oxide. [Example]

[0013] The switching element 10 of the embodiment shown in FIG. 1 has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC (i.e., silicon carbide). The semiconductor substrate 12 has a body contact region 20, a source region 22, a body region 24, a drift region 26, and a drain region 28. The body contact region 20 is a p-type region having a high p-type impurity concentration and is provided in a range including a portion of the upper surface 12a of the semiconductor substrate 12. The source region 22 is an n-type region having a high n-type impurity concentration and is provided in a range including a portion of the upper surface 12a of the semiconductor substrate 12. The source region 22 is disposed adjacent to the body contact region 20. The body region 24 is a p-type region having a lower p-type impurity concentration than the body contact region 20. The body region 24 is in contact with the body contact region 20 and the source region 22 from below. The drift region 26 is an n-type region having a lower n-type impurity concentration than the source region 22. The drift region 26 contacts the body region 24 from below. The drain region 28 is an n-type region having a higher n-type impurity concentration than the drift region 26. The drain region 28 contacts the drift region 26 from below. The drain region 28 is arranged in a range that includes the lower surface 12b of the semiconductor substrate 12.

[0014] A drain electrode 44 is provided on the lower surface 12b of the semiconductor substrate 12. The drain electrode 44 is in ohmic contact with the drain region 28 over almost the entire area of ​​the lower surface 12b.

[0015] A plurality of trenches 30 are provided on the upper surface 12a of the semiconductor substrate 12. The trenches 30 extend parallel to one another on the upper surface 12a. Each trench 30 penetrates the source region 22 and the body region 24 to reach the drift region 26. The inner surface of each trench 30 is covered with a gate insulating film 32. A gate electrode 34 is disposed in each trench 30. Each gate electrode 34 is insulated from the semiconductor substrate 12 by the gate insulating film 32. Each gate electrode 34 faces the drift region 26, the body region 24, and the source region 22 via the gate insulating film 32. The upper surface of each gate electrode 34 is covered with an interlayer insulating film 36. The interlayer insulating film 36 is made of silicon oxide. The upper surface of each interlayer insulating film 36 is covered with a filling layer 38. The filling layer 38 is made of borophosphosilicate glass (BPSG: i.e., silicon oxide containing boron and phosphorus). The interlayer insulating film 36 and the filling layer 38 may be integrated. The density of the filling layer 38 is lower than the density of the interlayer insulating film 36. The upper surface 12a of the semiconductor substrate 12 is covered with a contact layer 40. The contact layer 40 is in ohmic contact with the source region 22 and the body contact region 20. The contact layer 40 is adjacent to the filling layer 38. The contact layer 40 is made of an alloy of a metal and the material of the semiconductor substrate 12. In this embodiment, the contact layer 40 is made of nickel silicide (i.e., an alloy of nickel and silicon). The upper surfaces of the filling layer 38 and the contact layer 40 are covered with an electrode layer 42. In this embodiment, the electrode layer 42 is made of titanium. However, the electrode layer 42 may be made of any conductor. For example, the electrode layer 42 may be a conductor containing at least one element selected from Ni, Mo, Al, Ti, Cu, Si, W, Nb, C, Mg, and N. The electrode layer 42 is connected to the semiconductor substrate 12 via the contact layer 40. The electrode layer 42 is insulated from the gate electrode 34 by the interlayer insulating film 36 and the fill layer 38 .

[0016] FIG. 2 shows an enlarged cross-sectional view of the contact layer 40 and the filling layer 38. As shown in FIG. 2, the upper surface 12a in the area between the trenches 30 has a gently curved, upwardly convex shape. Therefore, the contact layer 40 is gently curved along the upper surface 12a. Each contact layer 40 has an overhang portion 40a at its end, extending from the upper surface 12a to the top of the trench 30. The overhang portions 40a are provided at both ends of the contact layer 40. Therefore, the overhang portions 40a are located on both sides of the trench 30. Within each trench 30, the interlayer insulating film 36 is located below the upper surface 12a of the semiconductor substrate 12. Each filling layer 38 extends from a position contacting one of the contact layers 40 located on both sides of the trench 30 to a position contacting the other. Each filling layer 38 fills the lower portions of adjacent overhang portions 40a without any gaps and contacts the lower surfaces of each overhang portion 40a. That is, each filling layer 38 extends from a position contacting the lower surface of one of the two overhanging portions 40a disposed on both sides of the trench 30 to a position contacting the lower surface of the other.

[0017] FIG. 3 shows an enlarged view of the overhang portion 40a. In FIG. 3, thickness H1 denotes the thickness of the filling layer 38. Also in FIG. 3, distance H2 denotes the distance in the thickness direction of the semiconductor substrate 12 between the tip of the overhang portion 40a (i.e., the end of the overhang portion 40a toward the trench center) and the lower end of the overhang portion 40a. Also in FIG. 3, distance H3 denotes the distance in the thickness direction of the semiconductor substrate 12 between the upper end of the contact layer 40 and the lower end of the overhang portion 40a. Thickness H1 is greater than distance H2. Therefore, the entire region below the overhang portion 40a (i.e., the region between the lower surface of the overhang portion 40a and the upper surface of the interlayer insulating film 36) is filled with the filling layer 38. Also, thickness H1 is smaller than distance H3. Therefore, the upper surface of the contact layer 40 is exposed from the filling layer 38. Therefore, the electrode layer 42 is in contact with the upper surfaces of both the filling layer 38 and the contact layer 40.

[0018] The switching element 10 operates as a MOSFET (i.e., a metal oxide semiconductor field effect transistor). When a potential equal to or higher than the gate threshold is applied to the gate electrode 34, a channel is formed in the body region 24 near the gate insulating film 32, and the switching element 10 is turned on. Then, electrons flow from the electrode layer 42 to the drain electrode 44 via the contact layer 40, the source region 22, the channel, the drift region 26, and the drain region 28. Because the electrode layer 42 is connected to the source region 22 via the contact layer 40 with low resistance, the on-resistance of the switching element 10 is low.

[0019] Next, a method for manufacturing the switching element 10 will be described. First, a body contact region 20, a source region 22, a body region 24, a drift region 26, and a drain region 28 are formed in the semiconductor substrate 12 by appropriate ion implantation or epitaxial growth. Next, a trench 30 is formed in the upper surface 12a, and a gate insulating film 32 and a gate electrode 34 are formed in the trench 30. Next, as shown in FIG. 4, a thick interlayer insulating film 36 (i.e., a silicon oxide layer) is formed on the upper surface of the gate electrode 34 and on the upper surface 12a of the semiconductor substrate 12. Next, as shown in FIG. 5, the interlayer insulating film 36 is etched back to remove the interlayer insulating film 36 on the upper surface 12a, exposing the upper surface 12a from the interlayer insulating film 36. Furthermore, the interlayer insulating film 36 is left in each trench 30. The upper surface of the interlayer insulating film 36 remaining in each trench 30 is located below the upper surface 12a of the semiconductor substrate 12. According to this method, the interlayer insulating film 36 can be formed in a self-aligned manner on top of each gate electrode 34 without using an etching mask or the like.

[0020] Next, as shown in FIG. 6 , a metal layer 50 is formed to cover the upper surface of the interlayer insulating film 36 and the upper surface 12a of the semiconductor substrate 12. In this embodiment, the metal layer 50 is made of nickel. Next, the semiconductor substrate 12 is heat-treated at a high temperature to react the metal layer 50 with the semiconductor substrate 12. As a result, as shown in FIG. 7 , a contact layer 40 made of nickel silicide is formed at the interface between the metal layer 50 and the semiconductor substrate 12. The contact layer 40 thus formed makes low-resistance contact with the semiconductor substrate 12. A silicidation reaction is likely to occur near the upper end of the trench 30 (i.e., the corner between the side surface of the trench 30 and the upper surface 12a of the semiconductor substrate 12), and the contact layer 40 is likely to grow. Therefore, an overhang portion 40a extending from the upper surface 12a of the semiconductor substrate 12 to the top of the trench 30 is formed at the end of the contact layer 40. Furthermore, the interlayer insulating film 36 is also exposed to high temperatures during the heat treatment to form the contact layer 40. This densifies the interlayer insulating film 36, increasing its density. Next, the metal layer 50 that was not silicided is removed by etching. As a result, the interlayer insulating film 36 and the contact layer 40 are exposed, as shown in FIG. 8. Furthermore, when the metal layer 50 that was not silicided is removed, a gap 52 is formed below the overhang portion 40a (i.e., between the lower surface of the overhang portion 40a and the upper surface of the interlayer insulating film 36).

[0021] Next, as shown in FIG. 9 , a filling layer 38 made of BPSG is grown on the interlayer insulating film 36 and the contact layer 40 by CVD or the like. The overhanging portion 40a inhibits the growth of the filling layer 38 in the gap 52. Therefore, at this stage, as shown in FIG. 9 , the gap 52 cannot be completely filled with the filling layer 38, and voids are formed in the gap 52. Next, the semiconductor substrate 12 is heat-treated. Here, the heat treatment is performed at a temperature lower than that used for forming the contact layer 40. When the semiconductor substrate 12 is heat-treated, the filling layer 38 (i.e., BPSG) is heated and flows. As a result, the gap 52 is filled with the filling layer 38, and the voids disappear, as shown in FIG. 10 . As a result, the filling layer 38 contacts the entire lower surface of the overhanging portion 40a. In this way, the filling layer 38 can completely fill the lower portion of the overhanging portion 40a.

[0022] As described above, the interlayer insulating film 36 is densified during the high-temperature heat treatment for forming the contact layer 40. On the other hand, the filling layer 38 is not subjected to the high-temperature heat treatment for forming the contact layer 40. Therefore, the density of the filling layer 38 is lower than the density of the interlayer insulating film 36.

[0023] 11, the filling layer 38 is etched back to expose the upper surface of the contact layer 40. The filling layer 38 is left in the upper part of the trench 30 (i.e., the upper part of the interlayer insulating film 36). Here, the thickness H1 of the remaining filling layer 38 is set to be equal to the thickness H2 shown in FIG.

[0024] Next, an electrode layer 42 is grown on the contact layer 40 and the filling layer 38. Next, a drain electrode 44 is formed on the lower surface 12b of the semiconductor substrate 12. Through the above steps, the switching element 10 shown in FIGS.

[0025] ​FIG. 12 shows a cross section of an interlayer insulating film 36 and a contact layer 40 grown with an electrode layer 42 without forming a filling layer 38. In this case, the electrode layer 42 cannot fill the lower portion of the overhang 40a, resulting in a void 60 formed below the overhang 40a. The formation of the void 60 below the overhang 40a reduces the reliability of the switching element. In contrast, the manufacturing method of the embodiment fills the gap 52 below the overhang 40a with the filling layer 38. Therefore, a switching element 10 without a void below the overhang 40a can be manufactured. This manufacturing method allows the manufacturing of a highly reliable switching element 10.

[0026] In the above-described embodiment, the contact layer 40 is made of nickel silicide. However, the contact layer 40 may be made of other alloys. The contact layer 40 may be made of an alloy of a metal and the material of the semiconductor substrate. The semiconductor substrate may contain, for example, at least one of Si, C, Ga, In, N, and O. For example, the semiconductor substrate may be made of Si, SiC, GaN, InGaN, Ga2O3, or the like. Furthermore, the metal contained in the contact layer 40 (i.e., the metal layer 50 in FIG. 6) may be at least one of Ni, Mo, Al, Ti, Cu, W, Nb, and Mg.

[0027] In the above-described embodiment, the filling layer 38 is made of silicon oxide. However, various materials can be used for the filling layer 38 as long as they can fill the gap 52 below the overhang portion 40a. The filling layer 38 may be an insulator or a conductor. For example, a material containing at least one of Ni, Mo, Al, Ti, Cu, Si, W, Nb, C, Mg, Ga, In, N, B, P, and O can be used for the filling layer 38.

[0028] In the manufacturing method of the above-described embodiment, the interlayer insulating film 36 is formed so that the upper surface of the interlayer insulating film 36 is located lower than the upper surface 12a of the semiconductor substrate 12. However, the interlayer insulating film 36 may be formed so that the upper surface of the interlayer insulating film 36 is located at the same height as the upper surface 12a of the semiconductor substrate 12.

[0029] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0030] 10: switching element, 12: semiconductor substrate, 30: trench, 36: interlayer insulating film, 38: filling layer, 40: contact layer, 40a: overhang portion, 42: electrode layer

Claims

1. A switching element, a semiconductor substrate having a trench on an upper surface; a gate electrode disposed within the trench; an interlayer insulating film covering an upper surface of the gate electrode in the trench; a contact layer in contact with the top surface of the semiconductor substrate, the contact layer being made of an alloy of a metal and a material of the semiconductor substrate, and having an overhang portion extending from the top surface of the semiconductor substrate to an upper portion of the trench; a filling layer covering an upper surface of the interlayer insulating film and extending from a position contacting a lower surface of one of the two overhang portions disposed on both sides of the trench to a position contacting a lower surface of the other of the two overhang portions; an electrode layer made of a conductor of a material different from that of the contact layer, the electrode layer being in contact with the upper surface of the filling layer and the upper surface of the contact layer; and The tip of the overhang portion is located above the lower end of the overhang portion, a thickness of the filling layer is greater than a distance in the thickness direction of the semiconductor substrate between the tip of the overhang portion and the lower end of the overhang portion, and is smaller than a distance in the thickness direction between an upper end of the contact layer and the lower end of the overhang portion; Switching element.

2. the semiconductor substrate includes a substrate material that is at least one of Si, C, Ga, In, N, and O; the contact layer is made of an alloy of at least one of Ni, Mo, Al, Ti, Cu, W, Nb, and Mg and the substrate material; The switching element according to claim 1 .

3. the interlayer insulating film is made of silicon oxide, the filling layer is made of silicon oxide having a density lower than that of the interlayer insulating film; The switching element according to claim 1 or 2.

4. 4. The switching element according to claim 3, wherein the filling layer is made of silicon oxide containing B and P.

5. A method for manufacturing a switching element, comprising: forming a gate electrode within a trench in a semiconductor substrate having a trench on an upper surface thereof; forming an interlayer insulating film covering an upper surface of the gate electrode in the trench so that the upper surface of the interlayer insulating film is positioned at the same height as or lower than an upper end of the trench; forming a metal layer covering the upper surface of the semiconductor substrate and the upper surface of the interlayer insulating film; a step of forming a contact layer at an interface between the semiconductor substrate and the metal layer by heating the semiconductor substrate, in which the semiconductor substrate and the metal layer are alloyed, and an overhang portion extending from the top surface of the semiconductor substrate to an upper portion of the trench is formed as a part of the contact layer; a step of removing a portion of the metal layer that has not been alloyed, the step of removing the metal layer on the interlayer insulating film to form a gap between a lower surface of the overhang portion and an upper surface of the interlayer insulating film; forming a filling layer covering the upper surface of the interlayer insulating film, the filling layer being formed so that the two gaps disposed on both sides of the trench are filled with the filling layer and the upper surface of the contact layer is exposed from the interlayer insulating film; forming an electrode layer made of a conductor of a material different from that of the contact layer, the electrode layer being in contact with an upper surface of the filling layer and an upper surface of the contact layer; The manufacturing method has the following features.

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