Systems and methods for using multi-layer qubit lattice arrays for quantum computing

Abstract

A quantum computing (QC) system comprising a plurality of qubits generally arranged in a plurality of generally planar regions generally parallel to one another, at least some of the generally planar regions comprising two or more qubits, one or more qubits in each generally planar region configured to interact with one or more qubits in at least one other generally planar region.

Description

Detailed Description of the Invention

[0001] [background] <Field> This application is directed generally to quantum computing (QC), and more particularly to quantum computer architectures that employ lattice array structures in more than one dimension.

[0002] <Description of Related Art> There are many different technology pathways for scalable quantum computing. Performance, as measured by various figures of merit, varies significantly depending on the type of physical quantum bit (also called "qubit") employed by each approach. Approaches based on trapped ions, or superconducting qubits, have consistently led the field for over two decades. [overview]

[0003] Certain embodiments disclosed herein provide quantum computer architectures that employ lattice array structures greater than one dimension for implementing and interconnecting quantum gates in which more than two qubits can be simultaneously entangled. Certain embodiments disclosed herein provide quantum microprocessor structures and gate array design platforms for quantum processing chips similar to field programmable gate arrays (FPGAs) that can advantageously provide a degree of reconfigurability. Certain embodiments disclosed herein provide quantum microprocessor structures and gate array design platforms for quantum processing chips similar to application specific integrated circuits (ASICs) that can be advantageously optimized for specific applications and advantageously offer custom design flexibility.

[0004] Certain embodiments disclosed herein include lattice arrangements comprising a plurality of fully connected qubits arranged as an array of three-dimensional (3D) lattice structures (e.g., cells), where simultaneous operation of multi-qubit gates is enabled by the qubits arranged in the geometric layout. For example, certain embodiments may be configured as a plurality of two-dimensional (2D) (e.g., planar) qubit arrays oriented generally parallel to one another to form an array of three-dimensional (3D) cells. In another example, certain other embodiments may be configured as a plurality of one-dimensional (1D) (e.g., linear) qubit arrays (e.g., rows and columns, lattices, chains) oriented generally parallel to one another. In both of these examples, the array of cells can be analogized to, and referred to as, a 3D crystal structure. While various embodiments are described herein as utilizing trapped-ion qubits (e.g., in a microchip structure) to illustrate the nature of the quantum interactions utilized (e.g., optimized), other embodiments may employ one or more alternative qubit technologies.

[0005] Certain embodiments disclosed herein provide quantum computing (QC) systems comprising a plurality of qubits generally arranged in a plurality of generally planar regions (e.g., planes, layers) that are generally parallel to one another, at least some of the generally planar regions comprising two or more qubits, one or more qubits in each generally planar region configured to interact with one or more qubits in at least one adjacent generally planar region. For example, the QC system can comprise a first substrate and a second substrate, the first substrate and the second substrate being generally parallel to one another, and the QC system can further comprise a multi-qubit gate array comprising a plurality of qubits arranged as a plurality of multi-qubit gates located in a region between the first substrate and the second substrate. The qubits of the multi-qubit gate array may include surface electrode traps configured to contain ions (e.g., charged atoms, charged molecules) at or near the surfaces of at least one of the first and second substrates, and may be generally arranged in a plurality of generally planar regions (e.g., planes, layers, horizontal surfaces) with at least some of the qubits in at least one generally planar region configured to interact (e.g., be quantum mechanically entangled) with at least some of the qubits in at least one other (e.g., adjacent) generally planar region.

[0006] Certain embodiments disclosed herein provide quantum computing (QC) systems comprising a plurality of qubits arranged generally in multiple linear arrays generally parallel to one another, at least some of the linear arrays comprising two or more qubits, with one or more qubits in each linear array configured to interact with one or more qubits in at least one adjacent linear array. For example, the QC system may comprise a multi-qubit gate array comprising a plurality of qubits arranged as multiple multi-qubit gates positioned in a region between two or more substrates. The qubits of the multi-qubit gate array may comprise surface electrode traps configured to contain ions (e.g., charged atoms, charged molecules) at or near the surface of at least one of the substrates, and may be arranged generally in multiple linear arrays, with at least some of the qubits in at least one linear array configured to interact (e.g., quantum mechanically entangle) with at least some of the qubits in at least one other (e.g., adjacent) linear array. [Brief explanation of the drawings]

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments described herein and, together with the description, explain these embodiments. [Figure 1A] 1A-1C schematically illustrate various aspects of an example multi-qubit gate (e.g., cell) in accordance with certain embodiments described herein. [Figure 1B] 1A-1C schematically illustrate various aspects of an example multi-qubit gate (e.g., cell) in accordance with certain embodiments described herein. [Figure 1C] 1A-1C schematically illustrate various aspects of an example multi-qubit gate (e.g., cell) in accordance with certain embodiments described herein. [Figure 2A] 1A-1C schematically illustrate various aspects of an example multi-qubit gate (e.g., cell) in accordance with certain embodiments described herein. [Figure 2B]1A-1C schematically illustrate various aspects of an example multi-qubit gate (e.g., cell) in accordance with certain embodiments described herein. [Figure 2C] 1A-1C schematically illustrate various aspects of an example multi-qubit gate (e.g., cell) in accordance with certain embodiments described herein. [Figure 2D] 1A-1C schematically illustrate various aspects of an example multi-qubit gate (e.g., cell) in accordance with certain embodiments described herein. [Figure 2E] 1A-1C schematically illustrate various aspects of an example multi-qubit gate (e.g., cell) in accordance with certain embodiments described herein. [Figure 2F] 1A-1C schematically illustrate various aspects of an example multi-qubit gate (e.g., cell) in accordance with certain embodiments described herein. [Figure 3A] 1A-1C schematically illustrate top views of four example first portions (e.g., bases) of example arrays having four multi-ion qubit gates (e.g., cells) according to certain embodiments described herein. [Figure 3B] 1A-1C schematically illustrate top views of four example second portions (e.g., caps) of an array and four example multi-ion qubit gates according to certain embodiments described herein. [Figure 3C] 3C and 3D are schematic diagrams illustrating exploded and top views, respectively, of the example array and four multi-ion qubit gates of FIGS. 3A-3B in accordance with certain embodiments described herein. [Figure 3D] 3C and 3D are schematic diagrams illustrating exploded and top views, respectively, of the example array and four multi-ion qubit gates of FIGS. 3A-3B in accordance with certain embodiments described herein. [Figure 3E] FIG. 10 schematically illustrates an exploded view of another example array having four 10-ion qubit gates in accordance with certain embodiments described herein. [Figure 4A] 1A-1C are schematic diagrams illustrating an exploded view and an overlaid view from above of an example array having a 4×4 array of 16 multi-ion qubit gates, in accordance with certain embodiments described herein. [Figure 4B] 1A-1C are schematic diagrams illustrating an exploded view and an overlaid view from above of an example array having a 4×4 array of 16 multi-ion qubit gates, in accordance with certain embodiments described herein. [Figure 4C] FIG. 10 schematically illustrates a top-down view of another example multi-ion qubit gate array having 16 multi-ion qubit gates in accordance with certain embodiments described herein. [Figure 4D] FIG. 10 schematically illustrates a top-down view of another example multi-ion qubit gate array having four multi-ion qubit gates in accordance with certain embodiments described herein. [Figure 4E] FIG. 10 schematically illustrates a top-down view of another example multi-ion qubit gate array having 16 multi-ion qubit gates in accordance with certain embodiments described herein. [Figure 4F] 10A-10C are schematic diagrams illustrating exploded and overlaid views, respectively, of another example array having a 4×4 array of 16 multi-ion qubit gates in accordance with certain embodiments described herein. [Figure 4G] 10A-10C are schematic diagrams illustrating exploded and overlaid views, respectively, of another example array having a 4×4 array of 16 multi-ion qubit gates in accordance with certain embodiments described herein. [Figure 5A] 1A-1C schematically illustrate various views of some example QC structures according to certain embodiments described herein. [Figure 5B] 1A-1C schematically illustrate various views of some example QC structures according to certain embodiments described herein. [Figure 5C] 1A-1C schematically illustrate various views of some example QC structures according to certain embodiments described herein. [Figure 5D] 1A-1C schematically illustrate various views of some example QC structures according to certain embodiments described herein. [Figure 5E]1A-1C schematically illustrate various views of some example QC structures according to certain embodiments described herein. [Figure 5F] 1A-1C schematically illustrate various views of some example QC structures according to certain embodiments described herein. [Figure 5G] 1A-1C schematically illustrate various views of some example QC structures according to certain embodiments described herein. [Figure 5H] 1A-1C schematically illustrate various views of some example QC structures according to certain embodiments described herein. [Figure 5I] 1A-1C schematically illustrate various views of some example QC structures according to certain embodiments described herein. [Figure 6A] FIG. 10 schematically illustrates a top-down view of an example 4×4 array of alternating 4-ion qubit gates and 13-ion qubit gates with multiple optical ports in accordance with certain embodiments described herein. [Figure 6B] 6B illustrates a schematic diagram of a light signal illuminating ions in the array of FIG. 6A in accordance with certain embodiments described herein. [Figure 6C] 6B illustrates a schematic diagram of a light signal illuminating ions in the array of FIG. 6A in accordance with certain embodiments described herein. [Figure 6D] 6B illustrates a schematic diagram of a light signal illuminating ions in the array of FIG. 6A in accordance with certain embodiments described herein. [Figure 6E] FIG. 10 schematically illustrates a top view of the base portion and the overlay of the base and cap portions of another example of a 4×4 array of 10-ion qubit gates with multiple ion entry apertures and optical ports in accordance with certain embodiments described herein. [Figure 6F] 10A-10C schematically illustrate the overlap of the base and cap portions of another example 4×4 array of 10 ion qubit gates with multiple microwave antenna regions in accordance with certain embodiments described herein. [Figure 7A] 1A and 1B illustrate schematic side views of portions of example QC structures according to certain embodiments described herein. [Figure 7B] 7B schematically illustrates a close-up view of a smaller portion of the QC structure of FIG. 7A in accordance with certain embodiments described herein. [Figure 7C] 10A and 10B schematically illustrate diagrams of another example of a QC structure according to certain embodiments described herein. [Figure 7D] 10A and 10B schematically illustrate diagrams of another example of a QC structure according to certain embodiments described herein. [Figure 7E] 1 illustrates a schematic diagram of an ion injection aperture and single ion photodetector according to certain embodiments described herein. [Figure 8] 1A and 1B illustrate schematic side and top views of an example QC structure comprising an example 16x16 cell array in accordance with certain embodiments described herein. [Figure 9] 10 shows four tables comparing total qubit counts for various 4×4 cell arrays according to certain embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0008] [Detailed explanation] <Summary> Certain embodiments of the quantum computing (QC) systems described herein advantageously provide a multi-layer architecture that allows an optimal number of qubits to be entangled simultaneously between nearest and second-nearest neighbors. Certain embodiments include electrical and optical access channels for addressing, control, detection, and readout, as required to build scalable quantum processors. Arrays of fully connected qubits offer a more efficient and flexible option for executing quantum algorithms in hardware than designs in which entanglement gate operations are limited to a specific set depending on the type of qubits employed or their layout. This improved efficiency and flexibility scales rapidly with the number of qubits in the array. Adding the ability to perform gate operations involving more than two qubits at once can significantly accelerate efficiency gains over designs limited to one- and two-qubit gates, allowing a single four-qubit gate to replace dozens of one- and two-qubit gates. Certain embodiments described herein use multi-qubit arrays (e.g., multiple planar and / or linear arrays directly coupled) to advantageously avoid problems with one- and two-dimensional geometries (e.g., connectivity limitations, crowding of electrodes required to control each qubit within a gate, which can significantly increase gate spacing). In certain embodiments, multidimensional cells of qubits are formed that resemble crystals such as pyrochlore. Flipping the qubits and cells (e.g., in alternating rows) can enable closer tiling of cells and spacing for optical access, control, and readout. Utilizing a large number of qubits per gate can also reduce the need for circuit depth, error correction, and interference mitigation. Interchangeable component cells can enable quantum FPGA (QFPGA) and quantum ASIC (QASIC) chips.

[0009] Certain embodiments of the QC systems described herein are configured with multi-layer arrangements comprising multiple fully-connected qubits arranged as an array of three-dimensional (3D) lattice structures (e.g., cells), where simultaneous operation of multi-qubit gates is enabled by the qubits arranged in the geometric layout. For example, multiple planar or linear qubit arrays (e.g., rows and columns, lattices, chains) in layers may be oriented substantially parallel to one another to form an array of 3D cells that resembles and may be referred to as a crystalline structure. In certain embodiments, qubits may be equivalently suspended (e.g., trapped) above and below (or above and below, left and right, etc.) multiple mutually aligned qubit storage regions (e.g., opposing parallel ion trap arrays) to enable optimal coherent connectivity (e.g., entanglement) directly between nearest neighbor qubits, next-nearest neighbor qubits, etc. across substantially planar regions (e.g., layers, horizontal planes, planes) of multiple arrays without requiring photon or other mutual coupling or significant time delays that would entail degradative (irreversible) conversion of the qubits to other species or data bits for processing in situ. Certain such embodiments utilize geometrically symmetric cell structures that provide the ability to perform gate operations involving more than two qubits at once, which can greatly accelerate efficiency gains over designs limited to one- and two-qubit gates; one four-qubit gate can replace dozens of one- and two-qubit gates. Certain embodiments described herein use qubit arrays in multiple directly coupled, generally planar regions (e.g., layers, horizontal planes, faces) to advantageously avoid one- and two-dimensional geometric problems (e.g., connectivity limitations, electrode crowding required to control each qubit within a gate, which can significantly increase gate spacing). In certain embodiments, multidimensional cells of qubits are formed, which resemble crystals such as pyrochlore. Inverting the qubits and cells (e.g., in alternating rows) can allow for closer tiling of cells and spacing for optical access, control, and readout.Utilizing a large number of qubits involved per gate may also reduce and minimize the need for circuit depth, error correction, and interference mitigation. Interchangeable component cells may enable quantum FPGA (QFPGA) and quantum ASIC (QASIC) chips.

[0010] While various embodiments are described herein that rely on the physics of the trapped ion qubit approach, other qubit (e.g., superconducting qubit) approaches may also be used in certain embodiments described herein without loss of generality.

[0011] Certain embodiments of the QC systems described herein include multiple multi-qubit three-dimensional (3D) gate cells, each cell including at least three qubits that can be simultaneously fully coupled across three dimensions, where the multiple multi-qubit cells are configured for gating two or more multi-qubit gates. The QC system of certain such embodiments may include multiple mutually aligned qubit storage regions, such as opposing parallel ion trap arrays, which enable optimal coherent connectivity or entanglement directly between nearest-neighbor qubits and second-neighbor qubits across layers, horizontal planes, or faces of the arrays without requiring photonic or other mutual coupling. The multi-qubit cells may be configured using geometric symmetry to allow the multi-qubit gate to be naturally affected by a single gate operation without relying on the concatenation of multiple one- and two-qubit gates. Exploiting the symmetry of equilateral coupling distances between multiple qubits within a cell allows more than two entangled qubits to perform a gate operation at once, which would otherwise require more qubit gate operations involving only one- and two-qubit gates. Multi-qubit cells may include or may contain asymmetric 3D structures with complementary bases and caps arranged in alternating directions, such as top-bottom, left-right, or other opposing planes. This alternating arrangement of asymmetric 3D cells can allow for alternating arrangements of non-identical adjacent cell bases and caps, including their extended or overlapping electrode areas, resulting in optimal tiling and spacing of cells for a given size or area. A grid or array of multiple alternating directions of asymmetric cell structures can reduce one- and two-dimensional geometric problems, such as crowding of electrodes required to control each qubit within a gate, detrimentally increasing gate spacing, limited optical access, complex stray light management, and limited electrical connectivity. Qubits and cells may be inverted in alternating rows in a manner that allows for closer cell tiling and open cell-to-cell transmission line spacing for optical access, control, and readout.Symmetric or equilateral coupling geometries of multiple qubits per cell can enable more complex quantum gates to be performed in a single gate operation, further reducing the need for circuit depth, error correction, and interference mitigation. Interchangeable component cells can enable quantum FPGA (QFPGA) and quantum ASIC (QASIC) chips, which can be highly reconfigurable.

[0012] Certain embodiments of the QC systems described herein advantageously provide a three-dimensional (3D) layout of qubits and / or qubit gates, which facilitates the use of more qubits and / or qubit gates for a computation than can be accommodated using a one-dimensional (1D) or two-dimensional (2D) layout (see, e.g., J. I Chirac and P. Zoller, "A scalable quantum computer with ions in an array of microtraps," Nature, Vol. 404, p. 579 (2000); J. Chiaverini et al., Quant. Inf. Comp. Vol. 5, 419 (2005)). For example, certain embodiments described herein provide a 3D layout of qubit gates, each of which comprises multiple ions (e.g., four or more simultaneously entangled ions), while providing sufficient spacing and line-of-sight access angles to facilitate electrical coupling and optical paths for addressing, manipulation, control, readout, and potential sideband cooling of each qubit.

[0013] When a particular arrangement or set of qubits allows every qubit to be directly quantum mechanically entangled with every other qubit in the set, the qubits can be described as "fully coupled." Even a small number of qubits, including fully coupled ions in a one-dimensional (1D) linear ion trap, can exhibit significantly higher potential processing power than the same number of qubits simply coupled pairwise (see, e.g., N.M. Linke et al., "Experimental comparison of two quantum computing architectures," PNAS, Vol. 114, No. 13 (2017)).

[0014] Quantum computing (QC) designs demonstrated over the past two decades show that the parameter that most influences how quickly a quantum computer can outperform its classical counterpart is not simply based on how many qubits are coupled in some way. This is illustrated by the greater interest in circuit-model QC hardware, which often features more than 100 times fewer qubits than the number of qubits required by major quantum annealing approaches that do not perform single-gate operations. The demonstrated performance of such systems ultimately depends on the fidelity of the qubits (e.g., how accurately the system can perform gate operations), how the qubits are interconnected, and how much overhead is used to enable the qubits to work together to compute solutions to difficult problems.

[0015] A one-qubit gate simply entails the qubit switching itself from "0" to "1" or into a unique quantum superposition of "0" and "1." A two-qubit gate couples two qubits using superposition combined with quantum entanglement so that anything that happens to one of the qubits affects the other. In such a two-qubit gate, the target qubit can start in state "0" or state "1," or it can be from any superposition of "0" and "1" (e.g., halfway between "0" and "1"). For example, the function of a quantum controlled-NOT (CNOT) gate is to switch the target qubit if the control qubit is in state "1" and do nothing otherwise. One- or two-qubit gates can be directly implemented in many different quantum gate-type architectures. For more complex gate operations, implementations that can entangle more than two qubits at a time can significantly impact the total number of qubits, the steps performed to achieve the operation, and the algorithms that implement them (see, for example, C. Figgatt et al., "Parallel entangling operations on a universal ion-trap quantum computer," Nature, Vol. 571 (2019); Y. Lu et al., "Global entangling gates on arbitrary qubits," Nature, Vol. 571 (2019)). In some instances, a significant reduction in the number of qubits and steps used in advance can dramatically reduce the overhead required to achieve successful results. One example would be a prototype demonstration that could provide a solution to an otherwise intractable problem, even temporarily, without extensive error correction and with fewer ancillaries.

[0016] Certain embodiments described herein use multiple fully coupled high fidelity qubits. The advantage of certain such embodiments (e.g., how much more efficient a particular quantum gate operation can be compared to using a combination of one and two qubit gates) is that quantum triple controlled NOT (C) gates with four fully coupled high fidelity qubits are also advantageous. 3 This can be illustrated by considering the example of a NOT gate. 3 The NOT gate is also called a super-Toffoli gate. 3 In the example of a NOT gate, all three control qubits must be in a particular state (e.g., (1,1,1)) to switch a fourth target qubit from "1" to "0." When combined with one or more single-qubit gate operations, such multi-qubit quantum gates can be used to complete a universal set for quantum computation. Multiple-controlled NOT gates are described in references as generally including an extended series of one- and two-qubit gate operations (see, e.g., MA Nielsen and ILChuang, "Quantum Computing and Quantum Information," 1st ed. (Cambridge University Press, 2000)). How much further these one- and two-qubit gate series can be expanded in physical implementations depends on the types of qubits used and how many qubits can be fully coupled and entangled with one another. However, in the appropriate physical layout, a C gate implemented using four qubits that are fully coupled and simultaneously multiply entangled can be implemented. 3 The NOT gate is implemented with only one and two qubit gates. 3 It can be constructed with a much smaller number of quantum gate operations than those used in the NOT gate. This is due to the simpler C 2This can be implemented by starting from an extension of the method described for the implementation of the NOT Toffoli gate (see, for example, J.I. Cirac and P. Zoller, "Quantum Computations with Cold Trapped Ions," Phys. Rev. Lett. Vol. 74(20) (1995)) and subsequently demonstrated (see, for example, T. Monz et al., "Realization of the Quantum Toffoli gate with Trapped Ions," Phys. Rev. Lett. Vol. 102, 040501 (2009)). 2 The implementation of NOT has already shown a significant reduction in the number of contributing gates and the time required to complete all gate operations, while providing an improvement in net fidelity due to aggregate gate errors for concatenations of one- and two-qubit gates, even if they are individually very fidelity. This three-qubit gate can be realized in a linear trap without strong requirements for geometric symmetry. In contrast, certain embodiments described herein utilize the full 3D symmetry of the designs described herein to achieve C n In this way, the improved efficiency examples described above can be realized by reducing the number of quantum gates required to implement them. n The number of controls in a NOT gate can be greatly expanded. Other multi-control gate operations, including phase rotation, show similar improvements in efficiency using physical configurations involving more than two entangled qubits simultaneously. These prior improvements can significantly reduce error correction.

[0017] Even the highest quality qubits exhibit a significant error rate, which may be small per qubit but multiplied by the number of gates used to execute the algorithm. When the total error rate reaches a threshold where error correction is required to perform an operation with a sufficient chance of giving a reliable result even with a small set of quanta, the efficiency of the architecture quickly decreases in proportion to the amount of overhead used for error correction.

[0018] For small quantum computers with hundreds of relatively high-quality qubits intended to perform logical operations, the overhead of error-correction qubits plus ancillaries can represent an order of magnitude, or roughly a factor of ten, increase in the number of qubits, with a proportional decrease in efficiency. For larger systems, the overhead can increase by several orders of magnitude. However, in certain embodiments described herein, quantum computers that benefit from the overall efficiency of fully coupled high-quality qubits and employ multi-qubit gate operations (e.g., performed naturally by utilizing multidimensional geometries) can use significantly fewer steps and a significantly smaller total number of qubits. As used herein, the term "natural" gate operations indicates that the geometric layout allows for more than two qubits to be simultaneously involved. Certain natural multi-qubit gate embodiments described herein can advantageously execute algorithms without extensive error-correction overhead. Furthermore, the significant improvement in overall design efficiency due to the reduced overhead can be realized using orders of magnitude fewer quantum resources to execute basic quantum computing algorithms or subroutines, demonstrating increased speed and utility compared to classical computer systems.

[0019] To date, many QC systems using trapped ions employ one-dimensional (e.g., linear) traps that can then be electrically or photonically interconnected (see, e.g., U.S. Patent No. 9,858,531; Debnath et al., "Demonstration of a small programmable quantum computer with atomic qubits," Nature, Vol. 536, p. 63 (2016)). Such 1D traps allow linear chains of qubits to be fully coupled within a common potential well or trapping region. The scale of full connectivity is limited by how many qubits can be tethered together before the coupling forces between qubits at or near both ends of the linear chain become too weak to be used for reliable multi-qubit gate operations; thus, it may be desirable to create interconnections between multiple linear traps of limited length. For example, optical interconnections can be employed to transfer a qubit state from an ion to a photon and then send the photon to another linear trap where the quantum state has been transferred to another ion. One type of protocol commonly used for such processes is called "quantum teleportation." Such interconnections impose time delays and potential inefficiencies in the conversion (e.g., from a trapped ion qubit to a photon, and from a trapped ion qubit to a second trapped ion). Certain embodiments described herein advantageously provide alternative arrangements for simultaneously better optimizing direct qubit-to-qubit interactions than can be efficiently achieved using linear or 2D elements in conjunction with optical interconnections. When scaling to larger numbers of qubits, certain such embodiments may advantageously reduce or avoid the number of optical interconnections between nodes, along with their associated disadvantages (e.g., time delays, ion-to-photon conversion losses).

[0020] Rectangular two-dimensional (2D) grid arrangements have already been employed in some trapped ion approaches, as well as in superconducting qubit (SCQ) concepts. However, interactions between qubits have been limited to one- and two-qubit operations occurring within trapped ion grid lanes (e.g., by shuttling qubits in and out of lanes through intersections). Such approaches rely on significant redundancy to increase the degree of fault tolerance in order to raise the probability of successful algorithm execution to a usable level. For example, some approaches use global addressing of ensembles of qubits, where qubits are shuttled in and out of aligned intersections of the grid, redundantly producing a single one- or two-qubit operation among many qubits, which are then averaged to reduce errors. The overhead in such approaches, in terms of the number of redundant qubits required to produce a single logical operation with sufficient fidelity, increases exponentially with the scale of the logical operations performed by the quantum computer. Conversely, certain embodiments described herein, by having qubits arranged in two or more dimensions, enable entanglement between more than two qubits, thereby simultaneously participating and enabling multi-qubit gate operations to occur directly or spontaneously.

[0021] To distinguish certain embodiments described herein from other approaches that may appear similar in descriptive terminology and visual layout, it should be noted that the overall layout of a 2D periodic crystal structure, such as a triangular lattice Penning trap (e.g., the surface of an extended 2D crystal or a periodic electronic potential well in which ions may be arranged to form a triangular lattice, is useful for studying the physics of many-body interactions but not for implementing gate operations between multiple qubits), and the hexagonal Kitaev model may be similar to, but different from, some (e.g., single layer) of certain multilayer embodiments described herein (e.g., A. Kitaev, Ann. Phys. Vol. 321, 2 (2006); R. Schmied et al. New J. Phys. 13 115011 (2011) (“Schmied 2011). However, such 2D periodic crystal structures differ significantly in design complexity and purpose from certain embodiments described herein. For example, such crystal lattice structures have been designed solely for the simulation of quantum systems. Such structures are generally not intended to perform gate operations and may be used to create energy topologies that mimic those of modeled quantum systems (e.g., to find the lowest electronic energy configuration for a given molecule). In particular, quantum simulators with 2D hexagonal lattice ions (e.g., following the Kitaev model) may generally use fewer electrode structures than a “full-scale” quantum computer capable of quantum gate operations. Therefore, the geometry of the electrode structures of a quantum simulator is less affected by overall design constraints than the geometry of electrode structures for scalable gate-based quantum computing.

[0022] Nevertheless, the algorithms can be used to aid in the design (e.g., optimize) of electrode structures for trapping and holding individual ions in periodic lattices (e.g., for individual trapping regions within larger trapped ion architectures) for gate-model quantum computers (see, e.g., R. Schmied, et al., Phys Rev. Lett. 2009 ("Schmied 2009"). One general guideline for electrode structure design, taken from Schmied 2009, is that, assuming M traps (e.g., microtraps) per unit cell, the number of surface patch electrodes is typically at least 8M for fully controlled and effective gate operation.

[0023] Furthermore, crowding of surface electrodes can occur to control each ion in a 2D layer of trapped ions for gate operation. Such crowding can result in regions of eight or more surface electrodes providing complete control of the ion within its electronic potential well, limiting how close together ion trapping regions can be placed while still allowing a strong coupling for effective gate interaction. The binding strength is strongly dependent on the inter-ion distance (d), and the binding strength or exchange frequency Ω ex is the equation

number

[0024] Certain embodiments described herein advantageously facilitate solving other hardware challenges that arise exponentially when designing gate-model QC structures that scale up from 2D trapped ion lattices and may appear prohibitively difficult or infeasible. For example, certain embodiments described herein incorporate optical components (e.g., lasers, optical ports, fibers, detectors) into the QC structure to address, process, readout, and potential sideband cooling of each qubit, and provide line-of-sight access angles.

[0025] Certain embodiments described herein advantageously provide scalable hardware configurations that enable direct "writing" and execution of complex quantum algorithms by allowing simultaneous entanglement between an optimal number of adjacent qubits. In certain embodiments, multidimensional quantum gate implementations, similar to conventional firmware such as field programmable gate arrays (FPGAs), can be directly written and flexibly reprogrammed in the form of multi-qubit gates.

[0026] Certain embodiments described herein advantageously enable multiple controlled quantum gate operations to be naturally performed by utilizing multidimensional geometries. In certain embodiments, quantum gate operations are performed on a quantum firmware platform with a minimal number of steps (e.g., without using concatenation of one and two qubit gate operations to produce multiple controlled NOT operations).

[0027] Certain embodiments described herein advantageously provide a feasible engineering structure that enables an arbitrarily scalable quantum firmware platform to enable universal quantum computing by integrating electrical and optical transmission lines for full control and readout of each qubit within a circuit model architecture.

[0028] Certain embodiments described herein advantageously provide multi-layer quantum computing structures configured to allow an optimal number of qubits to be simultaneously entangled, potentially beyond nearest-neighbor, second-neighbor, and beyond. Certain such embodiments include electrical and optical access channels for addressing, controlling, and readout of qubits in scalable quantum processors. For example, arrays of fully connected qubits advantageously provide a more efficient and flexible option for implementing quantum algorithms in hardware than other designs in which entanglement gate operations are limited to specific pairs (e.g., by the type of qubits employed or their layout). This improved efficiency and flexibility can increase rapidly with the number of qubits in the array.

[0029] Certain embodiments described herein can advantageously perform gate operations involving more than two qubits at a time, thereby providing significant efficiency improvements over conventional designs limited to one- and two-qubit gates (e.g., by replacing tens of such gates with a single four-qubit gate). Certain embodiments described herein advantageously overcome the connectivity limitations found in one- and two-dimensional geometries using trapped ions. For example, arranging qubits in multi-qubit arrays (e.g., multi-planar and / or linear qubit arrays) with direct connectivity (e.g., entanglement) between qubit arrays can solve the significant time delay and inefficiency of converting ion qubits to photon qubits and back again as we continue to scale up from tens of ions in 1D chains. Furthermore, arrays of qubits in multiple planes can solve problems arising from crowding of electrodes to control each qubit in a gate, which would otherwise significantly increase gate spacing. In another example, selectively inverting the electron potential well between opposing surfaces may allow a maximum number of adjacent qubits to participate in a gate operation.

[0030] Certain embodiments described herein advantageously utilize a first set of trapped ions above a first surface and a second set of trapped ions below a second surface, the second surface facing the first surface, such that at least some of the second set of ions are entangled with at least some of the first set of ions. By merging and interleaving the first and second sets of trapped ions, and by adjusting the trapping height of the central ion of the qubit gate relative to the apex ions of the qubit gate, certain embodiments advantageously produce multidimensional entanglement shapes similar to complex 3D crystal structures (e.g., pyrochlore). Furthermore, the space between the first and second surfaces of certain embodiments advantageously provides optical access from the side for global or local addressing of the qubit, as well as optical access for readout by a detector. Multi-ion qubit gates (e.g., cells) can be constructed asymmetrically, whereby each cell's cap (e.g., either up- or down-facing) provides additional space for integrating optics and electronics used to initialize, process, and readout qubits, individually or collectively. For example, rows of these multi-ion qubit gates (e.g., cells) can be interleaved, alternating "up" and "down" cell orientations to form transmission paths that provide additional multi-angle optical access and electronic control lines between rows of cells. Because gravity is not the dominant force with respect to the trapped ions, the overall arrangement can be oriented at any angle (e.g., tilted 90 degrees, with "up" and "down" replaced by "left" and "right"). For other types of qubits, this general insensitivity to the orientation of trapped ions may not apply to the same extent, and other types of qubits may limit the choice of orientation. <Example>

[0031] Certain embodiments described herein utilize multidimensional cells of qubits that may resemble 3D crystalline structures (e.g., pyrochlore). In certain embodiments, inverting the cells in alternating rows allows for closer tiling of cells and spacing for optical access, control, and readout. Certain embodiments utilize a large number of qubits per gate, advantageously reducing (e.g., minimizing) circuit depth, error correction, and interference mitigation. Certain embodiments utilize interchangeable component cells, which may advantageously enable quantum FPGA (QFPGA) and quantum ASIC (QASIC) chips.

[0032] While the physical structure of certain embodiments is described herein using high-fidelity trapped ion qubits (e.g., with low error rates), any type of qubit (e.g., naturally occurring, artificially formed) that can be entangled with multiple other qubits simultaneously in multiple dimensions can be used in accordance with certain embodiments described herein. Examples of qubits compatible with certain embodiments described herein include, but are not limited to, subatomic particles, neutral atoms, ions, neutral molecules, charged molecules, Bose-Einstein condensates, electrons, electron holes, excitons, magnetic qubits, nitrogen-vacancy centers in diamond, phonons, photons, quantum dots, Rydberg atoms, spins in silicon, and, in some cases, superconducting qubits. In certain embodiments, the qubits are suitable for directly (e.g., naturally) generating gate operations between more than two qubits in certain configurations. For example, the physical architecture of certain embodiments can advantageously directly yield complex gate operations such as multiple controlled-NOT or phase rotation without using a serial concatenation of one- and two-qubit gates.

[0033] The trapped ion qubits utilized in certain embodiments described herein exhibit optimized quantum interaction properties. Relevant figures of merit exhibited by trapped ions include, but are not limited to, (i) the fact that they are identical within a given species and therefore extensive calibration or tuning can be advantageously avoided, (ii) the ability to form qubits with exceptional long-term stability, and (iii) sustained and demonstrated high-fidelity gate operation compared to competing qubit technologies. In certain embodiments described herein, simultaneous multi-qubit gate operation can be achieved by ions arranged in a 3D geometric layout of multiple identical, fully coupled qubits.

[0034] 1A-1C and 2A-2D schematically illustrate various aspects of an example multi-qubit gate (e.g., cell) according to certain embodiments described herein. The qubit gate is formed by interspersing electron potential wells both above and below parallel surface planes and using the electron potential wells to trap ions that are entangled with other trapped ions. Examples of ions compatible with certain embodiments described herein include, but are not limited to, Ba. + , Be + , Cd + , Ca + , Mg + , Hg + , Sr + , Yb + The vertical direction is not required, hence "top" and "bottom" are not used.

[0035] 1A schematically illustrates side and top views of an example single-ion portion 10 of an example four-ion qubit gate 100 according to certain embodiments described herein. The single-ion portion 10 includes a generally planar substrate region 12, one or more electrical traces 14, an electrode region 16 including one or more electrodes (not shown), an electron potential well 17, and a single ion 18. In certain embodiments, the substrate region 12 includes a portion of an electrical insulator and / or semiconductor (e.g., silicon oxide, silicon) chip, and at least some of the electrical traces 14 are in electrical communication with electrodes in the electrode region 16. At least some of the other electrical traces 14 may be in electrical communication with electrodes in the electrode region of another adjacent qubit portion. For example, the electrical traces 14 and the electrodes in the electrode region 16 may be composed of a conductive material (e.g., aluminum, copper, gold) deposited on the surface of the substrate region 12 and may include at least one hermetic coating configured to seal the conductive material from contaminants and / or corrosion. The electrodes of electrode region 16 are configured to create an electron potential well 17 configured to contain (e.g., suspend or trap) a single ion 18 at a location spaced from planar substrate region 12 (e.g., in a direction generally perpendicular to substrate region 12).

[0036] 1B schematically illustrates side and top views of an example three-ion portion 30 of an example four-ion qubit gate 100, according to certain embodiments described herein. The three-ion portion 30 includes a generally planar substrate region 32, one or more electrical traces (not shown), an electrode region 36 including a plurality of electrodes (not shown), three electron potential wells 37a-c, and three ions 38a-c. In certain embodiments, the substrate region 32 includes a portion of an electrical insulator and / or semiconductor (e.g., silicon oxide, silicon) chip, and at least some of the electrical traces are in electrical communication with electrodes in the electrode region 36. At least some of the other electrical traces may be in electrical communication with electrodes in electrode regions of other portions of adjacent qubits. For example, the electrical traces and the electrodes in the electrode region 36 may include a conductive material (e.g., aluminum, copper, gold) deposited on the surface of the substrate region 32 and may include at least one hermetic coating configured to seal the conductive material from contaminants and / or corrosion. In certain embodiments, electrical traces 14 in electrical communication with electrodes in region 36 or other electrode regions may reside in a substrate layer (not shown) below the surface (e.g., subsurface) and may run generally coincident with other electrical traces 14 on the surface. The electrodes in electrode region 36 are configured to create three electron potential wells 37a-c, each configured to contain (e.g., suspend or trap) a corresponding one of three ions 38a-c at a location spaced apart from the planar substrate region 32 (e.g., in a direction generally perpendicular to the substrate region 32). In certain embodiments, the three ions 38a-c form an equilateral triangle (e.g., spaced apart from each other by a distance ranging from 30 microns to 40 microns) such that the triangle is generally parallel to the substrate region 32. The three ions 38a-c in the triangle are an example of three qubits arranged in a generally planar region and configured to interact, according to certain embodiments described herein.

[0037] In certain embodiments, as shown in FIGS. 1A-1B, substrate region 12 of single-ion portion 10 and substrate region 32 of three-ion portion 30 (e.g., the portions of the respective chips that generally correspond to four-ion qubit gate 100) have a generally hexagonal shape, while in certain other embodiments, substrate regions 12, 32 have other shapes (e.g., rectangular, square, triangular, circular, elliptical, geometric, non-geometric, symmetric, asymmetric).

[0038] The hatched areas in Figures 1A and 1B corresponding to electrode regions 16, 36 (e.g., electrode patch regions) indicate general "trapping" zones positioned and shaped to accommodate multiple individual electrodes within each zone to create electron potential wells 17, 37a-c for confining corresponding ions 18, 38a-c. The positioning and shaping of the various electrodes for a particular configurable gate embodiment can be designed using algorithms (e.g., as provided by Schmied 2009). In certain embodiments, electrode regions 16, 36 are configured to trap, fully control, and perform gate operations with corresponding ions 18, 38a-c. For example, electrode region 36 in Figure 1B can include eight or more electrodes per ion trapping zone. In certain embodiments, the electrodes and electrode regions 16, 36 are based on electrodes and electrode regions already developed for 2D layout of trapped ions (see, e.g., C.W. Hogle et al., "Characterization of Microfabricated Surface Ion Traps," Sandia National Lab., SAND2017-6113C (2017)).

[0039] 1C schematically illustrates side and top views of an example four-ion qubit gate 100 having the single-ion portion 10 of FIG. 1A (e.g., as the “cap” of the four-ion qubit gate 100) and the three-ion portion 30 of FIG. 1B (e.g., as the “base” of the four-ion qubit gate 100), along with ions 18, 38a-c configured to be fully coupled to each other and / or to ions of adjacent qubit gates (e.g., simultaneously or in any subset combination), according to certain embodiments described herein. The example four-ion qubit gate 100 of FIG. 1A has a generally hexagonal shape, while in certain other embodiments, the qubit gate 100 has other shapes (e.g., rectangular, square, triangular, circular, elliptical, geometric, non-geometric, symmetric, asymmetric). In certain embodiments, the qubit gate 100 has a width W (e.g., in the range of 0.2 mm or less). While the right side of FIG. 1C shows at least some of the electrical traces 14 on the surface of portion 30, in certain embodiments, at least some of the electrical traces 14 may be in a substrate layer (not shown) below the surface (e.g., subsurface) and run generally coincident with other electrical traces 14 on the surface. In certain embodiments, substrate region 12 is generally parallel to substrate region 32, and substrate region 12 is spaced from substrate region 32 by a distance S (e.g., in the range of 0.2 mm or less). In certain embodiments, a single ion 18 is spaced from each of three ions 38a-c (e.g., by a distance in the range of 30 microns to 45 microns) and positioned above the center of the triangle formed by the three ions 38a-c. Each of the ions 18, 38a-c is entangled with each of the other ions 18, 38a-c, as indicated by the dashed lines in FIG. 1C. In certain embodiments, the example four-ion qubit gate 100 has a width W (e.g., in the range of 0.2 mm or less).The three ions 38a-c are examples of three qubits located in a first substantially planar region (e.g., the three ions 38a-c may be within ±5 microns, ±2 microns, and / or ±1 micron of one another from the substrate region 32), and the single ion 18 is an example of a qubit located in a second substantially planar region that is substantially parallel to the first substantially planar region. The qubits in the second substantially planar region are configured to interact with the three qubits in the first substantially planar region that are configured to interact, according to certain embodiments described herein.

[0040] In one particular embodiment, the example four-ion qubit gate 100 of FIG. 1C is a “natural” C 3 as a NOT gate (e.g., a triple-controlled NOT gate) and / or as a "natural" C 3 φ gate (e.g., a triple-controlled phase gate). The example four-ion qubit gate 100 of a particular embodiment uses significantly fewer gate operations than would be used by only one or two qubit gates. 3 NOT / C 3 In certain embodiments, the four-ion qubit gate 100 does not aggregate the errors of many successive operations to obtain its result, and therefore the natural C 3 NOT / C 3 The net fidelity of the φ gate is much higher than that of a C gate containing many two-qubit gates, which may have much higher individual gate fidelity. 3 NOT / C 3 In one particular such embodiment, the C provided by the example four-ion qubit gate 100 3 NOT / C 3 The φ gate is a C gate containing many two-qubit gates. 3 NOT / C 3 Using a small fraction of the steps of the φ gate, the C provided by the example four-ion qubit gate 100 3 NOT / C 3The φ-gate is faster and less error-prone (e.g., it uses significantly less error correction at the start), as can be seen in the comparison of the probability of successful gating using both structure and fidelity estimates.

[0041] 2A schematically illustrates a side view of an example seven-ion qubit gate 200 in accordance with certain embodiments described herein. In certain embodiments, the example seven-ion qubit gate 200 of FIG. 2A is a gate of natural C 6 NOT / C 62A includes the single-ion portion 10 of FIG. 1A (e.g., as the "cap" of the seven-ion qubit gate 200) and the six-ion portion 50 (e.g., as the "base" of the seven-ion qubit gate 200). The six-ion portion 50 includes a planar substrate region 52, one or more electrical traces (not shown), six electrode regions 56a-f, six electron potential wells 57a-f, and six ions 58a-f. The electrodes of the electrode regions 56a-f are configured to create six electron potential wells 57a-f, each of which is configured to contain (e.g., suspend or trap) a corresponding one of the six ions 58a-f at a location spaced apart from the planar substrate region 52 (e.g., in a direction generally perpendicular to the substrate region 52). As shown schematically in FIG. 2A , an example seven-ion qubit gate 200 may have an additional electrode 59 (e.g., a cover electrode) positioned below the single ion 18 of the single-ion portion 10 and configured to assist in tuning the distance of the single ion 18 relative to the six-ion portion 50 (see, e.g., C.E. Pearson et al., Phys. Rev. A Vol. 73, 032307 (2006)). In a particular embodiment, the six ions 58a-f form an equilateral hexagon (e.g., spaced apart by a distance ranging from 35 microns to 70 microns), with the hexagon being substantially parallel to the substrate region 52. The spacing between the hexagons may be set based on various parameters, including, but not limited to, tuning parameters, the type of ions, and the angle of the crystal lattice formed. In a particular embodiment, the distance from the substrate of the nearest neighbor of each qubit in the hexagon may have variability (e.g., a nominal distance of 40 microns ±5 microns) depending on the 3D angle in the crystal lattice. The seven ions 18, 58a-f are configured to be fully coupled to each other and / or to the ions of adjacent qubit gates (e.g., simultaneously or in any subset combination), as shown schematically by the dotted lines indicating entanglement between the seven ions 18, 58a-f.2A , in certain embodiments, portions of electrode regions 56a-f of six-ion portion 50 extend over the substrate region of the base of an adjacent qubit, and portions of the electrode regions of the adjacent portions extend over substrate region 12 of single-ion portion 10. Six ions 58a-f are examples of six qubits generally disposed in a first generally planar region (e.g., the distances of six ions 58a-f from substrate portion 52 may be within ±5 microns, ±2 microns, and / or ±1 micron of one another), and single ion 18 is an example of one qubit disposed in a second generally planar region generally parallel to the first generally planar region. The qubit in the second generally planar region is configured to interact with the six qubits in the first generally planar region that are configured to interact according to certain embodiments described herein.

[0042] In certain embodiments, a single ion 18 is contained (e.g., suspended or trapped) in a first electronic potential well 17, where the single ion 18 is contained at a first distance (e.g., 40 microns) from the electrode region 16. In certain other embodiments, the single ion 18 is contained in a second electronic potential well, where the single ion 18 is contained at a second distance (e.g., 80 microns) from the substrate region 52, where the second distance is approximately twice the first distance. For example, the second electronic potential well can be formed naturally (see, e.g., M. Mielenz et al., "Arrays of individually controlled ions suitable for two-dimensional quantum simulations," Nature Communications, 7:11839 (2016)). In certain embodiments, the first electron potential well 17 and the second electron potential well coincide or overlap with one another such that a single ion 18 is contained in both the first and second electron potential wells simultaneously, while in certain other embodiments, the first and second electron potential wells are separate from one another.

[0043] 2B is a schematic diagram illustrating a side view and a top view of an example eight-ion qubit gate 300 in accordance with certain embodiments described herein. In certain embodiments, the example eight-ion qubit gate 300 of FIG. 7 NOT / C 71A (e.g., as the "cap" of the eight-ion qubit gate 300) and a seven-ion portion 70 (e.g., as the "base" of the eight-ion qubit gate 300). The seven-ion portion 70 includes a planar substrate region 72, one or more electrical traces (not shown), seven electrode regions 76a-g, seven electron potential wells 77a-g, and seven ions 78a-g. The electrodes of the electrode regions 76a-g are configured to create seven electron potential wells 77a-g, each of which is configured to contain (e.g., suspend or trap) a corresponding one of the seven ions 78a-g at a location spaced apart from the planar substrate region 72 (e.g., in a direction generally perpendicular to the substrate region 72). The eight-ion qubit 300 example of FIG. 2B is similar to the seven-ion qubit gate 200 of FIG. 2A with the addition of an eighth electrode region 76g, an eighth electron potential well 77g, and an eighth ion 78g (e.g., positioned 30 to 60 microns above electrode region 76g). The distance of the eighth ion 78g from the substrate region 72 can be based on various factors, including, but not limited to, whether the seven-ion portion 70 is combined with a single-ion portion 10, a three-ion portion 30, or another multi-ion portion described herein. The eight ions 18, 78a-g, are configured to be fully coupled with each other and / or with ions of adjacent qubit gates (e.g., simultaneously or in any subset combination). (The dotted lines indicating entanglement between the eight ions 18, 78a-g are omitted in FIG. 2B for clarity.) The six ions 78a-f are examples of six quantum bits that are generally disposed in a first generally planar region (e.g., the distances of the six ions 78a-f from the substrate portion 72 may be within ±5 microns, ±2 microns, and / or ±1 micron of each other), the seventh ion 78g is an example of one quantum bit that is disposed in a second generally planar region that is generally parallel to the first generally planar region, and the single ion 18 is an example of one quantum bit that is disposed in a third generally planar region that is generally parallel to the first generally planar region.The qubits in the second generally planar region and the qubits in the third generally planar region are configured to interact with each other and with the six qubits in the first generally planar region that are configured to interact, according to certain embodiments described herein.

[0044] 2A and 2B, in certain embodiments, each of the qubit gates 200, 300 has a generally hexagonal shape, while in certain other embodiments, the qubit gates 200, 300 have other (e.g., rectangular, square, triangular, circular, elliptical, geometric, non-geometric, symmetric, asymmetric) shapes. In certain embodiments, the substrate regions 52, 72 comprise portions of an electrically insulating and / or semiconductor (e.g., silicon oxide, silicon) chip, with at least some of the electrical traces in electrical communication with the electrodes of the electrode regions 56, 76 and other electrical traces in electrical communication with the electrode regions of the other base. In certain embodiments, each of the electrode regions 56, 76 includes one or more electrodes in electrical communication with at least some of the electrical traces, and the electrical traces and electrodes in the electrode regions 56, 76 may include a conductive material (e.g., aluminum, copper, gold) deposited on the surface of the substrate region 52, 72 and may include at least one hermetic coating configured to seal the conductive material from contaminants and / or corrosion. The electrodes of the electrode regions 56, 76 in certain embodiments extend at least partially into adjacent regions (e.g., regions of adjacent qubits) to provide space for the qubit gates 200, 300 and / or electrical traces that run to the electrode regions of adjacent qubits. In certain embodiments, the 7-ion qubit gate 200 and / or the 8-ion qubit gate 300 have a width W (e.g., in the range of 0.2 mm or less), the substrate region 12 is substantially parallel to the substrate region 52, 72, and the substrate region 12 is spaced a distance S (e.g., in the range of 0.2 mm or less) from the substrate region 52, 57.

[0045] 2C schematically illustrates a side view of an example nine-ion qubit gate 400 in accordance with certain embodiments described herein. In certain embodiments, the nine-ion qubit gate 400 may facilitate cross-chip connectivity (e.g., in QFPGA or QASIC architectures). In certain embodiments, the example nine-ion qubit gate 400 of FIG. 2C may also be configured for use in multiple control gate operations or to employ redundant control combinations and / or target qubits to facilitate self-error-correcting gates at desired nodes. The example nine-ion qubit gate 400 of FIG. 2C includes the six-ion portion 50 of FIG. 2A (e.g., as the "cap" of the nine-ion qubit gate 400) and the three-ion portion 30 (e.g., as the "base" of the nine-ion qubit gate 400). The nine ions 38a-c, 58a-f are configured to be fully coupled (e.g., simultaneously or in any subset combination) with each other and / or with ions of adjacent qubit gates (the dotted lines indicating entanglement between the nine ions 38a-c, 58a-f are omitted from FIG. 2C for clarity). Six ions 58a-f are examples of six qubits generally disposed in a first substantially planar region (e.g., the six ions 58a-f may be within ±5 microns, ±2 microns, and / or ±1 micron of each other from substrate portion 52), and three ions 38a-c are examples of three qubits generally disposed in a second substantially planar region generally parallel to the first substantially planar region (e.g., the three ions 38a-c may be within ±5 microns, ±2 microns, and / or ±1 micron of each other from substrate portion 32). According to certain embodiments described herein, the six qubits 58a-f in the first generally planar region are configured to interact, and the three qubits 38a-c in the second generally planar region are configured to interact with each other and with the qubits in the first generally planar region.In certain embodiments, the three ions 38a-c and / or the six ions 58a-f are further configured to interact (e.g., inter-cell interactions) with ions of other qubit gates adjacent to the nine-ion qubit gate 400.

[0046] 2D schematically illustrates a side view of an example 10-ion qubit gate 450 in accordance with certain embodiments described herein. In certain embodiments, the 10-ion qubit gate 450 may facilitate cross-chip connectivity (e.g., in a QFPGA or QASIC architecture). In certain embodiments, the example 10-ion qubit gate 450 of FIG. 2D may also be used in conjunction with a C 9 NOT / C 9φ gate) or to facilitate self-error-correcting gates at desired nodes. The example 10-ion qubit gate 450 of FIG. 2D has the 7-ion portion 70 of FIG. 2B (e.g., as the "cap" of the 10-ion qubit gate 450) and the 3-ion portion 30 (e.g., as the "base" of the 10-ion qubit gate 450). The 10 ions 38a-c, 78a-g are configured to be fully coupled (e.g., simultaneously or in any subset combination) with each other and / or with ions of adjacent qubit gates (the dotted lines indicating entanglement between the nine ions 38a-c, 78a-g are omitted in FIG. 2D for clarity). Six ions 78a-f are examples of six quantum bits that are positioned approximately in a first substantially planar region (e.g., the distances of the six ions 78a-f from the substrate portion 72 may be within ±5 microns, ±2 microns, and / or ±1 micron of each other), the seventh ion 78g is an example of one quantum bit that is positioned in a second substantially planar region that is substantially parallel to the first substantially planar region, and three ions 38a-c are examples of three quantum bits that are positioned in a third substantially planar region that is substantially parallel to the first substantially planar region (e.g., the distances of the three ions 38a-c from the substrate portion 32 may be within ±5 microns, ±2 microns, and / or ±1 micron of each other). According to certain embodiments described herein, the six qubits 78a-f in the first generally planar region are configured to interact, the three qubits 38a-c in the third generally planar region are configured to interact with each other and with the qubits in the first generally planar region, and the single qubit in the second generally planar region is configured to interact with the qubit in the first generally planar region and with the qubit in the second generally planar region. In certain embodiments, the three ions 38a-c and / or the seven ions 78a-g are further configured to interact (e.g., inter-cell interactions) with ions in other qubit gates adjacent to the 10-ion qubit gate 450.

[0047] 2E schematically illustrates two side views of an example 13-ion qubit gate 500 (e.g., a "pyrochlore" cell) according to certain embodiments described herein. In certain embodiments, the example 13-ion qubit gate 500 of FIG. 2E is a C 12 NOT / C 122B (e.g., as the "cap" of the 13-ion qubit gate 500), has an increased length of electron potential well 77g and a corresponding distance from electrode region 76g of ions 78g, and has a 6-ion portion 50 (e.g., as the "base" of the 13-ion qubit gate 500). The 13 ions 58a-f, 78a-g are configured to be fully coupled (e.g., simultaneously or in any subset combination) with each other and / or with ions of adjacent qubit gates (dotted lines indicating entanglement between the 13 ions 58a-f, 78a-g are omitted in FIG. 2E for clarity). The six ions 58a-f are examples of six qubits located approximately in a first substantially planar region 502 (e.g., the six ions 58a-f may be located within ±5 microns, ±2 microns, and / or ±1 micron of each other at a distance H1 of about 40 microns from the substrate portion 52), the six ions 78a-f are examples of six qubits located approximately in a second substantially planar region 504 that is substantially parallel to the first substantially planar region 502 (e.g., the six ions 78a-f may be located within ±5 microns, ±2 microns, and / or ±1 micron of each other at a distance H1 of about 40 microns from the substrate portion 72), and the single ion 18 is an example of one qubit located in a third substantially planar region 506 that is substantially parallel to the first substantially planar region 502 (e.g., at a distance H2 in the range of 50 microns to 60 microns from the substrate portion 72). According to certain embodiments described herein, the six qubits in the first generally planar region 502 are configured to interact, the six qubits in the second generally planar region 504 are configured to interact with each other and with the six qubits in the first generally planar region 502, and the qubits in the third generally planar region 506 are configured to interact with the qubits in the first generally planar region 502 and the qubits in the second generally planar region 504.In certain embodiments, the six ions 58a-f and / or the seven ions 78a-g are further configured to interact (e.g., inter-cell interactions) with ions of other qubit gates adjacent to the 13-ion qubit gate 500.

[0048] 2F schematically illustrates two side views of an example 14-ion qubit gate 550 in accordance with certain embodiments described herein. In certain embodiments, the example 14-ion qubit gate 550 of FIG. 2F is a C 13 NOT / C 13 2F includes a first seven-ion portion 70 (see, e.g., FIG. 2B ) (e.g., as a “cap” of the 14-ion qubit gate 550), where the ions 78g and electron potential well 77g of the first seven-ion portion 70 are positioned at a greater distance from the substrate portion 72 than the ions 78g and electron potential well 77g of FIG. 2B . The example 14-ion qubit gate 550 of FIG. 2F also includes a second seven-ion portion 70 (see, e.g., FIG. 2B ) (e.g., as a “base” of the 14-ion gate qubit gate 550), where the ions 78g and electron potential well 77g of the second seven-ion portion 70 are positioned at a shorter distance from the substrate portion 72 than the ions 78g and electron potential well 77g of FIG. 2B . The first set of ions 78a-g of the first seven-ion portion 70 and the second set of ions 78a-g of the second seven-ion portion 70 are configured to be fully coupled (e.g., simultaneously or in any subset combination) with each other and / or with the ions of adjacent qubit gates (dotted lines indicating entanglement between the first set of ions 78a-g and the second set of ions 78a-g are omitted in FIG. 2F for clarity).

[0049] The six "base" ions 78a-f are exemplary six qubits generally disposed in a first generally planar region 552 (e.g., the six ions 78a-f may be spaced within ±5 microns, ±2 microns, and / or ±1 micron from the substrate portion 72 at a distance H1 of about 40 microns from the substrate portion 72), and the six "cap" ions 78a-f are exemplary six qubits generally disposed in a second generally planar region 554 that is generally parallel to the first generally planar region 552 (e.g., the six ions 78a-f may be spaced within ±5 microns, ±2 microns, and / or ±1 micron from the substrate portion 72 at a distance H1 of about 40 microns from the substrate portion 72). ion 78g above the base is an example of one qubit located in a third substantially planar region 556 that is generally parallel to the first substantially planar region 552 (e.g., at a distance H2 in the range of 30 microns to 40 microns from substrate portion 72), and one ion 78g below the cap is an example of one qubit located in a fourth substantially planar region 558 that is generally parallel to the second substantially planar region 554 (e.g., at a distance H3 in the range of 50 microns to 60 microns from substrate portion 72). The qubits in the first substantially planar region 552 are configured to interact, and the qubits in the second substantially planar region 554 are configured to interact with each other and with the qubits in the first substantially planar region 552. The qubit in third generally planar region 556 is configured to interact with the qubit in first generally planar region 552 and the qubit in second generally planar region 554. According to certain embodiments described herein, the qubit in fourth generally planar region 558 is configured to interact with the qubit in first generally planar region 552, the qubit in second generally planar region 554, and the qubit in third generally planar region 556. In certain embodiments, first set of ions 78a-g and / or second set of ions 78a-g are further configured to interact (e.g., inter-cell) with ions of other qubit gates adjacent to 14-ion qubit gate 550.

[0050] The examples provided, for ease of discussion, correspond to structures configured to be employed in subsequent multi-qubit gate array embodiments (such as QFPGA or QASIC embodiments). Other cell combinations of "cap" and "base" are also compatible with certain embodiments described herein. For example, in a QASIC embodiment, the C ion portion 70 of FIG. 2B may be combined with the C ion portion 70 of FIG. 2F, modified by increasing or decreasing the length of electron potential well 77g and the associated distance of ions 78g from electrode region 76g, as described above. 13 NOT / C 13 It may be advantageous to create a 14-ion qubit gate that can be used with up to a φ gate. Furthermore, these and other numbers of qubits (e.g., 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or more qubits) per first portion 810 and / or second portion 820 are compatible with certain embodiments described herein.

[0051] Certain embodiments described herein provide a quantum computing (QC) system 1000 comprising a substantially planar first substrate 600 and a substantially planar second substrate 700, wherein the first substrate 600 and the second substrate 700 are substantially parallel to one another. The quantum computing system 1000 further comprises a multi-qubit gate array 800 having a plurality of multi-qubit gates 802 positioned in a region between the first substrate 600 and the second substrate 700. Each multi-qubit gate 802 in the array 800 comprises a first portion 810 (e.g., base) on a surface of the first substrate 600 (e.g., above, below, on top) and a second portion 820 (e.g., cap) on a surface of the second substrate 700 (e.g., above, below, on top), wherein the qubits interact between the surfaces of the first and second substrates 600, 700. A first portion 810 of each multi-qubit gate 802 in array 800 is selected from the group consisting of single qubit portion 10, three qubit portion 30, six qubit portion 50, and seven qubit portion 70. First portion 810 is disposed along the surface of first substrate 600 (e.g., substrate regions 12, 32, 52, 72 of single qubit portion 10, three qubit portion 30, six qubit portion 50, and seven qubit portion 70 are regions of first substrate 600). A second portion 820 of each multi-qubit gate 802 in array 800 is selected from the group consisting of single qubit portion 10, three qubit portion 30, six qubit portion 50, and seven qubit portion 70. Second portion 820 is disposed along a surface of second substrate 700 (e.g., substrate regions 12, 32, 52, 72 of single qubit portion 10, three qubit portion 30, six qubit portion 50 and seven qubit portion 70 are regions of second substrate 700). In each multi-qubit gate 802, a qubit in each of first portion 810 and second portion 820 of multi-qubit gate 802 is configured to be quantum mechanically entangled with another qubit in first portion 810 and second portion 820 of multi-qubit gate 802, respectively.

[0052] 3A schematically illustrates a top view of an example of four first portions 810 (e.g., bases) of an example array 800 having four multi-ion qubit gates (e.g., cells) 802, according to certain embodiments described herein. The four first portions 810 in FIG. 3A include a single-ion portion 10, a three-ion portion 30, a six-ion portion 50, and a seven-ion portion 70. These four first portions 810 are tiled with their respective substrate regions 12, 32, 52, and 72 that are part of a common first substrate 600 (e.g., substrate regions 12, 32, 52, and 72 are coplanar with one another on the surface of the first substrate 600). The tiling includes a diamond-shaped region 830 surrounded by the four first portions 810. As shown in FIG. 3A , at least some of the electrode areas (e.g., electrode areas 56 a-f, 76 a-f) of the six-ion portion 50 and the seven-ion portion 70 extend into adjacent first portions 810 and / or diamond-shaped regions 830. In certain embodiments, adjacent rows of first portions 810 are configured to facilitate tight tiling of the first portions 810 (e.g., without electrode areas overlapping one another). While FIG. 3A shows the first portions 810 in a generally rectangular pattern, the first portions 810 of other embodiments may be in a generally hexagonal pattern or a generally diagonal pattern. Furthermore, while the first portions 810 in FIG. 3A are shown schematically as a 2×2 array, other tiling combinations of arrays of two, three, or more portions are also compatible with certain embodiments described herein. For example, first portion 810 may be tiled in an array in linear (e.g., 1x2, 1x3, or larger), square or rectangular (e.g., 2x3, 3x3, 2x4, 3x4, 4x4, 2x5, etc.) shapes, and other geometric shapes that may be regular or irregular (e.g., similar to domino tiling), and / or symmetrical or asymmetrical.

[0053] 3B schematically illustrates a top view of an example array 800 and four example second portions 820 (e.g., caps) of four example multi-ion qubit gates 802, according to certain embodiments described herein. The four second portions 820 in FIG. 3B include a single-ion portion 10, a three-ion portion 30, a six-ion portion 50, and a seven-ion portion 70. These four second portions 820 are tiled with their respective substrate regions 12, 32, 52, and 72 that are part of a common second substrate 700 (e.g., the substrate regions 12, 32, 52, and 72 are coplanar with one another on the surface of the second substrate 700). The tiling includes a diamond-shaped region 840 surrounded by the four first portions 820. As shown in FIG. 3B , at least some of the electrode areas (e.g., electrode areas 56 a-f, 76 a-f) of the six-ion portion 50 and the seven-ion portion 70 extend into adjacent second portions 820 and / or diamond-shaped regions 840. In certain embodiments, adjacent rows of second portions 820 are configured to facilitate tight tiling of the second portions 820 (e.g., without electrode areas overlapping one another). While FIG. 3B shows the second portions 820 in a generally rectangular pattern, the second portions 820 of other embodiments may be in a generally hexagonal pattern or a generally diagonal pattern. Furthermore, while the second portions 820 in FIG. 3B are shown schematically as a 2×2 array, other tiling combinations of arrays of two, three, or more portions are also compatible with certain embodiments described herein. For example, second portion 820 may be tiled in an array in linear (e.g., 1x2, 1x3, or larger), square or rectangular (e.g., 2x3, 3x3, 2x4, 3x4, 4x4, 2x5, etc.) shapes, and other geometric shapes that may be regular or irregular (e.g., similar to domino tiling), and / or symmetrical or asymmetrical.

[0054] 3C-3D schematically illustrate exploded and top-down views, respectively, of the example array 800 and four multi-ion qubit gates 802 of FIGS. 3A-3B , according to certain embodiments described herein. The four multi-ion qubit gates 802 include two four-ion qubit gates 100 and two thirteen-ion qubit gates 500 between a first substrate 600 and a second substrate 700. One of the four-ion qubit gates 100 has a three-ion base portion 30 and a single-ion cap portion 10; another four-ion qubit gate 100 has a single-ion base portion 10 and a three-ion cap portion 30; one of the thirteen-ion qubit gates 500 has a seven-ion base portion 70 and a six-ion cap portion 50; and another thirteen-ion qubit gate 500 has a six-ion base portion 50 and a seven-ion cap portion 70. Other tiling combinations of bases and caps into a 3D gate cell layout may be used, as described herein with respect to FIGS. 3A and 3B .

[0055] FIG. 3E schematically illustrates an exploded view of another example array 800 having four multi-ion qubit gates 802, according to certain embodiments described herein. The four multi-ion qubit gates 802 include four 10-ion qubit gates 450 between a first substrate 600 and a second substrate 700. Two of the 10-ion qubit gates 450 each have a 3-ion base portion 30 and a 7-ion cap portion 70, while the other two 10-ion qubit gates 450 each have a 7-ion base portion 70 and a 3-ion cap portion 30. In the 2×2 array on substrate 600, the 3-ion base portions 30 and the 7-ion base portions 70 alternate with each other, and in the 2×2 array on substrate 700, the 7-ion cap portions 70 and the 3-ion cap portions alternate with each other. The layout of the electrical trace lines shown in FIG. 3E differs from that of FIGS. 3C-3D.

[0056] 4A-4B schematically illustrate exploded and top-down views, respectively, of an example array 900 having a 4×4 array of 16 multi-ion qubit gates 902, in accordance with certain embodiments described herein. Other multi-qubit gate arrays having different numbers (e.g., greater than 16) of qubit gate arrays and / or different geometric arrangements (e.g., linear, rectangular, square, regular, irregular, symmetric, asymmetric) are also compatible with certain embodiments described herein. The 16 multi-ion qubit gates 902 of array 900 are arranged in a generally rectangular pattern, with four rows, each having four multi-ion qubit gates 902, and four columns, each having four multi-ion qubit gates 902. The multi-ion qubit gates 902 in each row include two alternating four-ion qubit gates 100 and two thirteen-ion qubit gates 500 (e.g., "4-13-4-13"), and the multi-ion qubit gates 902 in each column include two alternating four-ion qubit gates 100 and two thirteen-ion qubit gates 500 (e.g., "4-13-4-13"). The first (e.g., base) portion 810 of the array 900 is arranged such that every four nearest first portions 810 include a single-ion portion 10, a three-ion portion 30, a six-ion portion 50, and a seven-ion portion 70, and the second (e.g., cap) portion 820 of the array 900 is arranged such that every four nearest second portions 820 include a single-ion portion 10, a three-ion portion 30, a six-ion portion 50, and a seven-ion portion 70. In certain embodiments, first portion 810 and second portion 820 of array 900 (e.g., for a QFPGA) are configured to reduce (e.g., minimize) quantum bit-to-qubit spacing and / or optimize cell-to-cell connectivity.

[0057] As shown schematically in Figures 4A-4B, at least some of the electrical traces 14 extending along the first substrate 600 and / or the second substrate 700 have substantially straight portions that are substantially perpendicular to the boundaries between adjacent first portions 810 of the first substrate 600 and / or the boundaries between adjacent second portions 820 of the second substrate 700. For example, the electrical traces 14 shown vertically in Figure 4B are substantially perpendicular to the horizontal boundaries in Figure 4B. Figure 4C schematically shows a top-down view of another example multi-ion qubit gate array 900 having 16 multi-ion qubit gates 902 according to certain embodiments described herein. At least some of the electrical traces 14 extending along the first substrate 600 and / or the second substrate 700 in Figure 4C have substantially straight portions that are not substantially perpendicular to the boundaries between adjacent first portions 810 of the first substrate and / or the boundaries between adjacent second portions 820 of the second substrate 700. For example, the electrical traces 14, which are shown generally vertical in Figure 4C, extend beyond at least some of the boundaries of the hexagons in Figure 4C, but are not generally perpendicular to those hexagonal boundaries. Other positions and / or orientations of the electrical traces 14 are also compatible with certain embodiments described herein. For example, the electrical traces 14 may be curved to create space for optical ports for inputting and / or outputting laser signals to and / or from the region between the first substrate 600 and the second substrate 700.

[0058] 4D schematically illustrates a top-down view of another example multi-ion qubit gate array 800 having four multi-ion qubit gates 802, in accordance with certain embodiments described herein. The four multi-ion qubit gates 802 include two eight-ion qubit gates 300 (see, e.g., FIG. 2B ) and two nine-ion qubit gates 400 (see, e.g., FIG. 2C ) between a first substrate 600 and a second substrate 700. One of the eight-ion qubit gates 300 has a seven-ion base portion 70 and a single-ion cap portion 10, another eight-ion qubit gate 300 has a single-ion base portion 10 and a seven-ion cap portion 70, one nine-ion qubit gate 400 has a three-ion base portion 30 and a six-ion cap portion 50, and another nine-ion qubit gate 400 has a six-ion base portion 50 and a three-ion cap portion 30.

[0059] 4E schematically illustrates a top-down view of another example multi-ion qubit gate array 900 having 16 multi-ion qubit gates 902, in accordance with certain embodiments described herein. The 16 multi-ion qubit gates 902 of the array 900 are arranged in a generally rectangular pattern with four rows, each having four multi-ion qubit gates 902, and four columns, each having four multi-ion qubit gates 902. The rows of the multi-ion qubit gates 902 alternate between four nine-ion qubit gates 400 (e.g., 9-9-9-9) and four eight-ion qubit gates 300 (e.g., “8-8-8-8”), and each column of multi-ion qubit gates 902 includes two alternating nine-ion qubit gates 400 and two eight-ion qubit gates 300 (e.g., “9-8-9-8”). In one particular embodiment, the layout of the first portion 810 and second portion 820 of the array 900 (e.g., for a QFPGA) is configured to provide a constant spacing between ions in adjacent first portion 810 and second portion 820 of the array 900.

[0060] 4F-4G schematically illustrate exploded and top-down views, respectively, of another example array 900 having a 4×4 array of 16 multi-ion qubit gates 902, in accordance with certain embodiments described herein. The 16 multi-ion qubit gates 902 of array 900 are arranged in a generally rectangular pattern with four rows, each having four multi-ion qubit gates 902, and four columns, each having four multi-ion qubit gates 902. Each row of multi-ion qubit gates 902 includes four 10-ion qubit gates 450, and each column of multi-ion qubit gates 902 includes four 10-ion qubit gates 450. The rows and columns of the first (e.g., base) portion 810 of the array 900 have alternating 3-ion portions 30 and 7-ion portions 70 (e.g., "3-7-3-7"), and the rows and columns of the second (e.g., cap) portion 820 of the array 900 are alternating (e.g., "3-7-3-7"). In certain embodiments, the layout of the first and second portions 810, 820 of the array 900 is configured to provide more uniform spacing.

[0061] 5A-5I schematically illustrate portions of an example QC structure 1000 in various views, according to certain embodiments described herein. The example QC structure 1000 may be used in a QASIC or QFPGA layout. In certain embodiments, the QC structure 1000 advantageously provides sufficient space for cooling and magnetic field systems to operate the QC structure 1000. In certain embodiments, the overall layout preserves transmission line space for electrical traces to control multiple electrodes per electrode region, while advantageously addressing electrode overlap issues that arise between adjacent qubit gates in a two-dimensional (2D) layout when the adjacent qubit gates are closely tiled (e.g., to maintain effective coherence).

[0062] QC structure 1000 comprises an example of array 900 of FIG. 4C with electrical traces 14 similar to those of FIG. 4C. In certain embodiments, the alternating inverted rows of cells in the base and / or cap portions of array 900 facilitate the formation of electrical transmission paths through which electrical signals may be supplied to the ion trap of array 900. For example, as shown in FIG. 5A, electrical traces 14 are configured to supply electrical signals to various electrodes of the ion trap. Other arrangements of rows and columns of cells, electrical traces, and cells having other numbers of ions and / or qubits are also compatible with certain embodiments described herein.

[0063] In certain embodiments, the alternating inverted rows of cells in the base and / or cap portions of array 900 facilitate the formation of an optical transmission path through which optical signals may be input to and / or output from the ion trap of array 900. The example QC structure 1000 further comprises a plurality of optical ports 905, in accordance with certain embodiments described herein. The plurality of optical ports 905 of the example QC structure 1000 includes a first plurality of optical ports 910 in optical communication with a first plurality of optical fibers 912, the first plurality of optical ports 910 being within the first portion 810 of the first substrate 600. The plurality of optical ports 905 of the example QC structure 1000 further includes a second plurality of optical ports 920 in optical communication with a second plurality of optical fibers 922, the second plurality of optical ports 920 being within the second portion 820 of the second substrate 700. At least some of the optical ports 910 are configured to emit optical signals 914 (e.g., pulses generated by one or more lasers, not shown) configured to illuminate specific ions in the array 900 (e.g., to address and / or control specific quantum bits in the array 900), and at least some of the optical ports 920 are configured to emit optical signals 924 (e.g., pulses generated by one or more lasers, not shown) configured to illuminate specific ions in the array 900 (e.g., to address and / or control specific quantum bits in the array 900). The plurality of optical ports 905 of the example QC structure 1000 further comprises a third plurality of optical ports 930 and a third plurality of optical fibers 932. The optical port 930 can be in optical communication with a third plurality of optical fibers 932, which are positioned outside the periphery of the array 900 and configured to emit optical signals 934 (e.g., pulses generated by one or more lasers, not shown), which are configured to irradiate specific ions in the array 900 (e.g., to address and / or control specific quantum bits in the array 900).In one specific embodiment, optical ports 910 , 920 , 930 have polished fiber ends configured to direct laser light signals 914 , 924 , 934 to corresponding specific ions in array 900 .

[0064] The plurality of optical ports 905 of the example QC structure 1000 further comprises a fourth plurality of optical exit ports 940 in the first portion 810 and / or the second portion 820, configured to allow light from the optical signals 914, 924 passing through certain illuminated ions to be emitted or absorbed, thereby reducing (e.g., minimizing) crosstalk or other noise from optical reflection or scattering toward unintended quantum bits. The optical exit ports 940 may comprise holes and / or optically absorbing materials.

[0065] The example QC structure 1000 further includes a plurality of photodetectors 950 in optical communication with the fourth plurality of optical fibers 952. The plurality of photodetectors 950 (e.g., charge-coupled device (CCD) cameras, superconducting nanowire single-photon detectors (SNSPDs), photomultiplier tubes (PMTs), bolometers) are configured to receive optical signals (e.g., fluorescence 926) from the ions of the array 900 to read out the states of the quantum bits of the array 900.

[0066] 5A schematically illustrates a top view of an example first portion 810 of an array 900 on a first substrate 600 with the second substrate 700 removed. As shown in FIG. 5A, electrical traces 14 may extend along the array 900 to provide electrical connectivity with various electrodes of the first portion 810. Optical ports 910 may be positioned (e.g., staggered) within the first portion 810 and oriented such that optical signals 914 are directed to specific ions of the second portion 820.

[0067] 5B-5C schematically illustrate perspective and side views, respectively, of an example QC structure 1000 including both first and second substrates 600, 700 of the example QC structure 1000 (eg, a multi-chip structure).

[0068] 5D schematically illustrates a perspective view (without the second substrate 700) and a side view (with both the first substrate 600 and the second substrate 700) of an example QC structure 1000 with optical signals 934 launched from the third plurality of optical ports 930. These optical signals 934 are directed at an ion 904 positioned at the center of the multi-ion qubit gate 902, which ion 904 is a different distance from the first substrate 600 and the second substrate 700 than other non-central ions 906 of the multi-ion qubit gate 902.

[0069] According to certain embodiments described herein, Figure 5E schematically illustrates a perspective view (without optical signals 914, 924), Figures 5F-5G schematically illustrate two side views of QC structure 1000, and Figure 5H schematically illustrates another side view of QC structure 1000. Figure 5F illustrates three of the optical signals 914 originating from three of the first plurality of optical ports 910, each of the three optical signals 914 directed to a corresponding ion in the second portion 820 (e.g., the six-ion portion 50) of the multi-ion qubit gate 902. Additionally, Figure 5F illustrates an optical signal 934 originating from a third plurality of optical ports 930. Figure 5G shows six of the optical signals 914 originating from six of the first plurality of optical ports 910, with each of the six optical signals 914 directed to a corresponding ion in the second portion 820 (e.g., 6-ion portion 50) of the multi-ion qubit gate 902. Additionally, Figure 5G shows an optical signal 934 originating from a third plurality of optical ports 930 and six of the optical signals 924 originating from six of the second plurality of optical ports 920, with each of the six optical signals 924 directed to a corresponding ion in the first portion 810 (e.g., 7-ion portion 70) of the multi-ion qubit gate 902. FIG. 5H shows optical signals 924 emitted from the second plurality of optical ports 920 to irradiate corresponding ions, with some of the light from the optical signals 924 being allowed to exit through corresponding optical exit ports 940 (e.g., exiting the area between the first and second substrates 600, 700 and then being detected and / or absorbed).

[0070] FIG. 5I schematically illustrates a side view of the example QC structure 1000 of FIGS. 5C-5D , adding an additional row of optical ports 930 for launching optical signals 934. For example, as shown in FIG. 5I , the back support includes two rows of optical ports 930 and one row of photodetectors 950, while the front support includes one row of optical ports 930 and two rows of photodetectors 950. In certain embodiments, multiple optical signals may be advantageously used to utilize multiple ion species and perform optimal gating operations for each ion species. The type of optical addressing and optical transitions employed to address, initialize, and / or perform quantum gating operations on one or more ions may depend on the ion species used. For example, a particular ion species may be addressed using a single optical wavelength transition, resulting in an "optical qubit" (e.g., 40 Ca + ) In certain embodiments, at least one optical signal 934 is used to illuminate the plurality of ions 904 (e.g., to initialize or reset their qubit states to their lowest energy, ground state). In certain embodiments, at least one optical signal 934 is used to entangle the plurality of ions 904 and perform certain quantum gate operations involving one or more ions. Certain other ionic species can enter hyperfine states and may be referred to as "hyperfine qubits" (e.g., 43 Ca + , 171 Yb + ions, etc.), which typically employ two lasers at Raman transitions. In certain embodiments, optical signals 934 of two different wavelengths are advantageously used to address one or more ions and perform quantum gate operations.

[0071] FIG. 6A schematically illustrates a top-down view of an example 4×4 array 900 having multiple optical ports 905 alternating with four-ion qubit gates 100 and thirteen-ion qubit gates 500, according to certain embodiments described herein. The array 900 shown in FIG. 6A is an example QFPGA layout. At least some of the optical ports 910, 920 (shown by open circles in FIG. 6A ) are configured to launch optical signals 914, 924 into the region between the first substrate 600 and the second substrate 700, and at least some of the optical exit ports 940 (shown by filled circles in FIG. 6A ) are configured to allow the optical signals 914, 924 to exit and / or be absorbed. The optical exit ports 940 in certain embodiments are configured to prevent reflections of the optical signals 914, 924 from interfering with or degrading the performance of the example QC structure 1000. For example, the optical output ports 940 may comprise an optical absorber. At least some of the optical ports 910, 920 and the optical output ports 940 may be positioned within the hexagonal first and second portions 810, 820 of the multi-ion qubit gate 902, while at least some of the optical output ports 940 may be positioned in diamond-shaped regions 830, 840 between the hexagonal first and / or second portions 810, 820. For example, as shown in FIG. 6A , the optical ports 910, 920 and at least some of the optical output ports 940 are positioned between the “petal-shaped” electrode regions 16, and some of the optical output ports 940 are positioned in diamond-shaped regions 830, 840.

[0072] 6B-6D schematically illustrate optical signals illuminating ions of the array 900 of FIG. 6A , according to certain embodiments described herein. In each of FIG. 6B-6D , the central ion of the 4-ion qubit gate 100, the 7-ion qubit gate 200, and the 13-ion qubit gate 500 can be the laser-addressed and / or manipulated (e.g., target) ion and can be illuminated by an optical signal from an optical port 930 positioned outside the periphery of the array 900. The other ions of the 4-ion qubit gate 100, the 7-ion qubit gate 200, and the 13-ion qubit gate 500 can be the laser-addressed (e.g., control) ions.

[0073] As shown in FIG. 6B , three of the optical ports 910 transmit optical signals 914 that illuminate three corresponding ions of the four-ion qubit gate 100, and three of the optical exit ports 940 allow a portion of the optical signal 914 that passes through the three corresponding ions to exit in order to reduce (e.g., minimize) optical reflection or scattering within the array 900. In one particular embodiment, natural C 3 Using the four-ion qubit gate 100 as a NOT gate, a single gate operation can advantageously exploit geometric symmetry and replace many one- and two-qubit gate operations with greater speed and less aggregate error.

[0074] As shown in FIG. 6C , six of the optical ports 910 transmit optical signals 914 that illuminate six corresponding ions of the seven-ion qubit gate 200, and six of the optical exit ports 940 allow a portion of the optical signal 914 that passes through the six corresponding ions to exit in order to reduce (e.g., minimize) optical reflection or scattering within the array 900. In one particular embodiment, natural C 6 Using the seven-ion qubit gate 200 as a NOT gate, a single gate operation can advantageously exploit geometric symmetry and replace hundreds of one- and two-qubit gate operations with greater speed and less aggregate error.

[0075] As shown in FIG. 6D , six of the optical ports 910 transmit optical signals 914, six of the optical ports 920 transmit optical signals 924 that illuminate twelve corresponding ions of the 13-ion qubit gate 500, and twelve of the optical exit ports 940 allow the portions of the optical signals 914, 924 that pass through the twelve corresponding ions to exit in order to reduce (e.g., minimize) optical reflection or scattering within the array 900. 12 Using the 13-qubit gate 500 as a NOT gate, a single gate operation can advantageously exploit geometric symmetry and replace thousands of one- and two-qubit gate operations with greater speed and less aggregate error.

[0076] 6E schematically illustrates a top view of the base portion and the overlap of the base and cap portions of an example 4×4 array 900 of 10-ion qubit gates 450 having multiple ion entry apertures and optical ports 910, 920, according to certain embodiments described herein. The base portion has eight 3-ion portions 30 and eight 7-ion portions 70 that are interleaved with one another, and the cap portion has eight 3-ion portions 30 and eight 7-ion portions 70 that are interleaved with one another (see, e.g., FIGS. 4C, 4F, and 4G).

[0077] 6F schematically illustrates the overlap of the base and cap portions of an example 4×4 array 900 of 10-ion qubit gates 450 having multiple microwave antenna regions 942 located on at least one chip substrate 600, 700, according to certain embodiments described herein. 9 Be + , 43 Ca + , 171 Yb +, and many others), certain embodiments described herein advantageously provide microwave addressing and control of trapped ions in addition to, or instead of, certain optical methods (see, e.g., C. Ospelkaus et al., Phys Rev. Lett. Vol. 101, 090502 (2008); T. P. Harty et al., Phys Rev. Lett. Vol. 113, 220501 (2014)).

[0078] 7A schematically illustrates a side view of a portion of an example QC structure 1000, and FIG. 7B schematically illustrates a close-up view of a smaller portion of the QC structure 1000 of FIG. 7A, in accordance with certain embodiments described herein. As shown in FIG. 7A, optical signals 924 (e.g., light having a laser wavelength from an ion-addressing laser through optical fibers 912, 922) emitted from optical ports 910, 920 are directed to illuminate corresponding ions 18, 38, 58, 78. In response to the optical signal 924, the ions 18, 38, 58, 78 may fluoresce and emit fluorescent light 926. In certain embodiments, the ion fluorescence wavelength may be at or near the laser wavelength of the optical signal 924, while in certain other embodiments, the ion fluorescence wavelength is different from the laser wavelength of the optical signal 924. The light propagating to and passing through the optical output port 940 may include a mixture of fluorescent light 926 from the irradiated ions 18, 38, 58, and 78 and the optical signal 924 emitted from the optical ports 910 and 920, as shown in FIG. 7B.

[0079] 7A and 7B, the QC structure 1000 comprises at least one light selective layer 1100 configured to separate the optical signal 924 from the fluorescent light 926. For example, as shown in FIGS. 7A and 7B, the at least one light selective layer 1100 includes a wavelength selective material positioned between the optical output port 940 and the corresponding photodetector 950 and configured to block (e.g., refract, deflect, reflect, diffract) the optical signal 924 from reaching the photodetector 950 while allowing (e.g., allowing) the fluorescent light 926 to reach (e.g., travel directly to) the photodetector 950. Examples of light selective layers 110 configured to separate the optical signal 924 from the fluorescent light 926 according to certain embodiments described herein are described herein as including, but not limited to, a layer having a wavelength-dependent refractive index, a prismatic layer, and a diffraction grating. In certain other embodiments, at least one light selective layer 1100 includes a polarization-selective material (e.g., a polarizing filter, a birefringent crystal lattice) and / or a phase-selective material (e.g., a quarter-wave plate, a highly dispersive material, a prismatic layer) configured to block optical signal 924 from reaching photodetector 950 (e.g., by orthogonally polarizing and / or shifting the phase) while allowing fluorescent light 926 to reach photodetector 950. In certain such embodiments, light selective layer 1100 may reduce the intensity of fluorescent light 926 by an acceptable amount (e.g., approximately a factor of two, −3 dB) such that half of fluorescent light 926 passes through light selective layer 1100 while optical signal 924 is blocked or highly attenuated, resulting in fluorescent light 926 with a favorable signal-to-noise ratio reaching photodetector 950. In certain embodiments, the use of the optical selection layer 1100 can be used in conjunction with the pulse timing of the optical signal 924 and the gating of the readout of the photodetector 950 to further increase the signal-to-noise detection of the fluorescence 926 signal relative to the optical signal 924.

[0080] 7C and 7D are schematic illustrations of two views of another example of a QC structure 1000, according to certain embodiments described herein. As shown schematically by FIGS. 7C and 7D, the QC structure 1000 includes an optical exit port 940 and an optical detector 950 positioned such that (i) an optical signal 924a used to irradiate a first predetermined ion 928a propagates through the corresponding optical exit port 940 but does not reach the corresponding optical detector 950, and (ii) a fluorescent light 926 from a second predetermined ion 928b propagates from the ion 928b through the optical exit port 940 to the corresponding optical detector 950, while an optical signal 924 (e.g., irradiating ion 924b, or another ion) does not propagate through the optical exit port 940 to the corresponding optical detector 950. For example, certain such arrangements may be useful for QC structures 1000 in which the fluorescent light 926 and the optical signal 924 are not easily distinguishable from one another (eg, by wavelength, polarization, and / or phase).

[0081] 7E schematically illustrates a side view of a portion of an example QC structure 1000 including an ion injection aperture 1200 (e.g., a vertical interconnect (VIA), a through-silicon via (TSV), a carbon nanotube (CNT) structure) and a single-ion photodetector 1210 (e.g., a charge-coupled device (CCD), a PMT, an SNSPD, a bolometer) in accordance with certain embodiments described herein. In certain embodiments, the ion injection apertures 1200 are configured to inject ions 18, 38, 58, 78 into corresponding electron potential wells 17, 37, 57, 77 and to be controllably opened and / or closed in response to a signal from the corresponding single-ion photodetector 1210. For example, when the single-ion photodetector 1210 detects that a single ion has passed through the corresponding ion injection aperture 1200, the single-ion photodetector 1210 can close the ion injection aperture 1200 to prevent further ions from passing through. If the corresponding electron potential well 17, 37, 57, 77 does not contain an ion 18, 38, 58, 78, the single ion photodetector 1210 may open the ion injection aperture 1200 so that a single ion 18, 38, 58, 78 is provided to the electron potential well 17, 37, 57, 77.

[0082] 8A and 8B show a schematic side view (left side of FIG. 8A ) of an example QC structure 1000 having an example 16×16 cell array 1300, and a top-down projection of the 16×16 cell array 900 (right side of FIG. 8 ), in accordance with certain embodiments described herein. The 16×16 cell array 1300 of FIG. 8 comprises sixteen of the 4×4 cell arrays 900 of FIGS. 5A-5D tiled together. As shown on the right side of FIG. 8 , the 16×16 cell array 1300 has a nominal area of ​​one square centimeter (1 cm ). 2 ) on a substrate of 600,700 mm, approximately one-quarter square centimeter (0.25 cm 2) area. For example, a 16×16 cell array 1300 can achieve 16,437 qubits (e.g., with a trap spacing of about 40 microns) within the area of ​​the substrate 600, 700 by alternating 4-ion gate arrays 100 and 13-ion gate arrays 500. In another embodiment, a 16×16 cell array 1300 can achieve 19,400 qubits (e.g., with a trap spacing of about 40 microns) within the area of ​​the substrate 600, 700 by only including 10-ion gate arrays 450.

[0083] The number of qubits can be increased if the QC structure 100 has a cell array with a larger number of cells and extending over a larger area, e.g., 1 cm 2 A cell array with alternating 4-ion gate arrays 100 and 13-ion gate arrays 500 over an area of ​​1 cm may allow for 65,750 qubits per square centimeter (e.g., using a trap spacing of about 40 microns), and 2 A cell array with only 10 ion gate arrays 450 over an area of ​​10 ion may allow for over 77,000 qubits per square centimeter (eg, using a trap spacing of about 40 microns).

[0084] 9 shows four tables comparing total qubit counts for various 4×4 cell arrays according to certain embodiments described herein, along with examples of how array reconfiguration advantageously allows multiple complementary attributes to be selected. As shown in FIG. 9, in a 4×4 cell array having eight alternating four-ion gate arrays 100 and eight thirteen-ion gate arrays 500 (e.g., designated “QFPGA I” in FIG. 9), the total qubit count is 136. While this represents a relatively low qubit density within the overall trade space, the interspersing of ultra-high-capacity gates with adjacent smaller-capacity gates provides opportunities for error correction to be efficiently performed in-place, and / or for the implementation of algorithms that benefit from multiple controlled-NOT or multiple controlled-phase gates with a large number (e.g., 10 or more) of controls. In a 4x4 cell array (e.g., designated "QASIC I" in FIG. 9) with six 4-ion gate arrays 100, seven 10-ion gate arrays 450, and three 13-ion gate arrays 500, the total number of qubits is 133. However, for example, in ASIC-type applications (e.g., with a small number of C 12 In cases where NOT gates are used but faster relay speeds or higher throughput are desired across the array, QASIC I can be more efficient than QFPGA I, despite having three fewer qubits in the array. A 4×4 cell array with sixteen 10-ion gate arrays 450 (e.g., designated "QFPGA II" in FIG. 9 ) has a total qubit count of 160. This is the highest qubit density offered for an array, and has the most efficient throughput and most uniform design across all directions. A 4×4 cell array with four 4-ion gate arrays 100, ten 10-ion gate arrays 450, and two 13-ion gate arrays 500 (e.g., designated "QASIC II" in FIG. 9 ) has a total qubit count of 142. This targets the middle of the qubit density range, yet such an array can achieve a small number of C 12NOT gates are used and it would be advantageous to use special ASIC types where the direction of maximum relay speed or throughput (e.g. bottom left to top right or vice versa) can be predetermined.

[0085] The present invention has been described in several non-limiting embodiments. It will be understood that these embodiments are not mutually exclusive, and that elements described in connection with one embodiment may be combined, rearranged, or removed from other embodiments in any suitable manner to achieve desired design goals. No single feature or group of features is necessary or essential for each embodiment.

[0086] For purposes of summarizing the invention, certain aspects, advantages, and novel features of the invention are described herein. It will be understood, however, that not all such advantages may necessarily be achieved in accordance with any particular embodiment. Thus, the invention may be embodied or practiced in a manner that achieves one or more advantages without necessarily achieving other advantages as may be taught or suggested herein.

[0087] As used herein, all references to "an embodiment" or "some embodiments" or "one embodiment" mean that a particular element, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" in various places within the specification do not necessarily all refer to the same embodiment. As used herein, conditional terms such as "may," "could," "might," "may," "for example," and the like, among others, are generally intended to convey that a particular embodiment includes certain features, elements, and / or steps, while other embodiments do not, unless otherwise specified or understood otherwise within the context in which they are used. Furthermore, as used in this application and the appended claims, the articles "a," "an," or "the" shall be interpreted to mean "one or more" or "at least one" unless otherwise specified.

[0088] As used herein, degree language, such as terms such as "approximately," "about," "generally," and "approximately," refers to a value, amount, or characteristic that is close to the stated value, amount, or characteristic that still performs a desired function or achieves a desired result. For example, terms such as "approximately," "about," "generally," and "approximately" may refer to an amount that is within ±10%, ±5%, ±2%, ±1%, or ±0.1% of the stated amount. As another example, terms such as "generally parallel" and "approximately parallel" refer to a value, amount, or characteristic that deviates from exactly parallel by ±10 degrees, ±5 degrees, ±2 degrees, ±1 degree, or ±0.1 degrees, and terms such as "generally perpendicular" and "approximately perpendicular" refer to a value, amount, or characteristic that deviates from exactly perpendicular by ±10 degrees, ±5 degrees, ±2 degrees, ±1 degree, or ±0.1 degrees. Ranges disclosed herein also encompass any overlapping, subranges, and combinations thereof. For example, language such as "up to," "at least," "greater than," "less than," and "between" includes the recited numbers. As used herein, the meanings of "a," "an," and "said" include plural references unless the context clearly dictates otherwise. Also, as used herein, the meaning of "in" includes "into" and "on," unless the context clearly dictates otherwise.

[0089] As used herein, the terms "comprises," "comprising," "includes," "including," "having," "having," or any other variations thereof, are open-ended terms and are intended to cover a non-exclusive inclusion. For example, a process, method, article, or apparatus that includes a list of elements need not be limited to only those elements but may include other elements not expressly listed or inherent in such process, method, article, or apparatus. Furthermore, unless expressly stated otherwise, "or" refers to an inclusive or, not an exclusive or. For example, condition A or B is satisfied by either: A is true (or present) and B is false (or absent); A is false (or absent) and B is true (or present); or both A and B are true (or present). As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items, including one component. As an example, "at least one of A, B, or C" is intended to cover A, B, C, A and B, A and C, B and C, and A, B, and C. Transitional language such as phrases such as "at least one of X, Y, and Z" is understood differently in context, as is commonly used to convey that an item, term, etc. can be at least one of X, Y, or Z, unless specifically stated otherwise. Thus, such transitional language does not generally imply that a particular embodiment requires that at least one of X, at least one of Y, and at least one of Z, respectively, be present.

[0090] Therefore, while only certain embodiments have been specifically described herein, it will be apparent that numerous modifications may be made thereto without departing from the spirit and scope of the present invention. Furthermore, acronyms are used solely to improve the readability of the specification and claims. It should be noted that these acronyms are not intended to reduce the generality of the terms used, and should not be construed to limit the scope of the claims to the embodiments described herein.

Claims

1. 1. A quantum computing (QC) system comprising: a first substrate and a second substrate, the first substrate and the second substrate being generally parallel to one another, each of the first substrate and the second substrate being configured to create a plurality of trapping regions disposed between the first substrate and the second substrate in a corresponding plurality of generally planar regions; a plurality of qubits, each qubit included in one of the plurality of trapping regions in one of the corresponding plurality of substantially planar regions; at least one of the corresponding plurality of substantially planar regions comprises two or more qubits; A system in which one or more qubits in one substantially planar region are simultaneously entangled with two or more qubits in another substantially planar region to define a multi-qubit quantum gate.

2. A plurality of qubits arranged as a multi-qubit gate array having a plurality of multi-qubit gates contained in the plurality of trapping regions between the first substrate and the second substrate, the qubits being provided on or near a surface of at least one of the first substrate and the second substrate and being generally arranged in the corresponding plurality of substantially planar regions; The system of claim 1 further comprising:

3. The system of claim 2 , wherein the first substrate is substantially planar and the second substrate is substantially planar.

4. 3. The system of claim 2, wherein each of the multi-qubit gates in the array has a first portion at a surface of the first substrate and a second portion at a surface of the second substrate.

5. 5. The system of claim 4, wherein the multi-qubit gates are arranged along a surface of the first substrate in a generally rectangular pattern, or a generally hexagonal pattern, or a generally diagonal pattern having at least one row and at least one column.

6. 6. The system of claim 5, wherein the generally rectangular pattern has four rows, each having four of the multi-qubit gates, and four columns, each having four of the multi-qubit gates.

7. 7. The system of claim 6, wherein the multi-qubit gates in each row are comprised of two alternating 4-qubit gates and two 13-qubit gates, and the multi-qubit gates in each column are comprised of two alternating 4-qubit gates and two 13-qubit gates.

8. 8. The system of claim 7, wherein the first portions are arranged such that any four nearest neighboring first portions include a single qubit portion, a three qubit portion, a six qubit portion, and a seven qubit portion, and the second portions are arranged such that any four nearest neighboring second portions include a single qubit portion, a three qubit portion, a six qubit portion, and a seven qubit portion.

9. 5. The system of claim 4, wherein the first portion of each multi-qubit gate in the array is selected from the group consisting of a single qubit portion, a three qubit portion, a six qubit portion, and a seven qubit portion, and the second portion of each multi-qubit gate in the array is selected from the group consisting of a single qubit portion, a three qubit portion, a six qubit portion, and a seven qubit portion.

10. 5. The system of claim 4, wherein, for each said multi-qubit gate, each said qubit is configured to be quantum mechanically entangled with at least one other said qubit of the multi-qubit gate.

11. 5. The system of claim 4, wherein the first portion of the multi-qubit gates in each of the arrays comprises 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, or more qubits, and / or the second portion of the multi-qubit gates in each of the arrays comprises 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, or more qubits.

12. 10. The system of claim 1, wherein the two or more qubits and the one or more qubits in each of the substantially planar regions are configured to directly interact with one or more qubits in at least one other of the substantially planar regions to form a 3D cell array configured to undergo multi-qubit gate operations involving more than two of the qubits simultaneously.

13. 1. A quantum computing (QC) system comprising: at least a first substrate and a second substrate, the first substrate and the second substrate being generally parallel to one another, each of the first substrate and the second substrate being configured to create, in a corresponding plurality of planar regions, a plurality of trapping regions (a) disposed between the first substrate and the second substrate, and (b) each including a plurality of fully coupled multi-ion qubit gates; 1. A system comprising: a plurality of fully coupled multi-ion qubit gates (i) having a plurality of qubits from the plurality of trapping regions created by the first substrate and the second substrate; and (ii) a plurality of fully coupled multi-ion qubit gates arranged in a substantially rectangular lattice having a plurality of rows and a plurality of columns, each of the plurality of multi-ion qubit gates configured to gate using more than two qubits at a time.

14. 14. The system of claim 13 , wherein the multi-ion qubit gates in at least one of the plurality of rows and / or at least one of the plurality of columns comprise alternating four-ion qubit gates and thirteen-ion qubit gates.

15. 14. The system of claim 13, wherein the multi-ion qubit gates in at least one of the plurality of rows and / or at least one of the plurality of columns include a plurality of ten-ion qubit gates.

16. 14. The system of claim 13 , wherein the multi-ion qubit gates in at least one of the plurality of rows and / or at least one of the plurality of columns include a four-ion qubit gate, a thirteen-ion qubit gate, and a plurality of ten-ion qubit gates.

17. The multi-ion qubit gate comprises: an equal number of 4-ion qubit gates and 13-ion qubit gates alternating with each other along each row and each column; all said multi-ion qubit gates in the lattice including a 10-ion qubit gate; 14. The system of claim 13, comprising one of:

18. 1. A quantum computing (QC) system comprising: a first substrate and a second substrate, the first substrate and the second substrate being generally parallel to one another, each of the first substrate and the second substrate being configured to create a plurality of trapping regions in corresponding planar regions disposed between the first substrate and the second substrate, each of the plurality of trapping regions including one of a plurality of atomic qubits; a plurality of multi-qubit three-dimensional (3D) gate cells, each of the 3D gate cells comprising at least three qubits from each of the regions of the corresponding multi-qubit plane configured to be simultaneously fully coupled to one another across three dimensions, the plurality of multi-qubit 3D gate cells configured for gating two or more of the multi-qubit 3D gate cells; A system comprising:

19. 20. The system of claim 18, wherein the plurality of multi-qubit 3D gate cells comprises an ion trap array configured to have optimal coherent connectivity or direct entanglement between nearest neighbor qubits or second nearest neighbor qubits without mutual coupling of photons between the qubits.

20. 20. The system of claim 18, wherein the multi-qubit 3D gate cell does not rely on a concatenation of multiple one- and two-qubit gates, has a geometrically symmetric structure, and is configured to be spontaneously activated by a single gate operation.

21. 20. The system of claim 18, wherein the multi-qubit 3D gate cell has an asymmetric 3D structure with complementary bases and caps arranged in alternating directions, with alternating bases and caps of non-identical adjacent cells.

22. 20. The system of claim 18, wherein the plurality of multi-qubit 3D gate cells are configured to be operated as at least one quantum FPGA (QFPGA) and / or quantum ASIC (QASIC) chip.

23. The system of claim 18, wherein the multi-qubit 3D gate cell has an array of one or more 9-qubit gates, 8-qubit gates, or 7-qubit gates.

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