Semiconductor Devices

Abstract

To provide a semiconductor device capable of preventing quality deterioration.SOLUTION: A semiconductor device comprises: a plurality of trenches 4 containing extension parts extended in a first direction and arranged with an interval in a second direction; a gate insulation film 5 that is provided inside the trench 4; and a p-type protection region that is provided under the trench 4 and contains a first protection layer 11a and a second protection layer 11b. The semiconductor device further comprises: first conductive type first main electrode regions (source regions) 7a and 7b that contain parts provided along a side wall of the first trench 4 as one of the trenches 4; second conductive type base regions 3a and 3b that are provided under the first main electrode regions 7a and 7b. In a depth direction, the concentration of an impurity element in a second protection layer 11b provided between the first protection layer 11a and a bottom part of the first trench 4 is lower than a peak concentration in a first region along a side wall of the first trench 4 of the base regions 3a and 3b. The first protection layer 11a has a concentration of the impurity element that is higher than those in the base regions 3a and 3b.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] In trench MOSFETs using silicon carbide (SiC) semiconductors, when a reverse bias voltage is applied during turn-off (hereinafter simply referred to as "off"), a high voltage is applied between the drain and source, which can degrade the quality of the gate insulating film. When a reverse bias voltage is applied, the bottom of the trench is the most susceptible to damage in the gate insulating film.

[0003] As a technique for protecting the gate insulating film at the bottom of the trench, for example, Patent Document 1 discloses a technique in which a highly doped p-type electric field shield region is placed directly below the trench to protect the gate insulating film from high voltage when the device is off. However, with the technique disclosed in Patent Document 1, the electric field shield region blocks the path of the main current when the device is turned on (hereinafter simply referred to as "on"). This poses a problem of an increase in the on-resistance (JFET resistance) due to the junction field-effect transistor (JFET) effect, in which a depletion layer extends from the adjacent channel region and narrows the path of the main current. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4738562 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in view of the above-mentioned problems, and has an object to provide a semiconductor device that can prevent quality degradation. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems, one aspect of the semiconductor device according to the present invention is a semiconductor device comprising: trenches each including an extension portion extending in a first direction, the extension portions being spaced apart and arranged in a second direction; an insulating film provided inside the trench; and a p-type protection region provided below the trench and including a first protection layer and a second protection layer, the semiconductor device further comprising: a first main electrode region of a first conductivity type including a portion provided along the sidewall of a first trench, which is one of the trenches; and a base region of a second conductivity type provided below the first main electrode region, wherein the concentration of impurity elements in the second protection layer provided between the first protection layer and the bottom of the first trench in the depth direction is lower than the peak concentration in a first region of the base region along the sidewall of the first trench, and the first protection layer has a higher concentration of impurity elements than the base region.

[0007] In order to solve the above-mentioned problems, one aspect of the semiconductor device of the present invention is a semiconductor device comprising: a trench including an extension portion extending in a first direction, the extension portions being arranged at intervals in a second direction; an insulating film provided inside the trench; and a p-type protection region provided below the trench and including a first protection layer and a second protection layer, wherein the semiconductor device further comprises a first main electrode region of the first conductivity type including a portion provided along the sidewall of a first trench, which is one of the trenches, and a base region of the second conductivity type provided below the first main electrode region, wherein the protection region is composed of three or more layers, and the second protection layer is provided in contact with the bottom of the first trench. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a semiconductor device that can prevent quality degradation. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view for schematically explaining an outline of a configuration of a semiconductor device according to an embodiment of the present invention; [Figure 2] 1 is a cross-sectional view for schematically explaining an outline of a state of a main current flowing in a semiconductor device according to an embodiment of the present invention; [Figure 3]10 is a cross-sectional view for schematically explaining the outline of the state of a main current flowing in a semiconductor device according to a comparative example; FIG. [Figure 4] 10A and 10B are partially enlarged cross-sectional views for schematically explaining the outline of the state of a main current flowing in the semiconductor device according to the embodiment of the present invention and the semiconductor device according to the comparative example. [Figure 5] 10 is a graph showing the relationship between the concentration of the conductive path forming layer below the bottom of the trench and the on-resistance of the semiconductor device. FIG. [Figure 6] 1A to 1C are cross-sectional views (part 1) that schematically illustrate a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 5A to 5C are cross-sectional views (part 2) that schematically illustrate the method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] 5A to 5C are cross-sectional views (part 3) that schematically illustrate a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] 4 is a cross-sectional view (part 4) for schematically explaining the method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 10] 5 is a cross-sectional view (part 5) for schematically explaining the method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 11] 6 is a cross-sectional view (part 6) for schematically explaining the method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 12] 7 is a cross-sectional view (part 7) for schematically explaining the method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 13] 8 is a cross-sectional view (part 8) for schematically explaining the method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 14] 9 is a cross-sectional view for schematically explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. [Figure 15] 1A to 1C are cross-sectional views (part 1) for schematically explaining a method for manufacturing a semiconductor device according to a first modified example of the embodiment of the present invention. [Figure 16] 10A and 10B are cross-sectional views (part 2) for schematically explaining a method for manufacturing a semiconductor device according to a first modified example of the embodiment of the present invention. [Figure 17] 10A to 10C are cross-sectional views (part 3) for schematically explaining a method for manufacturing a semiconductor device according to a first modified example of the embodiment of the present invention. [Figure 18] 10 is a cross-sectional view (part 4) for schematically explaining a method for manufacturing a semiconductor device according to a first modified example of the embodiment of the present invention. FIG. [Figure 19] FIG. 10 is a partially enlarged cross-sectional view for schematically explaining the outline of the configuration of a semiconductor device according to a second modification of the embodiment of the present invention. [Figure 20] FIG. 10 is a partially enlarged cross-sectional view for schematically explaining the outline of the state of a main current flowing in a semiconductor device according to a second modification of the embodiment of the present invention. [Figure 21] FIG. 10 is a partially enlarged cross-sectional view for schematically explaining the outline of the configuration of a semiconductor device according to a third modified example of the embodiment of the present invention. [Figure 22] FIG. 10 is a partially enlarged cross-sectional view for schematically explaining the outline of the state of a main current flowing in a semiconductor device according to a third modified example of the embodiment of the present invention. [Figure 23] FIG. 10 is a partially enlarged cross-sectional view for schematically explaining the outline of the configuration of a semiconductor device according to a fourth modification of the embodiment of the present invention. [Figure 24] FIG. 10 is a partially enlarged cross-sectional view for schematically explaining the outline of the state of a main current flowing in a semiconductor device according to a fourth modification of the embodiment of the present invention. [Figure 25] FIG. 10 is a partially enlarged cross-sectional view for schematically explaining an outline of the configuration of a semiconductor device according to a fifth modified example of the embodiment of the present invention. [Figure 26] FIG. 13 is a partially enlarged cross-sectional view for schematically explaining the outline of the state of a main current flowing in a semiconductor device according to a fifth modified example of the embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] An embodiment of the present invention will be described below. In the following drawings, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each component, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0011] Furthermore, the directions of "left and right" and "up and down" in the following description are merely definitions for the convenience of explanation and do not limit the technical concept of the present invention. Therefore, for example, if the page is rotated 90 degrees, "left and right" and "up and down" are read interchangeably, and if the page is rotated 180 degrees, "left" becomes "right" and "right" becomes "left." Furthermore, in the following description, a case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example, but the conductivity types may be reversed, with the first conductivity type being p-type and the second conductivity type being n-type. Furthermore, + or - attached to n or p indicates a semiconductor region with a relatively higher or lower impurity element concentration, respectively, compared to a semiconductor region without a + or - attached thereto.

[0012] In this specification, the term "first main electrode region" refers to a semiconductor region that becomes either a source region or a drain layer in a field-effect transistor (FET) or a static induction transistor (SIT). In an insulated gate bipolar transistor (IGBT), the term "second main electrode region" refers to a semiconductor region that becomes either a source region or a drain layer that does not become the first main electrode region in a FET or SIT, and to a region that becomes either an emitter region or a collector region that does not become the first main electrode region in an IGBT.

[0013] <Semiconductor device> 1, a semiconductor device according to an embodiment of the present invention is a MOSFET including an n-type drift region 2 using a SiC semiconductor substrate and a plurality of p-type base regions 3a, 3b provided in an upper portion of the drift region 2. A trench 4 is provided in an upper portion of the drift region 2, extending from the base regions 3a, 3b to the drift region 2.

[0014] The semiconductor device shown in Figure 1 is a diagram focusing on one trench 4 and the region surrounding this trench 4 in a semiconductor device according to an embodiment of the present invention. In reality, a plurality of trenches 4 are provided, and each trench extends parallel to and spaced apart from one another along a direction penetrating the plane of the drawing. The semiconductor device according to the embodiment of the present invention is configured by repeatedly forming and integrating a structure such as that shown in Figure 1 on both the left and right sides of Figure 1.

[0015] 1 also includes a gate insulating film 5 provided inside the trench 4, a gate electrode 6 provided inside the trench 4 via the gate insulating film 5, and an interlayer insulating film 8 provided on the surface of the gate electrode 6. The concentration of impurity elements in the base regions 3a and 3b—the impurity density—is, for example, 4.0×10 17 cm -3 When a predetermined gate voltage is applied to the gate electrode 6 while a positive bias is applied to the channel region, the conductivity type of the channel region is inverted.

[0016] A plurality of p-type base regions 3a and 3b are formed between adjacent trenches 4 at the upper part of the p-type base regions 3a and 3b. + p-type base contact regions 12a and 12b are provided. Also, p-type first under-contact base regions 13a and 13b and p-type second under-contact base regions 14a and 14b are provided directly below base regions 3a and 3b located below base contact regions 12a and 12b, stacked in this order from bottom to top.

[0017] The semiconductor device shown in FIG. 1 also has a plurality of n-type junctions selectively provided in the upper part of the p-type base regions 3a and 3b. +The semiconductor device includes source regions 7a and 7b and a source electrode 9 provided on the source regions 7a and 7b via a barrier metal layer 15. The source regions 7a and 7b correspond to the "first main electrode region" of the present invention. The source electrode 9 is connected to the source regions 7a and 7b. The barrier metal layer 15 has a three-layer structure made of titanium (Ti), titanium nitride (TiN), etc., and is provided on the drift region 2, over the interlayer insulating film 8, the top surfaces of the source regions 7a and 7b, and the base contact regions 12a and 12b. The barrier metal layer 15 suppresses the growth of silicon (Si) nodules or the diffusion of aluminum (Al) contained in the source electrode 9. An ohmic contact is formed at the contact portions between the barrier metal layer 15 and the source regions 7a and 7b and the base contact regions 12a and 12b by providing a nickel silicide layer (not shown).

[0018] A passivation film such as polyimide is deposited on the top surface of the source electrode 9 as the outermost layer, and the main surface of the lower source electrode 9 is exposed in a window (opening) formed in the passivation film. The exposed main surface of the source electrode 9 can be used as a source bonding pad. Similarly, a wiring layer connected to the gate electrode 6 is exposed in a window formed in the passivation film in a location separate from the source electrode 9. The exposed portion of the wiring layer can be used as a gate bonding pad. The passivation film, bonding pad, etc. are not shown in the drawings.

[0019] The semiconductor device shown in FIG. 1 also has a n + The semiconductor device includes a drain region 1 and a drain electrode 10 provided below and connected to the drain region 1. The drain region corresponds to the "second main electrode region" of the present invention.

[0020] Further provided below the trench 4 within the drift region 2 are a p-type protective layer 11a that extends outward beyond the width of the trench 4, and a p-type conductive path-forming layer 11b that is provided between this protective layer 11a and the bottom of the trench 4. The conductive path-forming layer 11b extends outward by a certain amount beyond the width of the trench 4, and the concentration and thickness of the impurity element in the extending region are set so that it is inverted to n-type when on. The protective layer 11a and the conductive path-forming layer 11b form a two-layer protective conductive region (11a, 11b).

[0021] The protective conduction regions (11a, 11b) are provided at approximately the same height as the first under-contact base regions 13a, 13b below the base contact regions 12a, 12b. The protective conduction regions (11a, 11b) have approximately the same thickness t as the first under-contact base regions 13a, 13b, and their upper surfaces are in contact with the lower surface of the gate insulating film 5 at the bottom of the trench 4. The protective layer 11a and the conductive path-forming layer 11b of the protective conduction regions (11a, 11b) both have rectangular cross-sectional shapes shown in FIG. 1 and extend parallel to the trench 4, which extends in the direction penetrating the page inside the drift region 2.

[0022] The protective layer 11a is formed to protect the gate insulating film 5 when the gate is turned off. 18 cm -3 High concentrations of p + The protective layer 11a is formed to have a rectangular shape. The protruding width w at both ends of the rectangular shape of the protective layer 11a is longer than the protruding width at both ends of the rectangular shape of the conductive path-forming layer 11b. Therefore, the overall cross-sectional shape of the protective conductive region (11a, 11b) made up of the protective layer 11a and the conductive path-forming layer 11b has a stepped shape at both ends from the bottom to the top and from the outside to the inside of the trench 4.

[0023] The conductive path forming layer 11b is provided directly on the protective layer 11a, and an inversion layer is formed in the conductive path forming layer 11b when the layer is on. The upper limit of the p-type impurity element concentration in the conductive path forming layer 11b is set to a concentration that allows the thickness of the conductive path forming layer 11b to be inverted to n-type when an on-voltage is applied. As an example of inverting the conductive path forming layer 11b to n-type, it is preferable to make the impurity element concentration in the conductive path forming layer 11b lower than the impurity element concentration in the base regions 3a and 3b. On the other hand, the lower limit of the p-type impurity element concentration in the conductive path forming layer 11b is set to at least the impurity element concentration in the n-type drift region 2 so that the conductivity type can be maintained as p-type when the layer is off. Specifically, if the semiconductor device is of the 1200V class, the upper limit of the p-type impurity element concentration in the conductive path forming layer 11b is set to, for example, 8.0×10 15 cm -3 The impurity element concentration in the protective layer 11a and the impurity element concentration in the conductive path forming layer 11b may be set to be the same.

[0024] In the semiconductor device according to the embodiment of the present invention, the thickness as well as the concentration are set so as to more reliably realize the formation of an inversion layer when the semiconductor device is on. Specifically, the overhang width at both ends of the conductive path-forming layer 11b is approximately 0.1 μm to 0.5 μm. If the overhang width and thickness exceed their respective upper limits, there is a concern that the inversion layer may not be sufficiently formed.

[0025] The total thickness t of the protective conductive regions (11a, 11b) is set so as to achieve both the realization of an inversion layer in the conductive path forming layer 11b and the protection of the gate insulating film 5 by the protective layer 11a.

[0026] As shown in FIG. 2, in the semiconductor device according to the embodiment of the present invention, when the drain region 1 is biased to a positive potential, an inversion layer 11b, whose conductivity type is inverted from p-type to n-type, is formed inside the conductive path forming layer 11b in the on-state. inv Then, a main current I flows from the drain region 1 toward the source regions 7a and 7b along the left and right sidewalls of the trench 4. L 1,I R 1 flows. Main current I L 1,I RThe flow of the main current I rises along the side of the protective layer 11a in the n-type drift region 2, reaches the upper side of the protective layer 11a, and then changes direction by about 90 degrees so as to follow the upper surface of the end of the protective layer 11a. L 1,I R 1 is the inversion layer 11b inv It penetrates into the inside of the end.

[0027] Then the main current I L 1,I R 1 is the inversion layer 11b inv Inside the trench 4, the direction of the main current I changes by about 90 degrees along the side wall of the trench 4. L 1,I R 1 is the inversion layer 11b inv The main current I L 1,I R The flow of 1 flows upward along the sidewall of trench 4, passes through the inversion layers of channel regions 3a1 and 3b1 formed in base regions 3a and 3b, and reaches source regions 7a and 7b.

[0028] That is, the main current I L 1,I R 1 does not flow along the shape of the corners at the ends of the conductive path forming layer 11b in the protective conductive region (11a, 11b), but flows along the inversion layer 11b of the conductive path forming layer 11b. inv 2, the hatching of the inversion layer portions of the channel regions 3a1 and 3b1 is omitted for ease of viewing.

[0029] <Comparative Example> On the other hand, as shown in FIG. 3, in the case of the semiconductor device according to the comparative example that does not have a conductive path forming layer, the main current I L z,I RThe flow current flows along the step shape of the end of the protective layer 11z. The semiconductor device according to the comparative example differs from the semiconductor device according to the embodiment of the present invention in that it does not have a two-layer protective conductive region (11a, 11b) including the conductive path forming layer 11b, but has only a single-layer protective layer 11z. That is, the shape of the outer edge of the protective layer 11z of the semiconductor device according to the comparative example is equivalent to the shape of the outer edge of the protective conductive region (11a, 11b) of the semiconductor device according to the embodiment of the present invention, but the inner conductivity type is a high concentration p + Only the type is formed, and no inversion layer is formed. The concentration of the impurity element in the protective layer 11z of the semiconductor device according to the comparative example is, for example, 5.0×10 18 cm -3 On the other hand, the concentration of impurity elements in the conductive path forming layer 11b of the protective conductive region (11a, 11b) of the semiconductor device according to the embodiment of the present invention is 4.0×10, which is the same as the concentration in the drift region 2. 17 cm -3 It is set fairly low.

[0030] 4, the main current I L 1,I R 1 and the main current I in the semiconductor device according to the comparative example shown in FIG. L z,I R 4, the flow of the main current I z in the semiconductor device according to the embodiment of the present invention is illustrated by a solid line. L 1,I R 1 is the inversion layer 11b inv After entering the interior of the trench 4 from the side end face, the gas flows smoothly and curves to approach the side wall of the trench 4 .

[0031] On the other hand, in the comparative example illustrated by the dashed line, the main current I L z,I R The main current Iz cannot pass through the inside of the protective layer 11z in the path from the upper side of the protective layer 11z to the side wall of the trench 4. L z,I RThe main current Iz is forced to travel along a significantly bent path that is longer than the path in the embodiment of the present invention, along the stepped shape of the outer edge of the protective layer 11z. L 1,I R 1 The overall path length can be shortened, and the on-resistance can be reduced accordingly.

[0032] 5 shows the relationship between the impurity element concentration of the conductive path forming layer 11b in the protective conductive region (11a, 11b) and the on-resistance Ron of the semiconductor device. It can be seen that the on-resistance Ron decreases as the impurity element concentration of the conductive path forming layer 11b decreases. th 1, the peak concentration of the channel regions 3a1 and 3b1 of the semiconductor device is 3.0×10 17 cm -3 In this case, the positions where the threshold voltages of the channel regions 3a1 and 3b1 exist are visually shown.

[0033] The solid vertical line L in Figure 5 th In the range to the left of 1, the on-resistance Ron is th As the impurity element concentration in the conductive path forming layer 11b decreases, the locus of the solid line connecting the plotted points indicated by the white circles becomes flatter. th In the range to the right of 1, the on-resistance Ron is th As the impurity element concentration in the conductive path formation layer 11b increases, the locus of the solid line connecting the plotted points approaches a flat line.

[0034] Also, the dashed vertical line L in Fig. 5 th 2, the peak concentration of the channel regions 3a1 and 3b1 of the semiconductor device is 4.0×10 17 cm -3 In this case, the vertical line L visually indicates the position where the threshold voltage of the channel regions 3a1 and 3b1 exists. th In the range to the left of 2, the peak concentration of the channel regions 3a1 and 3b1 is 3.0 × 10 17 cm -3As in the case of th As the impurity element concentration in the conductive path forming layer 11b decreases, the locus of the solid line connecting the plotted points indicated by the white circles becomes flatter. th In the range to the right of 2, the on-resistance Ron is th 2 is higher overall than the range to the left of the impurity element concentration in the conductive path formation layer 11b, and as the impurity element concentration in the conductive path formation layer 11b increases, the locus of the broken line connecting the plotted points approaches a flat line.

[0035] In the semiconductor device according to the embodiment of the present invention, a conductive path forming layer 11b in which an inversion layer is formed when the device is on is provided on the protective layer 11a that protects the gate insulating film 5 at the bottom of the trench 4. Therefore, the main current I L 1,I R 1 path to inversion layer 11b inv By inducing the main current I L 1,I R Therefore, it is possible to realize a semiconductor device that can protect the gate insulating film 5 at the bottom of the trench 4 and reduce the on-resistance at the same time.

[0036] <Method of manufacturing a semiconductor device> Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 6 to 14. First, as shown in FIG. 6, for example, + 4H-SiC semiconductor substrate 1 sub A semiconductor substrate 1 is prepared by epitaxial growth. sub An n-type 4H—SiC semiconductor layer is epitaxially grown on top of this to form drift region 2. Next, a first mask film 16 is deposited to a predetermined thickness on the upper surface of drift region 2. As first mask film 16, a silicon oxide (SiO2) film or silicon nitride (Si3N4) film formed by thermal oxidation or deposited by chemical vapor deposition (CVD) or the like can be used.

[0037] Next, a photoresist film is applied onto the first mask film 16 by photolithography, etching, or the like, and the photoresist film is patterned. Then, as shown in Fig. 7, using the patterned photoresist film as a mask, portions of the first mask film 16 located above the regions where trenches 4 are to be formed are selectively removed to form windows. The windows can be formed by etching techniques such as reactive ion etching (RIE).

[0038] After removing the photoresist film, first mask 16p having windows is used as an ion implantation mask to implant ions of an impurity element such as Al into drift region 2 by multi-stage ion implantation or the like to form protective layer-planned region 11a0. Note that the photoresist film used in etching first mask film 16 may be left on drift region 2 without being removed, and used as an ion implantation mask together with first mask 16p.

[0039] Next, as shown in FIG. sub The structure (hereinafter simply referred to as "semiconductor substrate 1") has a sub The protective layer-planned region 11a0 is activated by vacuum annealing or the like, and p + A protective layer 11a for the mold is formed so that both ends of the protective layer 11a extend outward by a certain width w beyond the width of the trench 4 to be formed later.

[0040] 9, drift region 2 is excavated by etching such as RIE using a first mask 16p having a window portion in succession to form trenches 4. The position of trench 4 is controlled so that the distance between the bottom surface and the lower surface of protective layer 11a is equal to the thickness t of protective conductive regions (11a, 11b) to be formed later.

[0041] Next, semiconductor substrate 1 subAfter cleaning and removing the first mask 16p, a second mask film 17 is deposited to a predetermined thickness on the exposed upper surface of the drift region 2, as shown in Fig. 10. As the second mask film 17, for example, a protective film such as an SiO2 film deposited by a plasma CVD method or the like can be used.

[0042] Next, a photoresist film is applied onto the second mask film 17 by photolithography, etching, or the like, and the photoresist film is patterned. Then, using the patterned photoresist film as a mask, the portions of the second mask film 17 located above the trenches 4 are selectively removed by RIE or the like to form windows, exposing the bottoms of the trenches 4 as shown in Fig. 11. At this time, the opening dimensions of the windows are adjusted so that the sidewall portions of the second mask film 17 on the trenches 4 remain.

[0043] 12, ion implantation is performed through a second mask 17p having a window formed therein to form a conductive path formation layer region 11b0 between the protective layer 11a and the bottom of the trench 4 within the drift region 2. The ion implantation is performed by controlling the implantation depth of p-type impurity element ions such as Al. During the ion implantation, the sidewalls of the trench 4 are protected by the second mask 17p.

[0044] Next, semiconductor substrate 1 sub The conductive path formation layer planned region 11b0 is activated by vacuum annealing or the like. Through activation, the conductive path formation layer 11b, which will be the second layer of the protective conductive region (11a, 11b), is formed to have a projecting width planned to shorten the path length of the main current. Then, the second mask 17p remaining on the structure is removed by etching or the like to expose the top surface of the drift region 2 and the sidewall of the trench 4, as shown in FIG. 13, and the semiconductor substrate 1 is sub The material is then subjected to cleaning and other treatments.

[0045] Next, as shown in Figure 14, an insulating film such as an SiO2 film is deposited on the surface of the drift region 2, including the inside of the trench 4, by thermal oxidation or other processes. The deposited insulating film is then patterned using photolithography and dry etching to form a gate insulating film 5. A doped polysilicon film doped with an n-type impurity element is then deposited on the entire upper surface of the drift region 2 by low-pressure CVD or other processes. After that, the doped polysilicon film is embedded inside the trench 4 by etch-back or chemical mechanical polishing (CMP) or other processes to form a gate electrode 6.

[0046] Thereafter, photolithography, etching, ion implantation, and the like are used to provide first under-contact base regions 13a, 13b and second under-contact base regions 14a, 14b in predetermined patterns in this order in the regions between the trenches 4 inside the drift region 2. Next, base regions 3a, 3b are similarly provided in the regions between the trenches 4 inside the drift region 2. When the base regions 3a, 3b are formed by implanting ions of a p-type impurity element such as Al, the ions are implanted so that the peak dose of the implanted ions is higher than the dose of the impurity element ions used to form the conductive path-forming layer 11b.

[0047] In other words, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, the ion dose during formation of the conductive path-forming layer 11b is lower than the peak ion dose during formation of the base regions 3a, 3b. By controlling the respective doses, the concentration of the impurity element during formation of the conductive path-forming layer 11b is realized to be lower than the peak concentration of the impurity element in the channel regions 3a1, 3b1, as shown in FIG.

[0048] Thereafter, the base contact regions 12a, 12b and the source regions 7a, 7b are formed in a predetermined pattern within the base regions 3a, 3b using photolithography, etching, ion implantation, etc. Then, an interlayer insulating film 8 such as an SiO2 film is deposited over the gate electrode 6, the base contact regions 12a, 12b, and the source regions 7a, 7b using a CVD method, etc.sub The lower surface of the drain region 1 is thinned and flattened by CMP or the like to form the drain region 1. A metal film such as nickel (Ni) is then formed under the drain region 1, and the formed metal film is patterned to form the drain electrode 10.

[0049] Then, after performing a predetermined annealing process as necessary, a barrier metal layer 15, which is a laminate of three metal layers, for example, a Ti layer, a TiN layer, and a Ti layer, is formed by vacuum deposition, sputtering, CVD, etc. The barrier metal layer 15 is provided over the interlayer insulating film 8, the source regions 7a and 7b, and the base contact regions 12a and 12b.

[0050] Then, for example, an alloy film containing Al as a main component is deposited on the barrier metal layer 15 and patterned into a predetermined shape by photolithography, etching, or the like to form the source electrode 9. Thereafter, a sintering process such as annealing is performed. Through the above series of steps, the semiconductor device according to the embodiment of the present invention can be obtained.

[0051] According to the method for manufacturing a semiconductor device of an embodiment of the present invention, by providing a protective layer 11a and a conductive path forming layer 11b, it is possible to manufacture a semiconductor device that can simultaneously protect the gate insulating film 5 at the bottom of the trench 4 and reduce the on-resistance.

[0052] Furthermore, in the semiconductor device manufacturing method according to the embodiment of the present invention, the protective layer 11a is formed longer than the width of the trench 4 so that both ends extend outward from the trench 4 by a certain width w. Here, it is possible to align the length of the protective layer 11a with the length of the trench 4. However, in semiconductor device manufacturing sites where photolithography is heavily used, if the width of the protective layer 11a is set to the same value as the width of the trench 4, transfer misalignment due to limitations in current alignment accuracy may be unavoidable. Transfer misalignment may result in a portion where the protective layer 11a and the trench 4 do not overlap, resulting in insufficient protection of the gate insulating film 5. In the semiconductor device according to the embodiment of the present invention, the width of the protective layer 11a is intentionally ensured to be sufficiently longer than the width of the trench 4, thereby ensuring reliable protection of the gate insulating film 5 at the bottom of the trench 4 even if transfer misalignment occurs.

[0053] In the method for manufacturing a semiconductor device according to the embodiment of the present invention, trench 4 is first excavated, and then ions are implanted through the space inside trench 4 to form conductive path-forming layer 11b. This allows for shallow ion implantation to be performed easily and without increasing processing energy. Furthermore, conductive path-forming layer 11b is formed shallowly directly below trench 4 so that its upper surface contacts the lower surface of gate insulating film 5, making ion implantation even easier.

[0054] In the method for manufacturing a semiconductor device according to an embodiment of the present invention, the dose of impurity element ions during the formation of the conductive path-forming layer 11b is controlled to be lower than the peak dose of impurity element ions during the formation of the base regions 3a, 3b. Because ion implantation equipment that is widely used as existing manufacturing equipment can be used as is, the semiconductor device according to an embodiment of the present invention can be manufactured with reduced investment in new equipment.

[0055] Furthermore, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, the same first mask 16p is used in both the process of excavating the trench 4 and the ion implantation process for forming the protective layer 11a. Since there is no need to change masks between the two processes, the manufacturing process can be simplified and the burden can be reduced.

[0056] In the method for manufacturing a semiconductor device according to the embodiment of the present invention, the protective layer 11a and the conductive path-forming layer 11b are formed by controlling the concentration and thickness t separately from the first under-contact base regions 13a and 13b located at the same depth as the protective conductive regions (11a and 11b). Therefore, the concentration and thickness of the impurity elements in the protective layer 11a and the conductive path-forming layer 11b can be formed with higher accuracy.

[0057] Furthermore, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, the sidewalls of trenches 4 are protected by second mask 17p during ion implantation for conductive path-forming layer 11. This prevents quality degradation of channel regions 3a1, 3b1 of base regions 3a, 3b corresponding to the sidewalls of trenches 4.

[0058] -First modified example- Next, a method for manufacturing a semiconductor device according to a first modification of the embodiment of the present invention will be described with reference to FIGS. + 4H-SiC semiconductor substrate 1 sub A semiconductor substrate 1 is prepared by epitaxial growth. sub An n-type 4H—SiC semiconductor layer is epitaxially grown on top of the drift region 2 to form the drift region 2. Next, a first mask film 16 is deposited to a predetermined thickness on the upper surface of the drift region 2. The first mask film 16 can be an SiO2 film or Si3N4 film formed by thermal oxidation or deposited by CVD or the like. The steps up to this point are the same as those described above with reference to FIG. 6.

[0059] Next, a photoresist film is applied onto the first mask film 16 by photolithography, etching, or the like, and the photoresist film is patterned. Then, as shown in Fig. 15, using the patterned photoresist film as a mask, portions of the first mask film 16 located above the regions where trenches 4 are to be formed are selectively removed to form windows. The windows can be formed by etching techniques such as RIE.

[0060] After removing the photoresist film, first mask 16p with windows is used as an ion implantation mask to implant ions of an impurity element such as Al into drift region 2 by multi-stage ion implantation or the like. Through this implantation, protective layer-planned region 11a1 and conductive path formation layer-planned region 11b3 are formed with different heights so that they have the same impurity element concentration. The photoresist film used in etching first mask film 16 may be left on drift region 2 without being removed, and used as an ion implantation mask together with first mask 16p.

[0061] Next, as shown in FIG. sub The protective layer-planned region 11a1 and the conductive path-forming layer-planned region 11b3 are activated by vacuum annealing or the like, and a p-type protective layer 11a2 and a conductive path-forming layer 11b4 are formed as protective conductive regions. The protective layer 11a2 and the conductive path-forming layer 11b4 are formed so that both ends thereof extend outward by a certain width w beyond the groove width of the trench 4 to be formed later.

[0062] 17, drift region 2 is excavated by etching such as RIE using a first mask 16p having a window portion in succession to form trenches 4. The position of trench 4 is controlled so that the distance between the bottom surface and the lower surface of protective layer 11a2 is a predetermined thickness t.

[0063] Next, semiconductor substrate 1 subAfter cleaning and removing the first mask 16p, as shown in FIG. 18, an insulating film such as an SiO2 film is deposited on the surface of the drift region 2, including the inside of the trench 4, by thermal oxidation or the like. The deposited insulating film is then patterned using photolithography, dry etching, or the like to form a gate insulating film 5. Then, a doped polysilicon film doped with an n-type impurity element is deposited on the entire upper surface of the drift region 2 by low-pressure CVD or the like. Thereafter, the doped polysilicon film is embedded inside the trench 4 by etch-back or chemical mechanical polishing (CMP) or the like to form a gate electrode 6.

[0064] Thereafter, photolithography, etching, ion implantation, and the like are used to provide first under-contact base regions 13a, 13b and second under-contact base regions 14a, 14b in predetermined patterns in this order in the regions between the trenches 4 inside the drift region 2. Next, base regions 3a, 3b are similarly provided in the regions between the trenches 4 inside the drift region 2. When the base regions 3a, 3b are formed by implanting ions of a p-type impurity element such as Al, the ions are implanted so that the peak dose of the implanted ions is higher than the dose of the impurity element ions used to form the conductive path-forming layer 11b.

[0065] In other words, in the method for manufacturing a semiconductor device according to the first modified example of the embodiment of the present invention, the ion dose during the formation of the conductive path-forming layer 11b4 and the protective layer 11a2 is lower than the peak ion dose during the formation of the base regions 3a, 3b. By controlling the respective doses, the concentration of the impurity element during the formation of the conductive path-forming layer 11b4 is realized to be lower than the peak concentration of the impurity element in the channel regions 3a1, 3b1.

[0066] Thereafter, the base contact regions 12a, 12b and the source regions 7a, 7b are formed in a predetermined pattern within the base regions 3a, 3b using photolithography, etching, ion implantation, etc. Then, an interlayer insulating film 8 such as an SiO2 film is deposited over the gate electrode 6, the base contact regions 12a, 12b, and the source regions 7a, 7b using a CVD method, etc. sub The bottom surface of the drain region 1 is thinned and flattened by CMP or the like to form the drain region 1. A metal film such as Ni is then formed under the drain region 1, and the formed metal film is patterned to form the drain electrode 10.

[0067] After performing a predetermined annealing process as necessary, a barrier metal layer 15, which is a three-layer stack of metal layers, for example, a Ti layer, a TiN layer, and a Ti layer, is formed by vacuum deposition, sputtering, CVD, or the like. The barrier metal layer 15 is provided over the interlayer insulating film 8, the source regions 7a and 7b, and the base contact regions 12a and 12b. A nickel silicide layer (not shown) is provided between the barrier metal layer 15 and the source regions 7a and 7b and the base contact regions 12a and 12b.

[0068] Then, for example, an alloy film containing Al as a main component is deposited on the barrier metal layer 15 and patterned into a predetermined shape by photolithography, etching, or the like to form the source electrode 9. Thereafter, a sintering process such as annealing is performed. Through the above series of steps, the semiconductor device according to the embodiment of the present invention can be obtained.

[0069] According to the method for manufacturing a semiconductor device according to the first modified example of the embodiment of the present invention, by providing the protective layer 11a2 and the conductive path-forming layer 11b4, it is possible to manufacture a semiconductor device that can simultaneously protect the gate insulating film 5 at the bottom of the trench 4 and reduce the on-resistance. The protective layer 11a2 and the conductive path-forming layer 11b4 have the same concentration of impurity elements, but by making the concentration lower than that of the base regions 3a, 3b, for example, the conductive path-forming layer 11b4 at the bottom of the trench 4 can be inverted when on.

[0070] Furthermore, in the semiconductor device according to the first modified example of the embodiment of the present invention, the protective layer 11a2 and the conductive path forming layer 11b4 can be formed using the same mask, so that transfer misalignment does not occur.

[0071] -Second variant- Next, semiconductor devices according to modifications of the embodiments of the present invention will be described with reference to Figures 19 to 26. As in the semiconductor device according to a second modification shown in Figure 19, the impurity element concentrations inside the p-type conduction path-forming layers (21b1 to 21b3) whose upper surfaces are provided in contact with the bottoms of the trenches 4 may be made different for each region along the width direction of the trenches 4. The protective conduction regions (21a, 21b1 to 21b3) of the semiconductor device according to the second modification have a two-layer structure made up of the protective layer 21a and the conduction path-forming layers (21b1 to 21b3).

[0072] The conductive path forming layers (21b1 to 21b3) of the semiconductor device according to the second modification have a high concentration p + The central protection region 21b1 has a low concentration p - The left conductive path forming region 21b2 and the right conductive path forming region 21b3 of the mold are provided with approximately the same thickness.

[0073] The central protection region 21b1 is provided on the protection layer 21a directly below the trench 4, and has a width substantially equal to the width of the trench 4, extending in the direction of the trench 4, that is, through the paper on which the drawing is drawn. The impurity element concentration of the central protection region 21b1 is set so that the conductivity type is not inverted and remains p-type even in the on-state.

[0074] The left conduction path-forming region 21b2 has approximately the same thickness as the central protection region 21b1, and, like the central protection region 21b1, extends along the direction of the trench 4. The impurity element concentration of the left conduction path-forming region 21b2 is set to a low concentration that inverts the conductivity type to n-type in the on state.

[0075] The right-side conductive path-forming region 21b3 is provided so as to be symmetrical with the left-side conductive path-forming region 21b2 with respect to the central protection region 21b1. The impurity element concentration of the right-side conductive path-forming region 21b3, like the left-side conductive path-forming region 21b2, is set to a low concentration that inverts the conductivity type to n-type in the on-state. The structure of the semiconductor device according to the second modified example, other than the conductive path-forming layers (21b1 to 21b3), is equivalent to the components with the same names in the semiconductor device according to the embodiment of the present invention shown in FIG. 1, and therefore redundant description will be omitted.

[0076] As shown in FIG. 20, in the semiconductor device according to the second modification, when a gate voltage is applied in the on state, an inversion layer 21b1 is formed in the left conduction path forming region 21b2, similarly to the channel regions 3a1 and 3b1. inv In addition, an inversion layer 21b2 is formed in the right-side conductive path forming region 21b3. inv is formed. inv and inversion layer 21b2 inv is the inversion layer 11b1 of the conductive path forming layer 11b in the semiconductor device shown in FIG. inv As in the case of the main current I L 1,I R 1 forms a conductive path.

[0077] In the semiconductor device according to the second modification, the main current I L 1,I R 1 flows from the bottom of the drift region 2 toward the channel regions 3a1 and 3b1. The main current I L 1,I R In the second modification, both ends of the conductive path-forming layers (21b1 to 21b3) are located at positions that interfere with the path of the main current I. In the second modification, the left conductive path-forming region 21b2 and the right conductive path-forming region 21b3, whose conductivity type is reversed when the conductive path-forming layers (21b1 to 21b3) are provided at both ends of the conductive path-forming layers (21b1 to 21b3). L 1,I R Since the electrons 1 are guided to the sidewalls of the trenches 4 and can pass through a shorter path, the on-resistance of the semiconductor device can be reduced.

[0078] In the first modification, in which the concentration of impurity elements in the conductive path-forming layers (21b1-21b3) decreases in the direction from the center to the outside, the high-concentration central protection region 21b1 can be disposed directly below the bottom of the trench 4. This further improves protection of the gate insulating film 5 when the device is off. Other effects of the semiconductor device according to the second modification are the same as those of the semiconductor device according to the embodiment of the present invention shown in FIG.

[0079] -Third variant- 21, the impurity element concentration inside the p-type conduction path-forming layers (31b1-31b5) whose upper surfaces are provided in contact with the bottoms of the trenches 4 may be varied in more stages than in the second modification along the groove width direction of the trenches 4. The protective conduction regions (31a, 31b1-31b5) of the semiconductor device according to the third modification have a two-layer structure made up of the protective layer 31a and the conduction path-forming layers (31b1-31b5).

[0080] The conductive path-forming layers (31b1 to 31b5) of the semiconductor device according to the third modification have a central protection region 31b1 provided in the center and a first left-side conductive path-forming region 31b2 provided on the left side of the central protection region 31b1 in contact with the central protection region 31b1. A second left-side conductive path-forming region 31b4 is provided next to the first left-side conductive path-forming region 31b2 on the side of the first left-side conductive path-forming region 31b2 opposite to the central protection region 31b1.

[0081] The conductive path-forming layers (31b1-31b5) also have a right-side first-conductive-path-forming region 31b3 provided on the right side of the central protective region 31b1 in contact with the central protective region 31b1. On the opposite side of the right-side first-conductive-path-forming region 31b3 from the central protective region 31b1, a right-side second-conductive-path-forming region 31b5 is provided alongside the right-side first-conductive-path-forming region 31b3. The central protective region 31b1, the left-side first-conductive-path-forming region 31b2, the left-side second-conductive-path-forming region 31b4, the right-side first-conductive-path-forming region 31b3, and the right-side second-conductive-path-forming region 31b5 all have approximately the same thickness and the same p-type conductivity.

[0082] The central protection region 31b1 is provided on the protection layer 31a directly below the trench 4, has approximately the same width as the trench 4, and extends in the direction of extension of the trench 4. The impurity element concentration in the central protection region 31b1 is high enough that no inversion layer is formed even in the on-state. + It is set to maintain its type.

[0083] The left first conductive path-forming region 31b2 and the left second conductive path-forming region 31b4 extend in the same direction as the trench 4, similar to the central protection region 31b1. The impurity element concentration of the left first conductive path-forming region 31b2 is set to a low concentration p-type so that the conductivity type is inverted to n-type in the on-state. The impurity element concentration of the left second conductive path-forming region 31b4 is set to an even lower concentration p-type than that of the left first conductive path-forming region 31b2 so that the conductivity type is inverted to n-type in the on-state. - Set to type It has been done.

[0084] The right-side first conductive path-forming region 31b3 and the right-side second conductive path-forming region 31b5 are provided symmetrically with the left-side first conductive path-forming region 31b2 and the left-side second conductive path-forming region 31b4, with the central protection region 31b1 as the center. The impurity element concentrations of the right-side first conductive path-forming region 31b3 and the right-side second conductive path-forming region 31b5 are mirror-symmetrical with the left-side first conductive path-forming region 31b2 and the left-side second conductive path-forming region 31b4, and are low-concentration p-type and p-type impurities. - The right-side first-conductive-path-forming region 31b3 and the right-side second-conductive-path-forming region 31b5 are also inverted in conductivity type to n-type in the on state, similar to the left-side first-conductive-path-forming region 31b2 and the left-side second-conductive-path-forming region 31b4. The structures of the semiconductor device according to the third modification other than the conductive path-forming layers (31b1 to 31b5) are equivalent to the members of the same names in the semiconductor device shown in FIG. 1, and therefore redundant explanations will be omitted.

[0085] As shown in FIG. 22, in the semiconductor device according to the third modification, when a gate voltage is applied in the on state, an inversion layer 31b2 is formed in the left first conduction path forming region 31b2, similarly to the channel regions 3a1 and 3b1. invIn addition, an inversion layer 31b4 is formed in the left second conductive path forming region 31b4. inv At the same time, an inversion layer 31b3 is formed in the right first conduction path forming region 31b3. inv However, an inversion layer 31b5 is formed in the right second conductive path forming region 31b5. inv are formed. inv , inversion layer 31b3 inv , inversion layer 31b4 in and inversion layer 31b5 inv is the inversion layer 11b1 of the conductive path forming layer 11b in the semiconductor device shown in FIG. inv As in the case of the main current I L 1,I R 1 forms a conductive path.

[0086] In the semiconductor device according to the third modification, the main current I L 1,I R 1 flows from the bottom of the drift region 2 toward the channel regions 3a1 and 3b1. The main current I L 1,I R In the second modified example, both ends of the conductive path-forming layers (31b1 to 31b5) are located at positions that interfere with the path of I. In the second modified example, a first left-side conductive path-forming region 31b2 and a second left-side conductive path-forming region 31b4 are provided on the left end sides of the conductive path-forming layers (31b1 to 31b5). Also, a first right-side conductive path-forming region 31b3 and a second right-side conductive path-forming region 31b5 are provided on the right end sides of the conductive path-forming layers (31b1 to 31b5). The conductivity types of the first left-side conductive path-forming region 31b2, the second left-side conductive path-forming region 31b4, the first right-side conductive path-forming region 31b3, and the second right-side conductive path-forming region 31b5 are all inverted when on. Therefore, when on, the main current I L 1,I R Since the electrons 1 are guided to the sidewalls of the trenches 4 and can pass through a shorter path, the on-resistance of the semiconductor device can be reduced.

[0087] In the second modification, in which the concentration of impurity elements in the conductive path-forming layers (31b1-31b5) decreases in the direction from the center to the outside, it is possible to arrange the high-concentration central protection region 21b1 directly below the bottom of the trench 4. Therefore, as in the first modification, it is possible to further strengthen the protection of the gate insulating film 5 when the device is off. Other effects of the semiconductor device according to the third modification are the same as those of the semiconductor device according to the embodiment of the present invention shown in FIG.

[0088] -Fourth variant- In the second and third modified examples, the conductive path-forming layer having a plurality of regions therein is set so that the impurity element concentration is highest in the central region corresponding to the center of the trench 4 and the concentration decreases in the region extending from the center to the outside. However, as in the semiconductor device according to the fourth modified example shown in Fig. 23, the impurity element concentration inside the p-type conductive path-forming layers (41b1, 41b2) whose upper surfaces are provided in contact with the bottom of the trench 4 may be made to vary along the depth direction of the trench 4. The protective conductive regions (41a, 41b1, 41b2) of the semiconductor device according to the fourth modified example have a two-layer structure consisting of a protective layer 41a and conductive path-forming layers (41b1, 41b2).

[0089] The conductive path forming layers (41b1, 41b2) are composed of a p-type lower conductive path forming region 41b1 located below two layers provided on the protective layer 41a, and a low-concentration p - The lower conductive path forming region 41b1 has both ends extending outward from the trench 4 and extends in the same direction as the trench 4 extends.

[0090] The impurity element concentration of the lower conductive path-forming region 41b1 is set to a low concentration such that the conductivity type is inverted to n-type in the on state. The upper conductive path-forming region 41b2 has approximately the same thickness as the lower conductive path-forming region 41b1 and extends along the extension direction of the trench 4, similar to the lower conductive path-forming region 41b1. The impurity element concentration of the upper conductive path-forming region 41b2 is set to an even lower concentration than that of the lower conductive path-forming region 41b1 so that the conductivity type is inverted to n-type in the on state. The structure of the semiconductor device according to the fourth modification, other than the conductive path-forming layers (41b1, 41b2), is equivalent to the components of the same name in the semiconductor device shown in FIG. 1, so duplicated explanations will be omitted.

[0091] As shown in FIG. 24, in the semiconductor device according to the fourth modification, when a gate voltage is applied in the on state, an inversion layer 41b1 is formed in the lower conduction path forming region 41b1, similarly to the channel regions 3a1 and 3b1. inv In addition, an inversion layer 41b2 is formed in the upper conductive path forming region 41b2. inv An inversion layer 41b1 is formed. inv and inversion layer 41b2 inv is the inversion layer 11b1 of the conductive path forming layer 11b in the semiconductor device shown in FIG. inv As in the case of the main current I L 1,I R 1 forms a conductive path.

[0092] In the semiconductor device according to the fourth modification, the main current I L 1,I R The two ends of the conductive path forming layers (41b1, 41b2) are located at positions that interfere with the path of the main current I L 1,I R The main current I flows from the lower side of the drift region 2 toward the channel regions 3a1 and 3b1. In the fourth modification, a lower conductive path-forming region 41b1 and an upper conductive path-forming region 41b2, whose conductivity type is reversed when the transistor is turned on, are provided at both ends of the conductive path-forming layers (41b1 and 41b2). L 1,I R Since the electrons 1 are guided to the sidewalls of the trenches 4 and can pass through a shorter path, the on-resistance of the semiconductor device can be reduced.

[0093] Furthermore, the concentration of the impurity elements in the conductive path-forming layers (41b1, 41b2) increases from the position contacting the bottom of the trench 4 downward, thereby enabling the concentration to be increased throughout the p-type semiconductor region located below the trench 4. This further strengthens the protection of the gate insulating film 5 when the gate insulating film 5 is off. Other effects of the semiconductor device according to the fourth modification are the same as those of the semiconductor device according to the embodiment of the present invention shown in FIG. 1. The structure of the conductive path-forming layer, the interior of which is divided into multiple parts in the vertical direction, is not limited to the two-layer structure shown in the fourth modification. A conductive path-forming layer can also be realized by using multiple regions of three or more layers, each with an impurity element concentration that increases with depth.

[0094] - Fifth variant - 25, the overhang width of the protective layer 51a and the overhang width of the conductive path forming layer 51b may be equal, and the outer edge of the cross section of the protective conductive region (51a, 51b) consisting of the protective layer 51a and the conductive path forming layer 51b may be rectangular. The impurity element concentration of the conductive path forming layer 51b may be a low concentration p-type impurity that inverts the conductivity type to n-type in the on state. - The structures of the semiconductor device according to the fifth modification, other than the conductive path forming layer 51b, are equivalent to the members of the same names in the semiconductor device shown in FIG.

[0095] As shown in FIG. 26, in the semiconductor device according to the fifth modification, when a gate voltage is applied in the on state, an inversion layer 51b is formed in the conductive path forming layer 51b in the same manner as in the channel regions 3a1 and 3b1. inv is formed. inv is the inversion layer 11b of the conductive path forming layer 11b in the semiconductor device shown in FIG. inv As in the case of the main current I L 2,I R 2 is the conducting Make a road.

[0096] In the semiconductor device according to the fifth modification, the main current I L2,I R Both ends of the conductive path forming layer 51b are located at positions where they interfere with the path of the main current I L 2,I R 2 flows from the lower side of the drift region 2 toward the channel regions 3a1 and 3b1. In the case of the fifth modification, when the transistor is turned on, the inversion layer 51b includes both ends of the conduction path forming layer 51b. inv Therefore, the main current I L 2,I R 2 is guided to the sidewall of trench 4 and can pass through a shorter path, thereby reducing the on-resistance of the semiconductor device. Other effects of the semiconductor device according to the fifth modification are similar to those of the semiconductor device according to the embodiment of the present invention shown in FIG.

[0097] As in the semiconductor device according to the fifth modification, the main current I L 1,I R As long as an inversion layer is formed at a position that interferes with the path through which 1 flows when turned on, the overall shape of the protective conduction region is not limited to one with stepped ends and can be modified as appropriate.

[0098] <Other embodiments> Although the present invention has been described by the above disclosed embodiments, the descriptions and drawings forming part of this disclosure should not be understood as limiting the present invention. It should be understood that various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0099] The structure of the semiconductor device according to the present invention is not limited to the above and can be modified as appropriate according to desired specifications. For example, in addition to the structure of the semiconductor device shown in FIG. 1 , a heavily doped n-type region can be separately provided as a counter-doped layer below the base regions 3a and 3b within the drift region 2 at a depth including the protective conductive regions (11a and 11b). The heavily doped counter-doped layer intentionally concentrates an electric field toward the counter-doped layer rather than toward the trench 4, thereby inducing an avalanche current, thereby further enhancing protection of the gate insulating film 5 at the bottom of the trench 4. When the heavily doped n-type region is provided, the concentration of the added p-type impurity element is set to a value equal to or greater than the concentration of the impurity element in the heavily doped n-type region so that the conductive path-forming layer 11b maintains p-type conductivity when turned off.

[0100] Furthermore, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, when forming the conductive path forming layer 11b by ion implantation, the region of the second mask film 17 corresponding to the bottom of the trench 4 is removed. However, the present invention is not limited to this, and it is also possible to form the conductive path forming layer 11b by performing ion implantation while leaving the region corresponding to the bottom of the trench 4 in place. Eliminating the step of partially removing the second mask film 17 simplifies the manufacturing process.

[0101] In the semiconductor device manufacturing method according to the embodiment of the present invention, as shown in FIGS. 7 and 12, the protective layer 11a and the conductive path-forming layer 11b are formed by vertical ion implantation. However, in the present invention, the ion implantation direction is not limited to the vertical direction, and oblique ion implantation can also be performed. For example, even if the diffusion coefficient of impurities in SiC is very small and the intended overhang width of the protective layer 11a and the conductive path-forming layer 11b cannot be sufficiently achieved by vertical ion implantation alone, the desired overhang width can be achieved by oblique ion implantation. Note that during oblique ion implantation, protecting the trench sidewalls with a mask or the like can prevent ion irradiation to the sidewalls, thereby suppressing quality degradation.

[0102] Furthermore, for example, during diffusion in forming the protective layer 11a or the conductive path forming layer 11b, ultraviolet light from an excimer laser or the like can be irradiated at an oblique angle similar to that in the case of oblique ion implantation to promote diffusion by photoexcitation. Promotion of diffusion by photoexcitation or the like is effective in cases where the diffusion coefficient of impurities in SiC is so small that the protective layer 11a and the conductive path forming layer 11b cannot be sufficiently diffused by heat treatment alone.

[0103] In the method for manufacturing a semiconductor device according to the embodiment of the present invention, the base regions 3a, 3b are formed using ion implantation, but they can also be formed by other methods such as epitaxial growth. Even in the case of epitaxial growth, the doping epi concentration in the channel region of the base region is adjusted to be higher than the concentration of impurity element ions in the conductive path-forming layer, and a low concentration is achieved so that an inversion layer is formed when the conductive path-forming layer is on.

[0104] 1 to 26. The semiconductor device according to the present invention can also be realized by partially combining the structures of the semiconductor devices shown in Figures 1 to 26. As described above, the present invention includes various embodiments not described above, and the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description. [Explanation of symbols]

[0105] 1. Drain region 1 sub semiconductor substrate 2 Drift region 3a, 3b Base region 3a1, 3b1 Channel region 4. Trench 5 Gate insulating film 6 gate electrode 7a,7b Source region 8 Interlayer insulating film 9 Source electrode 10 Drain electrode 11a,11a2 Protective layer 11a0, 11a1 Protective layer planned area 11b,11b4 Conductive path forming layer 11b0, 11b3 Conductive path forming layer planned area 11b1 First conductive path formation area 11b1 inv inversion layer 11b2 Second conductive path forming area 11b2 inv inversion layer 11b inv inversion layer 11c Central protection area 11z protective layer 12a, 12b base contact region 13a, 13b: first contact under base region 14a, 14b: second contact under base region 15 Barrier metal layer 16. First mask coating 16p 1st Mask 17 Second mask membrane 17p 2nd Mask 21a Protective layer 21b1 Central protection area 21b1 inv inversion layer 21b2 Left side conductive path formation area 21b2 inv inversion layer 21b3 Right side conductive path formation area 31a Protective layer 31b1 Central protection area 31b2 Left side first conductive path formation area 31b2 inv inversion layer 31b3 Right side first conductive path formation area 31b3 inv inversion layer 31b4 Left side second conductive path formation area 31b4 inv inversion layer 31b5 Second conductive path formation area on the right side 31b5 inv inversion layer 41a Protective layer 41b1 Lower conductive path formation area 41b2 Upper conductive path formation area 41b1 inv inversion layer 41b2 inv inversion layer 51a Protective layer 51b Conductive path forming layer 51b inv inversion layer I L 1,I R 1 Main current I L 2,I R 2 Main current I L z,I R z Main current d Thickness w width

Claims

1. A semiconductor device comprising: a trench including an extension portion extending in a first direction, the extension portion being arranged in a second direction at intervals; an insulating film provided inside the trench; and a p-type protection region provided below the trench, the p-type protection region including a first protection layer and a second protection layer, a first main electrode region of a first conductivity type including a portion provided along a sidewall of a first trench, which is one of the trenches; a base region of a second conductivity type provided under the first main electrode region; Further provided with a concentration of an impurity element in the second protective layer provided between the first protective layer and a bottom of the first trench in a depth direction is lower than a peak concentration of an impurity element in a first region of the base region along a sidewall of the first trench; the first protective layer has a higher concentration of an impurity element than the base region; The first protective layer and the second protective layer extend in the first direction and have a rectangular shape in a cross section perpendicular to the first direction. Semiconductor device.

2. A semiconductor device comprising: a trench including an extension portion extending in a first direction, the extension portion being arranged in a plurality of intervals in a second direction; an insulating film provided inside the trench; and a p-type protective region provided below the trench and including a first protective layer and a second protective layer, a first main electrode region of a first conductivity type including a portion provided along a sidewall of a first trench, which is one of the trenches; a base region of a second conductivity type provided under the first main electrode region; Further provided with a concentration of an impurity element in the second protective layer provided between the first protective layer and a bottom of the first trench in a depth direction is lower than a peak concentration of an impurity element in a first region of the base region along a sidewall of the first trench; the first protective layer has a higher concentration of an impurity element than the base region; The peak concentration is 3×10 17 cm -3 ~4×10 17 cm -3 is Semiconductor device.

3. A semiconductor device comprising: a trench including an extension portion extending in a first direction, the extension portion being arranged in a plurality of intervals in a second direction; an insulating film provided inside the trench; and a p-type protective region provided below the trench and including a first protective layer and a second protective layer, a first main electrode region of a first conductivity type including a portion provided along a sidewall of a first trench, which is one of the trenches; a base region of a second conductivity type provided under the first main electrode region; Further provided with a concentration of an impurity element in the second protective layer provided between the first protective layer and a bottom of the first trench in a depth direction is lower than a peak concentration of an impurity element in a first region of the base region along a sidewall of the first trench; the first protective layer has a higher concentration of an impurity element than the base region; The first protective layer has a cross-sectional shape in which the width in the second direction is greater than that of the second protective layer. Semiconductor device.

4. The first protective layer and the second protective layer have a cross-sectional shape that extends beyond the bottom of the first trench in the second direction. The semiconductor device according to claim 1 .

5. The protection area is composed of three or more layers, The second protective layer is provided in contact with the bottom of the first trench. The semiconductor device according to claim 1 .

6. A semiconductor device comprising: a trench including an extension portion extending in a first direction, the extension portion being arranged in a second direction at intervals; an insulating film provided inside the trench; and a p-type protection region provided below the trench, the p-type protection region including a first protection layer and a second protection layer, a first main electrode region of a first conductivity type including a portion provided along a sidewall of a first trench, which is one of the trenches; a base region of a second conductivity type provided under the first main electrode region; Further provided with The protection area is composed of three or more layers, the second protective layer is provided in contact with a bottom portion of the first trench, The first protective layer and the second protective layer extend in the first direction and have a rectangular shape in a cross section perpendicular to the first direction. Semiconductor device.

7. the protective region includes a third protective layer below the second protective layer, the third protective layer having a higher concentration of an impurity element than the second protective layer; The first protective layer is provided under the third protective layer and has a higher concentration of impurity elements than the third protective layer.

7. The semiconductor device according to claim 5.

8. The concentration of the impurity element in the second protective layer is 8.0×10 15 cm -3 That's all The semiconductor device according to claim 1 .

9. a second trench, one of the trenches, adjacent to the first trench; a p-type base contact region provided between the first trench and the second trench; Equipped with The base contact region has a higher concentration of impurity elements than the base region and the second protective layer. The semiconductor device according to claim 1 .

10. a polysilicon film electrode provided inside the insulating film; The semiconductor device is a trench SiC-MOSFET. The semiconductor device according to claim 1 .

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