Low-overhead, high-bandwidth reconfigurable interconnect apparatus and method

Abstract

A low-overhead method and apparatus are described for reconfiguring a buffer interconnect link pair to operate in one of these three modes: a first mode (e.g., bandwidth mode), a second mode (e.g., latency mode), and a third mode (e.g., energy mode). In bandwidth mode, each link in the buffer interconnect link pair sends a unique signal from source to destination. In latency mode, both links in the pair send the same signal from source to destination, with one link in the pair being called the "primary" and the other the "assist." This time alignment of transitions in the buffer interconnect pair reduces the effective capacity of the primary, thereby reducing delay or latency. In energy mode, only one link in the pair (the primary) sends a signal while the other link in the pair is idle. An idle neighbor on one side reduces the energy consumption of the primary.

Description

[Technical Field]

[0001] (Reference to Related Application) This application claims priority to U.S. patent application Ser. No. 16 / 576,687, entitled "LOW OVERHEAD, HIGH BANDWIDTH RE-CONFIGURABLE INTERCONNECT APPARATUS AND METHOD," filed Sep. 19, 2019, the entire contents of which are incorporated by reference for all purposes. [Background technology]

[0002] Today, a single product design is required to operate at different power supply voltages. For example, the same processor may be designed to operate at a high-voltage power supply (e.g., 1.2V) and a low-voltage power supply (e.g., 0.5V). The power supply voltage (or voltage range) may be selected and fixed according to the performance and power requirements of a market segment (e.g., tablet, laptop, desktop, etc.). For example, a processor for the desktop market segment may operate at a higher voltage, providing a higher frequency and processing speed (e.g., higher performance), while the same processor for the tablet or laptop market segment may operate at a lower voltage and a lower frequency and processing speed. In most cases, a processor may be required to support a range from a minimum operating voltage (VMIN) to a maximum operating voltage (VMAX). The voltage may also be dynamically adjusted during operation (e.g., low power mode, normal mode, turbo mode, etc.).

[0003] For large heterogeneous platforms, low latency, low energy, and high bandwidth network-on-chip (NoC) are critical to maintaining performance compound annual growth rates (CAGRs) within a power envelope. Despite careful design, NoC fabrics (RING, MESH, or other topologies) struggle to meet competing demands for latency, bandwidth, and energy, often making trade-offs with one another. Specifically, the latency, bandwidth, and energy of NoC fabrics are often limited by long repeated / buffered wires / interconnects. For example, the latency, bandwidth, and energy of NoC fabrics are in turn limited by the buffered interconnects connecting two MESH or RING stops. For example, buffered interconnects constitute buses of 1000s of wires, typically spanning several millimeters across the chip and subject to dynamic voltage and frequency scaling (DVFS) to achieve high performance within the power envelope. Buffer interconnects are optimized by careful selection of repeater-to-repeater distance, buffer size, wire layer, wire width, wire spacing, etc. Technology scaling and wide operating ranges further exacerbate this challenge.

[0004] Embodiments of the present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure, which should not be understood to limit the disclosure to the particular embodiments, but are for illustration and understanding only. [Brief explanation of the drawings]

[0005] [Figure 1A] 1 illustrates a reconfigurable interconnect in high-speed mode.

[0006] [Figure 1B]1 shows a reconfigurable interconnect in a low energy mode.

[0007] [Figure 2] 1 illustrates a network-on-chip (NoC) including a 3x3 MESH with reconfigurable interconnects according to some embodiments.

[0008] [Figure 3] 1 shows a baseline iterative bus interconnect design.

[0009] [Figure 4] 1 illustrates a tri-mode reconfigurable interconnect according to some embodiments.

[0010] [Figure 5] 1 illustrates a tri-mode reconfigurable interconnect in bandwidth mode according to some embodiments.

[0011] [Figure 6] 1 illustrates a tri-mode reconfigurable interconnect in latency mode according to some embodiments.

[0012] [Figure 7] 1 illustrates a tri-mode reconfigurable interconnect in energy modes according to some embodiments.

[0013] [Figure 8A] 10 shows a plot illustrating bandwidth modes according to some embodiments. [Figure 8B] 10 shows a plot illustrating a latency mode according to some embodiments.

[0014] [Figure 9A] 10 shows a plot illustrating bandwidth modes according to some embodiments. [Figure 9B] 10 shows a plot illustrating a latency mode according to some embodiments.

[0015] [Figure 10] 1 illustrates a tri-mode reconfigurable interconnect with 3x repeat wires according to some embodiments.

[0016] [Figure 11] 1 illustrates a SOC or NoC with a tri-mode reconfigurable interconnect according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0017] The power and performance benefits of resistive interconnects are strongly dependent on power supply voltage. Thus, designs that operate best at low voltages operate less efficiently at high voltages, and vice versa. Adapting one design for different market segments and power modes offers design and manufacturing efficiencies but compromises performance and energy. This compromise can become more severe as interconnect resistance increases with scaling.

[0018] Current solutions for designing logic or processors with resistive interconnects are limited to two suboptimal approaches. In the first approach, an integrated circuit (IC) design is optimized for a given performance point (e.g., high performance or low power). In this case, other performance-targeted products suffer from operating significantly less than optimal performance. For example, an IC design optimized to operate at high performance (e.g., high frequency) may result in suboptimal power efficiency for a product operating at low voltage and low frequency because more power is consumed than the minimum actually required to operate at the lower performance.

[0019] Some embodiments provide a low-overhead method and apparatus for reconfiguring a pair of buffered interconnect links operating in one of these three modes: a first mode (e.g., bandwidth mode), a second mode (e.g., latency mode), and a third mode (e.g., energy mode). In bandwidth mode, each link in the pair of buffered interconnect links sends a unique signal from source to destination. In latency mode, both links in the pair send the same signal from source to destination, with one link in the pair being called the "primary" and the other the "assist." Time alignment of transitions in this pair of buffered interconnects reduces the effective capacity of the primary, thereby reducing delay or latency. In energy mode, only one link in the pair (i.e., the primary) sends a signal, and the other link in the pair is idle. Idle neighbors on either side reduce the energy consumption of the primary. These interconnects are part of a MESH or RING network (e.g., in a network-on-chip (NOC)). In some embodiments, arbiter circuits (e.g., MESH-stop and RING-stop) work in coordination with a master fabric controller (e.g., in a power management unit) to dynamically adapt buffered interconnect links to workload needs.

[0020] There are many technical effects of various embodiments. For example, the reconfigurable interconnect enables on-the-fly reconfiguration of the latency, bandwidth, and energy of the fabric. While delay and energy can be adjusted through dynamic voltage-frequency scaling, the reconfigurable interconnect provides powerful and reliable knobs for adjusting delay (e.g., latency), energy, and bandwidth. The reconfigurable interconnect enables these benefits without the use of additional wiring or any new process enhancements or sophisticated custom circuitry. The reconfigurable interconnect offers chip designers the potential to unify the design / optimization of physically buffered interconnect links, because pairs under the same physical link can be controlled and operated in different modes to achieve a range of latency, bandwidth, and energy targets. For example, the NoC / fabric interconnect configuration maintains inter-core communication (including processor core to lower-level-cache (LLC) communication), core to main memory communication, and core to I / O communication, which means that the lower latency and higher bandwidth fabric from the reconfigurable interconnect enables significant improvements in power performance for a variety of workloads. Other technical effects are apparent from the various embodiments and figures.

[0021] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present disclosure.

[0022] It should be noted that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate signal paths through more components and / or may have arrows at one or more ends to indicate the direction of primary information flow. Such designations are not intended to be limiting. Rather, lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or logic unit. Any represented signal, as dictated by design needs or preferences, may actually include one or more signals that may travel in either direction and may be implemented with any suitable type of signaling.

[0023] Throughout the specification and in the claims, the term "connected" means a direct connection, such as an electrical, mechanical, or magnetic connection, between the things that are connected, without any intermediate devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices.

[0024] The term "circuit" or "module" may refer to one or more passive and / or active components configured to cooperate with each other to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meaning of singular terms ("a," "an," and "the") includes plural references. The meaning of "in" includes "in" and "on."

[0025] The term "scaling" generally refers to converting a design (diagram and layout) from one process technology to another, with a subsequent reduction in layout area. The term "scaling" also generally refers to miniaturizing layouts and devices within the same technology node. The term "scaling" can also refer to adjusting other parameters, such as signal frequency relative to power supply levels (e.g., slowing down or speeding up, i.e., scaling down or scaling, respectively). The term "scaling" can also refer to adjusting the magnitude of power supply voltages to a circuit (e.g., voltage scaling).

[0026] "Substantially," "close," "approximately," "near," and "about" generally mean within + / - 10% of a target value. Unless otherwise specified, the use of ordinal adjectives such as "first," "second," and "third" to describe a common object merely indicates that different instances of a similar object are being referenced and is not intended to imply that the objects so described must be in a given order, temporally, spatially, in ranking, or in any other way.

[0027] The terms so used should be understood to be interchangeable under appropriate circumstances, such as when the embodiments of the invention described herein are operable in other orientations than those illustrated or otherwise described herein.

[0028] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). Terms such as "left," "right," "front," "back," "top," "bottom," "over," "under," and equivalents in this specification and claims, if present, are used for descriptive purposes and are not necessarily used to describe permanent relative positions.

[0029] For purposes of the embodiments, the transistors in the various circuits, modules, and logic blocks may be tunneling FETs (TFETs), or some transistors in various embodiments may include metal oxide semiconductor (MOS) transistors, including drain, source, gate, and bulk terminals. The transistors may also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Square Wire or Rectangular Ribbon Transistors, or other devices implementing transistor functionality, such as carbon nanotube or spintronic devices. The symmetrical source and drain terminals of a MOSFET are the same terminal and are used interchangeably herein. TFET devices, on the other hand, have asymmetrical source and drain terminals. Those skilled in the art will understand that other transistors, such as bipolar junction transistors—BJT PNP / NPN, BiCMOS, CMOS, etc., may be used for some transistors without departing from the scope of this disclosure.

[0030] As the power supply voltage (VDD:) for the processor or logic increases, the buffer interconnect becomes more wire-limited than device-limited (because device delay decreases with VDD, while wire delay does not decrease with VDD). To simultaneously enable lower delay at high VDD and lower power at low VDD, a reconfigurable interconnect can be used. In a typical reconfigurable interconnect, every buffer interconnect gets another identical buffer interconnect (driver and wire) as an "assist." The reconfigurable interconnect operates in two modes: a high-speed mode and a low-energy mode, as shown in Figures 1A-1B.

[0031] FIG. 1A shows reconfigurable interconnect architecture 100 in high-speed mode. FIG. 1B shows reconfigurable interconnect architecture 120 in low-energy mode. Architecture 100 shows wires 101a, 101b, 101c, and 101d, drivers (inverters) 102a, 102b, 102c, and 102d, and receivers (inverters) 103a, 103b, 103c, and 103d. The reconfigurable portion of the interconnect receives input "In" and provides output "Out." The reconfigurable portion of the interconnect consists of drivers 102a and 102b, wires 101b and 101c, and receivers 103a and 103b, where driver 102b is a tri-state driver (controlled by an enable signal) and receiver 103b is a tri-state receiver controllable by an enable signal.

[0032] Here, the capacitance C ab is the coupling capacitance between the wire 101a and the wire 101b, and the capacitance C bc is the coupling capacitance between wire 101b and wire 101c, and capacitance C cdis the coupling capacitance between wire 101c and wire 101d. In high-speed mode, as shown by Figure 1A, the time alignment of transitions on primary interconnect 101b and assist interconnect 101c reduces the effective cross-coupling capacitance between primary interconnect 101b and assist 101c, thereby reducing the delay and energy from input In to output Out. In low-energy mode, as shown in Figure 1B, the assist buffer interconnect is tri-stated and idle, which results in energy savings.

[0033] The reconfigurable interconnect of Figures 1A-1B is effective only in scenarios where wiring resources are not constrained. Furthermore, the tri-state inverters 102b and 103b in the assist path consume silicon area. For example, the high-speed mode configuration of Figure 1A reduces delay by reducing the effective wire capacitance of primary interconnect 101b when transitions in primary interconnect 101b and assist interconnect 101c are temporarily aligned, and the cross-coupling capacitance Cbc between them is reduced or eliminated. In the low-energy mode configuration of Figure 1B, assist interconnect 101c is disabled, reducing dynamic power. However, reconfigurable interconnect architecture 100 / 120 requires an additional wiring track for assist wire 101c.

[0034] 2 illustrates a network-on-chip (NoC) architecture including a 3x3 MESH with reconfigurable interconnects according to some embodiments. The NoC architecture 200 includes a power management unit (PMU) 201, and the MESH network includes routers, nodes, and / or arbiters 202. In this example, the 3x3 MESH network includes routers, nodes, and / or arbiters 202. 1.1 ~202 3.32. Each router, node, and / or arbiter has an interface for receiving mode control device 203 and an interface (e.g., driver and receiver) for coupling to traffic interconnect 204. In some embodiments, buffer interconnect 204 is typically a regular inverter path; tri-state inverters are not needed in the assist path, and by extension, control signals for tri-state inverters are not needed. Thus, the techniques of various embodiments are compatible with and readily employable for static timing analysis.

[0035] In some embodiments, the operating mode of the buffer interconnect is determined by the master fabric controller (or power management unit 201), which may be the same unit that controls dynamic voltage and frequency scaling (DVFS). In some embodiments, controller 201 sends the operating mode to every MESH-STOP or RING-STOP, where MESH-STOP or RING-STOP is a router, node, and / or arbiter 202. MESH-STOP and RING-STOP then determine and drive signals to the inputs of the buffer interconnect pair (depending on the operating mode). For example, based on the operating mode, the buffer interconnect pair is appropriately driven with unique signals (bandwidth mode), the same signals (latency mode), or no assist is driven (energy mode). In some embodiments, PMU 201 dynamically determines the operating mode of the interconnect fabric using operating system (OS) hints and / or on-chip power-performance counters.

[0036] For example, for latency-critical workloads, the OS issues a latency mode to PMU 201, and PMU 201 configures the arbiter in latency mode to reduce delay in the NOC to meet frequency requirements. For latency-non-critical workloads, the OS enables PMU 201 to perform DVFS, which reduces both power supply voltage and frequency to save energy, and PMU 201 configures the arbiter to be in energy mode, which reduces energy consumption of the NOC. For workloads requiring high bandwidth (e.g., data movement, memory access, etc.) that cannot be supported by boosting operating frequency with DVFS, PMU 201 can configure the arbiter to be in bandwidth mode, which communicates using available interconnects.

[0037] In traditional reconfigurable interconnects, such as those in Figures 1A-1B, performance-power tuning of buffer interconnects is typically limited to buffer and wire optimization. In some embodiments, MESH-STOP can affect the delay and energy of buffer interconnects by controlling the operating mode. This provides knobs for micro-architects and architects to tune fundamental fabric parameters in the architecture.

[0038] Compared to other logic controllers, a master fabric controller such as PMU 201 can better respond to bandwidth or latency requirements by controlling the operating mode of the MESH stops and then buffer interconnect links, which provides additional degrees of freedom beyond operating VDD and frequency (with DVFS).

[0039] 3 shows a baseline iterative bus interconnect design 300. The baseline design 300 shows an example of an interconnect between two possible MESH or RING-stops. In this example, the MESH or RING-stop is connected to a router (node ​​or arbiter) 302. 1.1 and 302 1.2 Two signal paths (or traffic interconnects) 304 are shown. The first signal path starts at input In1 and terminates at output Out1. The second signal path starts at input In2 and terminates at output Out2. Each signal path is a repeater bus interconnect with optimized inter-repeater distance, repeater size, wire layer, width, and inter-wire spacing. In this example, repeater 304a is shown as an inverter (which can also be implemented as a non-inverting buffer) and wire 304b. Passive shields are used to reduce Miller coupling capacitance between adjacent wires. In this example, the passive shields are power (Vcc) or ground (Vss) interconnects. Reverse-traveling signals also reduce Miller coupling capacitance. In this example, signal In1 propagates from right to left, while signal In2 propagates from left to right.

[0040] 4 illustrates a tri-mode reconfigurable interconnect 400 according to some embodiments. In this example, 2x repeating wires are shown forming a pack of signal paths that are shielded by Vcc or Vss interconnects. A first signal path begins at input In1 and terminates at output Out1. A second signal path begins at input In2 and terminates at output Out2. A third signal path begins at input In3 and terminates at output Out4. A fourth signal path begins at input In4 and terminates at output Out4. The second and fourth signal paths are connected to arbiter 301. 1.1 From Arbiter 302 1.2 While the first and third signal paths propagate signals to the arbiter 301, 1.2 From Arbiter 302 1.1 In the embodiment, the arbiter 301 1.1 and Arbiter 302 1.2Although signal paths between In3 and In4 are shown, embodiments are applicable to signal transmission between any MESH or RING-stop. In various embodiments, arbiter 3011.1 determines the input signals that drive In3 and In4, thereby setting the operating mode: bandwidth mode, latency mode, and energy mode. Table 1 summarizes the modes. [Table 1]

[0041] In some embodiments, a controller (e.g., PMU 201 or any other network controller) generates mode signal 203. This mode signal 203 is a multi-bit signal that indicates an operational mode for first and second of two or more interconnects. For example, mode signal 203 sets the operational mode of signal paths In1 to Out1, In3 to Out3, In2 to Out2, and In4 to Out4, where signal paths In1 to Out1 and In3 to Out3 are part of a first two or more interconnects and signal paths In2 ​​to Out2 and In4 to Out4 are part of a second two or more interconnects. In various embodiments, the propagation delays of the signal paths in a particular direction are identical (or substantially identical). For example, signal paths In2 ​​to Out2 and In4 to Out4 have the same (or substantially the same) propagation delay, while signal paths In1 to Out1 and In3 to Out3 have the same (or substantially the same) propagation delay.

[0042] The operating mode can be a first mode, a second mode, or a third mode. Various embodiments are described with reference to the mode signal being a two-bit signal, where the first mode is a bandwidth mode, the second mode is a latency mode, and the third mode is an energy mode. However, embodiments are not limited to these modes. Arbiter 402 (e.g., 402 1.1 and 402 1.2) can be configured to implement more than three modes. In one such embodiment, more signal paths are provided between the arbiters, and the bit size of the mode control signal 203 can be greater than two bits.

[0043] First Arbiter 402 1.2 are communicatively coupled to the controller 201. For example, the mode control 203 may include a first arbiter 402 1.2 In some embodiments, the first arbiter 402 1.2 is intended to configure a first interconnect of two or more interconnects (e.g., In1 to Out1 and In3 to Out3) to be in either the first, second, or third mode. For example, depending on the bit value of mode control signal 203, first arbiter 402 1.2 sets the input In1 and In3 nodes to be independent to send unique signals through their respective signal paths, shorted to send the same signal through their respective signal paths, or electrically open one of them to activate only one signal path.

[0044] In some embodiments, the second arbiter 402 1.1 The first arbiter 402 1.2 is communicatively coupled to controller 201. In some embodiments, second arbiter 402 1.1 is intended to configure a second interconnect of two or more interconnects (e.g., In2 to Out2 and In4 to Out4) to be in one of the first, second, or third modes. For example, depending on the bit value of mode control signal 203, second arbiter 402 1.1 sets the input In2 and In4 nodes to be independent to send unique signals through their respective signal paths, shorted to send the same signal through their respective signal paths, or electrically open one of them to activate only one signal path.

[0045] In various embodiments, the operational mode set by the first arbiter and the second arbiter is the same operational mode. For example, the first arbiter 402 1.2 and the second arbiter 402 1.1 causes a signal path (e.g., a first interconnect of the two or more interconnects and a second interconnect of the two or more interconnects) to be in a bandwidth mode, a latency mode, or an energy mode. In some embodiments, the operating modes set by the first and second arbiters are different operating modes.

[0046] In various embodiments, at least one of the first interconnects of the two or more interconnects and at least one of the second interconnects of the two or more interconnects are shielded by a power supply line (Vcc) or a ground line (Vss). In this example, signal path In1 to Out1 is shielded by one of Vcc or Vss, while signal path In2 to Out2 is shielded by one of Vcc or Vss.

[0047] In some embodiments, in a first mode (e.g., a bandwidth mode), the first arbiter 402 1.2 and the second arbiter 402 1.1 causes propagation of separate signals on a first interconnect and a second interconnect of two or more interconnects. For example, each signal path carries a unique signal. In this example, four different signals can be propagated between two arbiters in bandwidth mode.

[0048] In some embodiments, in the second mode (e.g., latency mode), the first arbiter 402 1.2 and the second arbiter 402 1.1 are intended to cause propagation of a first identical signal on a first interconnect of the two or more interconnects, and are intended to cause propagation of a second identical signal on a second interconnect of the two or more interconnects. For example, In1 and In3 are intended to cause propagation of a second identical signal on a second interconnect of the two or more interconnects.1.2 From Arbiter 402 1.1 In2 and In4 are the same signals that propagate to arbiter 402. 1.1 From Arbiter 402 1.2 is the same signal that propagates to

[0049] In some embodiments, in the third mode (e.g., the energy mode), the first arbiter 402 1.2 and the second arbiter 402 1.1 are intended to cause propagation of signals on alternate first interconnects of the two or more interconnects and alternate second interconnects of the two or more interconnects. For example, signal path In1 to Out1 is enabled while signal path In3 to Out3 is disabled. Similarly, signal path In2 to Out2 is enabled while signal path In4 to Out4 is disabled.

[0050] In various embodiments, the arbiter may be implemented using any suitable logic, such as multiplexers, pass gates, tri-state buffers or inverters, NAND gates, NOR gates, etc., controllable by mode control device 203 to route traffic on interconnect 304 according to bit values ​​in mode control device 203.

[0051] 5 illustrates a tri-mode reconfigurable interconnect 500 in bandwidth mode according to some embodiments. In this configuration, high bandwidth is achieved for a single signal path. Each physical link carries a unique logical signal. In this example, four physical wires are packed into the same wiring resource. Here, arbiter 301 1.1 and arbiter 302 1.2 is configured (signal router 502) so that inputs In1, In2, In3, and In4 send unique signals. 1.1 and 502 1.2 (as shown by

[0052] FIG. 6 illustrates a tri-mode reconfigurable interconnect 600 in latency mode according to some embodiments. A neighbor (e.g., signal path IN3) is reused as an assist path for signal path IN1. Here, arbiter 3011.1 and arbiter 3021.2 are configured (as shown by signal routers 6021.1 and 6021.2) so that IN1 and IN4 route the same signal and In1 and In3 route the same signal. By using parallel signal paths, cross-coupling capacitance between signal paths is reduced. Signal transitions in the assist path (IN3) and primary path (IN1) are aligned in time, effectively reducing (and in the best case eliminating) the coupling capacitance between IN1 and IN3. Driver size and wire layout are identical (or substantially identical) to allow IN1 and IN3 to be closely matched. Despite the time mismatch in the signal transitions between IN1 and IN3, the delay benefit degrades gracefully.

[0053] FIG. 7 illustrates a tri-mode reconfigurable interconnect 700 in an energy mode according to some embodiments. Here, arbiter 3011.1 and arbiter 3021.2 are configured to allow alternate signal paths (as shown by signal routers 7021.1 and 7021.2). Thus, signal paths that transmit signals are shielded by non-switching signal paths. This configuration not only enables a low-energy mode because fewer signal paths are switching, but also allows important signals (e.g., hard reset signals) to be shielded from noise. In this case, the adjacent signal path (IN3) does not switch; only signal path IN1 switches to save energy when the workload does not require low latency or high bandwidth.

[0054] 8A and 8B show plots 800 and 820 illustrating bandwidth and latency modes, respectively, according to some embodiments. Plot 800 compares peak bandwidth against latency for a typical interconnect 801, a reconfigurable interconnect 802 in latency mode, and a reconfigurable interconnect 803 in bandwidth mode. The plots show the performance of a tri-mode reconfigurable interconnect for a latency-critical server MESH link, where the four points on each curve are at different VDD points: 0.65V, 0.75V, 0.9V, and 1.1V. Plot 800 shows that in bandwidth mode, peak bandwidth can be increased by up to 33% at the expense of 46% energy over 801. Plot 820 compares energy against latency for a typical interconnect 821, a reconfigurable interconnect 822 in latency mode, and a reconfigurable interconnect 823 in bandwidth mode. Plot 820 shows that in latency mode, link latency can be reduced by 14% at the expense of a 68% increase in energy. Note that in this example, if both are undesirable, the reconfigurable interconnect can be in energy mode with less than a 5% increase in latency.

[0055] 9A and 9B show plots 900 and 920 illustrating bandwidth and latency modes, respectively, according to some embodiments. Plot 900 compares peak bandwidth against latency for an exemplary interconnect 901, a reconfigurable interconnect 902 in latency mode, and a reconfigurable interconnect 903 in bandwidth mode. The plots illustrate the performance of a tri-mode reconfigurable interconnect for a latency-critical server MESH link. For example, plots 900 and 920 illustrate the benefits that can be gained even under a fixed energy budget, as indicated by the different points in the curves, which are at different VDD points, i.e., 0.65V, 0.75V, 0.9V, and 1.1V. Peak bandwidth versus latency plot 900 shows that in bandwidth mode, there is a 27% increase in bandwidth even under an energy constraint (e.g., the maximum energy consumed by link 901). Plot 920 compares energy versus latency for a typical interconnect 921, a reconfigurable interconnect in latency mode 922, and a reconfigurable interconnect in bandwidth mode 923. Plot 920 shows that in latency mode, link latency can be reduced by 5% without any increase in energy. Note that more sophisticated (all-to-all) arbiters can also dynamically support 2x and 3x trimodal reconfigurable interconnects. Here, an all-to-all arbiter refers to an arbiter that can communicate directly with all other arbiters.

[0056] FIG. 10 illustrates a tri-modal reconfigurable interconnect 1000 with 3× repeat wires according to some embodiments. In an alternative embodiment of the present invention, instead of dynamically reconfiguring pairs of buffer interconnects, three buffer interconnects can be configured into three modes of operation: bandwidth mode, latency mode, and energy mode. A similar scheme can be used to configure “n” buffer interconnects, where “n” is greater than three. In some embodiments, arbiters 10021.1 and 10021.2 determine the input signals driving IN3, IN4, IN5, and IN4, thereby setting the modes of operation: bandwidth mode, latency mode, and energy mode. Table 2 summarizes the modes. The latency reduction, energy reduction, and bandwidth increase possible with a 3× tri-modal reconfigurable interconnect may be higher than the baseline for a particular buffer interconnect configuration. [Table 2]

[0057] 11 illustrates a SOC or NoC 2400 with a tri-mode reconfigurable interconnect according to some embodiments. In some embodiments, device 2400 represents any suitable computing device, such as a computing tablet, a mobile phone or smartphone, a laptop, a desktop, an Internet of Things (IoT) device, a server, a wearable device, a set-top box, a wireless-enabled e-reader, or the like. It will be understood that certain components are shown generically and that not all components of such a device are shown in device 2400. Any block in FIG. 11 can include a tri-mode reconfigurable interconnect of various embodiments.

[0058] In one example, device 2400 includes a system-on-chip (SoC) 2401. An example boundary of SOC 2401 is shown in Figure 15 using dotted lines, and several example components are shown contained within SOC 2401. However, SOC 2401 may include any suitable components of device 2400.

[0059] In some embodiments, device 2400 includes a processor 2404. Processor 2404 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, processing core, or other processing means. The processing operations performed by processor 2404 include the execution of an operating platform or operating system on which applications and / or device functions execute. The processing operations may include operations related to I / O (input / output) with a human user or other devices, operations related to power management, operations related to connecting computing device 2400 to other devices, and / or the like. The processing operations may also include operations related to audio I / O and / or display I / O.

[0060] In some embodiments, the processor 2404 includes multiple processing cores 2408a, 2408b, and 2408c (also referred to as cores). Although only three cores 2408a, 2408b, and 2408c are shown in FIG. 15, the processor 2404 may include any other suitable number of processing cores, such as tens or hundreds of processing cores. The processor cores 2408a, 2408b, and 2408c may be implemented on a single integrated circuit (IC) chip. Additionally, the chip may include one or more shared and / or private caches, buses or interconnects, graphics and / or memory controllers, or other components.

[0061] In some embodiments, processor 2404 includes cache 2406. In one example, a section of cache 2406 may be dedicated to an individual core 2408 (e.g., a first section of cache 2406 dedicated to core 2408a, a second section of cache 2406 dedicated to core 2408b, etc.). In one example, one or more sections of cache 2406 may be shared between two or more of cores 2408. Cache 2406 may be divided into different levels, e.g., a level 1 (L1) cache, a level 2 (L2) cache, a level 3 (L3) cache, etc.

[0062] In some embodiments, processor core 2404 may include a fetch unit for fetching instructions (including instructions with conditional branches) for execution by core 2404. The instructions may be fetched from any storage device, such as memory 2430. Processor core 2404 may include a decode unit for decoding fetched instructions. For example, the decode unit may decode the fetched instructions into multiple micro-operations. Processor core 2404 may include a schedule unit for performing various operations related to storing the decoded instructions. For example, the schedule unit may hold data from the decode unit until the instruction is ready to be dispatched, e.g., until all source values ​​of the decoded instruction are available. In one embodiment, the schedule unit may schedule the decoded instructions for execution and / or issue (or dispatch) the decoded instructions to an execution unit.

[0063] After a dispatched instruction is decoded (e.g., by a decode unit) and dispatched (e.g., by a schedule unit), the execution unit may execute the dispatched instruction. In some embodiments, the execution unit may include more than one execution unit (such as an imaging computation unit, a graphics computation unit, a general-purpose computation unit, etc.). The execution unit may perform various arithmetic operations such as addition, subtraction, multiplication, and / or division and may include one or more arithmetic logic units (ALUs). In some embodiments, a coprocessor (not shown) may operate in conjunction with the execution unit to perform various arithmetic operations.

[0064] Additionally, the execution units may execute instructions out of order. Thus, in one embodiment, processor core 2404 may be an out-of-order processor core. Processor core 2404 may include a retirement unit. The retirement unit may be retired after an executed instruction is committed. In some embodiments, retirement of an executed instruction may result in the processor state being committed from instruction execution, physical registers used by the instruction being deallocated, etc. Processor core 2404 may include a bus unit that enables communication between components of processor core 2404 and other components via one or more buses. Processor core 2404 may include one or more registers that store data accessed by various components of core 2404 (such as values ​​related to assigned application priorities and / or subsystem state (mode) associations).

[0065] In some embodiments, device 2400 includes connectivity circuitry 2431. For example, connectivity circuitry 2431 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and / or software components (e.g., drivers, protocol stacks), etc., to enable device 2400 to communicate with external devices. Device 2400 may be isolated from external devices, such as other computing devices, wireless access points or base stations, etc.

[0066] In one example, the connectivity circuitry 2431 may include multiple different types of connectivity. To generalize, the connectivity circuitry 2431 may include cellular connectivity circuitry, wireless connectivity circuitry, etc. The cellular connectivity circuitry of the connectivity circuitry 2431 generally refers to cellular network connectivity provided by a wireless carrier, such as provided via a global system for mobile communications (GSM) or a variant or derivative thereof, a code division multiple access (CDMA) or a variant or derivative thereof, a time division multiplexing (TDM) or a variant or derivative thereof, a 3rd Generation Partnership Project (3GPP) Universal Mobile Telecommunications System (UMTS) or a variant or derivative thereof, a 3GPP Long Term Evolution (LTE) system or a variant or derivative thereof, a 3GPP LTE-Advanced (LTE-A) system or a variant or derivative thereof, a fifth generation (5G) wireless system or a variant or derivative thereof, a 5G mobile network system or a variant or derivative thereof, a 5G New Radio (NR) system or a variant or derivative thereof, or other cellular service standard. The wireless connectivity circuitry (or wireless interface) of the connectivity circuitry 2431 refers to non-cellular wireless connectivity and can include personal area networks (such as Bluetooth, near field, etc.), local area networks (such as Wi-Fi), and / or wide area networks (such as WiMax), and / or other wireless communications. In some examples, the connectivity circuitry 2431 can include a network interface, such as a wired or wireless interface, such that system embodiments may be incorporated into wireless devices, e.g., mobile phones or personal digital assistants.

[0067] In some embodiments, device 2400 includes a control hub 2432 that represents hardware devices and / or software components involved in interacting with one or more I / O devices. For example, processor 2404 may communicate with one or more of a display 2422, one or more peripheral devices 2424, a storage device 2428, one or more other external devices 2429, etc. via control hub 2432. Control hub 2432 may be a chipset, a platform control hub (PCH), and / or the like.

[0068] For example, control hub 2432 represents one or more connection points for additional devices to connect to device 2400, e.g., through which a user may interact with the system. For example, devices that may be attached to device 2400 (e.g., device 2429) include a microphone device, a speaker or stereo system, an audio device, a video system or other display device, a keyboard or keypad device, or other I / O devices for use in specific applications, such as a card reader or other device.

[0069] As described above, the control hub 2432 can interact with audio devices, the display 2422, and the like. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the device 2400. Additionally, audio output can be provided instead of or in addition to display output. In another example, if the display 2422 includes a touchscreen, the display 2422 also functions as an input device that can be managed, at least in part, by the control hub 2432. There can be additional buttons or switches on the computing device 2400 to provide I / O functionality managed by the control hub 2432. In one embodiment, the control hub 2432 manages devices such as an accelerometer, a camera, a light sensor or other environmental sensors, or other hardware that can be included in the device 2400. The input can be part of direct user interaction, provide environmental input to the system, and affect system operation (such as filtering noise, adjusting the display for brightness detection, applying a flash for a camera, or other configuration).

[0070] In some embodiments, the control hub 2432 may couple to various devices using any suitable communication protocol, such as Peripheral Component Interconnect Express (PCIe), Universal Serial Bus (USB), Thunderbolt, High Definition Multimedia Interface (HDMI), Firewire, etc.

[0071] In some embodiments, display 2422 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and / or tactile display for a user to interact with device 2400. Display 2422 may include a display interface, a display screen, and / or a hardware device used to provide a display to a user. In some embodiments, display 2422 includes a touchscreen (or touchpad) device that provides both output and input to a user. In certain examples, display 2422 may communicate directly with processor 2404. Display 2422 can be one or more of an internal display device, such as in a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment, display 2422 can be a head-mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) or augmented reality (AR) applications.

[0072] In some embodiments, although not shown, in addition to (or instead of) processor 2404, device 2400 may include a graphics processing unit (GPU) including one or more graphics processing cores that may control one or more aspects of displaying content on display 2422.

[0073] The control hub 2432 (or platform controller hub) may include hardware interfaces and connectors, as well as software components (eg, drivers, protocol stacks) for making peripheral connections to the peripheral devices 2424 .

[0074] It will be appreciated that device 2400 may be a peripheral device to other computing devices and may have peripheral devices connected to it. Device 2400 may have a "docking" connector that connects to other computing devices for purposes of managing (e.g., downloading and / or uploading, modifying, synchronizing) content on device 2400. Additionally, the docking connector may enable device 2400 to connect to certain peripherals that allow computing device 2400 to control content output to, for example, audiovisual or other systems.

[0075] In addition to dedicated docking connectors or other proprietary connection hardware, device 2400 can make peripheral connections via common or standards-based connectors. Common types include Universal Serial Bus (USB) connectors (which can include any of a number of different hardware interfaces), DisplayPort, including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0076] In some embodiments, the connectivity circuitry 2431 may be coupled to a control hub 2432, for example, in addition to or instead of being directly coupled to the processor 2404. In some embodiments, the display 2422 may be coupled to the control hub 2432, for example, in addition to or instead of being directly coupled to the processor 2404.

[0077] In some embodiments, device 2400 includes memory 2430 coupled to processor 2404 via memory interface 2434. Memory 2430 includes memory devices for storing information within device 2400. Memory may include non-volatile (state does not change when power to the memory device is interrupted) and / or volatile (state is indeterminate when power to the memory device is interrupted) memory devices. Memory device 2430 may be a dynamic random access memory device (DRAM), a static random access memory device (SRAM), a flash memory device, a phase change memory device, or some other memory device with performance suitable for functioning as process memory. In one embodiment, memory 2430 may operate as system memory for device 2400, storing data and instructions for use by one or more processors 2404 when executing applications or processes. Memory 2430 may store (long-term or temporary) application data, user data, music, photos, documents, or other data, as well as system data related to the execution of applications and functions of device 2400.

[0078] Elements of various embodiments and examples may also be provided as a machine-readable medium (e.g., memory 2430) for storing computer-executable instructions (e.g., instructions implementing any other process discussed herein). The machine-readable medium (e.g., memory 2430) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD-ROMs, RAM, EPROMs, EEPROMs, magnetic or optical cards, phase-change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS), which may be transferred by data signal from a remote computer (e.g., server) to a requesting computer (e.g., client) over a communications link (e.g., modem or network connection).

[0079] In some embodiments, device 2400 includes temperature measurement circuitry 2440, for example, to measure the temperatures of various components of device 2400. In certain examples, temperature measurement circuitry 2440 may be embedded in, coupled to, or attached to the various components whose temperatures are to be measured and monitored. For example, temperature measurement circuitry 2440 may measure the temperatures of one or more of cores 2408a, 2408b, 2408c, voltage regulator 2414, memory 2430, SOC 2401's motherboard, and / or any suitable components of device 2400.

[0080] In some embodiments, device 2400 includes power measurement circuitry 2442, for example, to measure power consumed by one or more components of device 2400. In some examples, in addition to or instead of measuring power, power measurement circuitry 2442 may measure voltage and / or current. In some examples, power measurement circuitry 2442 may be embedded in, coupled to, or attached to various components whose power, voltage, and / or current consumption are intended to be measured and monitored. For example, power measurement circuitry 2442 may measure power, current, and / or voltage supplied by one or more voltage regulators 2414, power supplied to SOC 2401, power supplied to device 2400, power consumed by processor 2404 (or any other component) of device 2400, etc.

[0081] In some embodiments, device 2400 includes one or more voltage regulator circuitry, commonly referred to as voltage regulator (VR) 2414. VR 2414 generates signals at appropriate voltage levels that may be supplied to operate any appropriate component of device 2400. By way of example only, VR 2414 is shown providing signals to processor 2404 of device 2400. In some embodiments, VR 2414 receives one or more voltage identification (VID) signals and generates voltage signals at appropriate levels based on the VID signals. Various types of VRs may be utilized for VR 2414. For example, VR 2414 may include a “buck” VR, a “boost” VR, a combination buck and boost VR, a low dropout (LDO) regulator, a switching DC-DC regulator, etc. Buck VRs are typically used in power delivery applications that require an input voltage to be converted to an output voltage by a ratio less than one unit. Boost VRs are commonly used in power delivery applications that require an input voltage to be converted to an output voltage by a ratio greater than 1 (unit). In some embodiments, each processor core has its own VR controlled by the PCU 2410a / b and / or PMIC 2412. In some embodiments, each core has a network of distributed LDOs to provide efficient control for power management. The LDOs can be digital LDOs, analog LDOs, or a combination of digital and analog LDOs.

[0082] In some embodiments, device 2400 includes one or more clock generator circuitry, generally referred to as clock generator 2416. Clock generator 2416 generates a clock signal at an appropriate frequency level, which may be provided to any appropriate component of device 2400. By way of example only, clock generator 2416 is shown providing a clock signal to processor 2404 of device 2400. In some embodiments, clock generator 2416 receives one or more frequency identification (FID) signals and generates a clock signal at an appropriate frequency based on the FID signals. Clock generator 2416 is an adaptive clock source capable of providing an adaptive frequency output as discussed in connection with various embodiments.

[0083] In some embodiments, device 2400 includes a battery 2418 that powers various components of device 2400. By way of example only, battery 2418 is shown powering processor 2404. Although not shown, device 2400 may include charging circuitry for, for example, recharging the battery based on alternating current (AC) power received from an AC adapter.

[0084] In some embodiments, device 2400 includes a power control unit (PCU) 2410 (also referred to as a power management unit (PMU), power controller, etc.). In one example, some sections (partitions) of PCU 2410 may be implemented by one or more processing cores 2408; these sections of PCU 2410 are symbolically depicted using dotted boxes and labeled PCU 2410a. In one example, some other sections of PCU 2410 may be implemented outside of processing cores 2408; these sections of PCU 2410 are symbolically depicted using dotted boxes and labeled PCU 2410b. PCU 2410 may implement various power management operations for device 2400. PCU 2410 may include hardware interfaces, hardware circuitry, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks) to implement various power management operations for device 2400.

[0085] In some embodiments, device 2400 includes a power management integrated circuit (PMIC) 2412, for example, to implement various power management operations for device 2400. In some embodiments, PMIC 2412 is a reconfigurable power management IC (RPMIC) and / or an IMVP (Intel® Mobile Voltage Positioning). In one example, the PMIC is in an IC chip separate from processor 2404. It may implement various power management operations for device 2400. PMIC 2412 may include hardware interfaces, hardware circuitry, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks) to implement various power management operations for device 2400.

[0086] In some examples, device 2400 includes one or both of a PCU 2410 or a PMIC 2412. In some examples, either the PCU 2410 or the PMIC 2412 may not be present in device 2400, and therefore, these components are illustrated using dashed lines.

[0087] Various power management operations of device 2400 may be performed by PCU 2410, by PMIC 2412, or by a combination of PCU 2410 and PMIC 2412. For example, PCU 2410 and / or PMIC 2412 may select power states (e.g., P-states) for various components of device 2400. For example, PCU 2410 and / or PMIC 2412 may select power states (e.g., according to the Advanced Configuration and Power Interface (ACPI) specification) for various components of device 2400. By way of example only, PCU 2410 and / or PMIC 2412 may transition various components of device 2400 into a sleep state, an active state, an appropriate C-state (e.g., a C0 state or other appropriate C-state according to the ACPI specification), etc. In some examples, the PCU 2410 and / or the PMIC 2412 may control the voltage output by the VR 2414 and / or the frequency of the clock signal output by the clock generator, for example, by outputting a VID signal and / or an FID signal, respectively. In some examples, the PCU 2410 and / or the PMIC 2412 may control configurations related to battery power usage, charging of the battery 2418, and power saving operations.

[0088] The clock generator 2416 may include a phase locked loop (PLL), a frequency locked loop (FLL), or any suitable clock source. In some embodiments, each core of the processor 2404 has its own clock source. Thus, each core can operate at a frequency independent of the operating frequency of the other cores. In some embodiments, the PCU 2410 and / or PMIC 2412 perform adaptive or dynamic frequency scaling or adjustment. For example, the clock frequency of a processor core can be increased if the core is not operating at its maximum power consumption threshold or limit. In some embodiments, the PCU 2410 and / or PMIC 2412 determine the operating conditions of each core of the processor and, when the PCU 2410 and / or PMIC 2412 determines that a core is operating below its target performance level, adjust the frequency and / or power supply voltage of that core accordingly without the core's clock source (e.g., the core's PLL) losing lock. For example, if a core draws less current from the power supply rails than the total current allocated for that core or processor 2404, the PCU 2410 and / or PMIC 2412 can temporarily increase the power draw for that core or processor 2404 (e.g., by increasing the clock frequency and / or power supply voltage level) to allow the core or processor 2404 to operate at a higher performance level. Thus, the voltage and / or frequency can be temporarily increased for the processor 2404 without compromising product reliability.

[0089] In one example, the PCU 2410 and / or the PMIC 2412 may perform power management operations based at least in part on receiving measurements from, for example, the power measurement circuitry 2442, the temperature measurement circuitry 2440, the charge level of the battery 2418, and / or any other suitable information that may be used for power management. To this end, the PMIC 2412 is communicatively coupled to one or more sensors to sense / detect various values / fluctuations in one or more factors that have an impact on the power / thermal behavior of the system / platform. Examples of the one or more factors include current, voltage sag, temperature, operating frequency, operating voltage, power consumption, inter-core communication activity, etc. One or more of these sensors may be located in physical proximity (and / or in thermal contact / coupling) with one or more components or logic / IP blocks of the computing system. Additionally, in at least one embodiment, sensors may be directly connected to the PCU2410 and / or PMIC2412 to enable the PCU2410 and / or PMIC2412 to manage processor core energy based at least in part on values ​​detected by one or more of the sensors.

[0090] An exemplary software stack for device 2400 is shown (although not all elements of the software stack are shown). By way of example only, processor 2404 may execute application programs 2450, operating system 2452, one or more power management (PM)-specific application programs (e.g., generally referred to as PM applications 2458), and / or equivalent programs. PM applications 2458 may be executed by PCU 2410 and / or PMIC 2412. OS 2452 may also include one or more PM applications 2456a, 2456b, 2456c. OS 2452 may include various drivers 2454a, 2454b, 2454c, etc., some of which may be specific for power management purposes. In some embodiments, device 2400 may further include a basic input / output system (BIOS) 2420. The BIOS 2420 may communicate with the OS 2452 (eg, via one or more drivers 2454) and with the processor 2404.

[0091] For example, one or more of PM applications 2458, 2456, drivers 2454, BIOS 2420, etc. may be used to perform power management specific tasks, such as controlling the voltage and / or frequency of various components of device 2400, managing the awake, sleep, and / or any other suitable power states of various components of device 2400, controlling battery power usage, charging of battery 2418, configuration for power saving operations, etc.

[0092] References herein to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" mean that a particular configuration, structure, or feature described in connection with an embodiment is included in at least some embodiments, but not necessarily all embodiments. Various appearances of "an embodiment," "one embodiment," or "some embodiments" do not necessarily all refer to the same embodiments. When the specification states that a component, configuration, structure, or feature "may be included," "might be included," or "can be included," it does not require that the particular component, configuration, structure, or feature be included. When the specification or claims refer to a singular element, it does not mean that only one of the element is present. When the specification or claims refer to "additional" elements, it does not exclude the presence of more than one of the additional elements.

[0093] Furthermore, particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment, provided that the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0094] While the present disclosure has been described in connection with specific embodiments thereof, many alternatives, modifications, and variations of such embodiments will be apparent to those skilled in the art in light of the foregoing description. It is intended that the embodiments of the present disclosure embrace all such alternatives, modifications, and variations as fall within the broad scope of the appended claims.

[0095] Additionally, for ease of illustration and discussion, and to avoid obscuring the disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented figures. Furthermore, configurations may be shown in block diagram form to avoid obscuring the disclosure, and also in recognition of the fact that details regarding the implementation of such block diagram configurations will vary greatly depending on the platform on which the disclosure is implemented (i.e., such details should be well within the purview of one skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure may be practiced without these specific details or with variations thereon. Thus, the description should be considered illustrative and not limiting.

[0096] The following examples relate to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. Any optional features of the apparatus described herein may be implemented in the context of a method or process.

[0097] Example 1: An apparatus including: a controller that generates a mode signal, the mode signal indicating an operating mode of a first and a second interconnect of two or more interconnects, the operating mode including one of a first mode, a second mode, or a third mode; a first arbiter that is communicatively coupled to the controller and that configures the first interconnect of the two or more interconnects to be in one of the first, second, or third modes; and a second arbiter that is communicatively coupled to the controller and that configures the second interconnect of the two or more interconnects to be in the same mode as the first interconnect of the two or more interconnects.

[0098] Example 2: The apparatus of Example 1, wherein the first and second arbiters are operable to short-circuit an input of the first interconnection of two or more interconnections, connect the input of the first interconnection of the two or more interconnections to an input port or output port of the first or second arbiter, or isolate the input of one of the first interconnections of the two or more interconnections from an input port or output port of the first or second arbiter.

[0099] Example 3: The apparatus of Example 1, wherein at least one first interconnection of a first interconnection of the two or more interconnections and at least one second interconnection of a second interconnection of the two or more interconnections are shielded by a power line or a ground line.

[0100] Example 4: The apparatus of Example 1, wherein the first mode is a bandwidth mode, and the first and second arbiters cause propagation of separate signals on first and second interconnects of the two or more interconnects.

[0101] Example 5: The apparatus of Example 1, wherein the second mode is a latency mode, and the first and second arbiters cause propagation of a first identical signal on a first interconnection of the two or more interconnections and a second identical signal on a second interconnection of the two or more interconnections.

[0102] Example 6: The apparatus of Example 1, wherein the third mode is an energy mode, and the first and second arbiters cause propagation of signals on alternating first interconnects of the two or more interconnects and alternating second interconnects of the two or more interconnects.

[0103] Example 7: The apparatus of example 1, wherein the controller is a power management unit and is also operable to perform dynamic voltage and frequency scaling.

[0104] Example 8: An apparatus including: a power management unit (PMU) that generates a mode control; and a mesh network of arbiters coupled to the PMU, the mesh network of arbiters including: a first arbiter communicatively coupled to the PMU to receive the mode control; a second arbiter communicatively coupled to the PMU to receive the mode control; a first pair of signal paths having a first driver and a second driver coupled to the first arbiter; a first receiver and a second receiver coupled to the second arbiter; a second pair of signal paths having a third driver and a fourth driver coupled to the second arbiter; and a third receiver and a fourth receiver coupled to the first arbiter, wherein the first and second arbiters configure the first and second signal paths to be in one of a first mode, a second mode, or a third mode in accordance with the mode control.

[0105] Example 9: The apparatus of example 8, wherein the PMU performs dynamic voltage and frequency scaling.

[0106] Example 10: The device described in Example 8, wherein the first and second arbiters connect each input of the first pair of signal paths to a respective input port or output port of the first or second arbiter, or short-circuit the inputs of the first pair of signal paths to the same signal port of the first or second arbiter.

[0107] Example 11: The device described in Example 8, wherein the first and second arbiters open one electrical path of an input of one of the signal paths of the first pair of signal paths, or connect each input of the first pair of signal paths to a respective input port or output port of the first or second arbiter.

[0108] Example 12: The device described in Example 8, wherein the first and second arbiters connect each input of the second pair of signal paths to a respective input port or output port of the first or second arbiter, or short-circuit the inputs of the second pair of signal paths to the same signal port of the first or second arbiter.

[0109] Example 13: The device described in Example 8, wherein the first and second arbiters open one electrical path of the input of one of the signal paths of the second pair of signal paths, or connect each input of the first pair of signal paths to a respective input port or output port of the first or second arbiter.

[0110] Example 14: The apparatus of Example 8, wherein the first mode is a bandwidth mode, and the first and second arbiters cause propagation of distinct signals on the first and second pairs of signal paths.

[0111] Example 15: The apparatus of Example 8, wherein the second mode is a latency mode, and the first and second arbiters cause propagation of a first identical signal on a first pair of signal paths and a second identical signal on a second pair of signal paths.

[0112] Example 16: The apparatus of Example 8, wherein the third mode is an energy mode, and the first and second arbiters cause propagation of signals on alternating signal paths of the first and second pairs of signal paths.

[0113] Example 17: A system includes a memory, a processor core coupled to the memory, a power management unit (PMU) coupled to the processor core to perform dynamic voltage and frequency scaling, a network-on-chip (NOC) including a mesh or ring network, and a wireless interface communicatively coupled to the processor, the NOC including a network of arbiters coupled to the PMU, the network of arbiters including a first arbiter communicatively coupled to the PMU to receive mode control, and a second arbiter communicatively coupled to the PMU to receive mode control. a first pair of signal paths having a first driver and a second driver coupled to the first arbiter, a first receiver and a second receiver coupled to the second arbiter, a second pair of signal paths having a third driver and a fourth driver coupled to the second arbiter, and a third receiver and a fourth receiver coupled to the first arbiter, wherein the first and second arbiters configure the first and second signal paths to be in one of a first mode, a second mode, or a third mode according to a mode control.

[0114] Example 18: The system of Example 17, wherein the first mode is a bandwidth mode, and the first and second arbiters cause propagation of distinct signals on the first and second pairs of signal paths.

[0115] Example 19: The system of Example 17, wherein the second mode is a latency mode, and the first and second arbiters cause propagation of a first identical signal on a first pair of signal paths and a second identical signal on a second pair of signal paths.

[0116] Example 20: The system of Example 17, wherein the third mode is an energy mode, and the first and second arbiters cause propagation of signals on alternating signal paths of the first and second pairs of signal paths.

[0117] An Abstract is provided to allow the reader to ascertain the nature and gist of the technical disclosure. The Abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. a controller that generates a mode signal, the mode signal indicating an operating mode for two or more interconnects of a first set and two or more interconnects of a second set, the operating modes including a bandwidth mode, a latency mode, and an energy mode; a first arbiter communicatively coupled to the controller to configure two or more interconnects of the first set to be in one of the bandwidth mode, latency mode, and energy mode; a second arbiter communicatively coupled to the controller to configure two or more interconnects of the second set to be in the same mode as two or more interconnects of the first set. Device.

2. The first and second arbiters in the bandwidth mode, shorting the inputs of two or more interconnects of the first set; in the latency mode, connecting inputs of two or more interconnects of the first set to output ports of the first arbiter and connecting outputs of two or more interconnects of the first set to input ports of the second arbiter; in the energy mode, isolating an input of one of the two or more interconnects in the first set from an output port of the first arbiter and isolating an output of one of the two or more interconnects in the first set from an input port of the second arbiter; It is operable as 10. The apparatus of claim 1.

3. 3. The apparatus of claim 1, wherein at least one of the two or more interconnects in the first set and at least one of the two or more interconnects in the second set are shielded by a power line or a ground line.

4. 4. The apparatus of claim 1, wherein in the bandwidth mode, the first and second arbiters cause propagation of separate signals on two or more interconnects of the first and second sets, respectively.

5. 5. The apparatus of claim 1, wherein in the latency mode, the first and second arbiters cause propagation of a first identical signal on two or more interconnects in the first set and a second identical signal on two or more interconnects in the second set.

6. 6. The device of claim 1, wherein in the energy mode, the first and second arbiters enable propagation of signals on one interconnect of the first set of two or more interconnects and one interconnect of the second set of two or more interconnects, while disabling propagation of signals on another interconnect of the first set of two or more interconnects and another interconnect of the second set of two or more interconnects.

7. Apparatus according to any one of claims 1 to 6, wherein the controller is a power management unit and is also operable to perform dynamic voltage and frequency scaling.

8. a power management unit (PMU) for generating mode control; a mesh network of arbiters coupled to the PMU, the mesh network of arbiters comprising: a first arbiter communicatively coupled to the PMU to receive the mode control; a second arbiter communicatively coupled to the PMU to receive the mode control; a first pair of signal paths having a first driver and a second driver coupled to the first arbiter; and a first receiver and a second receiver coupled to the first pair of signal paths, the first receiver and the second receiver being coupled to the second arbiter; a second pair of signal paths having a third driver and a fourth driver coupled to the second arbiter; and a third receiver and a fourth receiver coupled to the second pair of signal paths, the third receiver and the fourth receiver coupled to the first arbiter; the modes include a bandwidth mode, a latency mode, and an energy mode, and the first and second arbiters configure the first pair of signal paths and the second pair of signal paths to be in one of the bandwidth mode, the latency mode, and the energy mode according to the mode control. Device.

9. The apparatus of claim 8 , wherein the PMU performs dynamic voltage and frequency scaling.

10. The first and second arbiters connecting each input of the first pair of signal paths to a respective output port of the first arbiter and connecting each output of the first pair of signal paths to a respective input port of the second arbiter; or shorting the inputs of the first pair of signal paths to the same signal port of the first arbiter; 10. Apparatus according to claim 8 or 9.

11. The first and second arbiters opening an electrical path at one input of one of the first pair of signal paths; or connecting each input of the first pair of signal paths to a respective output port of the first arbiter, and connecting each output of the first pair of signal paths to a respective input port of the second arbiter; Apparatus according to any one of claims 8 to 10.

12. The first and second arbiters connecting each input of the second pair of signal paths to a respective output port of the second arbiter and connecting each output of the second pair of signal paths to a respective input port of the first arbiter; or shorting the inputs of the second pair of signal paths to the same signal port of the second arbiter; Apparatus according to any one of claims 8 to 11.

13. The first and second arbiters opening one electrical path of the input of one of the second pair of signal paths; or connecting each input of the second pair of signal paths to a respective output port of the second arbiter, and connecting each output of the second pair of signal paths to a respective input port of the first arbiter; Apparatus according to any one of claims 8 to 12.

14. 14. The apparatus of claim 8, wherein in the bandwidth mode, the first and second arbiters cause propagation of separate signals on the first and second pairs of signal paths.

15. 15. The apparatus of claim 8, wherein in the latency mode, the first and second arbiters cause propagation of a first identical signal on the first pair of signal paths and a second identical signal on the second pair of signal paths.

16. 16. The apparatus of claim 8, wherein in the energy mode, the first and second arbiters enable propagation of a signal on one signal path of the first pair of signal paths and one signal path of the second pair of signal paths, while disabling propagation of a signal on the other signal path of the first pair of signal paths and the other signal path of the second pair of signal paths.

17. Memory and a processor core coupled to the memory; a power management unit (PMU) coupled to the processor core to perform dynamic voltage and frequency scaling; a network-on-chip (NOC) including a mesh or ring network; a wireless interface communicatively coupled to the processor core; The NOC includes a network of arbiters coupled to the PMUs, the network of arbiters comprising: a first arbiter communicatively coupled to the PMU to receive mode control; a second arbiter communicatively coupled to the PMU to receive the mode control; a first pair of signal paths having a first driver and a second driver coupled to the first arbiter; and a first receiver and a second receiver coupled to the first pair of signal paths, the first receiver and the second receiver being coupled to the second arbiter; a second pair of signal paths having a third driver and a fourth driver coupled to the second arbiter; and a third receiver and a fourth receiver coupled to the second pair of signal paths, the third receiver and the fourth receiver coupled to the first arbiter; the modes include a bandwidth mode, a latency mode, and an energy mode, and the first and second arbiters configure the first pair of signal paths and the second pair of signal paths to be in one of the bandwidth mode, the latency mode, and the energy mode according to the mode control. system.

18. 20. The system of claim 17, wherein in the bandwidth mode, the first and second arbiters cause propagation of separate signals on the first and second pairs of signal paths.

19. 20. The system of claim 17, wherein in the latency mode, the first and second arbiters cause propagation of a first identical signal on the first pair of signal paths and a second identical signal on the second pair of signal paths.

20. 20. The system of claim 17, wherein in the energy mode, the first and second arbiters enable signal propagation on one signal path of the first pair of signal paths and one signal path of the second pair of signal paths, while disabling signal propagation on the other signal path of the first pair of signal paths and the other signal path of the second pair of signal paths.

21. generating, by a controller, a mode signal indicating an operating mode for two or more interconnects of a first set and two or more interconnects of a second set, the operating modes including a bandwidth mode, a latency mode, and an energy mode; configuring, by a first arbiter communicatively coupled to the controller, two or more interconnects of the first set to be in one of the bandwidth mode, the latency mode, and the energy mode; and configuring, by a second arbiter communicatively coupled to the controller, two or more interconnects of the second set to be in the same mode as two or more interconnects of the first set. method.

22. in the bandwidth mode, shorting the inputs of two or more interconnects of the first set; in the latency mode, connecting inputs of two or more interconnects of the first set to output ports of the first arbiter and connecting outputs of two or more interconnects of the first set to input ports of the second arbiter; further comprising: in the energy mode, isolating an input of one interconnect of the first set of two or more interconnects from an output port of the first arbiter, and isolating an output of one interconnect of the first set of two or more interconnects from an input port of the second arbiter.

22. The method of claim 21.

23. 23. The method of claim 21 or 22, wherein in the bandwidth mode, the method comprises propagating respective separate signals on two or more interconnects of the first and second sets.

24. In the latency mode, the method includes propagating a first identical signal on two or more interconnects of the first set and a second identical signal on two or more interconnects of the second set; In the energy mode, the method includes enabling propagation of a signal on one interconnect of the first set of two or more interconnects and one interconnect of the second set of two or more interconnects, while disabling propagation of a signal on another interconnect of the first set of two or more interconnects and another interconnect of the second set of two or more interconnects. The method according to any one of claims 21 to 23.

25. 25. The method of any one of claims 21 to 24, further comprising shielding at least one of the two or more interconnects in the first set and at least one of the two or more interconnects in the second set with a power line or a ground line.

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