Controlling wafer bow in integrated circuit processing.

Abstract

A method for controlling wafer bow in an integrated circuit manufacturing process may include characterizing wafer bow occurring in response to performing one or more first manufacturing processes on an active side of an integrated circuit wafer, determining one or more second manufacturing processes to be performed on a backside of the integrated circuit wafer, and the method may further include performing the one or more second manufacturing processes on the backside of the integrated circuit wafer to reduce wafer bow below a predetermined threshold based on the one or more first manufacturing processes.

Description

[Technical Field]

[0001] <Incorporated by Reference> A PCT application is filed concurrently herewith as part of this application. Each application identified in the concurrently filed PCT application to which this application claims benefit or priority is incorporated herein by reference in its entirety for all purposes. [Background technology]

[0002] The background and content discussion contained herein is provided solely for the purpose of presenting a general overview of the content of the present disclosure. Although the majority of this disclosure presents the work of the inventors, merely because such work is set forth in the Background section or presented as content in other sections of this specification does not mean that such work is admitted to be prior art.

[0003] The fabrication of semiconductor wafers used to form integrated circuits can include many different processing steps. In certain processing steps, which may occur after various materials have been deposited on a semiconductor wafer, the material may be etched away so that additional materials, such as metals, can be deposited. Such deposition may involve the formation of conductive traces, transistor gates, vias, circuit elements, etc. However, in at least some instances, the deposited materials may create tensile stresses on the surface of the semiconductor wafer. Such tensile stresses can cause the semiconductor wafer to bow, resulting in a concave or convex shape of the semiconductor wafer. In response to the concave wafer shape, subsequent semiconductor processing, such as photolithography, masking, singulation, etc., can cause problems. In some instances, excessive semiconductor wafer bow can necessitate the entire wafer being scrapped. As such, techniques for improving control of semiconductor wafer bow remain an active area of ​​research. Summary of the Invention

[0004] A general aspect of the claims includes a method for performing processes on a wafer, the method including: (a) determining a change in wafer bow with temperature caused at least in part by one or more processes performed on a front side of the wafer; (b) using information about the determined change in wafer bow with temperature to determine a property of a backside process of the wafer that counteracts the wafer bow; (c) performing the backside process identified in (b) on an incoming wafer; and (d) performing the one or more processes on the front side of the incoming wafer, thereby at least in part preventing the backside process performed in (c) from warping the incoming wafer in response to the one or more processes.

[0005] In the above method, the one or more processes performed on the front side of the wafer may include a deposition process. The one or more processes performed on the front side of the wafer may include a multi-layer stack deposition. The one or more processes performed on the front side of the wafer may include an oxide / nitride (ONON) deposition. The one or more processes performed on the front side of the wafer may include an etch process. The determining the change in wafer bow with temperature may include measuring the wafer bow of a test wafer at a plurality of different temperatures while the temperature of the test wafer is being increased. The determining the change in wafer bow with temperature may include measuring the wafer bow of a test wafer at a plurality of different temperatures while the temperature of the test wafer is being decreased. The determining the change in wafer bow with temperature may include determining hysteresis in wafer bow in response to at least one cycle of increasing and decreasing temperature. Determining the variation of wafer bow with temperature may include measuring wafer bow of a test wafer at a plurality of different temperatures within a range of temperatures to which the input wafer is subjected during the one or more processes on the front side of the input wafer. The backside processing may include adding one or more layers to the backside of the input wafer. Utilizing the information regarding the determined variation of wafer bow with temperature to determine properties of backside processing of the wafer may include obtaining bow information with temperature for test wafers having one or more deposited layers on the backside of the test wafer. In certain aspects, a first test wafer may have a layer of a first material on its backside, and a second test wafer may have a deposited layer of a second material on its backside. Determining backside processing properties of the wafer using the information regarding the determined change in wafer bow with temperature may further include determining a backside processing including depositing a first layer of the first material on the backside of the wafer to a first thickness and depositing a second layer of the second material on the backside of the wafer to a second thickness.

[0006] In one or more additional aspects, an apparatus for controlling wafer bow in integrated circuit processing is provided, the apparatus including one or more processing stations of a multi-station fabrication chamber, the one or more processing stations configured to accommodate a corresponding number of semiconductor wafers, each having a backside thereof subjected to a fabrication process, the one or more processing stations further configured to perform a fabrication process on an active side of each wafer, and the one or more processing stations further configured, in conjunction with each accommodated semiconductor wafer, to maintain wafer bow below a threshold value during the fabrication process performed on the active side of each wafer.

[0007] In the above apparatus, the manufacturing process performed on the active side of each wafer may include increasing the temperature of the wafer and then decreasing the temperature of the wafer. The manufacturing process performed on the active side of each wafer may include depositing material. The manufacturing process performed on the active side of each wafer may include removing material from the wafer. In one embodiment, the threshold may be approximately 100 μm and each wafer may have a diameter of approximately 300 mm. In one embodiment, the threshold may be approximately 75 μm and each wafer may have a diameter of approximately 300 mm. The multi-station manufacturing chamber may include four processing stations. The manufacturing process on the backside of each wafer may include depositing a layer of silicon oxide and / or silicon nitride.

[0008] In one or more additional aspects, a method for controlling wafer bow in an integrated circuit manufacturing process is provided, the method including characterizing wafer bow caused in response to performing one or more active manufacturing processes on an active side of an integrated circuit wafer, determining one or more second manufacturing processes to be performed on a backside of the integrated circuit wafer, reducing the wafer bow below a predetermined threshold based on the one or more active manufacturing processes, and performing the one or more second manufacturing processes on the backside of the integrated circuit wafer.

[0009] In the above method, the one or more active manufacturing processes performed on the active side of the integrated circuit wafer may include increasing the temperature of the integrated circuit wafer. The one or more active manufacturing processes performed on the active side of the integrated circuit wafer may include depositing a material on the active side of the integrated circuit wafer. The material deposited on the active side of the integrated circuit wafer may include silicon nitride. The material deposited on the active side of the integrated circuit wafer may include silicon oxide. The one or more active manufacturing processes performed on the active side of the integrated circuit wafer may include removing a material from the active side of the integrated circuit wafer. Performing the one or more second manufacturing processes on the backside of the integrated circuit wafer may reduce the wafer bow to an amount less than about 100 μm when the wafer has a diameter of about 300 mm. Performing the one or more second manufacturing processes on the backside of the integrated circuit wafer may reduce the wafer bow to an amount less than about 75 μm when the wafer has a diameter of about 300 mm. Performing the one or more second manufacturing processes on the backside of the integrated circuit wafer can include depositing a silicon oxide layer, a silicon nitride layer, or both a silicon oxide layer and a silicon nitride layer on the backside. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a flowchart illustrating an example operation for reducing bowing in a substrate, according to one embodiment.

[0011] [Figure 2A] FIG. 2A is a diagram illustrating bowing of a semiconductor wafer that can occur during processing, according to one embodiment.

[0012] [Figure 2B] FIG. 2B is a graph illustrating the temperature-related hysteresis of a candidate material deposited on a substrate, according to one embodiment. [Figure 2C]FIG. 2C is a graph illustrating the temperature-related hysteresis of a candidate material deposited on a substrate, according to one embodiment. [Figure 2D] FIG. 2D is a graph illustrating temperature-related hysteresis of a candidate material deposited on a substrate, according to one embodiment.

[0013] [Figure 3] FIG. 3 is a diagram illustrating wafer bow of an oxide / nitride layer according to one embodiment.

[0014] [Figure 4] FIG. 4 shows wafer bow estimates for oxide / nitride layers, silicon oxide+silicon nitride, and composite layers according to one embodiment.

[0015] [Figure 5] FIG. 5 is a diagram illustrating the evolution of active side bow of a semiconductor wafer as a function of various layer types, according to one embodiment.

[0016] [Figure 6] FIG. 6 illustrates a substrate processing apparatus for depositing films on semiconductor substrates using any number of processes.

[0017] [Figure 7] FIG. 7 is a block diagram illustrating various components of a system used to perform semiconductor manufacturing processes, according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0018] In this application, the terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" are used interchangeably. Furthermore, the term "partially fabricated integrated circuit" may refer to a silicon wafer during any of the many stages of integrated circuit fabrication thereon. Wafers or substrates used in the semiconductor device industry typically have diameters of about 200 mm or about 300 mm, although the industry is transitioning to substrates having diameters of about 450 mm. In this description, the terms "front side" or "active side" are used to refer to the first side of a semiconductor wafer, while the term "back side" may refer to the opposite side of a semiconductor wafer. The active side or front side is understood to be where most deposition and processing occurs and where the semiconductor device itself is fabricated. The back side is the opposite side of the wafer and typically receives minimal or no processing during fabrication.

[0019] The flow rates and power levels described herein are suitable for processing on 300 mm substrates unless otherwise specified. It should be noted that these flows and power levels may be adjusted for other size substrates as needed. The following detailed description assumes that certain implementations may be performed on wafers. However, the implementations are not so limited. Workpieces may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may take advantage of at least certain of the various implementations include various articles such as printed circuit boards.

[0020] In the following description, numerous specific details are set forth to provide a thorough understanding of particular implementations. The disclosed embodiments may be practiced without some or all of the specific details. In other instances, well-known process operations are not described in detail so as not to unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with specific embodiments, it will be understood that they are not intended to limit the disclosed embodiments.

[0021] As mentioned above, deposition of materials on the active side of a wafer substrate can cause stress and warpage issues in the wafer. These issues are particularly likely when depositing large stacks of materials, such as in the context of 3D-NAND devices. Wafer warpage can complicate subsequent processing steps. For example, if the warpage is too great, the wafer may not chuck properly. Furthermore, certain processing steps (e.g., photolithography) are very precise and will produce poor results if the wafer is not substantially flat during processing.

[0022] One approach to addressing stress and bow issues is to deposit a film on the backside of the wafer. The backside film counters the stress from the active side deposition, resulting in a warped (or bowed less than a predetermined amount, such as at least 150 μm, 100 μm, 75 μm, 60 μm, etc.) wafer with neutral stress (or substantially neutral stress, e.g., less than about + / - 150 MPa). If the film deposited on the active side is stretchable, the backside film should also be stretchable to balance the overall stress. Similarly, if the active side film is compressible, the backside film should also be compressible. Backside films may be deposited by a variety of reaction mechanisms (e.g., chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), low-pressure chemical vapor deposition (LPCVD), etc.). In various cases, plasma-enhanced chemical vapor deposition is used due to the high deposition rates achieved with this type of reaction.

[0023] Certain deposition parameters can be adjusted to produce backside films with desired stress levels. One of these deposition parameters is the thickness of the deposited backside film. Thicker films induce more stress in the wafer, while thinner films (having the same composition and deposited under the same conditions) induce less stress in the wafer. Therefore, to minimize the amount of material consumed in the formation of the backside layer, this layer may be deposited relatively thin under conditions that promote the formation of a highly stressed film. In other implementations, backside films that provide a desired stress level may be produced by depositing silicon oxide and / or silicon nitride layers, each having a predetermined thickness to achieve the desired tensile or compressive stress. In addition to the predetermined thickness layers, the number of silicon oxide and / or silicon nitride layers may be adjusted to the desired tensile or compressive stress. In certain embodiments, the number of silicon oxide and / or silicon nitride layers may be tailored to counteract the tensile or compressive stress induced on the active side of the semiconductor wafer.

[0024] FIG. 1 is a flow chart showing an example of a sequence of operations for reducing warpage of a substrate.

[0025] At 102, an operation (A) can be performed to determine a change in wafer bow as a function of temperature applied to the wafer. Various metrology and / or analysis techniques can be employed to determine or estimate wafer bow, and in particular, wafer bow as a function of temperature. In certain embodiments, a test wafer can be employed to determine wafer bow. The test wafer can be subjected to several front-side or active-side processes, with the bow reflecting internal stresses caused by the front-side processes. In some embodiments, the goal of this processing is to determine a back-side process that compensates for the bow caused by the internal stresses caused by one or more front-side processes. Thus, the test wafer can be fully or partially processed according to the front-side process to be compensated. As an example, the test wafer can have a stack including alternating layers of silicon oxide and silicon nitride (ONON) deposited fully or partially on the front-side or active side of a semiconductor wafer.

[0026] Certain front-side processes result in temperature changes on the wafer. For example, some processes are performed at elevated temperatures (e.g., above about 300°C). Production wafers may be stored at room temperature (e.g., in a front-opening universal pod or FOUP) and wait in line for wafers to be processed. The wafers are heated when they are delivered to a processing chamber where the elevated temperature processing occurs. After processing is complete, the wafers may be cooled, for example, by removal from the processing chamber. This heating-processing-cooling process may introduce a bow sequence that culminates in bow for fully processed wafers.

[0027] To design a backside process (e.g., deposition of one or more backside layers) that accounts for the changes in bow experienced by production wafers during a particular process or group of processes involving temperature changes, test wafers may be evaluated at multiple temperatures that fall within or overlap the range of temperatures experienced by production wafers in the bow-inducing processes.

[0028] In certain embodiments, the test wafers are exposed to at least two or more different temperatures that are within or overlap the range of temperatures experienced by production wafers in the bow-inducing process. In certain embodiments, the test wafers are exposed to a temperature range that covers less than about 50% of the range of temperatures experienced by production wafers in the bow-inducing process. In certain embodiments, the test wafers are exposed to a temperature range that covers at least about 50% of the range of temperatures experienced by production wafers in the bow-inducing process. In certain embodiments, the test wafers are exposed to a temperature range that covers about 80% of the range of temperatures experienced by production wafers in the bow-inducing process. In certain embodiments, the test wafers are exposed to a temperature range that includes at least a range of about 50°C to about 400°C. In certain embodiments, the test wafers are exposed to a temperature range that includes at least a range of about 30°C to about 500°C.

[0029] In a particular embodiment, the test wafer is exposed to a sequence of two additional temperatures in an ascending order, and the same test wafer is exposed to a sequence of two additional temperatures in a descending order, in this manner measuring the temperature hysteresis of bow.

[0030] Wafer bow may be measured by various techniques. One example is a low-coherence laser interferometer that utilizes a Michelson interferometer with a low-coherence light source, such as one or more components of the 413 Series Thickness / Total Change (TTV) Mapping System sold by Frontier Semiconductor Company, 165 Topaz Blvd., Milpitas, California. Such an instrument can measure substrate thickness, warpage, and TTV with or without tape for wafer backgrinding and etch thinning processes. In certain embodiments, bow is not measured directly, or a proxy for bow is measured. For example, internal stresses that cause bow due to front-side processing are measured.

[0031] At 104, an operation (B) can be performed in which information regarding the determined change in wafer bow as a function of temperature is used to determine properties of the backside processing. The temperature response to wafer bow contains information that allows for the design of backside processing to counter wafer bow over a range of temperatures relevant to frontside processing.

[0032] Various backside treatments may be employed. Examples include deposition of one or more layers, etching (wet or dry), implantation / doping, and exposure to plasma. This treatment may specify any one or more of these types of backside treatments to combat temperature-dependent warpage in one or more frontside treatments.

[0033] In various embodiments, the determination of the backside processing to combat warpage employs temperature-dependent information for one or more optional backside processes. For example, the determination may employ data on how a test wafer having a layer of one material (e.g., silicon oxide) warps at different temperatures. In some cases, the determination may employ data on how two different test wafers, each having a different layer of material (e.g., silicon oxide and silicon nitride), warp at different temperatures. In another example, the determination may employ data on how a test wafer from which some material has been etched away (or exposed to plasma) warps at different temperatures. In another example, a first test wafer may include a first material (e.g., silicon nitride) on its backside, and a second wafer may include a deposited layer of a second material (e.g., silicon oxide) on its backside.

[0034] In certain embodiments, one or more test wafers undergoing optional backside processing are exposed to a range of temperatures that substantially tracks the range of temperatures that production wafers are subjected to in a process that introduces bow (i.e., a process that the backside processing will compensate for). In certain embodiments, one or more test wafers undergoing optional backside processing are exposed to a range of temperatures that substantially tracks the range of temperatures that different test wafers are exposed to for the purpose of generating bow versus temperature information for frontside processing (e.g., operation (A) above).

[0035] Various analytical techniques may be employed to determine backside processing to be performed on production wafers to counteract bow caused by one or more processes performed on the front side of the wafer. For example, one technique may compare bow caused by one or more processes at various temperatures with bow caused by each of several optional backside processes at various temperatures. This method may determine a composite backside processing that accounts for bow over a range of temperatures. In certain embodiments, this temperature-dependent comparison may be achieved implicitly, such as by machine learning techniques.

[0036] It will be apparent that in some embodiments, the determined backside processing is a composite of two or more optional / single backside treatments. In one example, the backside processing includes depositing two or more layers on top of each other. In certain embodiments, the layers are of different materials.

[0037] At 106, an operation (C) can be performed in which the backside processing identified in (B) is applied to incoming wafers (e.g., production wafers). In certain embodiments, the same backside processing is applied to one or more batches of wafers without redetermining an appropriately compensatory backside processing. In some embodiments, the same backside processing is applied to all wafers that are subject to a defined process (or process sequence) for which a backside processing has been determined. The backside processing applied to the production wafers at least partially prevents those wafers from warping in response to the frontside processing.

[0038] At 108, an operation (D) can be performed on the front side of the incoming wafer to perform one or more processes.

[0039] If the front side processing parameters are changed (for a production run), the compensating back side processing may be re-determined via operations (A) and (B) described above, where at least warpage versus temperature information for the new or modified front side processing is generated, and the new information obtained is applied in operation (B) to determine the new back side processing.

[0040] In some examples, the backside processing is determined using (i) warpage measurements on test wafers that have undergone frontside processing equivalent to the production processing, (ii) warpage measurements on different test wafers that have undergone optional various backside processing that may counteract the warpage induced by the frontside processing, and (iii) an analytical approach that compares the temperature-dependent warpage obtained via (i) and (ii). This process may be performed on an irregular basis, for example, whenever frontside processing parameters are changed, a new processing chamber is used, or any other change to the production processing is made.

[0041] In certain embodiments, both active side and backside processing may be achieved using one or more RF signals that may operate to generate a plasma, thereby inducing or enhancing a particular wafer fabrication process. Active side and backside processing may be affected by the RF power coupled to the fabrication chamber, the frequency of the RF signal that causes the plasma to form, the plasma exposure time, the temperature of the substrate and reaction chamber, the pressure within the reaction chamber, the flow of inert gas, the composition of the reactants, etc. However, as the high frequency (HF, e.g., about 13.5 MHz or about 27.0 MHz) component of the RF power used to generate the plasma increases, the tensile stress response of the film may also increase, while the compressive stress response may show substantially no change. Exemplary HF RF power may range between about 0 and 2500 watts per station in a multi-station fabrication chamber. Increasing the low frequency (LF, e.g., about 356 kHz, about 400 kHz, etc.) component of the RF power used to generate the plasma may decrease the tensile stress response of the film and increase the compressive stress response of the film. Exemplary LF RF frequencies may range between about 200 kHz and 4 MHz. Exemplary LF power may range between about 0 and 2500 watts per station. In various cases, the combined LF and HF power may range between about 0 and 2500 watts per station. As the plasma exposure time and / or duty cycle increases, the stress response may change, as discussed above, depending on the frequency used and the type of film stress involved. Exemplary RF exposure times depend on the type of deposition occurring. For example, plasma-enhanced chemical vapor deposition involves relatively long plasma exposures, while plasma-enhanced atomic layer deposition involves much shorter, repeated plasma exposures. Increasing the temperature of the substrate during deposition increases both the tensile and compressive stress responses of the film. Exemplary substrate and chamber temperatures, depending on the deposition process, may be between about 25°C and about 650°C. Increasing the pressure in the reaction chamber during deposition may increase the tensile stress response of the film and decrease the compressive stress response of the film. Exemplary chamber pressures range between about 1 and 4 Torr.As the inert gas flow delivered to the reaction chamber during deposition increases, the tensile stress response remains unchanged and the compressive stress response increases. An exemplary flow rate for the inert gas can be between approximately 100 and 5000 sccm. Another parameter that can affect film stress is electrode spacing. Electrode spacing is important because it can affect the electric field above the wafer, which can affect the film density. As the electrode spacing increases, the tensile stress response disappears and the compressive stress response decreases. An exemplary electrode spacing can be between approximately 5 and 30 mm. Other reaction parameters relevant to backside deposition are discussed further below.

[0042] Another variable that can affect the degree of stress in the film is the hydrogen content of the film, which can be controlled by the flow of NH or other hydrogen-containing reactants. One or more of the variables mentioned above may also directly or indirectly affect the hydrogen content of the film.

[0043] As discussed above, stacks of deposited materials are particularly susceptible to wafer stress and bowing. One example of a stack that can cause these problems is a stack having alternating layers of oxide and nitride (e.g., silicon oxide / silicon nitride / silicon oxide / silicon nitride (ONON)). Another example of a stack that is prone to bowing includes alternating layers of oxide and polysilicon (e.g., silicon oxide / polysilicon / silicon oxide / polysilicon). Other examples of stack materials that can be problematic include, but are not limited to, tungsten and titanium nitride. The materials in the stack may be deposited by chemical vapor deposition techniques such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), or direct metal deposition (DMD). These examples are not intended to be limiting. Certain disclosed embodiments may be useful whenever wafer stress and / or bowing is induced due to materials present on the active side of the wafer.

[0044] The active side stack may be deposited to any number of layers and thickness. Typically, the stack includes between about 32 and 72 layers and has a total thickness between about 2 and 4 μm. The stress induced in the wafer by the stack may be between about −500 MPa and about +500 MPa, frequently resulting in bow of between about 200 and 400 μm (for 300 mm wafers), and in some cases even larger.

[0045] The material deposited on the backside of the wafer can be a dielectric material in various embodiments. In certain implementations, oxides and / or nitrides (e.g., silicon oxide and / or silicon nitride) are used. However, in other implementations, silicon-containing reactants that may be used include, but are not limited to, silanes, halosilanes, and aminosilanes. Silanes contain hydrogen and / or carbon groups but do not contain halogens. Examples of silanes include silane (SiH4), disilane (Si2H6), and organosilanes such as methylsilane, ethylsilane, isopropylsilane, t-butylsilane, dimethylsilane, diethylsilane, di-t-butylsilane, allylsilane, sec-butylsilane, t-hexylsilane, isoamylsilane, t-butyldisilane, and di-t-butyldisilane. Halosilanes contain at least one halogen group and may or may not contain hydrogen and / or carbon groups. Examples of halosilanes include iodosilane, bromosilane, chlorosilane, and fluorosilane. Halosilanes, particularly fluorosilanes, may form reactive halide species capable of etching silicon materials, but in certain embodiments described herein, no silicon-containing reactant is present when the plasma is generated. Specific chlorosilanes include tetrachlorosilane (SiCl), trichlorosilane (HSiCl), dichlorosilane (HSiCl), monochlorosilane (ClSiH), chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, t-butylchlorosilane, di-t-butylchlorosilane, chloroisopropylsilane, chloro-sec-butylsilane, t-butyldimethylchlorosilane, t-hexyldimethylchlorosilane, and the like. Aminosilanes contain at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogens, and carbon.Examples of aminosilanes are mono-, di-, tri-, and tetra-aminosilane (H3Si(NH2)4, H2Si(NH2)2, HSi(NH2)3, and Si(NH2)4, respectively), and substituted mono-, di-, tri-, and tetra-aminosilanes, such as t-butylaminosilane, methylaminosilane, tert-butylsilanamine, bis(tert-butylamino)silane (SiH2(NHC(CH3)3)2(BTBAS), tert-butylsilylcarbamate, SiH(CH3)-(N(CH3)2), SiHCl -(N(CH3)2)2, (Si(CH3)2NH)3, etc. A further example of an aminosilane is trisilylamine (N(SiH3)3). Other potential silicon-containing reactants include tetraethyl orthosilicate (TEOS), as well as tetramethoxysilane (TMOS), fluorotriethoxysilane (FTES), trimethylsilane (TMS), octamethyltetracyclosiloxane (OMCTS), tetramethylcyclotetrasiloxane (TMCTSO), dimethyldimethoxysilane (DMDS), hexamethyldisila Hexamethyldisiloxane (HMDS), hexamethyldisiloxane (HMDSO), hexamethylcyclotrisiloxane (HMCTSO), dimethyldiethoxysilane (DMDEOS), methyltrimethoxysilane (MTMOS), tetramethyldisiloxane (TMDSO), divinyltetramethyldisiloxane (VSI2), methyltriethoxysilane (MTEOS), dimethyltetramethoxydisiloxane (DMTMODSO), ethyltriethoxysilane (ETEOS), ethyltrimethoxysilane (ETMOS), hexamethoxydisilane ( cyclic and acyclic TEOS variants such as TEOS (HMODS), bis(triethoxysilyl)ethane (BTEOSE), bis(trimethoxysilyl)ethane (BTMOSE), dimethylethoxysilane (DMEOS), tetraethoxydimethyldisiloxane (TEODMDSO), tetrakis(trimethylsiloxy)silane (TTMSOS), tetramethyldiethoxydisiloxane (TMDEODSO), triethoxysilane (TIEOS), trimethoxysilane (TIMEOS), or tetrapropoxysilane (TPOS).

[0046] Exemplary nitrogen-containing reactants include, but are not limited to, ammonia, hydrazine, and amines (e.g., carbon-containing amines) such as methylamine, dimethylamine, ethylamine, isopropylamine, t-butylamine, di-t-butylamine, cyclopropylamine, sec-butylamine, cyclobutylamine, isoamylamine, 2-methylbutan-2-amine, trimethylamine, diisopropylamine, diethylisopropylamine, and di-t-butylhydrazine, as well as aromatic-containing amines such as aniline, pyridine, and benzylamine. The amines may be primary, secondary, tertiary, or quaternary (e.g., tetraalkylammonium compounds). The nitrogen-containing reactant may contain heteroatoms other than nitrogen; for example, hydroxylamine, t-butyloxycarbonylamine, and Nt-butylhydroxylamine are nitrogen-containing reactants.

[0047] Examples of oxygen-containing co-reactants include oxygen, ozone, nitrous oxide, carbon monoxide, nitric oxide, nitrogen dioxide, sulfur oxides, sulfur dioxide, oxygen-containing hydrocarbons (C x H y O z ), water, mixtures thereof, etc.

[0048] The flow rates of these reactants may depend on the type of reaction used to deposit the backside layer. When CVD / PECVD is used to deposit the backside layer, the flow rate of the silicon-containing reactant may be between about 0.5-10 mL / min (before atomization), e.g., between about 0.5-5 mL / min. The flow rate of the nitrogen-containing reactant, oxygen-containing reactant, or other co-reactant may be between about 3-25 SLM, e.g., between about 3-10 SLM.

[0049] The optimal thickness of the backside layer may depend on the amount of stress induced by deposition on the active side of the wafer and the conditions under which the backside layer is deposited. The backside layer may be deposited to a thickness that results in negligible stress in the wafer (e.g., less than about 150 MPa). In these or other embodiments, the backside layer may be deposited to a thickness that results in negligible wafer bow (e.g., bow less than about 150 μm). In some cases, this corresponds to a backside layer thickness of between about 0.1 and 2 μm, e.g., between about 0.3 and 2 μm, or between about 0.1 and 1 μm, or between about 0.3 and 1 μm. When silicon nitride is used to form the backside layer, a film having a thickness of about 0.3 μm is sufficient to mitigate bow of about 50 to 200 μm. As mentioned above, backside layers with higher stress may be used to reduce the required thickness of the layer, which helps conserve material and reduce costs.

[0050] Thus, in certain other cases, backside deposition is performed in an apparatus specifically designed for deposition on the backside of a wafer, even when the wafer is in the correct upside-down orientation (i.e., the active side of the wafer is facing up). Such an approach eliminates the need to form a protective layer on the active side of the wafer before backside deposition occurs. In some embodiments, the deposition apparatus may be used to deposit on both the active side and the backside of a wafer without flipping the wafer (i.e., the deposition apparatus can perform both active-side deposition and backside deposition without changing the orientation of the wafer). In such cases, various components of the apparatus may be included on both the top and bottom of the reaction chamber (e.g., showerheads or other inlets, outlets, plates or other components for providing a thin gap between the currently non-plated surface of the wafer and the plate, electrical connections, etc.).

[0051] FIG. 2A is a diagram illustrating bowing of a semiconductor wafer that can occur during processing, according to an embodiment.

[0052] As shown in 202 of Figure 2A, the active side of a semiconductor wafer may assume a shape in response to exposure to elevated temperatures during processing. Such elevated temperatures may include, for example, annealing temperatures that occur during deposition and / or etching processes. As shown in 204 of Figure 2A, the result of the hysteresis phenomenon is illustrated in that a semiconductor wafer at room temperature may remain warped after exposure to elevated temperatures. Thus, as shown, even at room temperature, tensile stresses on the active side of the semiconductor wafer may pull the edges of the wafer toward the center of the wafer, resulting in a warped wafer.

[0053] FIG. 2B is a graph of temperature-related hysteresis of a candidate material (referred to as "S1n") deposited on a substrate, according to one embodiment. In the graph of FIG. 2B, the vertical axis corresponds to bow height (in microns), with negative bow height values ​​corresponding to a semiconductor wafer with a convex shape and positive bow height values ​​corresponding to a semiconductor wafer with a concave shape. The horizontal axis of FIG. 2B corresponds to temperature, which may include temperatures from about room temperature (about 30°C) to a relatively high temperature, such as a temperature of about 650°C. The temperature of about 650°C may be a temperature likely to occur during one or more semiconductor processes. As shown in FIG. 2B, the bow height occurring during heating of the semiconductor substrate may be slightly lower, such as between about 0 and about 50 μm, than the bow height occurring during cooling of the wafer. Also, as shown in FIG. 2B, the bow height may differ by about 50 μm after heating and cooling, such as when returning to room temperature (e.g., about 30°C).

[0054] FIG. 2C shows a graph of temperature-related hysteresis of a candidate material (eg, silicon nitride or SiN) deposited on a substrate, according to one embodiment.

[0055] As shown in Figure 2C, when a semiconductor wafer having one or more silicon nitride layers is heated to a temperature between about 30°C (e.g., room temperature) and about 650°C, the height of the silicon nitride bow exhibits hysteresis. The hysteresis between heating and cooling of a semiconductor wafer having one or more silicon nitride layers is particularly pronounced in the temperature range between about 400°C and about 525°C. Furthermore, it should be noted that the height of the bow in Figure 2C is a negative value, which means that the semiconductor wafer exhibits a convex shape.

[0056] FIG. 2D shows a graph of temperature-related hysteresis of a candidate material (eg, silicon oxide or SiO 2 ) deposited on a substrate, according to one embodiment.

[0057] As shown in Figure 2D, when a semiconductor wafer comprising one or more silicon oxide layers is heated from about 30.0°C (e.g., room temperature) to about 425°C, the measured bow height is greater than the bow height measured during the temperature ramp down from about 425°C to about 30°C. During heating between about 425°C and about 550°C, the measured bow height is slightly less than the bow height measured during the cool down, such as from about 550°C to 425°C. Furthermore, it should be noted that the bow height in Figure 2D is depicted as consisting of positive values, indicating a concave shape.

[0058] 2C and 2D, it can be seen that the warpage of a semiconductor wafer can be adjusted to achieve a substantially neutral shape (e.g., substantially flat) without significant concave or convex warpage through the use of silicon oxide (SiO2) layers that can impart a positive warpage height (e.g., corresponding to a concave warpage) versus silicon nitride (SiN) layers that can impart a negative warpage height (e.g., corresponding to a convex warpage). Also, when mounting devices that impart positive or negative warpage to the semiconductor wafer in the active layer, the material composition of the backside of the semiconductor wafer can be adjusted using an appropriate number and thickness of SiN and / or SiO2.

[0059] 3 is a diagram illustrating wafer bow of an oxide / nitride (ONON) layer, according to one embodiment. It can be seen that FIG. 3 illustrates both negative bow (e.g., having a convex shape) as well as positive bow (e.g., having a concave shape) as a function of temperature. In the example shown in FIG. 3, at temperatures between about 25° C. and about 350° C., a semiconductor substrate having one or more oxide / nitride layers may assume a convex shape, and at temperatures between about 350° C. and about 650° C., the semiconductor substrate may assume a concave shape.

[0060] FIG. 4 illustrates wafer bow estimates for oxide / nitride layers (ONON), silicon oxide plus silicon nitride, and composite layers (e.g., layers including ONON and silicon oxide plus silicon nitride), according to one embodiment. As shown in FIG. 4, similar to FIG. 3, the oxide / nitride layer (labeled ONON in FIG. 4) is expected to exhibit negative bow from about 25°C to about 400-450°C, with the bow transitioning from negative to positive at about 450°C. FIG. 4 also illustrates wafer bow caused by SiO2 and SiN. As previously discussed herein, wafer bow may be controlled by adjusting the relative thicknesses of the SiO2 and SiN layers, as well as controlling the number of SiO2 and SiN layers.

[0061] Thus, in the example of FIG. 4, the oxide / nitride (ONON) present on the active side of the semiconductor wafer can be combined with an appropriate number of SiO2 and SiN layers on the backside of the wafer to suppress semiconductor wafer warpage. Thus, as also shown in FIG. 4, when (ONON) is combined with various layers of SiO2 and SiN (SiO2 + SiN in FIG. 4), the sum of the contributions of the active and backside layers is nominal and approaches zero. In certain implementations, some amount of semiconductor wafer warpage may be tolerated, e.g., 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, or more. As long as the semiconductor wafer warpage remains below the aforementioned tolerances, subsequent semiconductor processing, such as photolithography and die singulation, may not be affected.

[0062] FIG. 5 illustrates the evolution of active side bow of a semiconductor wafer as a function of various layer types, according to one embodiment. In FIG. 5, similar to the profiles in FIGS. 3 and 4, a semiconductor substrate comprising an ONON layer exhibits monotonically increasing bow as the temperature increases from approximately 25° C. to 600° C. FIG. 5 also illustrates backside deposition film heating, which corresponds to the backside film produced by a processing tool operating to deposit SiO and / or SiN layers on the backside of the semiconductor wafer. Thus, the backside deposition film heating profile in FIG. 5 generally matches the shape of FIG. 4, with bow increasing in a negative sense as a function of increasing temperature.

[0063] FIG. 5 also includes profiles corresponding to ONON+backside deposition film (heating) as well as ONON+backside deposition film (cooling). In the implementation of FIG. 5, these profiles correspond to the combined effect of ONON applied to the active side of the semiconductor wafer and a layer of SiN / SiO2 applied to the backside of the semiconductor wafer. Thus, as shown, the combined effect of the positive (e.g., concave) bow caused by the ONON deposited on the active side of the semiconductor substrate and the negative (e.g., convex) bow caused by the SiN / SiO2 applied to the backside of the semiconductor wafer results in only nominal bowing of the semiconductor wafer. As depicted in FIG. 5, in this example, bowing due at least in part to hysteresis of the semiconductor wafer may be limited to a value of approximately 20 μm. However, in other embodiments, bowing due to hysteresis may be limited to a different threshold, such as a value less than 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, or 100 μm.

[0064] It can be appreciated that, according to certain embodiments described herein, a set of semiconductor wafers having silicon oxide / silicon nitride films of varying thicknesses and varying numbers may be deposited on the backside of the wafer. Such deposition of silicon oxide / silicon nitride may occur before processing the active side of the semiconductor wafer. Wafers having a particular composition on the backside may be selected for processing according to a desired application, which may require applying a particular treatment to the active side of the semiconductor wafer. In this way, wafer bow may be maintained within a predetermined tolerance during (and after) processing of the wafer active side.

[0065] FIG. 6 illustrates a substrate processing apparatus for depositing films on semiconductor substrates using any number of processes. The apparatus 600 of FIG. 6 utilizes a single processing station 602 of a processing chamber having a single substrate holder 608 (e.g., pedestal) in an interior volume that can be maintained under vacuum by a vacuum pump 618. A gas delivery system 601 and a showerhead 606 are also fluidly coupled to the processing chamber for delivering (for example) film precursors, carrier gases, and / or purge gases, and / or process gases, secondary reactants, etc. An apparatus for generating a plasma within the processing chamber is also illustrated in FIG. 6. The apparatus illustrated schematically in FIG. 6 may be particularly adapted for performing plasma-enhanced CVD.

[0066] For simplicity, the processing device 600 is depicted as a stand-alone processing station (602) of a processing chamber for maintaining a low-pressure environment. However, it will be understood that multiple processing stations may be included in a common processing tool environment (e.g., within a common reaction chamber) as described herein. For example, FIG. 7 (described herein) illustrates a multi-station processing tool implementation, which will be discussed in further detail below. Furthermore, it will be understood that in some implementations, one or more hardware parameters of the processing device 600, including those discussed in detail herein, may be programmatically adjusted by one or more system controllers.

[0067] Station 602 has an electrode 650. Processing chamber station 602 is in fluid communication with a gas delivery system 601 for delivering process gases, which may include liquids and / or gases, to a distribution showerhead 606. Gas delivery system 601 includes a mixing vessel 604 for mixing and / or conditioning the process gases for delivery to the showerhead 606. One or more mixing vessel inlet valves 620 may control the introduction of process gases into the mixing vessel 604.

[0068] Some reactants may be stored in liquid form before vaporization and subsequent delivery to station 602 of the processing chamber. The implementation of FIG. 6 includes a vaporization point 603 for vaporizing the liquid reactant provided to mixing vessel 604. In some implementations, vaporization point 603 may be a heated liquid injection module. In some other implementations, vaporization point 603 may be a heated vaporizer. In still other implementations, vaporization point 603 may be removed from the processing station. In some implementations, a liquid flow controller (LFC) may be provided upstream of vaporization point 603 to control the mass flow of liquid for vaporization and delivery to processing station 602.

[0069] The showerhead 606 distributes process gases and / or reactants (e.g., film precursors) to the substrate 612 in the processing stations, with the flow controlled by one or more valves (e.g., valves 620, 620A, 605) upstream of the showerhead. In the implementation shown in FIG. 6, the substrate 612 is located below the showerhead 606 and is shown resting on a pedestal 608. The showerhead 606 may have any suitable shape and any suitable number and arrangement of ports for distributing process gases to the substrate 612. In some implementations having more than one station, the gas delivery system 601 may include valves or other flow control structures upstream of the showerhead that can independently control the flow of process gases and / or reactants to each station, such that gases are flowed to one station but not to the other stations. Additionally, the gas delivery system 601 may be configured to independently control the process gases and / or reactants delivered to each station in a multi-station apparatus such that the gas compositions provided to different stations are different (e.g., the partial pressures of the gas compositions may be varied simultaneously between stations).

[0070] Volume 607 is located below showerhead 606. In some implementations, pedestal 608 may be raised or lowered to expose substrate 612 to volume 607 and / or to change the volume of volume 607. Optionally, pedestal 608 may be lowered and / or raised during portions of the deposition process to adjust process pressure, reactant concentration, etc. within volume 607.

[0071] 6, the showerhead 606 and pedestal 608 are electrically coupled to a radio frequency power source 614 and matching network 616 for supplying power to the plasma generator. In some implementations, the plasma energy may be controlled (e.g., via a system controller having appropriate machine-readable instructions and / or control logic) by controlling one or more of the process station pressure, gas concentration, RF power source, etc. For example, the radio frequency power source 614 and matching network 616 may be operated at any suitable power for forming a plasma having a desired composition of radical species. Similarly, the RF power source 614 may provide RF power at any suitable frequency or frequencies, and power.

[0072] In some implementations, plasma ignition and maintenance conditions are controlled by appropriate hardware and / or appropriate machine-readable instructions in a system controller, which may provide control instructions via a sequence of input / output control (IOC) instructions. In one example, instructions for setting plasma conditions for plasma ignition or maintenance are provided in the form of a plasma activation recipe of a process recipe. In some cases, process recipes may be arranged sequentially such that all instructions for a process are executed simultaneously with that process. In some implementations, instructions for setting one or more plasma parameters may be included in a recipe preceding a plasma process. For example, a first recipe may include instructions for setting flow rates of an inert gas (e.g., helium) and / or a reactive gas, instructions for setting a plasma generator to a power setpoint, and a time delay instruction for the first recipe. A subsequent second recipe may include instructions for enabling the plasma generator and a time delay instruction for the second recipe. A third recipe may include instructions for disabling the plasma generator and a time delay instruction for the third recipe. It will be appreciated that these recipes may be further subdivided and / or repeated in any suitable manner within the scope of the present disclosure.

[0073] In some deposition processes, plasma strikes last on the order of several seconds or longer in duration. In certain implementations described herein, much shorter plasma strikes may be applied during a processing cycle. These may be on the order of less than 50 milliseconds, with 25 milliseconds being a specific example.

[0074] For simplicity, processing apparatus 600 is depicted in Figure 6 as a stand-alone station (602) of processing chambers for maintaining a low-pressure environment, however, it can be understood that multiple processing stations may be included in a multi-station processing tool environment, such as that shown in Figure 7, which is a schematic diagram of one embodiment of a multi-station processing tool.

[0075] Processing apparatus 700 employs an integrated circuit fabrication chamber 763 that includes multiple fabrication processing stations, each of which may be used to perform a processing operation on a substrate held on a wafer holder, such as pedestal 608 in FIG. 6 , at a particular processing station. In the embodiment of FIG. 7 , integrated circuit fabrication chamber 763 is shown with four processing stations 751, 752, 753, and 754, along with four cables 766 that provide RF power to each of the four processing stations via input port 767. Other similar multi-station processing apparatuses may have more or fewer processing stations depending on the implementation and, for example, the desired level of parallel wafer processing, size / space constraints, cost constraints, etc. Also shown in FIG. 7 is a substrate handler robot 775, which may operate under the control of system controller 790 and is configured to move substrates from a wafer cassette (not shown in FIG. 7 ) from load port 780 into integrated circuit fabrication chamber 763 and onto one of processing stations 751, 752, 753, and 754.

[0076] FIG. 7 also illustrates an embodiment of a system controller 790 employed to control the processing conditions and hardware states of the processing tool 700. The system controller 790 may include one or more memory devices, one or more mass storage devices, and one or more processors. The one or more processors may include a central processing unit, analog and / or digital input / output connections, stepper motor controller boards, etc. In some embodiments, the system controller 790 controls all activity of the processing tool 700. The system controller 790 executes system control software stored on mass storage devices that may be loaded into memory devices and executed on the system controller's hardware processor. The software executed by the system controller's 790 processor may include instructions that control the timing, mixture of gases, fabrication chamber and / or station pressure, fabrication chamber and / or station temperature, wafer temperature, substrate pedestal, chuck and / or susceptor position, number of cycles performed on one or more substrates, and other parameters of a particular process performed by the processing tool 700. These programmed processes may include a variety of processes, including, but not limited to, processes related to determining the amount of buildup on surfaces inside the chamber, processes related to film deposition on substrates, including cycle numbers, and processes related to cleaning the chamber. The system control software, which may be executed by one or more processors of the system controller 790, may be configured in any suitable manner. For example, subroutines or control objects for various process tool components may be written to control the operation of the process tool components necessary to perform various tool processes.

[0077] In some embodiments, software executed by the processor of the system controller 790 may include input / output control (IOC) sequence instructions for controlling the various parameters described above. For example, each stage and deposition cycle of a substrate's deposition may include one or more instructions executed by the system controller 790. Instructions for setting process conditions for an ALD / CFD deposition process stage may be included in the corresponding ALD / CFD deposition recipe stage. In some embodiments, recipe steps may be arranged sequentially such that all instructions for a process step are executed simultaneously with that process step.

[0078] Other computer software and / or programs stored on the mass storage device of the system controller 790 and / or on memory devices accessible to the system controller 790 may be employed in some embodiments. Examples of programs or portions of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program. The substrate positioning program may include program code for processing tool components used to load the substrate onto the pedestal 608 (of FIG. 6) and control the spacing between the substrate and other parts of the processing apparatus 700. The positioning program may include instructions for appropriately moving the substrate in and out of the reaction chamber as needed to deposit a film on the substrate and clean the chamber.

[0079] The process gas control program may include code for controlling gas composition and flow rates, and optionally for flowing gases into one or more processing stations prior to deposition to stabilize the pressure within the processing stations. In some embodiments, the process gas control program includes instructions for introducing gases during film formation on substrates within the reaction chamber. This may include introducing gases in different cycles for one or more substrates within a batch of substrates. The pressure control program may include code for controlling the pressure within the processing station by, for example, adjusting a throttle valve in the processing station's exhaust system, gas flow into the processing station, etc. The pressure control program may include instructions for maintaining the same pressure during different cycles of deposition performed on one or more substrates during batch processing.

[0080] The heater control program may include code for controlling the current to the heating unit 610 (of FIG. 6) used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (such as helium) to the substrate.

[0081] In some embodiments, there may be a user interface associated with the system controller 790. The user interface may include a display screen, a graphical software display of equipment and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0082] In some embodiments, the parameters adjusted by the system controller 790 may relate to processing conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions, etc. These parameters may be provided to a user in the form of a recipe, which may be entered using a user interface. A recipe for an entire batch of substrates may include a compensated number of cycles for one or more substrates in the batch to account for thickness trends during processing of the batch.

[0083] Signals for monitoring the process may be provided by analog and / or digital input connections of the system controller 790 from various process tool sensors. Signals for controlling the process may be output through analog and digital output connections of the process tool 700. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as pressure gauges), thermocouples, etc. Sensors may also be included and used to monitor and determine the buildup on one or more surfaces inside the chamber and / or the thickness of a material layer on a substrate within the chamber. Appropriately programmed feedback and control algorithms may be used in conjunction with data from these sensors to maintain process conditions.

[0084] The system controller 790 may provide program instructions for carrying out the deposition processes described above. The program instructions may control various process parameters such as DC power levels, pressure, temperature, number of cycles for the substrate, amount of buildup on at least one surface inside the chamber, etc. The instructions may control parameters for operating the in-situ deposition of film stacks according to various embodiments described herein.

[0085] For example, the system controller may include control logic for implementing techniques described herein, such as, for example, determining an amount of deposition material currently accumulated on at least an internal region within the deposition chamber, applying the determined amount of deposition material, or a parameter derived therefrom, to a relationship between (i) the number of ALD cycles necessary to achieve a target deposition thickness and (ii) a variable representing the amount of accumulated deposition material to obtain a compensated number of ALD cycles to produce a target deposition thickness that accounts for the amount of deposition material currently accumulated on the internal region within the deposition chamber, and performing the compensated number of ALD cycles on one or more substrates in the batch of substrates. The system may also include control logic for determining that accumulation in the chamber has reached an accumulation limit and, in response to the determination, for stopping processing of the batch of substrates and cleaning the chamber interior.

[0086] 7 , the controller may further control and / or manage the operation of RF subsystem 789, which may generate RF power (e.g., from RF signal source 776) and communicate RF power to integrated circuit fabrication chamber 763 via radio frequency input port 767. As described further herein, such operations may relate to, for example, determining upper and lower thresholds for RF power supplied to integrated circuit fabrication chamber 763, determining the actual (e.g., real-time) level of RF power supplied to integrated circuit fabrication chamber 763, RF power activation / deactivation times, RF power on / off durations, operating frequency, etc.

[0087] In certain embodiments, integrated circuit fabrication chamber 763 may include input ports in addition to input port 767 (additional input ports not shown in FIG. 7 ). Thus, integrated circuit fabrication chamber 763 may utilize eight RF input ports. In certain embodiments, processing stations 751-754 of integrated circuit fabrication chamber 665 may each utilize a first and second input port, where the first input port may transmit a signal having a first frequency and the second input port may transmit a signal having a second frequency. The use of dual frequencies may result in excited plasma characteristics, which may result in deposition rates within certain limits and / or more easily controlled deposition rates. Dual frequencies may produce other desirable results, although claimed subject matter is not limited in this respect. In certain embodiments, frequencies between about 300 kHz and about 65 MHz may be utilized. In some implementations, signal frequencies of about 2 MHz or less may be referred to as low frequency (LF) and frequencies greater than about 2 MHz may be referred to as high frequency (HF).

[0088] In the above detailed description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments or implementations. The disclosed embodiments or implementations may be practiced without some or all of the above specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments or implementations. While the disclosed embodiments or implementations are described in conjunction with specific embodiments or implementations, it will be understood that such description is not intended to limit the disclosed embodiments or implementations.

[0089] The above detailed description has been directed to particular embodiments or implementations for the purpose of illustrating the disclosed aspects. However, the teachings herein can be applied and implemented in many different ways. In the above detailed description, reference is made to the accompanying drawings. While the disclosed embodiments or implementations have been described in sufficient detail to enable those skilled in the art to practice the embodiments or implementations, it should be understood that these examples are not limiting. That is, other embodiments or implementations may be used, and changes may be made to the disclosed embodiments or implementations without departing from the spirit and scope thereof. In addition, the conjunction "or" should be understood to be intended in an inclusive sense herein, where appropriate, unless otherwise specified. For example, the phrase "A, B, or C" is intended to include the possibilities of "A," "B," "C," "A and B," "B and C," "A and C," and "A, B, and C."

[0090] Unless the context of this disclosure clearly requires otherwise, throughout this specification and claims, words like "comprises," "comprising," and the like should be construed in an inclusive sense, i.e., "including but not limited to," as opposed to an exclusive or exhaustive sense. Also, words using the singular or plural generally include the plural or singular, respectively. When the word "or" is used in connection with a list of two or more items, this word includes all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. The term "implementation" refers to implementations of the technologies and techniques described herein, as well as physical objects that embody the structures and / or incorporate the techniques and / or methods described herein. The present disclosure can also be realized in the following forms. [Form 1] 1. A method of performing a process on a wafer, comprising: (a) determining a change in wafer bow with temperature caused at least in part by one or more processes performed on the front side of the wafer; (b) utilizing the determined information regarding the change in wafer bow with temperature to determine a backside processing property of the wafer that counteracts the wafer bow; (c) performing the backside processing specified in (b) on the input wafer; and (d) performing the one or more processes on the front side of the incoming wafer, thereby at least partially preventing warpage of the incoming wafer in response to the one or more processes due to the backside processing performed in (c). A method comprising: [Form 2] 2. The method of claim 1, The method, wherein the one or more processes performed on the front side of the wafer comprises a deposition process. [Form 3] 2. The method of claim 1, The method, wherein the one or more processes performed on the front side of the wafer comprises a multi-layer stack deposition. [Form 4] 2. The method of claim 1, The method, wherein the one or more processes performed on the front side of the wafer comprises oxide / nitride (ONON) deposition. [Form 5] 2. The method of claim 1, The method, wherein the one or more processes performed on the front side of the wafer comprises an etching process. [Form 6] 6. The method according to any one of aspects 1 to 5, The method, wherein the determining the variation of wafer bow with temperature includes measuring wafer bow of a test wafer at a plurality of different temperatures while the temperature of the test wafer is increased. [Form 7] 6. The method according to any one of aspects 1 to 5, The method, wherein the determining the variation of wafer bow with temperature includes measuring wafer bow of a test wafer at a plurality of different temperatures while the temperature of the test wafer is ramped down. [Form 8] 6. The method according to any one of aspects 1 to 5, The method, wherein said determining the change in wafer bow with temperature includes determining hysteresis in wafer bow in response to at least one cycle of increasing and decreasing temperature. [Form 9] 6. The method according to any one of aspects 1 to 5, the determining the variation in wafer bow with temperature includes measuring wafer bow of a test wafer at a plurality of different temperatures within a range of temperatures to which the input wafer is subjected during the one or more processes on the front side of the input wafer. [Form 10] 6. The method according to any one of aspects 1 to 5, The method, wherein the backside processing includes adding one or more layers to the backside of the input wafer. [Form 11] 6. The method according to any one of aspects 1 to 5, The method, wherein determining backside processing properties of the wafer using the information regarding the determined change in wafer bow with temperature includes obtaining bow information with respect to temperature for the test wafer having one or more deposition layers on the backside of the test wafer. [Form 12] 12. The method of claim 11, further comprising: The method, wherein a first test wafer has a layer of a first material on its backside and a second test wafer has a deposited layer of a second material on its backside. [Form 13] 13. The method of claim 12, further comprising: utilizing the determined information regarding the change in wafer bow with temperature to determine backside processing properties of the wafer; depositing a first layer of the first material on the backside of the wafer to a first thickness; depositing a second layer of the second material on the backside of the wafer to a second thickness; The method further comprises determining a backside processing comprising: [Form 14] 1. An apparatus for controlling wafer bow in integrated circuit processing, comprising: one or more processing stations of a multi-station manufacturing chamber; the one or more processing stations are configured to accommodate a corresponding number of semiconductor wafers, each wafer having a backside that has undergone a manufacturing process; the one or more processing stations are further configured to perform a manufacturing process on the active side of each wafer; the one or more processing stations are further configured to cooperate with each semiconductor wafer accommodated therein to maintain wafer bow below a threshold value during the manufacturing process performed on the active side of each wafer. [Form 15] 15. The apparatus of claim 14, The apparatus, wherein the manufacturing process performed on the active side of each wafer includes raising the temperature of the wafer and then lowering the temperature of the wafer. [Form 16] 15. The apparatus of claim 14, The apparatus wherein the manufacturing process performed on the active side of each wafer includes deposition of a material. [Form 17] 15. The apparatus of claim 14, The apparatus wherein the manufacturing process performed on the active side of each wafer includes removal of material from the wafer. [Form 18] The device according to any one of aspects 14 to 17, The apparatus wherein the threshold is about 100 μm and each wafer has a diameter of about 300 mm. [Form 19] The device according to any one of aspects 14 to 17, The apparatus wherein the threshold is about 75 μm and each wafer has a diameter of about 300 mm. [Form 20] The device according to any one of aspects 14 to 17, The apparatus, wherein the multi-station manufacturing chamber includes four processing stations. [Form 21] The device according to any one of aspects 14 to 17, the fabrication process on the backside of each wafer includes depositing a layer of silicon oxide and / or silicon nitride. [Form 22] 1. A method for controlling wafer bow in an integrated circuit manufacturing process, comprising: characterizing wafer bow that occurs in response to performing one or more active manufacturing processes on an active side of an integrated circuit wafer; determining one or more second manufacturing processes to be applied to a backside of the integrated circuit wafer to cause the wafer bow to be below a predetermined threshold based on the one or more active manufacturing processes; performing the one or more second manufacturing processes on the backside of the integrated circuit wafer; A method comprising: [Form 23] 23. The method of claim 22, The method, wherein the one or more active manufacturing processes performed on the active side of the integrated circuit wafer includes elevating the temperature of the integrated circuit wafer. [Form 24] 24. The method of any one of claims 22 or 23, comprising: The method, wherein the one or more active manufacturing processes performed on the active side of the integrated circuit wafer includes depositing a material on the active side of the integrated circuit wafer. [Form 25] 25. The method of claim 24, The method, wherein the material deposited on the active side of the integrated circuit wafer comprises silicon nitride. [Form 26] 25. The method of claim 24, wherein the material deposited on the active side of the integrated circuit wafer comprises silicon oxide. [Form 27] 24. The method of any one of claims 22 or 23, comprising: The method, wherein the one or more active manufacturing processes performed on the active side of the integrated circuit wafer comprises removing material from the active side of the integrated circuit wafer. [Form 28] 24. The method of any one of claims 22 or 23, comprising: performing the one or more second manufacturing processes on the backside of the integrated circuit wafer to reduce the wafer bow to an amount of less than about 100 μm when the wafer has a diameter of about 300 mm. [Form 29] 24. The method of any one of claims 22 or 23, comprising: performing the one or more second manufacturing processes on the backside of the integrated circuit wafer, thereby reducing the wafer bow to an amount of less than about 75 μm when the wafer has a diameter of about 300 mm. [Form 30] 24. The method of any one of claims 22 or 23, comprising: 10. The method of claim 1, wherein performing the one or more second manufacturing processes on the backside of the integrated circuit wafer includes depositing a silicon oxide layer, a silicon nitride layer, or both a silicon oxide layer and a silicon nitride layer on the backside.

Claims

1. 1. A method of performing a process on a wafer, comprising: (a) determining a change in wafer bow with temperature caused at least in part by one or more processes performed on the front side of the wafer; (b) after (a), using the determined information about the change in wafer bow with temperature to determine a property of a backside process of the wafer that counteracts the wafer bow; (c) after (b), performing the backside processing specified in (b) on the input wafer; (d) after (c), performing the one or more processes on the front side of the incoming wafer, thereby at least partially preventing warpage of the incoming wafer in response to the one or more processes due to the backside processing performed in (c); A method comprising:

2. 10. The method of claim 1, The method, wherein the one or more processes performed on the front side of the wafer include a deposition process.

3. 10. The method of claim 1, The method, wherein the one or more processes performed on the front side of the wafer comprises a multi-layer stack deposition.

4. 10. The method of claim 1, The method, wherein the one or more processes performed on the front side of the wafer comprises oxide / nitride (ONON) deposition.

5. 10. The method of claim 1, The method, wherein the one or more processes performed on the front side of the wafer comprises an etching process.

6. The method according to any one of claims 1 to 5, The method, wherein the determining the variation of wafer bow with temperature comprises measuring wafer bow of a test wafer at a plurality of different temperatures while the temperature of the test wafer is increased.

7. The method according to any one of claims 1 to 5, The method, wherein the determining the variation of wafer bow with temperature includes measuring wafer bow of a test wafer at a plurality of different temperatures while the temperature of the test wafer is ramped down.

8. The method according to any one of claims 1 to 5, The method, wherein said determining the change in wafer bow with temperature includes determining hysteresis in wafer bow in response to at least one cycle of increasing and decreasing temperature.

9. The method according to any one of claims 1 to 5, the determining the variation in wafer bow with temperature comprises measuring wafer bow of a test wafer at a plurality of different temperatures within a range of temperatures to which the input wafer is subjected during the one or more processes on the front side of the input wafer.

10. The method according to any one of claims 1 to 5, The method, wherein the backside processing includes adding one or more layers to the backside of the input wafer.

11. The method according to any one of claims 1 to 5, The method, wherein determining backside processing properties of the wafer using the information regarding the determined change in wafer bow with temperature includes obtaining bow information with respect to temperature for the test wafer having one or more deposition layers on the backside of the test wafer.

12. 12. The method of claim 11, The method, wherein a first test wafer has a layer of a first material on its backside and a second test wafer has a deposited layer of a second material on its backside.

13. 13. The method of claim 12, utilizing the determined information regarding the change in wafer bow with temperature to determine backside processing properties of the wafer; depositing a first layer of the first material on the backside of the wafer to a first thickness; depositing a second layer of the second material on the backside of the wafer to a second thickness; The method further comprises determining a backside processing comprising:

14. 1. An apparatus for controlling wafer bow in integrated circuit processing, comprising: one or more processing stations of a multi-station manufacturing chamber; the one or more processing stations are configured to accommodate a corresponding number of semiconductor wafers, each wafer having a backside that has undergone a manufacturing process; the one or more processing stations are further configured to perform a manufacturing process on an active side of each wafer after performing the manufacturing process on the backside; the one or more processing stations are further configured to cooperate with each semiconductor wafer accommodated therein to maintain wafer bow below a threshold value during the manufacturing process performed on the active side of each wafer; the backside fabrication processing is performed prior to the active side fabrication processing to reduce the wafer bow in the fabrication processing performed on the active side, which is performed immediately after the backside fabrication processing.

15. 15. The apparatus of claim 14, The apparatus, wherein the manufacturing process performed on the active side of each wafer includes raising the temperature of the wafer and then lowering the temperature of the wafer.

16. 15. The apparatus of claim 14, The apparatus wherein the manufacturing process performed on the active side of each wafer includes deposition of a material.

17. 15. The apparatus of claim 14, The apparatus wherein the manufacturing process performed on the active side of each wafer includes removal of material from the wafer.

18. 18. The device according to any one of claims 14 to 17, The device, wherein the threshold is 100 μm.

19. 18. The device according to any one of claims 14 to 17, The threshold is 75 μm.

20. 20. The device of claim 18 or 19, The apparatus, each wafer having a diameter of 300 mm.

21. 18. The device according to any one of claims 14 to 17, The apparatus wherein the multi-station manufacturing chamber includes four processing stations.

22. 18. The device according to any one of claims 14 to 17, the fabrication process on the backside of each wafer includes depositing a layer of silicon oxide and / or silicon nitride.

23. 1. A method for controlling wafer bow in an integrated circuit manufacturing process, comprising: determining a change in wafer bow with temperature in response to performing one or more active manufacturing processes on an active side of an integrated circuit wafer; determining one or more second manufacturing processes to be applied to a backside of the integrated circuit wafer to reduce the wafer bow to less than a predetermined threshold based on the one or more active manufacturing processes; performing the one or more second manufacturing processes on the backside of the integrated circuit wafer before performing the one or more active manufacturing processes on the active side of the integrated circuit wafer; Including, The method, wherein the one or more second manufacturing processes are performed prior to the one or more active manufacturing processes to reduce the wafer bow in the one or more active manufacturing processes that are performed immediately after the one or more second manufacturing processes.

24. 24. The method of claim 23, The method, wherein the one or more active manufacturing processes performed on the active side of the integrated circuit wafer includes elevating the temperature of the integrated circuit wafer.

25. 25. The method of claim 23 or 24, The method, wherein the one or more active manufacturing processes performed on the active side of the integrated circuit wafer includes depositing a material on the active side of the integrated circuit wafer.

26. 26. The method of claim 25, The method, wherein the material deposited on the active side of the integrated circuit wafer comprises silicon nitride.

27. 26. The method of claim 25, wherein the material deposited on the active side of the integrated circuit wafer comprises silicon oxide.

28. 25. The method of claim 23 or 24, The method, wherein the one or more active manufacturing processes performed on the active side of the integrated circuit wafer comprises removing material from the active side of the integrated circuit wafer.

29. 25. The method of claim 23 or 24, performing the one or more second manufacturing processes on the backside of the integrated circuit wafer, thereby reducing the wafer bow to an amount less than 100 μm when the integrated circuit wafer has a diameter of 300 mm.

30. 25. The method of claim 23 or 24, performing the one or more second manufacturing processes on the backside of the integrated circuit wafer, thereby reducing the wafer bow to an amount less than 75 μm when the integrated circuit wafer has a diameter of 300 mm.

31. 25. The method of claim 23 or 24, performing the one or more second manufacturing operations on the backside of the integrated circuit wafer includes depositing a silicon oxide layer, a silicon nitride layer, or both a silicon oxide layer and a silicon nitride layer on the backside.

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