Chalcogenide material sealing layer

Abstract

The disclosed technology relates generally to encapsulation layers for semiconductor devices, particularly semiconductor devices that include chalcogenide materials, and methods for making the same. In one aspect, a method for making a semiconductor device includes providing a substrate having an exposed surface that includes a chalcogenide material. The method further includes forming a low-χ metal oxide layer on the chalcogenide material by cyclically exposing the substrate to a low-electronegativity (low-χ) metal precursor and an oxygen precursor that includes O2. The electronegativity of the low-χ metal of the metal precursor is 1.6 or less.

Description

[Technical Field]

[0001] The disclosed technology relates generally to semiconductor devices, and more particularly to encapsulation layers for semiconductor devices that include chalcogenide materials and methods for making the same. [Background technology]

[0002] Nonvolatile memory or storage devices can be switched between memory states, e.g., between logical 1 and 0, by changing the physical state of the storage element. For example, some nonvolatile memory devices, e.g., flash memory devices, can switch memory states by transferring charge into or out of a floating gate configured as a storage element. Some other nonvolatile or storage devices can switch between memory states by changing the resistance in the storage element. The latter type of nonvolatile memory device includes phase change memory (PCM) devices, which include a phase change material in the storage element. PCM devices can be switched by undergoing a phase change, including crystallization and amorphization, in the phase change material of the storage element. Summary of the Invention [Problem to be solved by the invention]

[0003] The need for continued dimensional scaling of PCM devices, improved performance, low temperature integration, variable resistance, voltage / current scaling, and / or three-dimensional (3D) integration, among many other trends, is driving a corresponding need for improved integration schemes in PCM devices. [Means for solving the problem]

[0004] In one embodiment, a method for fabricating a semiconductor device includes providing a substrate having an exposed surface comprising a chalcogenide material. The method further includes forming a low-electronegativity (low-χ) metal oxide layer on the chalcogenide material by cyclically exposing the substrate to a low-electronegativity (low-χ) metal precursor and an oxygen precursor comprising O. In this case, the electronegativity of the low-χ metal of the metal precursor is 1.6 or less.

[0005] In another aspect, a method for fabricating a semiconductor device includes providing a substrate having a chalcogenide layer formed thereon. The method further includes patterning the chalcogenide layer to expose sidewalls of the chalcogenide layer. The method further includes forming a low-electronegativity (low-χ) metal oxide layer on the sidewalls of the chalcogenide layer by cyclically exposing the substrate to a low-χ metal precursor and an oxygen precursor at or below 300° C. without the assistance of a plasma. The electronegativity of the low-χ metal in the metal oxide is 1.6 or less.

[0006] In another aspect, a method for fabricating a semiconductor device includes providing a substrate having a chalcogenide material formed thereon, where the chalcogenide material forms a chalcogenide oxide material in a surface region thereof. The method further includes at least partially chemically reducing the chalcogenide oxide material by exposing the chalcogenide oxide material to a low-electronegativity (low-χ) metal precursor. The low-χ metal of the metal precursor has an electronegativity of 1.6 or less, thereby reducing the oxygen content of the surface region compared to the surface region prior to exposing the chalcogenide oxide material to the low-χ metal precursor.

[0007] In another aspect, a phase change memory device includes a memory cell arranged vertically between a first conductive line extending in a first direction and a second conductive line extending in a second laterally direction intersecting the first laterally direction, the memory cell including a phase change storage element and a selector element. The memory device further includes a low electronegativity (low-χ) metal oxide layer formed on sidewalls of the memory cell, wherein the electronegativity of the low-χ metal of the low-χ metal oxide layer is 1.6 or less. [Brief explanation of the drawings]

[0008] Embodiments of the present disclosure will now be described, by way of non-limiting examples, with reference to the accompanying drawings, in which: [Figure 1] FIG. 1 illustrates an exemplary phase change memory cell configured to be protected by an encapsulation layer, according to an embodiment. [Figure 2] FIG. 2 shows a schematic example of an access operation that can be performed on a phase change memory device. [Figure 3A] FIG. 3A illustrates y- and x-views, respectively, of an exemplary cross-point memory array with memory cells having sidewalls covered with an encapsulation layer, according to an embodiment. [Figure 3B] FIG. 3B illustrates y- and x-views, respectively, of an exemplary cross-point memory array with memory cells having sidewalls covered with an encapsulation layer, according to an embodiment. [Figure 4] FIG. 4 illustrates a schematic diagram of an example precursor delivery sequence for forming an encapsulation layer, according to an embodiment. [Figure 5A] FIG. 5A illustrates a schematic diagram of a method for encapsulating a phase change memory cell, according to an embodiment. [Figure 5B] FIG. 5B illustrates a schematic of a method for forming a sealing layer as part of the encapsulation method illustrated in FIG. 5A. [Figure 6A] 6A-6D illustrate intermediate structures at various stages of fabricating a cross-point array with encapsulated phase change memory cells, according to an embodiment. [Figure 6B] 6B illustrates intermediate structures at various stages of fabricating a cross-point array with encapsulated phase change memory cells, according to an embodiment. [Figure 6C] 6A-6C illustrate intermediate structures at various stages of fabricating a cross-point array with encapsulated phase change memory cells, according to an embodiment. [Figure 6D]6D illustrates intermediate structures at various stages of fabricating a cross-point array with encapsulated phase change memory cells, according to an embodiment. [Figure 6E] 6E illustrates intermediate structures at various stages of fabricating a cross-point array with encapsulated phase change memory cells, according to an embodiment. [Figure 6F] 6F illustrates intermediate structures at various stages of fabricating a cross-point array with encapsulated phase change memory cells, according to an embodiment. [Figure 6G] 6G illustrates intermediate structures at various stages of fabricating a cross-point array with encapsulated phase change memory cells, according to an embodiment. [Figure 6H] 6H illustrates intermediate structures at various stages of fabricating a cross-point array with encapsulated phase change memory cells, according to an embodiment. [Figure 7A] FIG. 7A is a graph showing the experimentally measured change in thickness of a lanthanum oxide layer with aging as a function of the thickness of a hafnium oxide capping layer formed thereon. [Figure 7B] FIG. 7B is a graph showing the experimentally measured change in thickness of a lanthanum oxide layer over time as a function of the thickness of an aluminum oxide capping layer formed thereon. [Figure 8A] FIG. 8A shows a wafer map illustrating locations where experimental adhesion strength testing of encapsulation layers was performed according to an embodiment. [Figure 8B] FIG. 8B shows a scanning electron micrograph (SEM) of the area shown in FIG. 8A where the adhesion strength test was performed. [Figure 8C] FIG. 8C shows an energy dispersive X-ray spectrum (EDS) obtained from one of the locations shown in FIG. 8A where adhesion strength testing was performed. [Figure 9A] FIG. 9A shows a cross-sectional transmission electron micrograph (XTEM) of an encapsulation layer including a LaOx layer and a HfOx layer, according to an embodiment. [Figure 9B] FIG. 9B shows an elemental map obtained from the cross-sectional area shown in FIG. 9A, according to an embodiment. [Figure 9C] FIG. 9C shows the compositional depth profile of the encapsulation layer shown in FIG. 9A. DETAILED DESCRIPTION OF THE INVENTION

[0009] As discussed above, the need for continued dimensional scaling, performance improvements, voltage / current scaling, and / or three-dimensional (3D) integration in PCM devices, among other trends, is driving a corresponding need for improvements in their process integration schemes. Process integration schemes requiring improvements include passivation schemes for memory cells of PCM devices. To understand the need for such improvements, FIGS. 1 and 2 respectively illustrate an exemplary phase change memory cell and an exemplary access operation that can be performed thereon.

[0010] FIG. 1 illustrates an example of a phase-change memory (PCM) device 100 including a PCM cell that can benefit from improved passivation, according to an embodiment. The PCM device 100 includes a memory cell 30 including a phase-change storage element 34 having an intermediate electrode 36 formed on its bottom surface and a top electrode 32 formed on its top surface. The cell stack 30 can further include a selector element 38 that can have a bottom electrode 40 formed on its bottom surface and is separated from the phase-change storage element 34 by the intermediate electrode 36. The selector element 38 can be, for example, a two-terminal selection device. The cell stack 30 including the phase-change storage element 34 and the selector element 38 can be connected at one end to an upper metal line 20, e.g., one of a word line and a bit line, via the top electrode 32, and at the other end to a lower metal line 22, e.g., the other of a word line and a bit line, via the bottom electrode 40.

[0011] In PCM device 100, one or both of phase change memory element 34 and selector element 38 can include a chalcogenide material. Phase change memory element 34 is configured to store a plurality of memory states, which can be non-volatile or persistent. Selector element 38 is electrically connected in series with phase change memory element 34. Selector element 38 is configured as a switch to control the voltage and / or current that can be provided to phase change memory element 34 by a voltage source and / or current source to switch phase change memory element 34 between or among a plurality of memory states.

[0012] FIG. 2 schematically illustrates an exemplary access operation that can be performed on the PCM device 100 described above with respect to FIG. 1. An operation to induce a crystalline-to-amorphous transition in the phase-change storage element 34 (FIG. 1), i.e., a reset operation, is performed by applying a reset pulse 210, e.g., a current or voltage pulse, to the phase-change storage element 34 (FIG. 1) in a low-resistance or set state corresponding to a substantially crystalline state of the phase-change material. The pulse can be applied using the selector element 38 to control its duration and / or magnitude. The reset pulse 210 at least partially melts the phase-change material of the phase-change storage element 34 (FIG. 1) at the melting temperature (Tmelt) of the phase-change material. After the peak of the reset pulse 210 is reached, the phase-change storage element is rapidly quenched within a time sufficiently short enough to prevent substantial recrystallization of the phase-change material.

[0013] 2, the operation of inducing an amorphous-to-crystalline transition of the phase change material, i.e., a set operation, is performed by applying a set pulse 220, e.g., a current or voltage pulse, to the phase change storage element 34 (FIG. 1) in a high-resistance reset state corresponding to a substantially amorphous state of the phase change material. The pulse can be applied by the selector element 38 to control its duration and / or magnitude. The set pulse 220 at least partially recrystallizes the phase change material of the phase change storage element 34 (FIG. 1) at a crystallization temperature (Tcrys).

[0014] The operation to determine the state of the phase change storage element 34 (FIG. 1), i.e., the read operation, can be performed by applying a read pulse 230, e.g., a current or voltage pulse, and sensing the resulting electrical signal using a sensor amplifier. The pulse can be applied using a selector element to control its duration and / or magnitude.

[0015] In the example shown in FIG. 1 , the memory cells 30 are arranged as pillar structures formed from a stack of corresponding multiple layers. As described below, the sidewalls of each of the phase-change storage elements 34 and / or selector elements 38 may be exposed during fabrication. These sidewalls may be exposed to various process environments, such as air and moisture, as well as other process gases and / or liquids. As a result, one or more sidewalls of the phase-change storage elements 34 and / or selector elements 38 may undesirably absorb or chemically react with these gases and / or liquids from the process environment, thereby degrading the device performance of the PCM device 100. Additionally, as discussed above with respect to FIG. 2 , after fabrication, various operations of non-volatile memory devices such as those described herein may expose regions of the phase-change storage elements 34 and / or selector elements 38 to relatively high electric fields and / or high temperatures above the melting temperature of the phase-change material, which may exceed several hundred degrees. Furthermore, these operating conditions may cause chemical reactions between the phase-change storage elements 34 and / or selector elements 38 and elements from surrounding materials, such as oxygen and moisture. Because PCM device 100 may be cycled through these conditions tens or hundreds of thousands of times or more, one or more of the set, reset, or read voltages or currents may degrade over time, leading to reliability failures, some of which may be due to post-manufacturing contamination in various regions of the PCM device, including phase change memory element 34 and / or selector element 38.

[0016] [Phase-change memory cell lined with an encapsulation layer] To address the need to prevent degradation of the PCM device 100 described above, the inventors have identified the need to protect one or both of the phase change memory elements 34 and the selector elements 38 with an encapsulation layer to protect them from moisture, air, or other impurities during fabrication and / or operation. FIGS. 3A and 3B illustrate an exemplary cross-point memory array 300 formed on a semiconductor substrate 18, viewed from the y and x directions, respectively. The cross-point array 300 includes a plurality of memory cells 30 having sidewalls lined with encapsulation, according to an embodiment. Each memory cell 30 is vertically disposed between a first conductive line 20, e.g., a word line or bit line, extending in a first direction, and a second conductive line 22, e.g., the other word line or bit line, extending in a second horizontal direction that intersects the first horizontal direction. Each memory cell 30 has an encapsulation layer 46, 52 formed on one or both sidewalls. The encapsulation layer 46, 52 according to an embodiment includes a low electronegativity (low χ) metal oxide layer 46A, 52A, where the metal of the low χ metal oxide layer 46A, 52A has an electronegativity of 1.6 or less.

[0017] 3A and 3B , each memory cell 30 is a phase-change memory cell and is disposed between an upper conductive line 20 extending in the y-direction and a lower conductive line 22 extending in the x-direction. The upper conductive line 20 and the lower conductive line 22 are electrical conductors configured to transmit electrical signals, such as voltage or current pulses, between the memory cell 30 and peripheral circuitry (not shown), such as drive circuitry and sensor circuitry. The memory cell 30 includes a selector element 38 and a storage element 34 separated by an intermediate electrode 36. The illustrated memory cell 30 further includes a lower electrode 40 between the selector element 38 and the lower conductive line 22, and an upper electrode 32 between the upper conductive line 20 and the phase-change storage element 34. It will be understood that in some embodiments, the positions of the phase-change storage element 34 and the selector element 38 can be interchanged. Furthermore, in some embodiments, one or more of the upper electrode 32, the intermediate electrode 36, and the lower electrode 40 may be omitted.

[0018] Although not shown for clarity and ease of illustration, it will be understood that semiconductor substrate 18 may include various structures processed through the front end of the line and may include various peripheral and / or support devices, such as CMOS transistors that form part of word line and bit line driver circuitry and sensor amplifier circuitry. Additionally, semiconductor substrate 18 may include one or more various structures pre-formed thereon, including, for example, diffusion regions, insulating regions, electrodes, and metallization structures, such as contacts and metal lines, upon which array 300 may be disposed. Some of these devices and structures may limit the thermal budget of the process steps used to fabricate array 300, as described below.

[0019] 3A and 3B, the phase change material of the phase change storage element 34 can include chalcogenide alloy compositions including at least two elements of the GeSbTe (GST) alloy system, such as GeSbTe, GeSbTe, GeSbTe, GeSbTe, GeSbTe, GeSbTe, etc., or chalcogenide alloy compositions including at least two elements of the InSbTe (IST) alloy system, such as InSbTe, InSbTe, InSbTe, InSbTe, etc., among many other chalcogenide alloy systems. The chalcogenide alloy system may further include certain elements, such as doped Si. Other chalcogenide alloy systems may be used that include one or more chalcogenide elements and that can undergo a phase change directly or indirectly in response to an electrical signal. Any suitable deposition technique may be used to form thin film layers from which phase change memory elements can be formed. For example, thin film layers of phase change material may be deposited using, for example, physical vapor deposition, chemical vapor deposition, and atomic layer deposition, from which phase change memory elements 34 may be formed using a combination of suitable patterning techniques.

[0020] 3A and 3B, the upper conductive line 20 and / or the lower conductive line 22 may include a metal. Examples of metals include elemental metals such as Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides such as TiN, TaN, WN, and TaCN; conductive metal silicides such as tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide, and titanium silicide; and conductive metal oxides such as RuO.

[0021] The selector element 38 includes any suitable two-terminal or three-terminal device that can be used to switch the memory state of a phase-change memory element. In some embodiments, the selector element includes a semiconductor device, such as a metal-silicon-oxide (MOS) transistor, a bipolar junction transistor (BJT), a silicon-controlled rectifier (thyristor), a diac, a PN junction diode, or a Schottky diode. In some embodiments, the selector element 38 includes an Ovonic threshold switch (OTS), which is a bidirectional symmetrical two-terminal switch. Some OTSs include chalcogenide compositions. However, unlike the phase-change material of the phase-change memory element 34, the chalcogenide material of the OTS does not crystallize or undergo a phase change. Instead, when a voltage or electric field above a threshold is applied across the OTS, the OTS can be turned on to conduct current therethrough, and when the voltage or electric field is removed, the OTS can be turned off to block current flow therethrough. The OTS can include a chalcogenide composition including any of the chalcogenide alloy systems described above with respect to the phase change memory element 34, and can additionally include elements that can inhibit crystallization, such as arsenic (As), nitrogen (N), and carbon (C). Examples of OTS material systems include the Te-As-Ge-Si, Ge-Te-Pb, Ge-Se-Te, Al-As-Te, Se-As-Ge-Si, Se-As-Ge-C, Se-Te-Ge-Si, Ge-Sb-Te-Se, Ge-Bi-Te-Se, Ge-As-Sb-Se, Ge-As-Bi-Te, and Ge-As-Bi-Se systems, among others. Non-limiting examples of chalcogenide alloy systems that can form OTS include the TeAsGeSi, GeTePb, GeSeTe, AlAsTe, SeAsGeSi, SeAsGeC, SeTeGeSi, GeSbTeSe, GeBiTeSe, GeAsSbSe, GeAsBiTe, and GeAsBiSe alloy systems. A suitable combination of process techniques can be used to form thin film layers from which the OTS can be formed. For example, thin film layers of OTS material can be deposited using, for example, physical vapor deposition, chemical vapor deposition, and atomic layer deposition, and then a suitable combination of patterning techniques can be used to form the selector elements.

[0022] 3A and 3B, the top electrode 32, the middle electrode 36, and the bottom electrode 40 may include materials that electrically connect the working elements of the memory cell but prevent interaction and / or interdiffusion between adjacent materials. For example, depending on the adjacent materials, suitable electrode materials may include one or more conductive and semiconductive materials, such as carbon (C); n-doped polysilicon and p-doped polysilicon; metals including Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides including TiN, TaN, WN, and TaCN; conductive metal silicides including tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide, and titanium silicide; and conductive metal oxides including RuO.

[0023] 3A and 3B, in some embodiments, each layer of memory cells 30 and top and bottom conductive lines 20 and 22 can have lateral dimensions, e.g., widths in the x and y directions, respectively, selected for a particular lithography technology node and can range from about 3 nm to 60 nm, about 5 nm to 40 nm, or about 5 nm to 30 nm, depending on the technology node for the integrated circuit design. Note that smaller or larger dimensions are possible, limited only by the lithography capabilities employed by those skilled in the art. Top and bottom conductive lines 20 and 22 can have lengths in the y and x directions, respectively, selected to be much greater than their widths, e.g., at least 100 times greater or 1000 times greater than their widths.

[0024] Referring to FIG. 3A, the opposite sidewalls (in the x-direction) of the upper conductive lines 20 and the first opposite sidewalls (in the x-direction) of the memory cells 20 are lined with a first encapsulation layer 46, and the spaces between adjacent upper conductive lines 20 and the spaces between adjacent memory cells 30 are filled with a first insulating material 50. Referring to FIG. 3B, the opposite sidewalls (in the y-direction) of the lower conductive lines 22 and the second opposite sidewalls (in the y-direction) of the memory cells 30 are lined with a second encapsulation layer 52, and the spaces between adjacent lower conductive lines 22 and the spaces between adjacent memory cells 30 are filled with a second insulating material 48.

[0025] The first encapsulation layer 46 and the second encapsulation layer 52 may advantageously function to protect one or both of the phase change memory element 34 and the selector element 38 from moisture, air, or other impurities during fabrication. The first encapsulation layer 46 and the second encapsulation layer 52 may further function to minimize cross-contamination and / or material interdiffusion between various elements of the memory cell 30 and surrounding materials, such as adjacent memory cells and insulating materials, during fabrication.

[0026] [Phase-change memory cell sealing layer] As described above, the memory cells according to the embodiments have an encapsulation layer formed on the sidewalls of the phase change storage element and / or selector element to protect them from the environment during fabrication and / or operation. The physical and chemical properties of the encapsulation layer are described below.

[0027] 3A and 3B, one or both of the first and second encapsulation layers 46, 52 comprise an oxide of a low electronegativity metal, i.e., a low electronegativity (low-χ) metal oxide layer 46A, 52A. As described herein, a low-χ metal is a metal having an electronegativity that is less than the electronegativity of an element of the phase change memory element and / or selector element in contact with the low-χ metal oxide layer 46A, 52A. For various phase change materials described herein, the low-χ metal has an electronegativity value of about 1.6 or less. According to embodiments, the electronegativity of the low-χ metal is less than about 1.6, 1.5, 1.4, 1.3, 1.2, 1.1, 1.0, 0.9, 0.8, 0.7, or a value within a range defined by any of these values.

[0028] According to various embodiments, the low-χ metal oxide layer 46A, 52A can be an oxide of a metal (M) that has an electronegativity of less than 1.6 and is one of a rare earth metal, a transition metal, an alkaline earth metal, or an alkali metal. x where M is a low-χ metal and MO x indicates that the oxide may be stoichiometric or non-stoichiometric. For example, when M is La, the low χ metal oxide layers 46A, 52A may be LaO x where x is greater than zero and less than or equal to 1.5 and the stoichiometric lanthanum oxide is La2O3.

[0029] In some embodiments, the low-χ metal can be a rare earth metal. The rare earth metal can be one or more of a lanthanide element and an actinide element. The lanthanide element can be selected from the group consisting of La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. The actinide element can be selected from the group consisting of Ac, Th, Pu, Am, Cm, Bk, Cf, Es, Fm, Md, and No.

[0030] In some other embodiments, the low electronegativity metal may be an alkaline earth metal selected from the group consisting of Mg, Ca, Sr, Ba, and Ra.

[0031] In some other embodiments, the low electronegativity metal may be an alkali metal selected from the group consisting of Li, Na, K, Rb, Cs, and Fr.

[0032] In some other embodiments, the low electronegativity metal can be a transition metal selected from the group consisting of Sc, Ti, V, Mn, Zn, Y, Zr, Nb, Hf, Ta, and Tl.

[0033] 3A and 3B , the inventors have discovered that when the low-χ metal of the low-χ metal oxide layer 46A, 52A that is part of the encapsulation layer 46, 52 has an electronegativity sufficiently low compared to oxygen, which has an electronegativity of 3.44, the encapsulation layer 46, 52 not only functions as a diffusion barrier to protect the memory cell 30 during fabrication and operation, but the encapsulation layer 46, 52 can also chemically reduce existing oxides of the chalcogenide material that may have already formed. The inventors have discovered that this is due to at least some of the phase change storage elements 34 and / or selector elements 38 having an electronegativity that is substantially higher than the electronegativity of the low-χ metal. The inventors have discovered that the low-χ metal of the low-χ metal oxide can attract oxygen from the chalcogenide oxide material, at least in part, due to the relatively large electronegativity difference between the low-χ metal and oxygen compared to the electronegativity difference between the phase change element 34 / selector element 38 and oxygen. Thus, according to embodiments, when the chalcogenide oxide material is exposed to a low-χ metal precursor, the low-χ metal of the low-χ metal oxide 46A, 52A at least partially chemically reduces the chalcogenide oxide material, reducing its oxygen content. For this process to occur efficiently, the inventors have discovered that it can be important for the low-χ metal of the low-χ metal oxide layer 46A, 52A to have an electronegativity of about 1.6 or less.

[0034] According to some embodiments, the low-χ metal oxide layer 46A, 52A, comprising a metal oxide of a low-electronegativity metal, has a thickness effective to function as a barrier and / or chemically reduce the oxide of the chalcogenide material. On the one hand, its thickness must be thick enough to conformally and continuously cover the intended sidewalls of the memory cells 30. On the other hand, its thickness must be less than half the space between adjacent memory cells 30 in each direction, as shown in FIGS. 3A and 3B. The inventors have discovered that the thickness of the low-χ metal oxide layer 46A, 52A can be greater than 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, or a value within a range defined by any of these values.

[0035] The inventors have discovered that some low-χ metal oxide layers may, under certain circumstances, be hygroscopic and thus undesirably absorb or react with moisture over time. This absorption and / or reaction may result in an increase in the thickness of some low-χ metal oxide layers. The inventors have further discovered that, under these circumstances, it may be advantageous to form a capping layer as part of one or both of the first and second encapsulation layers 46, 52 to inhibit the absorption and / or reaction of the low-χ metal oxide with moisture. Thus, returning to FIGS. 3A and 3B , in some embodiments, one or both of the first and second encapsulation layers 46, 52 include corresponding capping layers 46B, 52B formed on the low-χ metal oxide layers 46A, 52A, respectively. The inventors have discovered that certain high-K dielectrics are particularly effective for this purpose.

[0036] According to these embodiments, one or both of the first and second encapsulation layers 46, 52 further include a corresponding capping layer 46B, 52B, which has a high-K dielectric material including an oxide of Al, Zr, or Hf. For example, the capping layer may include one or more of Al2O3, ZrO2, and HfO2. The capping layer may include AlO x , ZrO x , and HfO x The oxide layer may be a sub-stoichiometric oxide layer represented as:

[0037] It will be appreciated that the capping layer 46B, 52B, if present, has a thickness sufficient to conformally and continuously cover the corresponding low-χ metal oxide layer 46A, 52A, while its thickness must be small enough so that the total thickness of the first and second encapsulation layers 46, 52 is less than half the space between adjacent memory cells 30 in each direction, as shown in Figures 3A and 3B. The inventors have determined that the thickness of the capping layer, if present, does not exceed 0.5 nm, 1 nm, 2 nm, 4 nm, 5 nm, or a value within a range defined by any of these values.

[0038] Cyclic deposition of encapsulation layers for phase-change memory cells. As described above, memory cells according to embodiments have encapsulation layers formed on their sidewalls to protect one or both of the phase change storage element and the selector element from the environment during processing and / or operation. Returning to Figures 3A and 3B, in addition to the various properties described above, it is advantageous for one or both of the first and second encapsulation layers 46, 52 to be deposited using the cyclic deposition methods described herein.

[0039] Cyclic deposition processes, such as atomic layer deposition (ALD), can provide relatively conformal thin films with relatively high thickness uniformity and precision over structures with relatively high aspect ratios (e.g., 2:1). While generally less conformal and uniform than ALD, thin films deposited using continuous deposition processes, such as chemical vapor deposition (CVD), can offer high productivity and low cost. According to embodiments, first and second encapsulation layers 46, 52 are formed in spaces formed between lines or pillars of memory cell 30 (FIGS. 3A and 3B), where the spaces have relatively small widths and / or high aspect ratios. For example, the spaces may have widths less than 20 nm, 15 nm, 10 nm, 5 nm, or values ​​within a range defined by any of these values. Thus, according to embodiments, first and second encapsulation layers 46, 52 are advantageously formed using a cyclic deposition process, such as ALD, as described herein. In particular, the cyclic deposition process according to embodiments is a thermal cycle deposition process that relies on chemical reactions between thermally activated precursors without the assistance of a plasma.

[0040] Cyclic deposition processes, including atomic layer deposition (ALD) according to embodiments, involve alternately exposing a substrate to multiple precursors to form a thin film in a layer-by-layer manner, precisely controlling the film's properties, such as conformality, uniformity, stress, and barrier properties against oxygen, moisture, and various other impurities. Reactants, i.e., precursors, can include oxidizing and reducing reactants that are alternately introduced into a reaction chamber in which the substrate is disposed. The introduction of one or more reactants or precursors can be alternated with purging and / or pumping processes to remove excess reactants or precursors from the reaction chamber. Precursors or reactants can be introduced into the reaction chamber for a suitable period of time under conditions such that the surface on which the sealing layer is to be deposited is at least partially saturated, e.g., substantially saturated, with the precursors or reactants and / or reaction products of the reactants. Excess or residual precursors or reactants can then be purged and / or pumped out of the reaction chamber. The pumping process can be performed by a suitable suction pumping process, and the purging step can be performed by introducing a non-reactive or inert gas, such as nitrogen or a noble gas, into the reaction chamber. 4 shows an example precursor delivery sequence for forming an encapsulation layer, according to an embodiment. Referring to FIG. 4 , a cyclical deposition cycle, or ALD cycle, includes a first subcycle 400A, i.e., a vapor deposition phase, and a second subcycle 400B, i.e., a vapor deposition phase. The first subcycle 400A includes exposing 404 a substrate to a first precursor, and the second subcycle 400B includes exposing 416 a substrate to a second precursor. The first subcycle 400A can be performed through a first ALD precursor delivery line including a first ALD valve, and the second subcycle 400B can be performed through a second ALD precursor delivery line including a second ALD valve.

[0041] In some embodiments, one or both of the first subcycle 400A and the second subcycle 400B include respective continuous purges 412, 424 with an inert gas, such as Ar or N. In some embodiments, one or both of the first subcycle 400A and the second subcycle 400B include respective rapid purges 408, 420 with an inert gas, respectively, following exposure to one or both of the first and second precursors. The rapid purges 408, 420 can be performed at a higher flow rate than the continuous purges 412, 424. In some embodiments, one or both of the continuous purges and rapid purges can be omitted from one or both of the first and second subcycles 400A, 400B. In these embodiments, instead of a rapid purge, the precursors can be pumped out without a purge gas. It will be understood that the illustrated precursor delivery sequence may be a schematic representation of a sequence for forming one or both of the low-χ metal oxide layers 46A, 52A (FIGS. 3A and 3B) and capping layers 46B, 52B (FIGS. 3A and 3B) described above. In the following, the deposition method for forming the low-χ metal oxide layers 46A, 52A of the encapsulation layers 46, 52 will be described first, followed by the deposition method for forming the capping layers 46B, 52B.

[0042] Figure 5A illustrates a schematic diagram of a method for fabricating a phase change memory cell according to an embodiment. The method 500 includes providing a substrate and forming an encapsulation layer. Figure 5B illustrates a schematic diagram of forming the encapsulation layer as part of the method illustrated in Figure 5A.

[0043] 5A, a method 500 of fabricating a phase change memory cell includes providing a substrate having an exposed surface including a chalcogenide layer 510. The method 500 further includes forming an encapsulation layer 520 including a low-χ oxide layer on the chalcogenide layer by cyclically exposing the substrate to a low-χ metal precursor and an oxygen precursor, e.g., O, where the low-χ metal of the low-χ metal oxide layer has an electronegativity of 1.6 or less. Referring to FIG. 5B, forming the sealing layer 520 includes exposing the substrate to one or more first sub-cycles or vapor deposition stages 400A (FIG. 4), each including an exposure to a low-χ metal precursor, and exposing the substrate to one or more second sub-cycles or vapor deposition stages 400B (FIG. 4), each including an exposure to an oxygen precursor, 530.

[0044] 5A, providing a substrate 510 may include providing a semiconductor substrate 18 (FIGS. 3A and 3B) having a surface including a chalcogenide material. For example, providing a substrate may include lithographically patterning a layer stack to expose sidewalls of the memory cells 30 (FIGS. 3A and 3B) before forming one or both of the one or more first and second encapsulation layers 46, 52. The exposed sidewalls may expose one or both of the phase change storage elements 34 and the selector elements 38. Forming an encapsulation layer 520 may include forming at least a low-χ metal oxide layer, as described below.

[0045] 5B , in various embodiments, exposing the substrate 525 during each of the one or more first deposition stages includes exposing the substrate one or more times to a low-χ metal precursor and one or more times to an oxygen precursor. Each exposure to the low-χ metal precursor may result in the substrate surface being substantially or partially saturated with the metal precursor after the exposure. After exposing the substrate to the low-χ metal precursor, excess or residual metal precursor and / or its reaction products that do not remain adsorbed or chemisorbed on the substrate surface may be removed from the substrate surface, for example, by pumping and / or purging from the process chamber. Each exposure to the oxygen precursor can result in the substrate surface being substantially or partially saturated with the oxygen precursor after the exposure. After the substrate is exposed to the oxygen precursor, excess or residual oxygen precursor and / or its reaction products that do not remain adsorbed or chemisorbed on the substrate surface can be removed from the substrate surface, for example, by pumping and / or purging from the process chamber. The substrate can be subjected to one or more first and second deposition steps to form one or more monolayers or regions formed substantially of a low-χ metal oxide.

[0046] In some embodiments, multiple exposures to low-χ metal precursors in a given first deposition step may be performed sequentially. Similarly, multiple exposures to oxygen precursors in a given second deposition step may be performed sequentially. Advantageously, under some circumstances, exposing the substrate more than once to low-χ metal and / or oxygen precursors may result in higher surface saturation, for example, by exposing more reactive sites for adsorption of the respective precursors when substantial steric hindrance effects are present.

[0047] It will be appreciated that in various embodiments, the number of cycles, each comprising one or both of the first and second deposition steps, the frequency and number of repetitions of the first deposition step, the frequency and number of repetitions of the second deposition step, the frequency and number of repetitions of exposing the substrate to the low-χ metal precursor during the first deposition step, and the frequency and number of repetitions of exposing the substrate to the oxygen precursor during the second deposition step, as described herein, can be varied based on various considerations, including the susceptibility of the precursors to steric hindrance effects, to obtain the desired thickness, stoichiometry, and other properties described herein in the resulting low-χ metal oxide layer and the resulting encapsulating layer.

[0048] As discussed above, the inventors have discovered that low-χ metals can be effective for chemically reducing or depleting the oxygen content of chalcogenide oxide materials. In these embodiments, the inventors have discovered that it can be particularly advantageous to begin deposition of one or both of the first and second low-χ metal oxides 46A, 52A with a low-χ metal precursor. In these embodiments, referring to FIG. 5B , exposing the substrate to one or more first vapor-phase deposition steps 525, each including exposure to a low-χ metal precursor, precedes any exposing the substrate to one or more second vapor-phase deposition steps 530, each including exposure to an oxygen precursor. Exposing the substrate to the low-χ metal precursor as the first precursor effectively provides low-χ metal atoms in the vicinity of the underlying chalcogenide oxide material for chemical reaction with oxygen atoms of the chalcogenide oxide material.

[0049] Alternatively, in some embodiments, forming the low-χ metal oxide layers 46A, 52A as sub-stoichiometric oxide layers can have the similar effect of chemically reducing and reducing the oxygen content of the chalcogenide oxide material. In these embodiments, the low-χ metal oxide layers 46A, 52A of the first and second encapsulation layers 46, 52 can be deficient in oxygen content by at least 10%, 20%, 30%, or 50%, respectively, compared to a stoichiometric oxide, or can have a deficient value within a range defined by any of these values.

[0050] The following metal and oxygen precursors can be used as non-limiting examples to deposit low-χ metal oxide layers 46A, 52A (FIGS. 3A, 3B) according to embodiments.

[0051] A non-limiting example of an Sr precursor includes bis(2,2,6,6-tetramethyl-3,5-heptanedionato) strontium (“Sr(tmhd)2”).

[0052] Non-limiting examples of La precursors include tris-isopropylcyclopentadienyl lanthanum ("La(iPrCp)"), tris-formamidinate lanthanum ("La(fAMD)"), and tris(2,2,6,6-tetramethyl-3,5-heptanedionate) lanthanum ("La(tmhd)").

[0053] Non-limiting examples of Ti precursors include TiCl4, StarTi, tetrakis-dimethylaminotitanium ("TDMAT"), tetrakis-diethylaminotitanium ("TDEAT"), tetrakis-ethylmethylaminotitanium ("TEMAT"), titanium tetrakis-isopropoxide ("TTIP"), titanium methoxide, titanium ethoxide, titanium t-butoxide, chlorotriisopropoxytitanium, titanium 2-ethylhexyloxide, and titanium oxyacetylacetonate.

[0054] Non-limiting examples of Nb precursors include tert(butylimido)tris(diethylamido)niobium(V) (“TBTDENb”).

[0055] Non-limiting examples of Ta precursors include tert-butylimidotrisdiethyltantalum ("TBTDETa") and tert-butylimidotrisethylmethylaminotantalum ("TBITEMATa").

[0056] Non-limiting examples of Mg precursors include bis-ethylcyclopentadienyl magnesium ("Mg(CpEt)"), tetra(2,2,6,6-tetramethyl-3,5-heptanedionate) magnesium ("Mg(tmhd)"), and Mg(tmhd)(EtOH), where tmhd is 2,2,6,6-tetramethyl-3,5-heptanedionate.

[0057] Non-limiting examples of Ce precursors include Ce(iPrCp)3, Ce(tmhd)4, and Ce(tmhd)3phen, where iPrCp is isopropylcyclopentadienyl, where tmhd is 2,2,6,6-tetramethyl-3,5-heptanedionate, and where phen is 1,10-phenanthroline.

[0058] Non-limiting examples of Gd precursors include tris(2,2,6,6-tetramethyl-3,5-heptanedionate) gadolinium ("Gd(tmhd)"), trisisopropylcyclopentadienyl gadolinium ("Gd(iPrCp)"), (tris(2,3-dimethyl-2-butoxy) gadolinium(III)) ("Gd[OC(CH)CH(CH)]"), and Gd(CpCH), where Cp is cyclopentadienyl (CH).

[0059] Non-limiting examples of Dy precursors include Dy(tmhd)3, where tmhd is 2,2,6,6-tetramethyl-3,5-heptanedionate.

[0060] Non-limiting examples of Er precursors include Er(tmhd)3, where tmhd is 2,2,6,6-tetramethyl-3,5-heptanedionate.

[0061] Non-limiting examples of Y precursors include yttrium tris(N,N'-diisopropylacetamidinate) ("Y(iPr2amd)3"), (CpCH3)3Y, where Cp is cyclopentadienyl, and tris(2,2,6,6-tetramethyl-3,5-heptanedionate)yttrium ("Y(tmhd)3").

[0062] Non-limiting examples of Sc precursors include tris(2,2,6,6-tetramethyl-3,5-heptanedionato)scandium (Sc(tmhd)), Sc(MeCp), and Sc(MeCp)(Mepz), where MeCp is methylcyclopentadienyl and Mepz is 3,5-dimethylpyrazolate.

[0063] According to various embodiments, non-limiting examples of oxygen precursors for forming the first and second low-χ metal oxide layers 46A, 52A include O 2 , O 3 , and HO. The inventors have discovered that, depending on the circumstances, one oxygen precursor may be preferable to another. For example, the inventors have discovered that while O 3 can generally provide relatively high growth rates and high film density, it can detrimentally cause further oxidation of the chalcogenide material of one or both of the phase change memory element and the selector element. As a result, preferred embodiments employ O 2 to limit undesired oxidation of the chalcogenide material of one or both of the phase change memory element and the selector element. Limiting undesired oxidation can be important, for example, when the lateral dimensions of memory cells are on the scale of less than 20 nm. At such dimensions, the effective amount of chalcogenide material available for either storage or threshold switching can be significantly reduced by oxidation of the chalcogenide material. On the other hand, for example, when memory cells have relatively large dimensions, e.g., >20 nm, further oxidation is not a significant issue, and O 3 can be employed for high film quality and productivity.

[0064] To deposit capping layers 56B, 52B (FIGS. 3A, 3B) according to embodiments, the following metal precursors and oxygen precursors can be used, by way of non-limiting example:

[0065] A non-limiting example of an Al precursor includes Al(CH3)3 ("TMA").

[0066] Non-limiting examples of Hf precursors include Hf[N(CH3)(C2H5)]4 ("TEMAH") and Hf[N(CH3)2]4.

[0067] Non-limiting examples of Zr precursors include Zr[N(CH3)(C2H5)]4 ("TEMAZ"), Zr[N(CH3)(C2H5)]4 ("TEMAZ"), and Zr[N(CH3)2]4, and Zr[N(CH3)2]4.

[0068] Non-limiting examples of oxygen precursors for forming the capping layer include O, O, and HO. The inventors have discovered that because the capping layers 46B, 52B (FIGS. 3A, 3B) are formed on the low-χ metal oxide layers 46A, 52A (FIGS. 3A, 3B), if present, already formed on the chalcogenide material, the use of O may not cause substantial further oxidation of the chalcogenide material. Thus, O may be suitable for depositing the capping layer at higher growth rates and higher film densities under some circumstances, e.g., when the thickness of the low-χ metal oxide layers 46A, 52A exceeds 2 nm. However, if the first and second low-χ metal oxide layers 46A, 52A are relatively thin, e.g., less than 2 nm, O may be used such that further oxidation of the chalcogenide material of one or both of the phase change storage elements and the selector elements can still occur despite the presence of the low-χ metal oxide layers 46A, 52A.

[0069] The low-χ metal oxide layers 46A, 52A (FIGS. 3A and 3B) and capping layers 46B, 52B (FIGS. 3A and 3B) can be formed at relatively low temperatures. Low-temperature deposition can be important for several reasons to protect chalcogenide materials as described herein. For example, the encapsulation layers 46, 52 (FIGS. 3A and 3B) are advantageous in that they can be performed at deposition temperatures that do not exceed the thermal budgets of most back-end-of-line (BEOL) portions of the process flow for fabricating PCM memory devices. In some PCM devices, the thermal budget can be as low as 400°C or less to prevent degradation of metallization structures and / or alter the properties of diffused semiconductor regions or devices formed in the substrate, as discussed above. Furthermore, when formed after the formation of phase-change memory elements, the encapsulation layers 42, 56 are advantageous in that they can be formed at deposition temperatures that significantly alter the nanostructure or microstructure, e.g., crystallization, of the phase-change memory elements. When it is advantageous for the phase-change memory elements to maintain the amorphous phase throughout the manufacturing process, the low deposition temperature of the encapsulation layers 46, 52 can prevent substantial crystallization of the phase-change memory elements. In these embodiments, the deposition temperature can be lower than the crystallization temperature of the phase-change memory elements. Maintaining the amorphous phase of the phase-change memory elements throughout the manufacturing process can be advantageous in some situations, such as when reliability testing the phase-change memory elements after manufacturing without applying significant test currents. According to embodiments, to achieve these and other advantages, the low-χ metal oxide layers 46A, 52A and capping layers 46B, 52B can be formed at a substrate temperature between 200°C and 250°C, between 250°C and 300°C, between 300°C and 350°C, between 350°C and 390°C, between 350°C and 400°C, or a temperature within a range defined by any of these values, such as 285°C.

[0070] [Method of lining the sidewalls of a phase change memory cell with an encapsulation layer] The following describes, by way of example, an integration scheme for fabricating a phase-change memory device including encapsulated memory cells according to embodiments. Figures 6A-6H show intermediate structures at various stages in fabricating a cross-point array with encapsulated phase-change memory cells according to embodiments to arrive at array 300 (Figures 3A and 3B). Figures 6A, 6C, 6E, and 6G are cross-sectional views of the intermediate structure of the cross-point memory array at various stages of fabrication in the y-direction (e.g., bit line direction), and Figures 6B, 6D, 6F, and 6H are cross-sectional views of the intermediate structure of the cross-point array in the x-direction (e.g., word line direction).

[0071] 6A and 6B, a method for fabricating a memory array includes forming a memory cell material stack on a substrate 18. The illustrated stack includes a bottom conductive material 22a formed on the substrate 18 and a memory cell material stack formed thereon, which includes a bottom electrode material 40a on the bottom conductive material 22a, a selector element material 38a on the bottom electrode material 40a, an intermediate electrode material 36a on the selector element material 38a, a phase change memory element material 34a on the intermediate electrode material 36a, and a top electrode material 32a on the phase change memory element material 34a. The bottom conductive material 22a and the above features of the memory cell material stack can be formed by deposition techniques such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD), among others.

[0072] 6C and 6D, the method for fabricating a memory array further includes subtractively patterning the memory cell material stack and the bottom conductive material 22a (FIGS. 6A and 6B) by patterning with a first photomask and a first etching process to form a memory cell line stack on the bottom conductive line 22, both extending in the x-direction. The memory cell line stack includes a bottom electrode line 40b on the bottom conductive line 22, a first active element line 38b (e.g., a memory element line) on the bottom electrode line 40b, an intermediate electrode line 36b on the first active element line, a second active element line 34b (e.g., a memory element line) on the intermediate electrode line 36b, and an upper electrode line 32b on the second active element line 34b.

[0073] 6C and 6D, after the formation of the memory cell line stacks, an encapsulation layer 52a is formed on the line stacks extending in the x-direction, including on their sidewalls, as shown in FIG. 6D. The first encapsulation layer 52a can include one or both of a low-χ metal oxide layer and a capping oxide layer, each formed using the thermal cyclic deposition method described above. It will be appreciated that for advanced technology nodes, e.g., 20 nm and above, a thermal cyclic deposition process, such as thermal ALD, can be particularly advantageous in applying the encapsulation layer 52a inside the high-aspect ratio trenches between the memory cell line stacks.

[0074] 6C and 6D, the inter-line spaces between adjacent memory cell line stacks are filled with a dielectric material to form insulating dielectric regions 48a. Suitable dielectric materials for filling these spaces can include, for example, silicon oxide and silicon nitride, which can be deposited by any suitable gap-fill process known in the art. Once the inter-line spaces between adjacent memory cell line stacks are filled, the intermediate array structure 100b can be chemically mechanically polished (not shown) to form alternating memory cell line stacks in the y-direction and insulating dielectric regions 48a.

[0075] Referring to the intermediate array structure 100c of FIGS. 6E and 6F, the method for fabricating a memory array further includes depositing an upper conductive material and subtractively patterning it using a second photomask to form a plurality of upper conductive lines 20 extending in the y-direction. The upper conductive material can comprise a similar or identical material to the lower conductive lines 22 and can be formed using a substantially similar or identical process described above for forming the lower conductive lines 22. When so formed, the plurality of upper conductive lines 20 are disposed over the alternating memory cell line stacks and the insulating dielectric regions 48b. The upper conductive lines 20 extend in the y-direction and intersect with the memory cell line stacks extending in the x-direction. Forming the upper conductive lines 20 exposes portions of the top electrode lines 32b of the alternating line stacks, as well as portions of the initial insulating dielectric regions 48b between adjacent upper conductive lines 20, as shown in FIG. 6E.

[0076] 6G and 6H, the method of forming a memory array further includes removing at least the upper portions of the exposed portions of the memory cell line stacks of Figures 6E and 6F to form pillars of memory cells at the intersections of the lower conductive lines 22 and the upper conductive lines 20. In the illustrated embodiment, the entire exposed portions (top and bottom portions) of the memory cell line stacks are removed by stopping the etch at the lower conductive lines 22 (or at an etch stop layer thereon), and the resulting pillars include the top electrode 32, the phase change memory element 34, the middle electrode 36, the selector element 38, and the bottom electrode 40. In other embodiments, etching can be stopped after etching any layer above bottom conductive line 22, such that any one of the cell stack component layers, such as bottom electrode 40 or first active device 38, may form a line similar to bottom electrode line 22. The intermediate structure 100d thus formed includes pillars of memory cells formed at the intersections of bottom conductive line 22 and top conductive line 20 separated by spaces 50 in the x-direction.

[0077] After forming the pillars of the memory cells between the lower conductive lines 22 and the upper conductive lines 20, the method of forming the memory array includes forming a second encapsulation layer 46 on the sidewalls of the pillars shown in FIG. 6G, and then filling the gaps formed between the pillars with an insulating material 50, thereby arriving at the intermediate structure 300 described above with respect to FIGS. 3A and 3B. Similar to the first encapsulation layer 52, the second encapsulation layer 46 can include one or both of a low-χ metal oxide layer 46A and a capping oxide layer 46B formed using the thermal cyclic deposition process described above. A thermal cyclic deposition process, e.g., ALD, can be particularly advantageous for applying the encapsulation layer 46 inside the high-aspect-ratio trenches between memory cell pillars. In subsequent processing, the intermediate structure 300 can be chemical-mechanically polished to remove the insulating material 50 on the top surfaces of the upper conductive lines 20 before forming BEOL metallization structures to electrically connect the memory cells 30. When formed in this manner, the combination of the encapsulation layers 46 and 52 can surround the memory cells 30 to completely encapsulate them in all directions.

[0078] [Example] 7A is a graph showing experimentally measured changes in thickness of a lanthanum oxide layer over time as a function of the thickness of a hafnium oxide capping layer formed thereon, according to an embodiment. As discussed above, the increasing thickness over time can be an indication of absorption of and / or reaction with moisture from the environment into the low-χ oxide layer. FIG. 7B is a graph illustrating the experimentally measured change in thickness of a lanthanum oxide layer over time as a function of the thickness of an aluminum oxide capping layer formed thereon, according to an embodiment. In Figures 7A and 7B, the x-axis represents the thickness of the capping layer, and the y-axis represents the thickness of the underlying low-χ metal oxide layer. In each of the experimental measurements shown in Figures 7A and 7B, a lanthanum oxide layer was deposited as the low-χ metal oxide layer of the encapsulation layer with varying amounts of capping layer, and the measured changes in lanthanum layer thickness were determined by the inventors to correlate with absorption and / or reaction with moisture. The arrows indicate the magnitude of the change in lanthanum oxide layer thickness. Lanthanum oxide layers were deposited using a Eugenus QXP-8300® ALD system with 1 M tris(isopropylcyclopentadienyl)lanthanum (La(iPrCp)3) in decalin as the low-χ precursor and oxygen as the oxygen precursor. For samples with hafnium oxide and aluminum oxide layers to protect the underlying lanthanum oxide layer from moisture in the air, the hafnium oxide and aluminum oxide layers were deposited in situ at 285 °C to thicknesses of 6 Å and 10 Å, respectively, using the same QXP-8300® ALD system with TEMAH and TMA as metal precursors. As shown, the lanthanum oxide layer without a capping layer formed thereon increased in thickness by more than 50% compared to the original thickness. In contrast, the 6 Å capping layers of hafnium oxide and aluminum oxide significantly reduced the thickness increase. The 10 Å capping layers of hafnium oxide and aluminum oxide substantially maintained the thickness of the lanthanum oxide layer within experimental error.

[0079] 8A-8C illustrate experimental evaluations of the adhesion strength of encapsulation layers formed in accordance with embodiments. FIG. 8A shows a wafer map on which experimental adhesion strength testing of the encapsulation layer was performed. The encapsulation layer must have high adhesion strength to underlying layers, such as the sidewalls of the phase change memory cells described herein. Therefore, adhesion strength of lanthanum oxide layers formed on Si substrates was performed using a tape test, in which adhesive tape was applied to the lanthanum oxide layer, peeled off, and visually observed to determine whether the lanthanum oxide layer had detached. The center, middle, and edge regions of the wafer, marked on the substrate map shown on the left side of Figure 8A, were tested for within-wafer uniformity of adhesion strength. To statistically quantify adhesion failure, before tape application, each square region shown in Figure 8A was scribed with a diamond pencil to create a 10 × 10 matrix containing 100 squares, as shown on the right side of Figure 8A. Tape was then applied to the square region on the encapsulation layer and removed by pulling it perpendicularly away from the wafer surface. Adhesion strength was qualitatively evaluated after tape removal by counting the number of missing squares of the deposited encapsulation layer within the 10 × 10 matrix of 100 scribed squares.

[0080] Figure 8B shows a scanning electron micrograph (SEM) of one of the scribed squares in the 10 × 10 matrix that underwent adhesion strength testing. The SEM image shows residual adhesive from the tape across the entire scribed direction, indicating that the encapsulation layer was not peeled off. Analysis showed that none of the squares within any of the square regions lost any encapsulation layer, indicating excellent adhesion strength of the encapsulation layer on the Si substrate.

[0081] Figure 8C shows an energy dispersive X-ray spectrum (EDS) obtained from one of the square areas where adhesion strength testing was performed. This spectrum was obtained from 5 of the 100 scribed squares in the 10 × 10 matrix shown in Figure 8B. EDS peak analysis shows La and Al peaks on the film, which are LaO x Membrane and AlO x It shows that the sealing layer including the capping layer remains after the adhesion test.

[0082] FIG. 9A illustrates a LaO film formed on a Si substrate according to an embodiment. x layer and HfO x 9A and 9B show cross-sectional transmission electron micrographs (XTEM) of an encapsulation layer including a lanthanum oxide layer. FIG. 9B shows elemental maps obtained from electron energy loss spectroscopy (EELS) obtained from the XTEM shown in FIG. 9A, according to an embodiment. FIG. 9C shows a depth profile of the composition of the encapsulation layer imaged in FIG. 9A. The results indicate the presence of an interfacial oxide layer between the lanthanum oxide layer and the Si substrate, which indicates a strong affinity between La and oxygen atoms. Additionally, the results demonstrate that La and Hf do not diffuse into other layers and that LaO x layer and HfO x The layers are shown to remain as distinct layers.

[0083] While the present invention has been described herein with reference to particular embodiments, these embodiments do not serve to limit the invention but are set forth for purposes of illustration. It will be apparent to those skilled in the art that changes and modifications can be made without departing from the spirit and scope of the invention.

[0084] Such simple modifications and improvements of the various embodiments disclosed herein are within the scope of the disclosed technology, the specific scope of which will be further defined by the appended claims.

[0085] In the foregoing, it will be understood that the features of any one of the embodiments can be combined with or substituted for the features of any other one of the embodiments.

[0086] Unless the context clearly requires otherwise, throughout this specification and claims, words such as "comprise," "consisting," "include," "including," and the like are intended to be construed in an inclusive sense, i.e., "including but not limited to," as opposed to an exclusive or exhaustive sense. The term "coupled," as generally used herein, refers to two or more elements that are directly connected or connected via one or more intermediate elements. Similarly, the term "connected," as generally used herein, refers to two or more elements that are directly connected or connected via one or more intermediate elements. Furthermore, in this specification, the terms "herein," "above," "below," and similar terms refer to this specification as a whole, rather than to any particular portion of this specification. Furthermore, in the above description of the detailed description, words using the singular or plural number may also include the plural or singular number, as the context allows. The word "or" referring to a list of two or more items includes all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0087] Furthermore, as used herein, particularly conditional terms such as "can," "could," "might," "may," "e.g.," "for example," and "such as," are generally intended to convey that certain embodiments include certain features, elements, and / or conditions, and that other embodiments do not, unless otherwise specified or understood within the context in which they are used. Thus, such conditional terms are generally not intended to imply that features, elements, and / or conditions are in any way required by one or more embodiments, or that these features, elements, and / or conditions may or may not be included in or practiced in any particular embodiment.

[0088] While specific embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while functions are shown in a given arrangement, in alternative embodiments, similar functions may be performed with different components and / or sensor topologies, and some functions may be deleted, moved, added, subdivided, combined, and / or modified. Each of these functions may be implemented in a variety of different ways. Any appropriate combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The various functions and processes described above may be implemented independently of each other or may be combined in various ways. All possible combinations and subcombinations of features of the present disclosure are intended to be within the scope of the present disclosure.

Claims

1. 1. A method for manufacturing a semiconductor device, comprising: providing a substrate having an exposed surface comprising a chalcogenide material; By thermal atomic layer deposition without plasma support, low electronegativity (low χ) metal precursors and oxygen O ２ forming a low-χ metal oxide layer on the chalcogenide material by periodically exposing the substrate to an oxygen precursor comprising: The method, wherein the electronegativity of the low-χ metal of the low-χ metal precursor is 1.6 or less.

2. 10. The method of claim 1, wherein the electronegativity of the low-χ metal of the low-χ metal precursor is less than the electronegativity of the elements of the chalcogenide material.

3. The method of claim 2 , wherein the elements of the chalcogenide material are one or more of Ge, Sb, Te, Si, Se, and As.

4. 10. The method of claim 1, wherein forming the low-χ metal oxide layer comprises cyclically exposing the substrate to the low-χ metal precursor and the oxygen precursor at 300° C. or less.

5. 5. The method of claim 4, wherein the low-chi metal is a rare earth metal.

6. The rare earth metal is La and the low χ metal oxide layer is LaO ２ The method of claim 5 , comprising a layer.

7. The method of claim 6 , wherein periodically exposing comprises exposing the chalcogenide material to a La precursor as a first precursor.

8. The method of claim 7 , wherein the La precursor comprises tris(isopropylcyclopentadienyl)lanthanum.

9. 6. The method of claim 5, wherein providing a substrate comprises providing a chalcogenide material having a surface region comprising a chalcogenide oxide material, and forming the low-χ metal oxide layer comprises chemically reducing the chalcogenide oxide material with the rare earth metal.

10. The method of claim 5 , wherein the low χ metal oxide layer comprises a sub-stoichiometric rare earth metal oxide.

11. 10. The method of claim 1, further comprising forming a capping metal oxide layer on the low-χ metal oxide layer by cyclically exposing the substrate to a second metal precursor and a second oxygen precursor.

12. The capping metal oxide layer is HfO ｘ or AlO ｘ 12. The method of claim 11, comprising:

13. The second oxygen precursor is O ２ or ozone.

14. 2. The method of claim 1, wherein the substrate includes a cross-point array intermediate structure including a plurality of memory cells arranged between bit lines and word lines, the intermediate structure including the chalcogenide material as part of a phase change memory element, and forming the low χ metal oxide layer includes forming the low χ metal oxide layer directly on exposed sidewalls of the phase change memory element.

15. The method of claim 14 , wherein forming the low-χ metal oxide layer does not crystallize the phase change memory element.

16. 1. A method for manufacturing a semiconductor device, comprising: providing a substrate having a chalcogenide layer formed thereon; patterning the chalcogenide layer to expose sidewalls of the chalcogenide layer; forming a low-χ metal oxide layer on the sidewalls of the chalcogenide layer by cyclically exposing the substrate to a low-electronegativity (low-χ) metal precursor and an oxygen precursor at 300° C. or less by thermal atomic layer deposition without plasma assistance; The method, wherein the electronegativity of the low χ metal in the low χ metal oxide layer is 1.6 or less.

17. 17. The method of claim 16, wherein the substrate includes a cross-point array intermediate structure including a plurality of memory cells arranged between bit lines and word lines, the intermediate structure including the chalcogenide layer as part of a phase change memory element, and forming the low χ metal oxide includes forming directly on exposed sidewalls of the phase change memory element.

18. 20. The method of claim 17, wherein the exposed sidewalls of the phase change memory elements comprise a chalcogenide oxide material, and forming the low-χ metal oxide layer comprises chemically reducing the chalcogenide oxide material with the low-χ metal.

19. 18. The method of claim 17, wherein the elements of the chalcogenide layer include one or more of Ge, Sb, Te, Si, Se, and As.

20. 20. The method of claim 19, wherein the electronegativity of the low-χ metal is less than the electronegativity of the elements of the chalcogenide layer.

21. 17. The method of claim 16, wherein the low-χ metal is a lanthanide element.

22. The oxygen precursor is O ２ 22. The method of claim 21, comprising:

23. 17. The method of claim 16, wherein periodically exposing comprises exposing the chalcogenide layer to a rare earth metal precursor as a first precursor.

24. 24. The method of claim 23, wherein the rare earth metal precursor comprises a La precursor.

25. 17. The method of claim 16, further comprising forming a capping metal oxide layer on the low χ metal oxide layer by cyclically exposing the substrate to a first metal precursor and a second oxygen precursor.

26. The capping metal oxide layer is HfO ｘ or AlO ｘ 26. The method of claim 25, comprising:

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