Semiconductor device and method for manufacturing the same

Abstract

To suppress noise caused by di / dt at turn-on of vertical MOSFETs.SOLUTION: Provided is a semiconductor device including a semiconductor substrate having a substrate top surface and a substrate bottom surface, a first gate insulating film and a second gate insulating film provided on the substrate top surface and having different film thicknesses, a gate electrode on the gate insulating film top surface, a source electrode via an interlayer insulating film on the gate electrode top surface and a drain electrode on the substrate bottom surface, and a MOSFET section with different threshold values due to different thicknesses of gate insulating films.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] It has been known that when operating a semiconductor device such as an ASIC (Application Specific Integrated Circuit) at high speed, the reliability of the semiconductor device can be improved by reducing electrical noise by smoothing the current waveform that flows during the driving transition of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or the like that constitutes the ASIC (see, for example, Patent Document 1).It is also known that the switching frequency of a power conversion device incorporating the MOSFET can be increased by smoothing the rise and fall of the current during switching of the MOSFET (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-12841 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-253765 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a MOS type semiconductor device in which a large number of cell structures are built in to reduce on-resistance, and which can suppress an increase in di / dt at turn-on even when the cell density is improved by miniaturization. [Means for solving the problem]

[0005] The present invention provides a semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, a drift layer disposed on the upper surface side of the semiconductor substrate, a drain layer disposed on the lower surface side, a first well region and a second well region disposed adjacent to each other on the upper surface side of the drift layer with the drift layer interposed therebetween, a first source region selectively disposed on the upper surface side of the first well region, a second source region selectively disposed on the upper surface side of the second well region, a gate insulating film selectively disposed on the upper surface of the semiconductor substrate, a gate electrode disposed on the upper surface of the gate insulating film, and an interlayer insulating film disposed on the upper surface of the gate electrode, the gate insulating film having a first gate insulating film and a second gate insulating film directly adjacent to each other at a step portion, the first gate insulating film being disposed on the upper surfaces of the first well region and the first source region, and the second gate insulating film being disposed on the upper surfaces of the second well region and the second source region, the first gate insulating film being thinner than the second gate insulating film.

[0006] In the semiconductor device, the step portion is disposed on the boundary between the first well region and the drift layer, and the second gate insulating film is disposed on the boundary between the first well region and the drift layer. layer Alternatively, the step portion is disposed on the drift layer, the first gate insulating film is disposed on the upper surface of the drift layer, and the second gate insulating film is disposed on the upper surface of the drift layer. Alternatively, the step portion is disposed on the first well region, and the second gate insulating film is disposed on the upper surfaces of the drift layer and the first well region.

[0007] In the semiconductor device, the position of the edge of the gate insulating film coincides with the position of the edge of the interlayer insulating film.

[0008] In the semiconductor device, adjacent gate insulating films are arranged such that the first gate insulating films face each other or the second gate insulating films face each other.

[0009] In the semiconductor device, the thickness of the second gate insulating film is 1.3 times or more and 2 times or less than the thickness of the first gate insulating film.

[0010] The present invention provides a method for manufacturing a semiconductor device, the method comprising the steps of: a well region forming step of forming a well region on the upper surface side of a semiconductor substrate having an upper surface and a lower surface, a drift layer on the upper surface side, and a drain layer on the lower surface side; a source region forming step of forming a source region on the upper surface side of the well region; a gate insulating film forming step of forming a gate insulating film on the upper surface, the gate insulating film having a first gate insulating film and a second gate insulating film thicker than the first gate insulating film; a gate electrode forming step of forming a gate electrode on the upper surface of the gate insulating film; an interlayer insulating film forming step of forming an interlayer insulating film so as to cover the gate electrode; a source electrode forming step of forming a source electrode on the upper surface of the interlayer insulating film; and a drain electrode forming step of forming a drain electrode on the lower surface of the semiconductor substrate, In the gate insulating film formation step, the gate insulating film is formed over the entire semiconductor substrate, and immediately after selectively removing the gate insulating film, a gate insulating film is formed again, thereby forming a first gate insulating film with a different film thickness and a second gate insulating film with a film thickness greater than the first gate insulating film, and after the interlayer insulating film formation step, the interlayer insulating film and the gate insulating film are etched in the same process to form a contact hole that exposes the semiconductor substrate.

[0011] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a top view showing an overview of a semiconductor device 100 according to a first embodiment of the present invention. [Figure 2A] FIG. 2 is a cross-sectional view taken along the line AA′ in FIG. [Figure 2B] 2B is an enlarged view showing another example of the region A in FIG. 2A. FIG. [Figure 2C] 2B is an enlarged view showing another example of the region A in FIG. 2A. FIG. [Figure 3A] 1 is a diagram showing the relationship between the gate voltage and the drain current of the semiconductor device 100. FIG. [Figure 3B] FIG. 2 is a diagram showing the relationship between the drain current and time of the semiconductor device 100. [Figure 4]FIG. 2 is a diagram illustrating an example of a flowchart of a method for manufacturing the semiconductor device 100. [Figure 5] 2A to 2C are diagrams illustrating an embodiment of a method for manufacturing the semiconductor device 100. [Figure 6] 2A to 2C are diagrams illustrating an embodiment of a method for manufacturing the semiconductor device 100. [Figure 7] 2A to 2C are diagrams illustrating an embodiment of a method for manufacturing the semiconductor device 100. [Figure 8] 2A to 2C are diagrams illustrating an embodiment of a method for manufacturing the semiconductor device 100. [Figure 9] 2A to 2C are diagrams illustrating an embodiment of a method for manufacturing the semiconductor device 100. [Figure 10] 2A to 2C are diagrams illustrating an embodiment of a method for manufacturing the semiconductor device 100. [Figure 11] 2A to 2C are diagrams illustrating an embodiment of a method for manufacturing the semiconductor device 100. [Figure 12] 2A to 2C are diagrams illustrating an embodiment of a method for manufacturing the semiconductor device 100. [Figure 13] 2A to 2C are diagrams illustrating an embodiment of a method for manufacturing the semiconductor device 100. [Figure 14] 2A to 2C are diagrams illustrating an embodiment of a method for manufacturing the semiconductor device 100. [Figure 15] FIG. 10 is a cross-sectional view showing an overview of a semiconductor device 101 according to a modified embodiment of the present invention. [Figure 16] FIG. 1 is a cross-sectional view showing an overview of a semiconductor device 110 according to a second embodiment of the present invention. [Figure 17] FIG. 10 is a cross-sectional view showing an overview of a semiconductor device 120 according to a third embodiment of the present invention. [Figure 18] FIG. 10 is a cross-sectional view showing an overview of a semiconductor device 130 according to a fourth embodiment of the present invention. [Figure 19] 1 is a cross-sectional view showing an overview of a semiconductor device 200 according to a comparative example of the present invention. [Figure 20A] 1 is a diagram showing the relationship between the gate voltage and the drain current of the semiconductor device 100 and the semiconductor device 200 of the comparative example. [Figure 20B]FIG. 10 is a diagram showing the relationship between drain current and time for the semiconductor device 100 and the semiconductor device 200 of the comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0013] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, + and - appended to n or p indicate higher and lower impurity concentrations than layers and regions without these prefixes, respectively. When the notations of n and p, including + and -, are the same, these indicate similar concentrations, but do not necessarily mean that the concentrations are the same.

[0014] In this specification and drawings, elements having substantially the same functions and configurations are designated by the same reference numerals to avoid repetitive explanations, and elements not directly related to the present invention are not shown. Furthermore, in one drawing, elements having the same functions and configurations may be designated by the same reference numerals, and the reference numerals may be omitted for other elements.

[0015] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor module is mounted.

[0016] In this specification, technical matters may be described using orthogonal coordinate axes, i.e., the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. The +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is referred to without specifying positive or negative, it means a direction parallel to the +Z-axis and the -Z-axis. In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0017] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0018] A first embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a top view showing an overview of a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 is provided on a semiconductor substrate 10. The semiconductor substrate 10 may be a part of a wafer having a substantially circular shape when viewed from above. The material of the semiconductor substrate 10 is silicon, for example, but is not limited to silicon. The material of the semiconductor substrate 10 may also be silicon carbide (SiC). The semiconductor device 100 is separated into individual pieces by dicing the semiconductor substrate 10.

[0019] The semiconductor device 100 has an active region 14 and a breakdown voltage structure 12. A transistor such as a MOSFET is formed in the active region 14. In this example, a vertical MOSFET is formed.

[0020] A breakdown voltage structure 12 is provided on the top surface of the semiconductor device 100 to surround the active region 14. In this example, the breakdown voltage structure 12 is provided along the edge of the semiconductor substrate 10 in a top view. The breakdown voltage structure 12 has a guard ring, a field plate, or the like, and prevents an electric field from concentrating at an end portion of the active region 14, thereby improving the breakdown voltage of the semiconductor device 100. The end portion of the active region 14 is the boundary between the active region 14 and the breakdown voltage structure 12.

[0021] A gate pad 16 is selectively provided on the upper surface of the semiconductor device 100 so as to be surrounded by the active region 14 and the breakdown voltage structure 12 .

[0022] 1 does not illustrate the source electrode provided above the active region 14, the insulating film insulating the source electrode from the semiconductor substrate 10, etc. Also, it does not illustrate the guard ring or field plate provided in the breakdown voltage structure 12, etc. Also, it does not illustrate the wiring connecting the gate pad 16 to the gate terminal of the vertical MOSFET provided in the active region 14. Also, reference numeral 29 denotes a source electrode.

[0023] 2A is a diagram showing two unit cells of a vertical MOSFET, taken along the line AA′ in FIG. 1. The AA′ cross section is an XZ plane passing through the active region 14.

[0024] In FIG. 2A, the semiconductor device 100 includes n + type drain layer 17 and n + The n-type drift layer 18 is in contact with the upper surface of the n-type drain layer 17. + The stack of the n-type drain layer 17 and the n-type drift layer 18 is defined as a semiconductor substrate 10. The semiconductor substrate 10 has a substrate upper surface 19 and a substrate lower surface 20. The upper surface of the n-type drift layer 18 may be the substrate upper surface 19 of the semiconductor substrate 10. The substrate upper surface 19 may be the surface on which the gate structure of the vertical MOSFET is formed. The gate structure is a structure including at least one of a gate insulating film, a gate electrode, a source region, and a channel region, for example.

[0025] A p-type well region 22 is selectively provided on the substrate upper surface 19 side of the n-type drift layer 18. In Fig. 2A, the p-type well region 22 includes p-type well regions 22A, 22B, and 22C. The p-type well regions 22A, 22B, and 22C are provided side by side in the X-axis direction.

[0026] The p-type well region 22 is selectively n + A source region 23 is provided. + Two n-type source regions 23 may be provided side by side in the X-axis direction in one p-type well region 22. + n-type source region 23 + n-type source regions 23A, 23B, 23C, and 23D are provided. + The type source regions 23A, 23B, 23C, and 23D are arranged side by side in the X-axis direction.

[0027] 2A shows two unit cells 41A and 41B of a vertical MOSFET. The unit cell on the −X-axis direction is referred to as unit cell 41A, and the unit cell on the +X-axis direction is referred to as unit cell 41B. Unit cell 41A and unit cell 41B have the same structure.

[0028] First, the unit cell 41A will be described. The unit cell 41A has two adjacent p-type well regions 22A and 22B sandwiching the n-type drift layer 18. The two p-type well regions 22A and 22B are aligned in the X-axis direction. The p-type well region on the −X-axis direction side of the unit cell 41A is p-type well region 22A, and the p-type well region on the +X-axis direction side is p-type well region 22B.

[0029] The p-type well region 22A has n + The p-type source region 23A is formed in the p-type well region 22B. + A source region 23B is formed.

[0030] Although not shown, there is another n-type well region 22A in the −X-axis direction. + The n-type source region is formed as shown in FIG. +The n-type source region 23A is located on the +X-axis direction side of the p-type well region 22A. + Similarly, the p-type well region 22B has an n-type source region in the −X-axis direction. + The n-type source region 23B and the n-type source region 23B in the +X-axis direction are different from the n-type source region 23B. + In the first embodiment, an n-type source region 23C is formed. + p-type well regions 22A and 22B, and n-type source region 23A, p-type well regions 22A and 22B, and n-type well regions 22A and 22B, which are arranged with n-type drift layer 18 interposed therebetween. + A type source region 23B is included in unit cell 41A.

[0031] Next, the structure of the unit cell 41A will be described. A gate insulating film 26A is selectively provided on the substrate upper surface 19. The gate insulating film of the unit cell 41A is the gate insulating film 26A. One gate insulating film 26A may be provided in the unit cell 41A. The gate insulating film 26A is n + The n-type source region 23A, the p-type well region 22A, the n-type drift layer 18, the p-type well region 22B, and the n + The source region 23B is provided on the source region 23B.

[0032] The gate insulating film 26A has portions with different thicknesses. The gate insulating film 26A includes a gate insulating film 25A and a gate insulating film 25B, and the thickness of the gate insulating film 25A is thinner than the thickness of the gate insulating film 25B. The gate insulating film 25A and the gate insulating film 25B are aligned in the X-axis direction and continuously provided. The thickness of the gate insulating film 25A may be 50 to 500 nm. The thickness of the gate insulating film 25B may be 1.3 to 2 times the thickness of the gate insulating film 25A. For example, the thickness of the gate insulating film 25A may be 80 nm, and the thickness of the gate insulating film 25B may be 120 nm. The thicknesses of the gate insulating films 25A and 25B may be the thicknesses in the Z-axis direction at the portions whose upper surfaces are parallel to the X-axis.

[0033] In FIG. 2A, the gate insulating film 25A is formed on the p-type well region 22A and the n-type well region 22B. + The gate insulating film 25B is in contact with a part of the p-type well region 22B, the n-type source region 23A, and the n-type well region 22B. +The n-type source region 23B is in contact with a part of the n-type drift layer 18.

[0034] The gate insulating film 26A has a step C where the film thickness changes at the location where the gate insulating film 25A and the gate insulating film 25B are continuous. In top view, the step C is located at the boundary in the X-axis direction between the p-type well region 22A and the n-type drift layer 18. The reason why the step C is located at the boundary in the X-axis direction between the well region 22A and the n-type drift layer 18 is to create a difference in the film thickness of the gate insulating film between two MOSFET sections, which will be described later.

[0035] 2A, a gate electrode 27A is provided on the upper surface of a gate insulating film 26A. In this example, the gate electrodes are gate electrodes 27A and 27B. The gate electrode of unit cell 41A is gate electrode 27A. The gate electrode 27B is the gate electrode of unit cell 41B.

[0036] The gate electrode 27A is made of a conductive material such as polysilicon. In Fig. 2A, the thickness of the gate electrode 27A may be, for example, 300 to 1000 nm. The thickness of the gate electrode 27A may be the thickness in the Z-axis direction at the portions where the upper and lower surfaces of the gate insulating film 25A are parallel to the X-axis.

[0037] The film thickness of the gate electrode 27A may be uniform in a portion where the upper surface is parallel to the X-axis. The gate electrode 27A may have a shape that follows the shape of the step portion C of the gate insulating film 26A so that the gate insulating film 26A is not exposed. Therefore, the gate electrode 27A has a step at a position corresponding to the step portion C of the gate insulating film 26A.

[0038] 2A, an interlayer insulating film 28A is provided to cover the gate electrode 27A. In this example, the interlayer insulating films include interlayer insulating films 28A and 28B. The interlayer insulating film of the unit cell 41A is the interlayer insulating film 28A. The interlayer insulating film 28B is the interlayer insulating film of the unit cell 41B.

[0039] The interlayer insulating films 28A and 28B may be formed of, for example, BPSG (Boro Phospho Silicate Glass), PSG (Phosphorus Silicate Glass), etc. The interlayer insulating film 28 may be a laminated film in which, for example, an HTO (High Temperature Oxide), an NSG (Non-doped Silicate Glass), or a TEOS (Tetraethoxysilane) film is formed under the BPSG (between the BPSG and the gate electrode 27).

[0040] 2A, the thickness of interlayer insulating film 28 may be about 1 μm. The thickness of interlayer insulating film 28 may be the thickness in the Z-axis direction at a portion where the upper surface is parallel to the X-axis. The thickness of interlayer insulating film 28A may be uniform at the portions of gate insulating films 25A and 25B parallel to the X-axis.

[0041] The interlayer insulating film 28A may have a shape that follows the shape of the step portion of the gate electrode 27A so as not to expose the gate electrode 27A. Therefore, the interlayer insulating film 28A has a step at a position corresponding to the step portion C of the gate insulating film 26A.

[0042] As described above, a step portion C is formed in the gate insulating film 26A due to the difference in film thickness between the gate insulating films 25A and 25B. Therefore, a step is also formed in the gate electrode 27A stacked on the gate insulating film 26A due to the influence of the step portion C. Similarly, a step is also formed in the interlayer insulating film 28A stacked on the gate electrode 27A due to the influence of the step portion C.

[0043] When forming the gate electrode 27A with a predetermined thickness on the gate insulating film 26A, the gate electrode 27A is also formed on the side surfaces of the step portion C of the gate insulating film 26A so that the gate electrode is not interrupted at the step portion C of the gate insulating film 26A. Therefore, a step portion is also formed in the gate electrode 27A, shifted in the −X-axis direction from the step portion C of the gate insulating film 26A. Similarly, the interlayer insulating film 28A also covers the side surfaces of the gate electrode 27A, so a step is formed in the interlayer insulating film 28A, further shifted in the −X-axis direction by the step of the gate electrode 27A.

[0044] In FIG. 2A, the interlayer insulating film 28 has n + A contact hole 31 is provided, exposing the p-type source region 23 and the p-type well region 22 from the opening. An interlayer insulating film 28A is located on the −X-axis direction side of the contact hole 31, and an interlayer insulating film 28B is located on the +X-axis direction side of the contact hole 31. In other words, the boundary between adjacent unit cells 41A and 41B may be the center of the contact hole 31 in the X-axis direction.

[0045] A source electrode 29 is provided so as to cover the interlayer insulating film 28. The source electrode 29 may be a metal film such as aluminum or an alloy containing aluminum as a main component (Al-Si, Al-Cu, Al-Si-Cu), and is made of Al-Si, for example. The thickness of the source electrode 29 may be about 5 μm. The thickness of the source electrode 29 may be the height from the surface of the source electrode 29 that contacts the substrate upper surface 19 to the upper end of the source electrode 29. The interlayer insulating film 28 is provided between the source electrode 29 and the gate electrode 27 to insulate them from each other. The source electrode 29 fills a contact hole 31. The source electrode 29 is connected to the n-type semiconductor layer 21 through the contact hole 31. + The source electrode 29 is electrically connected to the p-type source region 23 and the p-type well region 22. A contact region (not shown) may be provided at a portion of the p-type well region 22 that contacts the source electrode 29 in order to reduce the contact resistance between the source electrode 29 and the p-type well region 22.

[0046] On the bottom surface 20 of the substrate + A drain electrode 30 is provided in contact with the type drain layer 17. The drain electrode 30 may be a laminated film (e.g., Ti / Ni / Au, Al / Ti / Ni / Au, etc.) formed of a metal film such as nickel (Ni), titanium (Ti), gold (Au), silver (Ag), aluminum (Al), or an alloy mainly composed of aluminum (Al-Si, Al-Cu, Al-Si-Cu), etc.

[0047] A gate neck portion 32A is provided below the gate insulating film 26A. The gate neck portion 32A is a part of the n-type drift layer 18, and is a portion sandwiched between two adjacent p-type well regions 22A and 22B. + The n-type source region 23A, the p-type well region 22A, the gate neck portion 32A, the p-type well region 22B, and the n-type source region 23A. + The source regions 23B are aligned in the X-axis direction, and are covered with the gate insulating film 26A.

[0048] As shown in FIG. 2A , the unit cell 41A includes two MOSFET portions 42A and 43A. The MOSFET portion 42A is located on the −X-axis side of the gate neck portion 32A, and the MOSFET portion 43A is located on the +X-axis side. The portion where a channel is formed during operation of the MOSFET portion 42A is the channel portion 44A. The portion where a channel is formed during operation of the MOSFET portion 43A is the channel portion 45A. That is, the MOSFET portions 42A and 43A are formed in one unit cell 41A, and the channel portions of these MOSFET portions 42A and 43A are the channel portions 44A and 45A, respectively. The gate insulating film of the MOSFET portion 42A is the aforementioned gate insulating film 25A, and the gate insulating film of the MOSFET portion 43A is the aforementioned gate insulating film 25B. The gate insulating films 25A and 25B have different thicknesses, and therefore the gate insulating film thicknesses of the MOSFET portions 42A and 43A are different. Therefore, the structure of the XZ plane of the unit cell 41 is asymmetrical with respect to the Z-axis center line passing through the center of the gate neck portion 32.

[0049] The p-type well region 22 in FIG. + The source region 23, the gate insulating film 26, and the gate electrode 27 may extend a predetermined length in the Y-axis direction. The predetermined length may be, for example, the same as the width of the active region 14 or may be shorter than the width of the active region 14.

[0050] Adjacent unit cells may share a p-type well region. In FIG. 2A, adjacent unit cells 41A and 41B share a p-type well region 22B. Therefore, the p-type well region 22B may include a portion of the unit cell 41A on the −X-axis direction side and a portion of the unit cell 41B on the +X-axis direction side within the p-type well region 22B. The portion of the unit cell 41A on the −X-axis direction side includes the channel portion 45A and the n + The part of the unit cell 41 on the +X-axis direction side may be the channel portion 44B and the n-type source region 23B. + It may be a source region 23C.

[0051] The unit cell 41A includes two MOSFET portions 42A and 43A. A channel portion 44A of the MOSFET portion 42A is formed in the p-type well region 22A. A channel portion 45A of the MOSFET portion 43A is formed in the p-type well region 22B. A gate electrode 27A and an interlayer insulating film 28A are provided in common to the gate insulating films 25A and 25B.

[0052] Similarly, unit cell 41B includes two MOSFET portions 42B and 43B. A channel portion 44B of MOSFET portion 42B is formed in p-type well region 22B. A channel portion 45B of MOSFET portion 43B is formed in p-type well region 22C. Gate electrode 27B and interlayer insulating film 28B are provided in common to gate insulating film 26B.

[0053] The gate insulating film 26B includes a continuous gate insulating film 25C and a gate insulating film 25D. The thickness of the gate insulating film 25C is thinner than the thickness of the gate insulating film 25D. The gate insulating films 25A and 25C, and the gate insulating films 25B and 25D have the same thickness.

[0054] In the p-type well region 22B, a channel portion 45A of the MOSFET portion 43A of the unit cell 41A and a channel portion 44B of the MOSFET portion 42B of the unit cell 41B are formed.

[0055] That is, two MOSFET sections are formed in a unit cell, one in one well region and the other in another well region, and these two MOSFET sections are provided with a common gate electrode. Also, one MOSFET section of one unit cell and one MOSFET section of another unit cell are formed in one well region.

[0056] FIG. 2B is a diagram showing a modified example of region A indicated by the dotted line in FIG. 2A. Region A includes gate insulating film 26A, gate electrode 27A, and interlayer insulating film 28A. In FIG. 2B, the shape of step portion C, where the thickness of thin gate insulating film 25A changes from that of thicker gate insulating film 25B, is different from the shape shown in FIG. 2A. That is, step portion C is step-like in FIG. 2A, whereas it is slope-like in FIG. 2B. The difference in thickness between gate insulating films 25A and 25B is necessary, and the shape of step portion C may be modified. The width of slope-like step portion C may be in the range of 0 to 300 nm.

[0057] FIG. 2C shows another modified example of region A in FIG. 2A. In FIG. 2C, the step portion C of the gate insulating film 26A has a sloped shape, and the −X-axis direction end of the gate insulating film 26A coincides with the −X-axis direction end of the interlayer insulating film 28A in the X-axis direction. The −X-axis direction end of the gate electrode 27A may be covered by the interlayer insulating film 28A. The −X-axis direction end of the gate electrode 27A may be located on the +X-axis direction side of the −X-axis direction end of the gate insulating film 26A. Similarly, the +X-axis direction end of the gate insulating film 26A may coincide with the +X-axis direction end of the interlayer insulating film 28A. The +X-axis direction end of the gate electrode 27A may be covered by the interlayer insulating film 28A. The +X-axis direction end of the gate electrode 27A may be located on the −X-axis direction side of the +X-axis direction end of the gate insulating film 26A.

[0058] The operation of the semiconductor device 100 according to the first embodiment of the present invention will be described. FIG. 3A is a diagram showing the relationship between the gate voltage and the drain current of the semiconductor device 100. In the semiconductor device 100, as described above, the gate insulating film 26A of the unit cell 41A includes a thin gate insulating film 25A and a thick gate insulating film 25B. That is, the thickness of the gate insulating film 26A is thin above the channel portion 44A of the MOSFET portion 42A and is thick above the channel portion 45A of the MOSFET portion 43A. Therefore, the threshold voltages of the MOSFET portion 42A and the MOSFET portion 43A are different. When the threshold voltage of the MOSFET portion 42 is Vth1 and the threshold voltage of the MOSFET portion 43 is Vth2, Vth1 <Vth2となる。

[0059] In semiconductor device 100, the same gate voltage is applied to MOSFET portion 42 and MOSFET portion 43. Therefore, as shown in Fig. 3A, when the gate voltage exceeds Vth1, drain current ID1 of MOSFET portion 42 begins to flow, and when the gate voltage exceeds Vth2, drain current ID2 of MOSFET portion 43 begins to flow and is added to ID1, so that drain current ID100 becomes ID1+ID2. In Fig. 3A, the first MOSFET portion is designated as MOSFET portion 42A, and the second MOSFET portion is designated as MOSFET portion 43A.

[0060] The channel widths of the two MOSFET portions of a unit cell may be the same. The channel width may be a width through which a drain current flows. If the gate insulating film thicknesses of the two MOSFET portions of a unit cell are the same, ID1 may be equal to ID2; however, in semiconductor device 100, ID1 and ID2 differ because the gate insulating film 25A and the gate insulating film 25B have different thicknesses. Drain currents begin to flow between MOSFET portion 42A and MOSFET portion 43A of unit cell 41A with a time difference, causing the drain current of semiconductor device 100 to change stepwise.

[0061] 3B is a diagram showing the relationship between the drain current and time of the semiconductor device 100. It shows the change in the drain current when a gate voltage is applied in the semiconductor device 100. FIG. 3B also shows the gate voltage VG.

[0062] In the semiconductor device 100, a common gate voltage V is applied to the MOSFET portions 42A and 43A of the unit cell 41A. When V exceeds Vth1, the drain current ID1 of the MOSFET portion 42 begins to flow. When V exceeds Vth2, the drain current ID2 of the MOSFET portion 43 begins to flow and is added to ID1. In the semiconductor device 100, the rate of current rise (di / dt) around the time when the drain current begins to flow is determined by the drain current ID1 flowing only through the MOSFET portion 42A of the unit cell 41A. In this way, in the semiconductor device 100, di / dt can be reduced by suppressing the current that begins to flow at Vth1.

[0063] In other words, near the point where the drain current starts to flow, the current flows through only one MOSFET portion of the unit cell, so di / dt is smaller than when the current starts to flow through two MOSFET portions of the unit cell.

[0064] In the present invention, the difference in threshold voltage between the MOSFET section 42 and the MOSFET section 43 of the unit cell 41 results in a gentler current waveform that flows during the transition period of MOSFET operation in the semiconductor device 100. Therefore, by using the semiconductor device 100, electrical noise is reduced, and it becomes easier to increase the speed or multi-function of semiconductor devices incorporating the semiconductor device 100.

[0065] Although it is possible to obtain a similar effect by forming the gate electrodes of the MOSFET portion 42 and the MOSFET portion 43 separately and applying different voltages to the respective gate electrodes, this would complicate the element structure and gate voltage control.

[0066] A method for manufacturing the semiconductor device 100 according to the first embodiment of the present invention will now be described. Figure 4 is a diagram illustrating an example of a flowchart for the method for manufacturing the semiconductor device 100 (see Figure 2A). The method for manufacturing the semiconductor device 100 includes well region formation step S101, source region formation step S102, gate insulating film formation step S103, gate electrode formation step S104, interlayer insulating film formation step S105, contact hole formation step S106, source electrode formation step S107, and drain electrode formation step S108. The manufacturing method will be described below with reference to Figures 5 to 14, along the lines of S101 to S108 in Figure 4.

[0067] In FIG. 5, the semiconductor device 100 is formed on a semiconductor substrate 10. The semiconductor substrate 10 in this example may be a part of a wafer having a substantially circular shape when viewed from above. A plurality of semiconductor devices 100 may be manufactured by dicing the semiconductor substrate 10. The material of the semiconductor substrate 10 may be silicon (Si). The material of the semiconductor substrate 10 is not limited to silicon (Si). The material of the semiconductor substrate 10 may also be silicon carbide (SiC).

[0068] The semiconductor device 100 is + The n-type drift layer 18 is provided in contact with the upper surface of the n-type drain layer 17. + The stack of n-type drain layer 17 and n-type drift layer 18 constitutes semiconductor substrate 10. Semiconductor substrate 10 has a substrate upper surface 19 and a substrate lower surface 20.

[0069] The semiconductor substrate 10 is + The n-type drift layer 18 may be formed on the n-type drain layer 17 by epitaxial growth. + The source drain layer 17 may be the initial semiconductor substrate 10. + The n-type drain layer 17 and the n-type drift layer 18 contain n-type impurities. The amount of n-type impurities in the n-type drift layer 18 is n + The amount of n-type impurities is less than that of the n-type drain layer 17. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The thickness of the n-type drift layer 18 may be, for example, 10 to 50 μm.

[0070] The semiconductor substrate 10 is formed by ion implantation into the n-type drift layer 18. + Alternatively, the n-type drift layer 18 may be formed by providing an n-type drain layer 17. In this case, the n-type drift layer 18 may be the initial semiconductor substrate 10. + The impurity for forming the n-type drain layer 17 may be, for example, phosphorus (P) or arsenic (As). Before the ion implantation, the n-type drift layer 18 may be ground from the back surface side to a predetermined film thickness.

[0071] When forming the n-type drift layer 18 by epitaxial growth, if the n-type drift layer 18 is thick, it takes time to epitaxially grow the n-type drift layer 18. + It is more effective to provide the type drain layer 17 .

[0072] 6, the well region forming step S101 of FIG. 4 will be described. A resist film (not shown) of a predetermined pattern is formed on the substrate upper surface 19 by photolithography, and p-type impurities are selectively ion-implanted into the semiconductor substrate 10 using the resist film as a mask. The p-type impurity is, for example, boron (B). Thereafter, the resist film is removed, and a predetermined heat treatment is performed to form a p-type well region 22. A plurality of p-type well regions 22 may be formed in the X-axis direction. In FIG. 6, from the −X-axis direction side, they are p-type well regions 22A, 22B, and 22C.

[0073] In Figure 6, p-type well regions 22A and 22C are partially not shown, and are therefore shown with a smaller width in the X-axis direction than p-type well region 22B, but p-type well regions 22A, 22B, and 22C may have the same width in the X-axis direction. The width W1 in the X-axis direction of p-type well region 22B may be, for example, 1 to 4 μm. A plurality of p-type well regions 22 are selectively formed side by side in the X-axis direction at a predetermined interval D1. The interval D1 may be, for example, 0.3 to 1 μm.

[0074] 7, the source region forming step S102 in FIG. 4 will be described. A resist film (not shown) of a predetermined pattern is formed on the substrate upper surface 19 by photolithography, and n-type impurities are selectively ion-implanted into the p-type well region 22 using the resist film as a mask. The n-type impurities are, for example, phosphorus (P). Thereafter, the resist film is removed, and a predetermined heat treatment is performed to form a plurality of n-type impurities. + The n-type source region 23 is formed. + Two n-type source regions 23 may be formed side by side in the X-axis direction in one p-type well region 22. In FIG. + 7, the n-type source regions 23A, 23B, 23C, and 23D are located on the −X-axis direction side of the p-type well region 22A. + n-type source region and p-type well region 22C on the +X-axis direction side + Some of the source regions are not shown.

[0075] n + The widths of the source regions 23A, 23B, 23C, and 23D in the X-axis direction may be the same. + The width W2 of the n-type source region 23 in the X-axis direction may be, for example, 0.3 to 1 μm. + The type source regions 23 are selectively formed side by side in the X-axis direction at a predetermined interval D2, which may be, for example, 0.3 to 1 μm.

[0076] From the −X-axis direction side end of the p-type well region 22 to the n + The distance from the +X-axis direction end of the p-type well region 22 to the -X-axis direction end of the p-type source region 23 may be a distance D3. The distance D3 may be, for example, 0.1 to 1 μm. + The distance to the end of the type source region 23 on the +X-axis direction side may also be the interval D3.

[0077] 8 to 10, the gate insulating film forming step S103 in FIG. 4 will be described. In the gate insulating film forming step S103, the silicon oxide film is formed in at least two separate steps. In FIG. 8, in the first silicon oxide film formation, the silicon oxide film 24 is formed over the entire substrate upper surface 19. The silicon oxide film 24 may be formed by thermally oxidizing the semiconductor substrate 10. The silicon oxide film 24 may also be formed by a CVD (Chemical Vapor Deposition) method.

[0078] Next, in FIG. 9, photolithography and etching are used to selectively leave silicon oxide films 24 on the substrate upper surface 19. The silicon oxide films 24 are aligned in the X-axis direction. In FIG. 9, the silicon oxide film 24 is a silicon oxide film 24A on the −X-axis direction side and a silicon oxide film 24B on the +X-axis direction side. The silicon oxide film 24A is formed on the n-type drift layer 18, the p-type well region 22B, and the n-type well region 22C. + The silicon oxide film 24B may be in contact with the top surface of the n-type drift layer 18, the p-type well region 22C, and the n-type source region 23B. + It may be in contact with the upper surface of the source region 23D.

[0079] The end of the silicon oxide film 24A on the −X-axis direction side may be located on the boundary in the X-axis direction between the p-type well region 22A and the n-type drift layer 18 in a top view. + Similarly, the end of the silicon oxide film 24B on the −X-axis direction side may be on the boundary in the X-axis direction between the p-type well region 22B and the n-type drift layer 18 in a top view. The end of the silicon oxide film 24A on the +X-axis direction side may be on the boundary in the X-axis direction between the p-type well region 22B and the n-type drift layer 18 in a top view. + It may be on the type source region 23D.

[0080] Next, in FIG. 10 , a second silicon oxide film is formed on the substrate upper surface 19. The silicon oxide film may be formed by thermally oxidizing the semiconductor substrate 10. The silicon oxide film may also be formed by a CVD method. In this case, the silicon oxide film will be thicker in the region where the silicon oxide film 24 has already been formed than in other regions. If the second silicon oxide film is formed by a CVD method, it is preferable to perform thermal oxidation after forming the silicon oxide film by the CVD method in order to improve the interface between the gate insulating film 26 and the semiconductor substrate. This is because thermal oxidation causes oxygen atoms in the atmosphere to react with silicon atoms in the semiconductor substrate to form the silicon oxide film, and therefore a clean interface between the silicon oxide film and the semiconductor substrate is formed closer to the interior of the semiconductor substrate (the −Z direction side) than the initial substrate upper surface 19.

[0081] By the gate insulating film forming step S103 described above, a gate insulating film 26 is formed, which includes a thick gate insulating film 25B and a gate insulating film 25A that is thinner than the gate insulating film 25B. A step portion C, which is a portion where the thicknesses of the gate insulating films 25A and 25B change, is formed in the gate insulating film 26. The step portion C may be located at the boundary between the p-type well region 22A and the n-type drift layer 18 in the X-axis direction in top view. The reason for positioning the step portion C at the boundary between the well region 22A and the n-type drift layer 18 in the X-axis direction is to create a difference in the thickness of the gate insulating film between the two MOSFET sections. The step portion C may have a predetermined width in the X-axis direction. The predetermined width in the X-axis direction may be, for example, in the range of 0 to 300 nm.

[0082] 11, the gate electrode formation step S104 of FIG. 4 will be described. A gate electrode layer 27 is formed on the upper surface of the gate insulating film 26. The gate electrode layer 27 covers the gate insulating film 26.

[0083] The gate insulating film 26 includes a thin gate insulating film 25A and a gate insulating film 25B that is thicker than the gate insulating film 25, and includes a step C at the portion where the film thickness changes. The gate electrode layer 27 may have a step formed at a position corresponding to the step C of the gate insulating film 26 when viewed from above. The step of the gate electrode layer 27 may have a shape that follows the shape of the step C of the gate insulating film 26 so that the gate insulating film 26 is not exposed.

[0084] The gate electrode layer 27 may be formed of a conductive material such as polysilicon. The gate electrode layer 27 may be formed by a CVD method. The film thickness of the gate electrode layer 27 may be the height in the Z-axis direction at the portion where the upper and lower surfaces are parallel to the X-axis. The film thickness of the gate electrode layer 27 is, for example, 300 to 1000 nm.

[0085] 12, a stacked structure of the gate insulating film 26 and the gate electrode 27 is selectively formed by photolithography and etching. The stacked structure of the gate insulating film 26 and the gate electrode 27 may be aligned in the X-axis direction. The stacked structure of the gate insulating film 26 and the gate electrode 27 may have a stacked structure of the gate insulating film 26A and the gate electrode 27A on the −X-axis direction side and a stacked structure of the gate insulating film 26B and the gate electrode 27B on the +X-axis direction side.

[0086] The stacked structure of the gate insulating film 26 and the gate electrode 27 may be formed so as to cover the adjacent p-type well regions 22, a part of one source region provided in each p-type well region 22, and the n-type drift layer 18. In other words, the stacked structure of the gate insulating film 26A and the gate electrode 27A covers the p-type well region 22A, the n-type well region 22B, the n-type well region 22C, the n-type well region 22D, the n-type well region 22E, the n-type well region 22F, the n-type well region 22G, the n-type well region 22H ... + a p-type source region 23A, a p-type well region 22B, and an n + The gate insulating film 26B and the gate electrode 27B may cover the p-type well region 22B, the n-type source region 23B, and the n-type drift layer 18. Similarly, the stacked structure of the gate insulating film 26B and the gate electrode 27B may cover the p-type well region 22B, the n-type drift layer 18, and the p-type source region 23B. + the p-type source region 23C, the p-type well region 22C, and the n + The n-type source region 23D and the n-type drift layer 18 may be covered.

[0087] In the stacked structure of the gate insulating film 26 and the gate electrode 27, the end of the gate insulating film 26 on the −X-axis direction side and the end of the gate electrode 27 on the −X-axis direction side may be approximately aligned in top view. The end of the gate insulating film 26 on the +X-axis direction side and the end of the gate electrode 27 on the +X-axis direction side may be approximately aligned in top view. By making the end of the gate insulating film 26 and the gate electrode 27 on the −X-axis direction side and the end of the gate electrode 27 on the +X-axis direction side approximately aligned, it becomes possible to manufacture them using one and the same etching mask.

[0088] The end of the gate insulating film 26 on the −X-axis direction side is, in top view, the n-type well region 22 on the +X-axis direction side in the p-type well region 22 on the −X-axis direction side. + The end of the gate insulating film 25 on the +X-axis direction side may be located on the n-type source region 23 on the −X-axis direction side in the p-type well region 22 on the +X-axis direction side in top view. + That is, the end of the gate insulating film 26A on the −X-axis direction side may be located on the n-type source region 23 in the p-type well region 22A on the −X-axis direction side in a top view. + The end of the gate insulating film 26A on the +X-axis direction side may be located on the n-type source region 23A in the p-type well region 22B on the +X-axis direction side in a top view. + The source region 23B may be located on the source region 23B.

[0089] Next, referring to FIG. 13, the interlayer insulating film forming step S105 of FIG. 4 will be described. The interlayer insulating film 28 is formed so as to cover the gate electrode 27. The interlayer insulating film 28 may be formed of, for example, BPSG or PSG (Phosphorus Silicate Glass). The interlayer insulating film 28 may be a laminated film in which, for example, an HTO (High Temperature Oxide), NSG (Non-doped Silicate Glass), or TEOS (Tetraethoxysilane) film is formed under the BPSG (between the BPSG and the gate electrode 27). The thickness of the interlayer insulating film 28 may be, for example, 1 μm. The thickness of the interlayer insulating film 28 may be the thickness in the Z-axis direction of the portions whose upper and lower surfaces are parallel to the X-axis.

[0090] 14, the contact hole forming step S106 of FIG. 4 will be described. A contact hole 31 is formed in the interlayer insulating film 28 by photolithography and etching. The contact hole 31 is n + 14, the contact hole 31 may expose the n-type source region 23 and the p-type well region 22. + The n-type source region 23B, the p-type well region 22B, and the n-type source region 23B + The source region 23C is exposed.

[0091] The contact holes 31 may be formed by anisotropic dry etching. After the contact holes 31 are formed, the interlayer insulating film 28 may be subjected to a reflow treatment. After the contact holes 31 are formed, the interlayer insulating film 28 does not necessarily have to be subjected to a reflow treatment. In FIG. 14 , the end faces of the gate insulating film 26 and the gate electrode 27 may be covered with the interlayer insulating film 28.

[0092] In FIG. 14, the −X-axis direction side of the contact hole 31 is the interlayer insulating film 28A, and the +X-axis direction side of the contact hole 31 is the interlayer insulating film 28B.

[0093] 2C, after forming gate electrode 27 on the upper surface of gate insulating film 26, only the polysilicon is etched by photolithography and etching, without etching the gate insulating film. Then, an interlayer insulating film is formed over the entire upper surfaces of gate insulating film 26 and gate electrode 27, and then, by photolithography and etching, interlayer insulating film 28 and gate insulating film 26 are etched in the same process to form contact holes.

[0094] 2A, the source electrode forming step S107 and the drain electrode forming step S108 will be described. First, in the source electrode forming step S107, a source electrode 29 is formed so as to cover the interlayer insulating film 28. The source electrode 29 may be a metal film such as aluminum or an alloy containing aluminum as a main component (Al-Si, Al-Cu, Al-Si-Cu). The source electrode 29 may be formed by sputtering. The source electrode 29 may be formed on the interlayer insulating film 28 via a barrier metal (not shown). The barrier metal may be a titanium film (Ti), a titanium nitride film (TiN), or a laminated film thereof (for example, Ti / TiN, etc.). The barrier metal may be formed by sputtering. The source electrode 29 may fill the contact hole 31. The source electrode 29 is an n + The p-type source region 23 and the p-type well region 22 are electrically connected to each other.

[0095] In the drain electrode formation step S108, a drain electrode 30 is formed in contact with the drain layer on the lower surface 20 of the substrate. The drain electrode 30 may be a laminated film (e.g., Ti / Ni / Au, Al / Ti / Ni / Au, etc.) formed from a metal film such as nickel (Ni), titanium (Ti), gold (Au), silver (Ag), aluminum (Al), or an alloy mainly composed of aluminum (Al-Si, Al-Cu, Al-Si-Cu). The drain electrode 30 may be formed by sputtering. Next, a heat treatment is performed to form a n + An ohmic junction is formed between the source-drain layer 17 and the drain electrode 30. After the source electrode formation step S107 and before the drain electrode formation step S108, the substrate lower surface 20 side may be ground. The semiconductor device 100 is completed by the manufacturing steps up to this point.

[0096] Referring to FIG. 15 , a semiconductor device 101 will be described as a variation of the semiconductor device 100. In the semiconductor device 101, the gate insulating films 26A and 26B have different shapes in adjacent unit cells 41A and 41B. The different shapes refer to the following: the gate insulating film 26A includes a thin gate insulating film 25A and a gate insulating film 25B that is thicker than the gate insulating film 25A, with the gate insulating film 25A located on the −X-axis direction side and the gate insulating film 25A located on the +X-axis direction side; whereas the gate insulating film 26B includes a thin gate insulating film 25C and a gate insulating film 25D that is thicker than the gate insulating film 25C, with the gate insulating film 25D located on the −X-axis direction side and the gate insulating film 25C located on the +X-axis direction side. The manufacturing method of the semiconductor device 101 may be the same as that of the semiconductor device 100. The semiconductor device 101 achieves the effect of reducing di / dt, similar to the semiconductor device 100.

[0097] A second embodiment of the present invention will be described with reference to FIG. 16. The semiconductor device 110 of the second embodiment differs from the semiconductor device 100 of the first embodiment in that the position of the step portion C of the gate insulating film 26A is provided above the gate neck portion 32A. The gate insulating film 26A is made of a gate insulating film 25A having a thin film thickness and a gate insulating film 25B having a film thickness greater than that of the gate insulating film 25A. The gate insulating film 25A and the gate insulating film 25B may be aligned in the X-axis direction. The gate insulating film 25A and the gate insulating film 25B are continuous. The step portion C is provided in a portion where the film thickness of the gate insulating film 25A and the gate insulating film 25B changes. The gate insulating film 25A has n + The gate insulating film 25B is provided on the upper surfaces of the n-type source region 23A, the p-type well region 22A, and the n-type drift layer 18. + The gate insulating film 26A is provided on the upper surfaces of the n-type source region 23B, the p-type well region 22B, and the n-type drift layer 18. The step portion C of the gate insulating film 26A is provided on the gate neck portion 32A in top view. In the unit cell 41A, the gate insulating film on the upper surface of the channel portion 44A of the MOSFET portion 42A is made of the gate insulating film 25A, and the gate insulating film on the upper surface of the channel portion 45A of the MOSFET portion 43A is made of the gate insulating film 25B.

[0098] In the semiconductor device 110 of the second embodiment, similarly to the semiconductor device 100 of the first embodiment, the thickness of the gate insulating film 25A above the channel portion 44 is thinner than the thickness of the gate insulating film 25B above the channel portion 45. Therefore, the threshold voltages of the MOSFET portions 42 and 43 are different, making it possible to adjust the di / dt characteristics. In the semiconductor device 110 of the second embodiment, the gate-drain capacitance is larger than that of the semiconductor device 100, which reduces dv / dt at turn-off and reduces noise.

[0099] The method for manufacturing the semiconductor device 110 of the second embodiment is the same as the method for manufacturing the semiconductor device 100 of the first embodiment, and therefore the description thereof will be omitted.

[0100] A third embodiment of the present invention will be described with reference to Fig. 17. A semiconductor device 120 of the third embodiment differs from the semiconductor device 100 of the first embodiment in that the step portion C of the gate insulating film 26A is located above the p-type well region 22A.

[0101] The gate insulating film 26A is made up of a gate insulating film 25A having a small thickness and a gate insulating film 25B having a thickness thicker than the gate insulating film 25A. The gate insulating film 25A and the gate insulating film 25B may be aligned in the X-axis direction. The gate insulating film 25A and the gate insulating film 25B may be continuous. A step portion C is provided at a portion where the thickness of the gate insulating film 25A and the gate insulating film 25B change. The gate insulating film 25A has a thickness of n + The gate insulating film 25B is provided on the upper surfaces of the n-type source region 23A and the p-type well region 22A. + The step C is provided on the upper surfaces of the n-type source region 23B, the p-type well region 22B, the n-type drift layer 18, and the p-type well region 22A. That is, the step C is on the p-type well region 22A in a top view. In the unit cell 41A, the gate insulating film on the upper surface of the channel portion 44A of the MOSFET portion 42A is made of the gate insulating film 25A and the gate insulating film 25B, and the gate insulating film on the upper surface of the channel portion 45A of the MOSFET portion 43A is made of the gate insulating film 25B.

[0102] In the semiconductor device 120 of the third embodiment, a gate insulating film 25A and a gate insulating film 25B are provided on the channel portion 44A. Therefore, as in the first embodiment, the threshold voltage differs between the MOSFET portion 42 and the MOSFET portion 43, making it possible to adjust the di / dt characteristics. In the semiconductor device 120 of the third embodiment, the step portion C of the gate insulating film 25 is located on the p-type well region 22A in top view, which reduces the gate-source capacitance compared to the semiconductor device 100, thereby suppressing Qg (charge amount) and reducing drive loss.

[0103] The method for manufacturing the semiconductor device 120 of the third embodiment is the same as the method for manufacturing the semiconductor device 100 of the first embodiment, and therefore the description thereof will be omitted.

[0104] A fourth embodiment of the present invention will be described with reference to Fig. 18. A semiconductor device 130 of the fourth embodiment differs from the semiconductor device 100 of the first embodiment in that the gate insulating film 26 and the gate electrode 27 are divided by an interlayer insulating film 28 above the gate neck portion 32.

[0105] In the semiconductor device 130, a thin gate insulating film 25A and a gate insulating film 25B that is thicker than the gate insulating film 25A are divided by an interlayer insulating film 28A. Furthermore, a gate electrode 27A of the semiconductor device 130 is formed on the gate insulating films 25A and 25B. The gate electrode 27A is divided by the interlayer insulating film 28A. The gate electrode 27A on the gate insulating film 25A has an end on the −X-axis direction that substantially coincides with an end on the −X-axis direction of the gate insulating film 25A, and an end on the +X-axis direction that substantially coincides with an end on the +X-axis direction of the gate insulating film 25A. Similarly, the gate electrode 27A on the gate insulating film 25B has an end on the −X-axis direction that substantially coincides with an end on the −X-axis direction of the gate insulating film 25B, and an end on the +X-axis direction that substantially coincides with an end on the +X-axis direction of the gate insulating film 25A. The gate electrode 27A on the gate insulating film 25A and the gate electrode 27A on the gate insulating film 25B may be connected to the gate pad 16 through the same gate wiring (not shown). The gate electrode 27A on the gate insulating film 25A and the gate electrode 27A on the gate insulating film 25B are electrically connected to each other.

[0106] In the semiconductor device 130, the gate insulating film 25A is + The gate insulating film 25B is in contact with the n-type source region 23A, the p-type well region 22A, and the n-type drift layer 18. In the semiconductor device 130, the gate insulating film 25B is in contact with the n-type source region 23A, the p-type well region 22A, and the n-type drift layer 18. + The unit cell 41A is in contact with the p-type source region 23B, the p-type well region 22B, and the n-type drift layer 18. In the unit cell 41A, the gate insulating film on the upper surface of the channel portion 44A of the MOSFET portion 42A is made of the gate insulating film 25A, and the gate insulating film on the upper surface of the channel portion 45A of the MOSFET portion 43A is made of the gate insulating film 25B.

[0107] In the semiconductor device 130 of the fourth embodiment, a gate insulating film 25A is provided on the channel portion 44, and a gate insulating film 25B is provided on the channel portion 45. Therefore, as in the first embodiment, the threshold values ​​differ between the MOSFET portion 42 and the MOSFET portion 43, making it possible to adjust the di / dt characteristics. In the semiconductor device 130 of the fourth embodiment, the gate insulating film 25A and the gate insulating film 25B are divided by the interlayer insulating film 28A, making it possible to reduce the gate-drain capacitance compared to the semiconductor device 100.

[0108] The manufacturing method of the semiconductor device 130 of the fourth embodiment differs from the manufacturing method of the semiconductor device 100 of the first embodiment in that the vicinity of the step portion C is also removed when processing the gate insulating film 26A and the gate electrode 27A by photolithography and etching, but the rest is the same, so the description will be omitted.

[0109] 19 is a diagram illustrating a comparative example of the first embodiment. In the semiconductor device 200 of the comparative example, the gate insulating film has a uniform thickness. That is, the MOSFET portion 42A and the MOSFET portion 43A in the unit cell 41A have the same gate insulating film thickness. Similarly, the MOSFET portion 42B and the MOSFET portion 43B in the unit cell 41B have the same gate insulating film thickness. Furthermore, the gate insulating films 26A and 26B have the same thickness. In this example, the thickness of the gate insulating films 26A and 26B may be the same as the thickness of the gate insulating film 25A of the semiconductor device 100 of the first embodiment.

[0110] 20A is a diagram showing the relationship between the gate voltage and the drain current of the semiconductor device 200. The relationship between the gate voltage and the drain current in the first embodiment shown in FIG. 3A is indicated by a dotted line, and the relationship between the gate voltage and the drain current in the comparative example is indicated by a solid line. In the semiconductor device 200, the threshold voltage Vth1 of the MOSFET portion 42A and the MOSFET portion 43A is determined by factors such as the film thickness of the gate insulating film 26A, but because the film thickness of the gate insulating film 26A is uniform, the threshold voltages Vth1 are the same.

[0111] The thickness of gate insulating film 26 of semiconductor device 200 is the same as the thickness of gate insulating film 25A of MOSFET portion 42A of semiconductor device 100. In semiconductor device 200, the same gate voltage is applied to MOSFET portion 42A and MOSFET portion 43A, and therefore drain current ID200 starts to flow simultaneously in MOSFET portion 42A and MOSFET portion 43A when the gate voltage exceeds Vth1. Therefore, semiconductor device 200 as a whole is turned on, and a drain current twice as large as ID1 in the first embodiment flows.

[0112] FIG. 20B illustrates the relationship between drain current and time. The dotted line indicates the relationship between drain current and time in the first embodiment shown in FIG. 3B, and the solid line indicates the relationship between drain current and time in the comparative example. FIG. 20B also illustrates the gate voltage V. When the gate voltage V exceeds Vth1, drain current ID1 begins to flow in the MOSFET section 42A and the MOSFET section 43A. Therefore, in the semiconductor device 200, when the gate voltage V exceeds Vth1, a drain current twice as large as ID1 in the first embodiment begins to flow. Therefore, in the semiconductor device 200, the slope of the current (solid line) when the gate voltage V exceeds Vth1 is larger than the slope of the current (dotted line) in the semiconductor device 100, resulting in a larger di / dt. When the density of unit cells 41 is increased by miniaturization to reduce the on-resistance of the MOSFET, a large di / dt at turn-on also increases the gain characteristics, creating a risk of electromagnetic interference (noise).

[0113] In this example, a vertical MOSFET is shown, but the same problem of reduced short-circuit resistance can be solved in the case of a vertical IGBT by increasing the thickness of the gate insulating film, which reduces the current flowing through the channel and suppresses the saturation current, thereby reducing the short-circuit current when the IGBT enters a short-circuit state and improving the short-circuit resistance.

[0114] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0115] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0116] 10. Semiconductor substrate 12 Pressure-resistant structure 14 Active area 16 Gate Pad 17 Drain layer 18 Drift Layer 19 Top surface of the board 20 Bottom surface of the board 22, 22A, 22B, 22C p-type well region, 23, 23A, 23B, 23C, 23D + Type Source Area 24 Silicon oxide film 25A, 25B, 25C, 25D Gate insulating film 26, 26A, 26B Gate insulating film 27, 27A, 27B gate electrodes 28, 28A, 28B Interlayer insulating film 29 Source electrode 30 drain electrode 31 Contact Hole 32A, 32B Gate neck 41A, 41B unit cell 42A, 43A, 42B, 43B MOSFET section 44A, 45A, 44B, 45B channel part

Claims

1. a semiconductor substrate having an upper surface and a lower surface; a drift layer is disposed on the upper surface side, and a drain layer is disposed on the lower surface side; a first well region and a second well region are arranged on the upper surface side of the drift layer with the drift layer interposed therebetween; a first source region is selectively disposed on the upper surface side of the first well region; a second source region is selectively disposed on the upper surface side of the second well region; a gate insulating film is selectively disposed on the upper surface of the semiconductor substrate; a gate electrode is disposed on an upper surface of the gate insulating film; an interlayer insulating film is disposed on an upper surface of the gate electrode; the gate insulating film has a first gate insulating film and a second gate insulating film that are directly adjacent to each other and continuous with each other at a step portion; the first gate insulating film is disposed on an upper surface of the first well region and the first source region; the second gate insulating film is disposed on an upper surface of the second well region and the second source region; The first gate insulating film has a thickness smaller than that of the second gate insulating film. A semiconductor device characterized by:

2. the step portion is disposed on a boundary between the first well region and the drift layer, The second gate insulating film is disposed on the drift layer.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

3. the step portion is disposed on the drift layer, the first gate insulating film is disposed on an upper surface of the drift layer; The second gate insulating film is disposed on the upper surface of the drift layer.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

4. the step portion is disposed on the first well region, the second gate insulating film is disposed on the upper surface of the drift layer and the first well region; 2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

5. The position of the edge of the gate insulating film coincides with the position of the edge of the interlayer insulating film.

5. The semiconductor device according to claim 1, wherein the first insulating film is a semiconductor substrate.

6. In the adjacent gate insulating films, the first gate insulating films are arranged to face each other, or the second gate insulating films are arranged to face each other.

6. The semiconductor device according to claim 1, wherein the first insulating film is a semiconductor substrate.

7. The thickness of the second gate insulating film is 1.3 times or more and 2 times or less than that of the first gate insulating film.

7. The semiconductor device according to claim 1, wherein the first insulating film is a semiconductor substrate.

8. a well region forming step of forming a well region on the upper surface side of a semiconductor substrate having an upper surface and a lower surface, a drift layer on the upper surface side, and a drain layer on the lower surface side; forming a source region on the upper surface side of the well region; forming a gate insulating film on the upper surface, the gate insulating film having a first gate insulating film and a second gate insulating film having a thickness greater than that of the first gate insulating film; forming a gate electrode on the upper surface of the gate insulating film; forming an interlayer insulating film to cover the gate electrode; forming a source electrode on the upper surface of the interlayer insulating film; forming a drain electrode on the lower surface of the semiconductor substrate; Equipped with in the gate insulating film formation step, the gate insulating film is formed over the entire semiconductor substrate, and immediately after selectively removing the gate insulating film, a gate insulating film is formed again, thereby forming the first gate insulating film having different film thicknesses and the second gate insulating film having a film thickness greater than that of the first gate insulating film; After the interlayer insulating film formation step, the interlayer insulating film and the gate insulating film are etched in the same process to form a contact hole exposing the semiconductor substrate.

10. A method for manufacturing a semiconductor device comprising the steps of:

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