High frequency device manufacturing method

Abstract

To provide a manufacturing method for a high-frequency device capable of suppressing costs.SOLUTION: The manufacturing method for a high-frequency device includes the steps for mounting a first chip 20a provided with a first pillar 16a on a top surface on a metal base 10, forming an insulating layer 12 covering the first chip 20a on the metal base 10, and exposing the top surface of the first pillar 16a from the insulating layer 12, and connecting the first pillar 16a on the insulating layer 12 to form first wiring lines 18a, 18b that transmit high-frequency signals.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a high frequency device. [Background technology]

[0002] High-frequency devices are known in which a chip is mounted face-up on a metal base in a package having an insulating frame on the metal base, and the pattern on the insulating frame and the chip are electrically connected using bonding wires (e.g., Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-176149 [Patent Document 2] Japanese Patent Application Laid-Open No. 2001-196865 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, high-frequency signals are transmitted through bonding wires, which degrades high-frequency characteristics. It is possible to use a microstrip line as the transmission line. However, if the alignment precision between the chip and the line is poor, the electrodes on the chip will need to be large, which increases the cost of the chip.

[0005] The present disclosure has been made in consideration of the above-mentioned problems, and aims to provide a method for manufacturing a high-frequency device that can reduce costs. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a method for manufacturing a high-frequency device, including the steps of mounting a first chip having a first pillar on an upper surface thereof on a metal base, forming an insulator layer on the metal base to cover the first chip, exposing the upper surface of the first pillar from the insulator layer, and forming a first wiring on the insulator layer to connect to the first pillar and transmit a high-frequency signal. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to provide a method for manufacturing a high-frequency device that can reduce costs. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view of a high-frequency device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram of the vicinity of chips 22a and 20a in the first embodiment. [Figure 3] FIG. 3 is a plan view of the vicinity of the chip 22a in the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view taken along line AA in FIG. [Figure 5] FIG. 5 is a plan view of the chip 20a and its vicinity in the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view taken along line AA in FIG. [Figure 7A] FIG. 7A is a cross-sectional view illustrating a method for manufacturing the high-frequency device according to the first embodiment. [Figure 7B] FIG. 7B is a cross-sectional view illustrating a method for manufacturing the high-frequency device according to the first embodiment. [Figure 8A] FIG. 8A is a cross-sectional view illustrating a method for manufacturing the high-frequency device according to the first embodiment. [Figure 8B] FIG. 8B is a cross-sectional view illustrating a method for manufacturing the high-frequency device according to the first embodiment. [Figure 9A] FIG. 9A is a cross-sectional view illustrating a method for manufacturing the high-frequency device according to the first embodiment. [Figure 9B] FIG. 9B is a cross-sectional view illustrating a method for manufacturing the high-frequency device according to the first embodiment. [Figure 10A] FIG. 10A is a cross-sectional view illustrating a method for manufacturing the high-frequency device according to the first embodiment. [Figure 10B] FIG. 10B is a cross-sectional view illustrating a method for manufacturing the high-frequency device according to the first embodiment. [Figure 11] FIG. 11 is a block diagram illustrating an example of an amplifier device according to the first embodiment. [Figure 12] FIG. 12 is a plan view of the vicinity of the chip 20a in the first comparative example. [Figure 13] FIG. 13 is a plan view of the chip 20a and its vicinity in the first embodiment. [Figure 14A] FIG. 14A is a cross-sectional view illustrating a method for manufacturing a high-frequency device according to a first modification of the first embodiment. [Figure 14B] FIG. 14B is a cross-sectional view illustrating a method for manufacturing a high-frequency device according to Modification 1 of Example 1. [Figure 15A] FIG. 15A is a cross-sectional view illustrating a method for manufacturing a high-frequency device according to a first modification of the first embodiment. [Figure 15B] FIG. 15B is a cross-sectional view illustrating a method for manufacturing a high-frequency device according to Modification 1 of Example 1. [Figure 16A] FIG. 16A is a cross-sectional view illustrating a method for manufacturing a high-frequency device according to a second modification of the first embodiment. [Figure 16B] FIG. 16B is a cross-sectional view illustrating a method for manufacturing a high-frequency device according to Modification 2 of Example 1. [Figure 17A] FIG. 17A is a cross-sectional view illustrating a method for manufacturing a high-frequency device according to a second modification of the first embodiment. [Figure 17B] FIG. 17B is a cross-sectional view illustrating a method for manufacturing a high-frequency device according to Modification 2 of Example 1. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a method for manufacturing a high-frequency device, including the steps of: mounting a first chip having a first pillar on an upper surface thereof on a metal base; forming an insulator layer on the metal base to cover the first chip; exposing an upper surface of the first pillar from the insulator layer; and forming a first wiring on the insulator layer to connect to the first pillar and transmit a high-frequency signal. This makes it possible to provide a method for manufacturing a high-frequency device that can reduce costs. (2) The method preferably includes a step of mounting a second chip on the metal base, a step of forming a first through hole in the insulator layer that reaches the top surface of the second chip, a step of forming a first through electrode in the first through hole that is connected to the top surface of the second chip, and a step of forming a second wiring on the insulator layer that connects to the first through electrode, and the step of forming the insulator layer preferably includes a step of forming the insulator layer that covers the first chip and the second chip. (3) The second chip is preferably a passive element including a dielectric substrate and an electrode provided on the upper surface of the dielectric substrate. (4) The first chip preferably includes a transistor. (5) It is preferable that the passive element is at least a part of a matching circuit connected to the transistor. (6) It is preferable that the first chip has a first electrode to which the first pillar is joined, the second chip has a second electrode to which the first through electrode is joined, and the width of the second electrode is larger than the width of the first electrode. (7) The step of forming the first through holes preferably includes the step of forming the first through holes by irradiating the insulating layer with laser light. (8) The method preferably includes the steps of: mounting the third chip, having a second pillar on its upper surface, on the metal base; and forming third wiring on the insulator layer to connect to the second pillar, wherein the step of forming the insulator layer includes the step of forming the insulator layer to cover the first chip and the third chip; and the step of exposing the upper surface of the first pillar from the insulator layer preferably includes the step of polishing or grinding the insulator layer covering the first pillar and the second pillar to expose the upper surfaces of the first pillar and the second pillar from the upper surface of the insulator layer. (9) It is preferable that the method includes the steps of forming a second through hole in the insulator layer that reaches the upper surface of the metal base, forming a second through electrode in the second through hole that is connected to the upper surface of the metal base, and forming a fourth wiring on the insulator layer that is connected to the second through electrode. (10) It is preferable to include a step of mounting an electronic component on a metal layer provided on the insulating layer.

[0010] [Details of the embodiments of the present disclosure] Specific examples of methods for manufacturing high-frequency devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0011] [Example 1] FIG. 1 is a cross-sectional view of a high-frequency device according to a first embodiment. As shown in FIG. 1, in a high-frequency device 100, a lead frame 11 includes a metal base 10 and a terminal 10a, which are separated from each other. The lead frame 11 is made primarily of copper, for example, and is coated with a silver film. Chips 20a, 20b, and 22a are mounted on the metal base 10. The chips 20a and 20b are, for example, semiconductor chips, each including a transistor. The chip 22a is, for example, a passive element, each including a capacitor and a line. The thickness Ta of the chip 20a is greater than the thickness Tb of the chip 20b. Electrodes 21a and 21b are provided on the top surfaces of the chips 20a and 20b, respectively. Electrodes 23a and 23b are provided on the top surface of the chip 22a. The electrodes 21a, 21b, 23a, and 23b are, for example, metal layers such as gold layers. An insulator layer 12 is provided on the lead frame 11 to cover the chips 20a, 20b, and 22a. The insulator layer 12 is a resin layer such as an epoxy resin. A metal layer 18 is provided on the insulator layer 12. The metal layer 18 forms wirings 18a to 18h as a rewiring layer. The metal layer 18 is, for example, a gold layer or a copper layer. The wirings 18a to 18h that transmit high-frequency signals form microstrip lines together with the metal base 10.

[0012] Through electrodes 14a to 14c and 14e, as well as pillars 16a and 16b, are provided through the insulator layer 12. The through electrode 14a electrically connects and shorts the wiring 18g to the metal base 10. The through electrode 14b electrically connects and shorts the wiring 18h to the terminal 10a. The through electrode 14c electrically connects and shorts the wirings 18c and 18d to the electrodes 23a and 23b of the chip 22a, respectively. The through electrode 14e electrically connects and shorts the wiring 18c to the terminal 10a. The through electrodes 14a to 14c and 14e are, for example, gold or copper layers. The pillar 16a electrically connects and shorts the wirings 18a and 18b to the electrodes 21a and 21b of the chip 20a, respectively. The pillar 16b electrically connects and shorts the wirings 18e and 18f to the electrodes 21a and 21b of the chip 20b, respectively. The pillars 16a and 16b are, for example, gold or copper layers, and the width of the pillars 16a and 16b is smaller than the width of the through electrodes 14a to 14c and 14e.

[0013] An electronic component 24 is mounted on the insulator layer 12. An electrode 25 of the electronic component 24 is bonded to the metal layer 18. Solder such as SnAgCu is used to bond the electrode 25 to the metal layer 18. The electronic component 24 is, for example, a discrete component, such as a chip resistor, a chip capacitor, or a chip inductor. An insulator layer 26 is provided on the insulator layer 12 so as to cover the electronic component 24. The insulator layer 26 is, for example, a resin layer made of epoxy resin. The lead frame 11 has a thickness of, for example, 200 μm, the insulator layer 12 has a thickness of, for example, 200 μm, and the insulator layer 26 has a thickness of, for example, 400 μm.

[0014] FIG. 2 is a circuit diagram of the chips 22a and 20a in the first embodiment. As shown in FIG. 2, in the chip 22a, a transmission line Z1 is connected between nodes N1 and N2. A capacitor C1 is shunt-connected to a node on the node N1 side of the transmission line Z1, and a capacitor C2 is shunt-connected to a node on the node N2 side of the transmission line Z1. The chip 22a functions as a CLC π-type circuit. The chip 20a is provided with a transistor Q1. The transistor Q1 is, for example, a FET (Field Effect Transistor). The source S is grounded, and the gate G is connected to a node N2 and its drain D is connected to node N3. Chip 22a functions as a matching circuit that matches the impedance seen from node N1 to chip 22a with the impedance seen from node N2 to gate G. Transistor Q1 amplifies a high-frequency signal input to node N1 and outputs it to drain D.

[0015] FIG. 3 is a plan view of the chip 22a in Example 1, viewed from the positive side toward the negative side along the Z direction. FIG. 4 is a cross-sectional view taken along the line AA in FIG. 3. In FIG. 3, the metal layer 32 is indicated by cross-hatching, and the through electrode 14c on the surface where the through electrode 14c is bonded to the metal layer 32 is indicated by a white dotted circle. As shown in FIGS. 3 and 4, the chip 22a is mounted on a metal base 10. The chip 22a includes a dielectric substrate 30 and metal layers 32 and 34. The metal layer 32 forms electrodes 23a and 23b. The electrodes 23a and 23b are separated on the upper surface of the dielectric substrate 30. The metal layer 34 is provided on the lower surface of the dielectric substrate 30. The metal layer 34 is provided on almost the entire lower surface of the dielectric substrate 30. The dielectric substrate 30 is, for example, a ceramic substrate. The dielectric constant of the dielectric substrate 30 is, for example, 5 to 200, which is higher than the dielectric constants of the insulator layers 12 and 26. Of the laminate 20c consisting of the metal layer 34, the dielectric substrate 30, and the metal layer 32, the region overlapping with the electrode 23a when viewed from the positive side to the negative side along the Z direction constitutes the capacitor C1. Furthermore, the region overlapping with the electrode 23b when viewed from the positive side to the negative side along the Z direction constitutes the capacitor C2. By increasing the dielectric constant of the dielectric substrate 30, the area of ​​the electrodes 23a and 23b can be reduced, thereby miniaturizing the capacitors C1 and C2 and the chip 22a. Furthermore, by overlapping at least a portion of the line 18i forming the transmission line Z1 with the dielectric substrate 30 when viewed from the Z direction, the line 18i can be made smaller, thereby miniaturizing the chip 22a. The metal layer 34 and the metal base 10 are bonded together by a bonding material 35. The bonding material 35 is a material obtained by sintering a metal paste such as silver paste.

[0016] An insulator layer 12 is provided on a metal base 10 so as to cover chip 22a. A through electrode 14c is provided so as to penetrate the insulator layer 12. The through electrode 14c is provided on electrodes 23a and 23b. A metal layer 18 is provided on the insulator layer 12. The metal layer 18 forms wiring 18c, 18d, and a line 18i. The wiring 18c and the line 18i are electrically connected to electrode 23a via the through electrode 14c. The wiring 18d and the line 18i are electrically connected to electrode 23b via the through electrode 14c. An insulator layer 26 is provided on the insulator layer 12 so as to cover the metal layer 18.

[0017] The electrode 23a and the metal layer 34 sandwiching the dielectric substrate 30 form a capacitor C1, and the electrode 23b and the metal layer 34 sandwiching the dielectric substrate 30 form a capacitor C2. A reference potential such as a ground potential is supplied to the metal base 10. As a result, the metal layer 34 is at ground potential. The line 18i, the metal layer 34, and the metal base 10 form a transmission line Z1 as a microstrip line. The wiring 18c and 18d and the metal base 10 form microstrip lines 19c and 19d, respectively. The width Wb1 of the electrodes 23a and 23b is, for example, 150 μm or more. The cross-sectional shape of the through electrode 14c is trapezoidal, and the width Wb3 of the through electrode 14c contacting the electrodes 23a and 23b is smaller than the width Wb2 of the through electrode 14c contacting the wiring 18c and 18d. Width Wb3 is, for example, 100 to 120 μm, width Wb2 is, for example, 130 to 150 μm.

[0018] FIG. 5 is a plan view of the chip 20a in Example 1, viewed from the positive side toward the negative side along the Z direction. FIG. 6 is a cross-sectional view taken along the line AA in FIG. 5. In FIG. 5, the metal layer 38 is indicated by cross-hatching, and the pillars 16a at the surface where the pillars 16a are bonded to the metal layer 38 are indicated by white dotted circles. As shown in FIGS. 5 and 6, the chip 20a is mounted on a metal base 10. In the chip 20a, a semiconductor layer 37 is provided on a substrate 36. If the transistor provided on the chip 20a is a GaN HEMT (Gallium Nitride High Electron Mobility Transistor), the substrate 36 is, for example, a SiC substrate or a sapphire substrate. The semiconductor layer 37 includes a GaN channel layer and an AlGaN barrier layer. A metal layer 38 is provided on the upper surface of the semiconductor layer 37, and a metal layer 39 is provided on the lower surface of the substrate 36. The metal layer 38 forms electrodes 21a and 21b. The electrodes 21a and 21b are, for example, source and drain electrodes. The metal layer 39 is electrically connected to, for example, a source electrode. The metal layer 39 is bonded to the metal base 10 via a bonding material 35. The bonding material 35 is, for example, a sintered metal paste.

[0019] An insulator layer 12 is provided to cover the chip 20a. A metal layer 18 is provided on the upper surface of the insulator layer 12. The metal layer 18 forms wirings 18a and 18b. The wirings 18a and 18b and the metal base 10 form microstrip lines 19a and 19b, respectively. An insulator layer 26 is provided on the insulator layer 12 to cover the metal layer 18. The wirings 18a and 18b are electrically connected to electrodes 21a and 21b, respectively, via pillars 16a. The pillars 16a may be formed on the electrodes 21a and 21b using a plating method. The pillars 16a may be formed on the electrodes 21a and 21b using a stud bump method. The width Wa1 of the electrodes 21a and 21b is, for example, 100 μm, and the width Wa2 of the pillars 16a is, for example, 70 μm.

[0020] As shown in FIGS. 3 to 6, microstrip lines 19a to 19d can be formed by wirings 18a to 18d connected to chips 20a and 22a, and therefore high frequency characteristics can be improved compared to using bonding wires as in Patent Document 1.

[0021] [Manufacturing method of Example 1] 7A to 10B are cross-sectional views illustrating a manufacturing method of a high-frequency device according to Example 1. As shown in FIG. 7A, a lead frame 11 is prepared. The size of the lead frame 11 is, for example, 500 mm × 500 mm. As shown in FIG. 7B, chips 20a, 20b, and 22a are mounted on a metal base 10. Pillars 16a and 16b are provided on electrodes 21a and 21b of chips 20a and 20b. No pillars are provided on electrodes 23a and 23b of chip 22a. A bonding material, such as a metal paste such as nanosilver paste, is partially applied to the metal base 10. Then, chips 20a, 20b, and 22a are mounted on the bonding material and heat-treated. The bonding material is sintered by the heat treatment. As a result, chips 20a, 20b, and 22a are mounted on the metal base 10. Because chip 20a is thicker than chip 20b, the top surface of pillar 16a is located on the +Z side in the Z direction relative to the top surface of pillar 16b.

[0022] As shown in FIG. 8A, an insulator layer 12 is formed on a lead frame 11 so as to cover chips 20a, 20b, and 22a. For example, a resin film is attached to the lead frame 11 using a vacuum laminator, and the insulator layer 12 is hardened by heat treatment. This forms the insulator layer 12. The insulator layer 12 may also be formed by applying softened resin to the lead frame 11, as in a molding method, and hardening the resin by heat treatment. The insulator layer 12 is formed so as to cover pillars 16a and 16b.

[0023] 8B, the top surface of the insulator layer 12 is polished or ground, thereby exposing the top surfaces of the pillars 16a and 16b from the top surface of the insulator layer 12. The top surfaces of the insulator layer 12 and the pillars 16a and 16b become approximately flat.

[0024] As shown in FIG. 9A, through-holes 15a to 15c and 15e are formed through the insulator layer 12. The through-holes 15a to 15c and 15e are formed by irradiating the insulator layer 12 with laser beams 13a to 13c and 13e, respectively. The laser beams 13a to 13c and 13e are, for example, ultraviolet light, visible light, or infrared light. The laser device used may be, for example, an ultraviolet laser device using a harmonic of a YAG (Yttrium Aluminum Garnet) laser or a carbon dioxide gas laser device. 15a When forming through-holes 15a, 15b, and 15e that reach the top surface of lead frame 11, such as through-hole 15c, the power of laser beam 13a, 13b, and 13e is increased. When forming through-hole 15c that reaches the top surface of chip 22a, such as through-hole 15c, the power of laser beam 13c is decreased.

[0025] 9B, through electrodes 14a-14c and 14e are formed in through holes 15a-15c and 15e. The through electrodes 14a-14c and 14e are formed by, for example, plating. As the plating method, for example, a seed layer is formed by electroless plating, and a plating layer is formed on the seed layer by electrolytic plating.

[0026] As shown in Fig. 10A, a metal layer 18 is formed on the insulator layer 12. For example, plating is used to form the metal layer 18. Desired regions of the metal layer 18 are removed by, for example, etching. Wirings 18a to 18h are formed from the metal layer 18. A metal film (for example, a gold film) that improves the wettability of the solder may be formed on the surface of the metal layer 18.

[0027] As shown in FIG. 10B, an electronic component 24 is mounted on the metal layer 18 using a bonding material. The bonding material bonds the electrodes 25 of the electronic component 24 to the metal layer 18. Then, an insulator layer 26 is formed on the insulator layer 12 so as to cover the metal layer 18 and the electronic component 24. For example, a molding method or a lamination method is used to form the insulator layer 26. The lead frame 11 and the insulator layers 12 and 26 are cut into individual pieces. For example, a dicing method using a dicing blade is used for cutting. This completes the high-frequency device according to Example 1.

[0028] As an example of a high-frequency device, a high-frequency power amplifier used in a mobile communication base station will be described. FIG. 11 is a block diagram showing an example of an amplifier according to a first embodiment. As shown in FIG. 11, an amplifier 102 includes transistors Q1 to Q3. The transistors Q1 to Q3 are, for example, FETs. The transistor Q1 is a driver amplifier, and the transistors Q2 and Q3 are a main amplifier and a peak amplifier, respectively, of a Doherty amplifier.

[0029] The input terminal Tin is connected to the gate G1 of the transistor Q1 via a matching circuit 60. The matching circuit 60 determines the impedance seen from the input terminal Tin to the matching circuit 60 and the impedance from the matching circuit 60 to the gate G1 The impedance seen from the matching circuit 61 is matched to the impedance seen from the matching circuit 61. A gate bias voltage is applied to the gate G1 from the bias terminal Tg1. The source S1 of the transistor Q1 is grounded. The drain D1 of the transistor Q1 is connected to the divider 66 via a matching circuit 61. The matching circuit 61 matches the impedance seen from the drain D1 to the matching circuit 61 and the impedance seen from the matching circuit 61 to the divider 66. A drain bias voltage is applied to the drain D1 from the bias terminal Td1. The divider 66 divides the high-frequency signal output from the matching circuit 61 into two.

[0030] The divider 66 is connected to the gate G2 of transistor Q2 via a phase shifter 68 and a matching circuit 62. The phase shifter 68 shifts the phase of the high-frequency signal output by the divider 66. The matching circuit 62 matches the impedance seen from the divider 66 at the matching circuit 62 with the impedance seen from the matching circuit 62 at the gate G2. A gate bias voltage is applied to the gate G2 via a bias terminal Tg2. The source S2 of transistor Q2 is grounded. The drain D2 of transistor Q2 is connected to a combiner 67 via a matching circuit 64. The matching circuit 64 matches the impedance seen from the drain D2 at the matching circuit 64 with the impedance seen from the matching circuit 64 at the combiner 67. A drain bias voltage is applied to the drain D2 via a bias terminal Td2.

[0031] The divider 66 is connected to the gate G3 of transistor Q3 via a phase shifter 69 and a matching circuit 63. The phase shifter 69 shifts the phase of the high-frequency signal output by the divider 66. The matching circuit 63 matches the impedance seen from the divider 66 at the matching circuit 63 with the impedance seen from the matching circuit 63 at the gate G3. A gate bias voltage is applied to the gate G3 via a bias terminal Tg3. The source S3 of transistor Q3 is grounded. The drain D3 of transistor Q3 is connected to a combiner 67 via a matching circuit 65. The matching circuit 65 matches the impedance seen from the drain D3 at the matching circuit 65 with the impedance seen from the matching circuit 65 at the combiner 67. A drain bias voltage is applied to the drain D3 via a bias terminal Td3.

[0032] The combiner 67 combines the high frequency signal output from the drain D2 and the high frequency signal output from the drain D3 and outputs the combined signal to the output terminal Tout. Bias circuits (not shown) are provided between the bias terminals Tg1 to Tg3 and Td1 to Td3 and the transistors Q1 to Q3.

[0033] The high-frequency signal input from the input terminal Tin is amplified by the transistor Q1. The transistors Q2 and Q3, the divider 66, and the combiner 67 form a Doherty amplifier. The divider 66 divides the amplified high-frequency signal and outputs it to the transistors Q2 and Q3. The transistor Q2 is a main amplifier that amplifies one of the high-frequency signals divided by the divider 66. The transistor Q3 is a peak amplifier that amplifies the other of the high-frequency signals divided by the divider 66. The combiner 67 combines the high-frequency signal amplified by the transistor Q2 and the high-frequency signal amplified by the transistor Q3, and outputs the combined high-frequency signal to the output terminal Tout. The high-frequency signal input to the input terminal Tin and output from the output terminal Tout is, for example, a signal of 0.5 GHz to 100 GHz, and typically a signal of 0.5 GHz to 10 GHz.

[0034] Transistor Q2 operates in class A or class B, while transistor Q3 operates in class C. When the input power is low, transistor Q2 primarily amplifies the input signal. When the input power is high, transistor Q3 amplifies the peaks of the input signal in addition to transistor Q2. This allows transistors Q2 and Q3 to amplify the input signal. When the input power is low and transistor Q3 is not operating, the impedance seen from transistor Q2 to combiner 67 is twice the load R at output terminal Tout (e.g., 2 × 50 Ω). When the input power is high and transistor Q3 is operating, the impedance seen from transistor Q2 to combiner 67 and the impedance seen from transistor Q3 to combiner 67 are both load R (e.g., 50 Ω). Matching circuits 62 and 64 are adjusted so that transistor Q2 operates optimally at saturated output with a load of 2R when transistor Q3 is not operating. Conversely, they are adjusted so that transistor Q2 operates optimally at saturated output with a load of R when transistor Q3 is operating. The matching circuits 63 and 65 are adjusted so that when the transistor Q3 is not operating, the impedance seen from the combiner 67 toward the transistor Q3 is open, and when the transistor Q3 is operating, the matching circuits 63 and 65 are adjusted so that the transistor Q3 operates optimally at saturated output with the load R.

[0035] At least one of the transistors Q1 to Q3 can be provided on the chip 20a or 20b provided with the pillar 16a or 16b, and at least one of the matching circuits 60 to 65 can be provided on the chip 22a not provided with a pillar. The input terminal Tin, the output terminal Tout, and the bias terminals Tg1 to Tg3 and Td1 to Td3 can be the terminal 10a.

[0036] Comparative Example 1 is an example in which the connection between chips 20a and 20b and metal layer 18 is achieved using through electrodes 14c, rather than pillars 16a and 16b. When through holes 15c are formed using laser light 13c as shown in FIG. 9A, the width Wb3 (see FIG. 4) of through electrodes 14c is set smaller than the width Wa1 (see FIG. 5) of electrodes 21a and 21b of chips 20a and 20b. For example, if the width Wa1 is 100 μm, the width Wb3 will be set to 80 μm, taking into account margins. It is difficult to achieve a width Wb3 of 100 μm or less using laser light.

[0037] Even if the width Wb3 of the through electrode 14c can be set to 80 μm, there is still a problem with alignment accuracy. FIG. 12 is a plan view of the vicinity of the chip 20a in Comparative Example 1. As shown in FIG. 12, a target mounting position 40, which is the target position for mounting the chip 20a on the metal base 10, is indicated by a dashed line. The alignment accuracy for mounting the chip 20a on the metal base 10 is 15 to 25 μm. Therefore, the mounting position of the chip 20a may deviate from the target mounting position 40. This causes the through electrode 14c to extend beyond the electrodes 21a and 21b. It is possible to increase the width Wa1 of the electrodes 21a and 21b. However, if the cost per unit area of ​​the chips 20a and 20b is high (for example, GaN HEMTs have a high cost per unit area), increasing the width Wa1 will increase costs.

[0038] FIG. 13 is a plan view of the chip 20a and its vicinity in Example 1. As shown in FIG. 13, in Example 1, pillars 16a are provided on the chip 20a. Because the pillars 16a are formed using a semiconductor manufacturing process, the alignment accuracy between the pillars 16a and the electrodes 21a and 21b is 10 μm or less, and the pillars 16a rarely deviate from the electrodes 21a and 21b. Therefore, even if the mounting position of the chip 20a deviates from the target mounting position 40, the pillars 16a do not deviate from the electrodes 21a and 21b. If the wirings 18a and 18b are formed large, the pillars 16a do not deviate from the wirings 18a and 18b. Therefore, the electrodes 21a and 21b of the semiconductor chip 20a do not need to be large, which reduces the cost of the semiconductor chip 20a.

[0039] According to Example 1, as shown in FIG. 7B, a chip 20a (first chip) having pillars 16a (first pillars) on its upper surface is mounted on a metal base 10. As shown in FIG. 8A, an insulator layer 12 is formed on the metal base 10 to cover the semiconductor chip 20a. As shown in FIG. 8B, the upper surfaces of the pillars 16a are exposed from the insulator layer 12. Wiring 18a and 18b (first wiring) that connect to the pillars 16a and transmit high-frequency signals are formed on the insulator layer 12. As a result, compared to Comparative Example 1, as shown in FIG. 13, even if the mounting position of the semiconductor chip 20a deviates from the target mounting position 40, the pillars 16a are prevented from coming off the electrodes 21a and 21b. Therefore, the chip 20a does not need to be enlarged, thereby reducing the manufacturing cost of the high-frequency device. While an example in which the chip 20a is a semiconductor chip has been described, the chip 20a may be a non-semiconductor chip as long as the cost of providing the pillars 16a is less than the cost of enlarging the chip 20a.

[0040] As shown in FIG. 7B, a chip 22a (second chip) is mounted on a metal base 10. As shown in FIG. 8A, in the step of forming an insulator layer 12, an insulator layer 12 is formed to cover the chips 20a and 22a. As shown in FIG. 9A, a through hole 15c (first through hole) is formed in the insulator layer 12, reaching the upper surface of the chip 22a. As shown in FIG. 9B, a through electrode 14c (first through electrode) connected to the upper surface of the chip 22a is formed in the through hole 15c. As shown in FIG. 10A, wiring 18c and 18d (second wiring) connected to the through electrode 14c are formed on the insulator layer 12. If the cost per unit area of ​​the chip 22a is low, the manufacturing cost may be reduced by enlarging the electrodes 23a and 23b rather than providing pillars. Furthermore, if the areas of the electrodes 23a and 23b are large to begin with, forming pillars on the chip 22a increases the manufacturing cost of the chip 22a. In these cases, it is preferable to provide the through electrode 14c rather than providing pillars on the chip 22a.

[0041] 3 and 4, the chip 22a is a passive element including a dielectric substrate 30 and electrodes 23a and 23b formed on the upper surface of the dielectric substrate 30. In this case, the areas of the electrodes 23a and 23b are large to begin with. Furthermore, passive elements have lower manufacturing costs per unit area than semiconductor chips. Therefore, it is preferable to provide the chip 22a with through electrodes 14c rather than pillars.

[0042] 5 and 6, the chip 20a includes a transistor Q1. The chip 20a on which the transistor Q1 is formed has a high manufacturing cost per unit area, so the areas of the electrodes 21a and 21b are small. Therefore, it is preferable to provide the pillars 16a on the chip 20a.

[0043] 2, the passive elements provided on chip 22a are at least part of a matching circuit connected to transistor Q1 provided on chip 20a, thereby reducing the cost of a high-frequency device including transistor Q1 and a matching circuit.

[0044] As shown in FIGS. 3 to 6, chip 20a has electrodes 21a and 21b (first electrodes) to which pillars 16a are joined. Chip 22a has electrodes 23a and 23b (second electrodes) to which through-electrodes 14c are joined. Width Wb1 of electrodes 23a and 23b is larger than width Wa1 of electrodes 21a and 21b. Since the minimum width Wa1 of electrodes 21a and 21b can be made small, the manufacturing cost of chip 20a can be reduced. Since pillars are not provided in chip 22a in which the minimum width Wb1 of electrodes 23a and 23b is large, the manufacturing cost of chip 22a can be reduced.

[0045] 9A, in the step of forming the through holes 15c, the insulator layer 12 is irradiated with laser light 13c to form the through holes 15c. When the through holes 15c are formed using the laser light 13c, the through holes 15c become larger. Therefore, it is preferable to provide the pillars 16a on the chip 20a having large electrodes 21a and 21b.

[0046] As shown in FIG. 7B, a chip 20b (third chip) having pillars 16b (second pillars) on its upper surface is mounted on a metal base 10. As shown in FIG. 8A, in the step of forming an insulator layer 12, an insulator layer 12 is formed to cover the chips 20a and 20b. As shown in FIG. 8B, the insulator layer 12 covering the pillars 16a and 16b is polished or ground to expose the upper surfaces of the pillars 16a and 16b from the upper surface of the insulator layer 12. As shown in FIG. 10A, wirings 18e and 18f (third wirings) connecting to the pillars 16b are formed on the insulator layer 12. This allows the metal layer 18 to contact the pillars 16a and 16b as shown in FIG. 10A, even if the heights (positions in the Z direction) of the upper surfaces of the pillars 16a and 16b are different as shown in FIG. 7B. As an example in which the heights of the upper surfaces of the pillars 16a and 16b are different, an example in which the thicknesses Ta and Tb of the chips 20a and 20b are different has been described. Due to differences in the manufacturing process or manufacturing errors, the heights of the pillars 16a and 16b may differ.

[0047] As shown in Fig. 9A, a through hole 15a (second through hole) reaching the upper surface of the metal base 10 is formed in the insulator layer 12. As shown in Fig. 9B, a through electrode 14a (second through electrode) connected to the upper surface of the metal base 10 is formed in the through hole 15a. As shown in Fig. 10A, a wiring 18g (fourth wiring) connecting to the through electrode 14a is formed on the insulator layer 12. This allows a wiring connected to the metal base 10 and supplied with a ground potential to be provided on the insulator layer 12.

[0048] 10B, electronic components 24 are mounted on metal layer 18 provided on insulator layer 12. This allows electronic components 24 to be mounted without increasing the size of the high-frequency device.

[0049] [Modification 1 of Example 1] 14A to 15B are cross-sectional views showing a method for manufacturing a high-frequency device according to Modification 1 of Example 1. As shown in FIG. 14A, the upper surface of the insulator layer 12 is not polished as in FIG. 8B of Example 1. 、 When forming the through holes 15a to 15c and 15e, the through hole 15d that exposes the top surfaces of the pillars 16a and 16b is formed using the laser beam 13d. The through hole 15d does not reach the top surfaces of the chips 20a and 20b.

[0050] 14B, when the through electrodes are formed in the through holes, through electrodes 14d connected to the pillars 16a and 16b are formed, which do not reach the top surfaces of the chips 20a and 20b.

[0051] 15A, when metal layer 18 is formed, a portion of metal layer 18 is formed so as to be connected to through-electrode 14d, thereby forming wirings 18a, 18b, 18e, and 18f that are connected to chips 20a and 20b via through-electrode 14d and pillars 16a and 16b.

[0052] 15B, the high-frequency device according to Modification 1 of Example 1 can be manufactured by mounting electronic components 24 and forming insulating layer 26. The other steps are the same as those in Example 1, and therefore the description thereof will be omitted.

[0053] As in Modification 1 of Example 1, the step of exposing the upper surfaces of pillars 16a and 16b from insulator layer 12 may be performed by exposing the upper surfaces of pillars 16a and 16b from insulator layer 12 via through-holes 15d, as shown in FIG. 14A . The step of forming wiring (metal layer 18) that connects pillars 16a and 16b on insulator layer 12 may be performed by connecting pillars 16a and 16b to metal layer 18 via through-electrodes 14d. Even in Modification 1 of Example 1, if the width of through-hole 15d is made sufficiently large, pillars 16a and 16b can be electrically connected to metal layer 18 even if the mounting positions of chips 20a and 20b are deviated from the target mounting positions.

[0054] [Modification 2 of Example 1] 16A and 16B are cross-sectional views showing a manufacturing method of a high-frequency device according to Modification 2 of Example 1. As shown in Fig. 16A, terminals 10a and through electrodes 14b as shown in Fig. 9B of Example 1 are not provided. As shown in Fig. 16B, metal layer 18 is formed, electronic components 24 are mounted, and insulator layer 26 is formed.

[0055] As shown in FIG. 17A, a through electrode 29 is formed, penetrating the insulator layer 26 and connecting to the metal layer 18. The through electrode 29 is formed by forming a through hole that penetrates the insulator layer 26 and reaches the upper surface of the metal layer 18, similar to the formation of the through electrode 14b in Example 1, and then forming the through electrode 29 in the through hole. As shown in FIG. 17B, a metal layer 28 is formed on the insulator layer 26. A shield layer 28a and a terminal 28b are formed by the metal layer 28. This allows the manufacture of a high-frequency device according to Modification 2 of Example 1. The other steps are the same as those in Example 1, and therefore a description thereof will be omitted.

[0056] As in the second modification of the first embodiment, the terminal 28b may be provided on the upper surface of the insulating layer 26. Also, a shielding layer 28a may be provided on the upper surface of the insulating layer 26. By supplying a ground potential to the metal base 10 and the shielding layer 28a, the upper and lower surfaces of the high-frequency device can be shielded.

[0057] In the first embodiment and its modified examples, an amplifier device has been described as an example of a high-frequency device, but the high-frequency device may be something other than an amplifier device. Although a Doherty amplifier has been described as an example of an amplifier device, an amplifier device other than a Doherty amplifier may also be used. The high-frequency device may include one or more passive elements, and may include one or more semiconductor chips.

[0058] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the meaning described above, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0059] 10 Metal Base 10a terminal 11 Lead frame 12, 26 Insulator layer 13a~13e Laser light 14a Through electrode (2nd through electrode) 14b, 14e, 29 Through electrode 14c Through electrode (1st through electrode) 15a Through hole (2nd through hole) 15b, 15d, 15e through holes 15c Through hole (1st through hole) 16a Pillar (1st pillar) 16b Pillar (Second Pillar) 18, 28, 32, 34, 38, 39 metal layer 18a, 18b wiring (first wiring) 18c, 18d wiring (second wiring) 18e, 18f wiring (third wiring) 18g wiring (4th wiring) 18h wiring 18i track 20a Chip (1st Chip) 20b Chip (3rd Chip) 20c laminate 21a, 21b electrode (1st electrode) 23a, 23b electrode (second electrode) 22a Chip (2nd Chip) 24 Electronic Components 25 electrodes 30 Dielectric substrate 35 Bonding material 36 PCB 37 Semiconductor layer 40 Target loading position 61~65 Matching circuit 66 Distributor 67 Synthesizer 68, 69 Phase shifter 100 High Frequency Device 102 Amplification equipment

Claims

1. Mounting a first chip having a first pillar on an upper surface thereof on a metal base; forming an insulating layer on the metal base to cover the first chip; exposing a top surface of the first pillar from the insulator layer; forming a first wiring on the insulator layer, the first wiring being connected to the first pillar and transmitting a high-frequency signal; Mounting a second chip on the metal base; forming a first through hole in the insulator layer that reaches the top surface of the second chip; forming a first through electrode connected to an upper surface of the second chip in the first through hole; forming a second wiring on the insulator layer, the second wiring being connected to the first through electrode; Including, The method for manufacturing a high frequency device, wherein the step of forming the insulator layer includes the step of forming the insulator layer to cover the first chip and the second chip.

2. 2. The method for manufacturing a high-frequency device according to claim 1, wherein the second chip is a passive element including a dielectric substrate and an electrode provided on an upper surface of the dielectric substrate.

3. The method for manufacturing a high frequency device according to claim 2 , wherein the first chip includes a transistor.

4. The method for manufacturing a high-frequency device according to claim 3 , wherein the passive element is at least a part of a matching circuit connected to the transistor.

5. the first chip includes a first electrode to which the first pillar is joined; the second chip includes a second electrode to which the first through-electrode is joined; The method for manufacturing a high-frequency device according to claim 1 , wherein the width of the second electrode is larger than the width of the first electrode.

6. The method for manufacturing a high-frequency device according to claim 1 , wherein the step of forming the first through holes includes the step of forming the first through holes by irradiating the insulating layer with laser light.

7. Mounting a third chip having second pillars on an upper surface thereof on the metal base; forming a third wiring on the insulator layer that is connected to the second pillar; Including, the step of forming the insulator layer includes the step of forming the insulator layer to cover the first chip and the third chip; 7. The method for manufacturing a high-frequency device according to claim 1, wherein the step of exposing the top surface of the first pillar from the insulator layer includes a step of polishing or grinding the insulator layer covering the first pillar and the second pillar to expose the top surfaces of the first pillar and the second pillar from the top surface of the insulator layer.

8. forming a second through hole in the insulator layer that reaches the upper surface of the metal base; forming a second through electrode connected to an upper surface of the metal base in the second through hole; forming a fourth wiring on the insulator layer, the fourth wiring being connected to the second through electrode; The method for manufacturing a high-frequency device according to claim 1 , further comprising:

9. The method for manufacturing a high-frequency device according to claim 1 , further comprising the step of mounting an electronic component on a metal layer provided on the insulating layer.

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