Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of reducing a capacity and a method for manufacturing the semiconductor device.SOLUTION: A semiconductor device comprises a semiconductor layer in which a trench is formed, a buried electrode provided inside the trench, an upper electrode provided above the buried electrode inside the trench, an insulation film provided inside the trench, a first electrode provided on an upper surface of the semiconductor layer, and a second electrode provided on a lower surface of the semiconductor layer. The insulation film includes a first portion between the buried electrode and a sidewall of the trench, a second portion between the upper electrode and the sidewall of the trench, and a third portion between the buried electrode and the upper electrode. A lower surface of the upper electrode has a recess in the central part.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] In the semiconductor device manufacturing method of Patent Document 1, a first insulating film covering the inner surface of a trench formed in a semiconductor layer and a second insulating film stacked on the first insulating film are formed. Next, a first control electrode is formed in the lower part of the trench, facing the semiconductor layer via the first and second insulating films. Next, a third insulating film is formed on the first control electrode. Next, the first and second insulating films formed on the upper wall surfaces of the trench are removed, and a fourth insulating film is formed. A second control electrode is formed in the upper part of the trench, facing the semiconductor layer via the fourth insulating film and facing the first control electrode via the third insulating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-175596 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device of Patent Document 1, part of the insulating film in the trench acts as an insulating film between the gate and collector. However, increasing the thickness of the insulating film increases the threshold voltage. For this reason, it is not possible to increase the thickness of the insulating film, and there is a risk that the capacitance between the gate and collector cannot be reduced.

[0005] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device and a method for manufacturing the semiconductor device that can reduce capacitance. [Means for solving the problem]

[0006] A semiconductor device according to a first disclosure includes a semiconductor layer in which a trench is formed, a buried electrode provided inside the trench, an upper electrode provided inside the trench above the buried electrode, an insulating film provided inside the trench, a first electrode provided on an upper surface of the semiconductor layer, and a second electrode provided on a lower surface of the semiconductor layer, wherein the insulating film has a first portion between the buried electrode and a sidewall of the trench, a second portion between the upper electrode and the sidewall of the trench, and a third portion between the buried electrode and the upper electrode, and the lower surface of the upper electrode has a recessed center, and the third portion is thicker at the center of the trench than at the sidewall of the trench. The second portion of the insulating film is thicker toward the bottom. stomach. The semiconductor device according to the third disclosure comprises a semiconductor layer in which a trench is formed, a buried electrode provided inside the trench, an upper electrode provided inside the trench above the buried electrode, an insulating film provided inside the trench, a first electrode provided on the upper surface of the semiconductor layer, and a second electrode provided on the lower surface of the semiconductor layer, wherein the insulating film has a first portion between the buried electrode and a sidewall of the trench, a second portion between the upper electrode and a sidewall of the trench, and a third portion between the buried electrode and the upper electrode, the lower surface of the upper electrode being recessed in the center, the third portion being thicker at the center of the trench than at the sidewall of the trench, and the upper electrode having a portion whose side surface is sloping toward the inside of the trench. a first insulating film provided inside the trench; a first electrode provided on an upper surface of the semiconductor layer; and a second electrode provided on a lower surface of the semiconductor layer, wherein the insulating film has a first portion between the buried electrode and a sidewall of the trench, a second portion between the upper electrode and a sidewall of the trench, and a third portion between the buried electrode and the upper electrode, wherein the lower surface of the upper electrode has a recessed center, and the third portion is thicker at the center of the trench than at the sidewall of the trench, and the semiconductor layer has a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type different from the first conductivity type provided on the first semiconductor layer, and wherein the second portion of the insulating film is thicker adjacent to the first semiconductor layer than to the second semiconductor layer.

[0007] A method for manufacturing a semiconductor device according to a second disclosure includes forming a trench in a semiconductor layer, forming a buried electrode and a first oxide film inside the trench that separates the buried electrode from a sidewall of the trench, removing a portion of the first oxide film so that a portion of the first oxide film above the buried electrode is tapered, forming a second oxide film so as to cover an upper surface of the buried electrode, the sidewall of the trench, and the tapered portion, and forming an upper electrode on the second oxide film inside the trench. [Effects of the Invention]

[0008] In the semiconductor device according to the first disclosure, the lower surface of the upper electrode has a recessed central portion, which allows the third portion of the insulating film to be formed thicker at the central portion of the upper electrode, thereby reducing the gate-emitter capacitance. Semiconductor device according to the second disclosure Manufacturing method In this method, a second oxide film is formed to cover the tapered portion of the first oxide film, and then a top electrode is formed on top of the second oxide film. This allows the portion of the second oxide film between the top electrode and the trench sidewall to be made thicker as it descends. This reduces the gate-collector capacitance while suppressing an increase in threshold voltage. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 3] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 16] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 17] FIG. 11 is an enlarged cross-sectional view of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] The semiconductor device and the method for manufacturing the semiconductor device according to each embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and the repeated description may be omitted.

[0011] Embodiment 1 1 is a cross-sectional view of a semiconductor device 100 according to a first embodiment. The semiconductor device 100 is, for example, an IGBT (Insulated Gate Bipolar Transistor) having a trench gate structure. In the semiconductor device 100, an n-type carrier accumulation layer 12 is formed on an n-type drift layer 11. A p-type base layer 13 and an n-type emitter layer 14 are formed in this order on the n-type carrier accumulation layer 12. An n-type buffer layer 15 and a p-type collector layer 16 are formed below the n-type drift layer 11.

[0012] The n-type drift layer 11, n-type carrier accumulation layer 12, p-type base layer 13, n-type emitter layer 14, n-type buffer layer 15, and p-type collector layer 16 correspond to semiconductor layers. Furthermore, n-type corresponds to a first conductivity type, and p-type corresponds to a second conductivity type different from the first conductivity type. The conductivity types of each layer may be reversed. The n-type drift layer 11 and n-type carrier accumulation layer 12 correspond to a first semiconductor layer, and the p-type base layer 13 corresponds to a second semiconductor layer.

[0013] A trench 20 is formed in the semiconductor layer. Two electrodes, a buried electrode 22 and an upper electrode 24, are provided inside the trench 20. The upper electrode 24 is provided above the buried electrode 22. An insulating film 21 is also provided inside the trench 20. The insulating film 21 has a first portion 21a between the buried electrode 22 and the sidewall of the trench 20, a second portion 21b between the upper electrode 24 and the sidewall of the trench 20, and a third portion 21c between the buried electrode 22 and the upper electrode 24. In other words, the first portion 21a separates the buried electrode 22 from the semiconductor layer. The second portion 21b separates the upper electrode 24 from the semiconductor layer. The third portion 21c separates the buried electrode 22 from the upper electrode 24.

[0014] The upper electrode 24 has a portion at its lower end whose side surface inclines toward the inside of the trench 20. As a result, the second portion 21b of the insulating film 21 is formed thicker toward the bottom. Further, the lower surface of the upper electrode 24 is recessed at the central portion.

[0015] On the upper surface of the semiconductor layer, a barrier metal 40 and an emitter electrode 41 which is a main electrode are provided. The interlayer insulating film 30 separates the upper electrode 2 4 and the emitter electrode 41. On the lower surface of the semiconductor layer, a collector electrode 42 which is a main electrode is provided. The emitter electrode 41 corresponds to the first electrode, and the collector electrode 42 corresponds to the second electrode.

[0016] The upper electrode 24 is connected to the gate potential, and the embedded electrode 22 is connected to the emitter potential. Thereby, the upper electrode 24 is shielded, and the gate-collector capacitance can be reduced. Further, when the thickness Ta of the second portion 21b of the insulating film 21 is increased, the gate-collector capacitance can be made even smaller. However, increasing the thickness of the insulating film 21 causes an increase in the threshold voltage. The threshold voltage is a basic characteristic of the semiconductor device 100. When the threshold voltage increases, other characteristics such as the saturation current may deteriorate. Therefore, it is not usually permitted to increase the thickness of the second portion 21b.

[0017] In contrast, in the present embodiment, the second portion 21b of the insulating film 21 is formed thicker toward the bottom. That is, Ta < Tb. Thereby, it is possible to reduce the gate-collector capacitance while suppressing an increase in the threshold voltage. In particular, the capacitance between the upper electrode 24 and the n-type carrier accumulation layer 12 is likely to contribute to the gate-collector capacitance. In the present embodiment, for example, in the second portion 21b of the insulating film 21, the portion adjacent to the n-type carrier accumulation layer 12 is thicker than the portion adjacent to the p-type base layer 13. Thereby, it is possible to effectively reduce the gate-collector capacitance while suppressing an increase in the threshold voltage.

[0018] Furthermore, the gate-emitter capacitance can be reduced by making the third portion 21c of the insulating film 21 thick. However, if the third portion 21c is formed thick, the lower end of the upper electrode 24 may be located above the bottom of the p-type base layer 13. In this case, if the insulating film 21 is too thick, a channel may not be formed, and the semiconductor device 100 may not operate.

[0019] In contrast, in this embodiment, the lower surface of the upper electrode 24 is recessed in the center. That is, the thickness Db of the third portion 21c of the insulating film 21 at the center of the trench 20 is thicker than the thickness Da on the semiconductor layer side. This configuration ensures that the third portion 21c is thick while suppressing the formation of a channel. Therefore, the gate-emitter capacitance can be reduced.

[0020] Next, a method for manufacturing the semiconductor device 100 will be described. FIGS. 2 to 15 are diagrams showing a method for manufacturing the semiconductor device 100 according to the first embodiment. First, as shown in FIG. 2, a semiconductor substrate including an n-type drift layer 11 is prepared. The semiconductor substrate is, for example, a so-called FZ wafer fabricated by the FZ (Floating Zone) method. The semiconductor substrate may also be a so-called MCZ wafer fabricated by the MCZ (Magnetic applied CZochralki) method. The semiconductor substrate may also be an n-type wafer containing n-type impurities.

[0021] The concentration of n-type impurities contained in the semiconductor substrate is appropriately selected depending on the breakdown voltage of the semiconductor device 100 to be fabricated. For example, in a semiconductor device 100 with a breakdown voltage of 1200 V, the concentration of n-type impurities is adjusted so that the resistivity of the n-type drift layer 11 is approximately 40 to 120 Ω·cm. As shown in FIG. 2 , in the process of preparing the semiconductor substrate, the entire semiconductor substrate becomes the n-type drift layer 11. P-type or n-type impurity ions are implanted from the first or second main surface side of such a semiconductor substrate, and then the impurity ions are diffused into the semiconductor substrate by heat treatment or the like. By forming the p-type or n-type semiconductor layer in this manner, the semiconductor device 100 is fabricated.

[0022] Next, as shown in Fig. 3, n-type impurities such as phosphorus (P) are implanted from the first main surface side of the semiconductor substrate to form an n-type carrier accumulation layer 12. Furthermore, p-type impurities such as boron (B) are implanted from the first main surface side of the semiconductor substrate to form a p-type base layer 13. The n-type carrier accumulation layer 12 and the p-type base layer 13 are formed by implanting impurity ions into the semiconductor substrate and then diffusing the impurity ions by heat treatment. Since the n-type impurities and p-type impurities are ion-implanted after a mask process is performed on the first main surface of the semiconductor substrate, The n-type carrier accumulation layer 12 and the p-type base layer 13 are The mask is selectively formed on the first main surface of the semiconductor substrate. In the mask process, a resist is applied to the semiconductor substrate, and openings are formed in predetermined areas of the resist using photolithography. Ion implantation or etching is performed on the predetermined areas of the semiconductor substrate through these openings.

[0023] Next, as shown in FIG. 4, n-type impurities are selectively implanted into the first main surface side of the p-type base layer 13 using a mask process to form an n-type emitter layer 14. The implanted n-type impurities are, for example, arsenic (As) or phosphorus (P). Furthermore, a p-type contact layer can be formed by selectively implanting p-type impurities into the first main surface side of the p-type base layer 13 using a mask process. The p-type contact layer is omitted in FIG. 4. The implanted p-type impurities are, for example, boron (B) or aluminum (Al).

[0024] Next, as shown in FIG. 5, trenches 20 are formed in the semiconductor layer. The trenches 20 penetrate from the first main surface side of the semiconductor substrate through the n-type emitter layer 14, the p-type base layer 13, and the n-type carrier accumulation layer 12 to reach the n-type drift layer 11. For example, the trenches 20 are formed by depositing an oxide film such as SiO2 on the semiconductor substrate and then forming openings in the oxide film by masking in the areas where the trenches 20 are to be formed. Next, the semiconductor substrate is etched using the oxide film with the openings as a mask to form the trenches 20. The pitch and planar pattern of the trenches 20 can be changed as appropriate by changing the mask pattern used in the masking.

[0025] Next, as shown in FIG. 6, the semiconductor substrate is heated in an oxygen-containing atmosphere to form a first oxide film 23a on the inner walls of the trench 20 and on the first main surface of the semiconductor substrate. Next, as shown in FIG. 7, polycrystalline silicon doped with n-type or p-type impurities is deposited in the trench 20, with the first oxide film 23a formed on the inner walls, by CVD (chemical vapor deposition) or the like. This forms a buried electrode 22 in the lower part of the trench 20. Instead of polycrystalline silicon, amorphous silicon doped with n-type or p-type impurities may be used as the buried electrode 22. The use of amorphous silicon reduces the unevenness of the upper surface of the buried electrode 22. As a result, the buried electrode 22 and the first oxide film 23a separating the buried electrode 22 from the sidewall of the trench 20 are formed inside the trench 20.

[0026] 8, the first oxide film 23a on the upper portion of the trench 20 and on the first main surface of the semiconductor substrate is removed by wet etching. This forms a first portion 21a of the insulating film 21 that separates the buried electrode 22 from the semiconductor layer. The insulating film 21 is characterized in that the portion above the buried electrode 22 remains tapered. That is, in this step, a portion of the first oxide film 23a is removed so that the portion above the buried electrode 22 of the first oxide film 23a becomes tapered.

[0027] 9, a second oxide film 23b is formed to cover the first main surface of the semiconductor substrate, the upper surfaces of the buried electrodes 22, the sidewalls of the trenches 20, and the tapered portion of the first oxide film 23a. The second oxide film 23b is formed, for example, by heating the semiconductor substrate in an atmosphere containing oxygen. The second oxide film 23b is further formed on the tapered portion of the first oxide film 23a, thereby forming a portion in the second portion 21b of the insulating film 21 that becomes thicker downward. In this way, the portion of the second oxide film 23b between the upper electrode 24 and the sidewall of the trench 20 becomes thicker downward.

[0028] Furthermore, since the buried electrode 22 is made of polycrystalline silicon doped with impurities, it is oxidized at an accelerated rate during the formation of the second oxide film 23b. Therefore, the second oxide film 23b formed on the upper surface of the buried electrode 22 is thicker than the second oxide film 23b formed on the sidewall of the trench 20. In other words, the third portion 21c of the insulating film 21 is formed thicker than the second portion 21b.

[0029] Next, as shown in FIG. 10, polycrystalline silicon doped with n-type or p-type impurities is deposited in the trench 20 by CVD (chemical vapor deposition) or the like. This forms an upper electrode 24 on the second oxide film 23b inside the trench 20. Instead of polycrystalline silicon, amorphous silicon doped with n-type or p-type impurities may also be used as the upper electrode 24. However, it is believed that the effect on characteristics of the upper electrode 24 due to unevenness on the top surface is small. For this reason, using polycrystalline silicon with a high deposition rate as the upper electrode 24 is more efficient in terms of production.

[0030] Next, as shown in FIG. 11, an interlayer insulating film 30 is deposited on the first main surface of the semiconductor substrate. Next, the second oxide film 23b formed on the first main surface of the semiconductor substrate is removed. The interlayer insulating film 30 is made of, for example, SiO2. Next, contact holes are formed in the interlayer insulating film 30 by mask processing. The contact holes are formed on the n-type emitter layer 14 and a p-type contact layer (not shown).

[0031] 12, a barrier metal 40 is formed on the first main surface of the semiconductor substrate and the interlayer insulating film 30. Furthermore, an emitter electrode 41 is formed on the barrier metal 40. The barrier metal 40 is formed by depositing, for example, titanium nitride by PVD (physical vapor deposition) or CVD. The emitter electrode 41 is formed by depositing an aluminum silicon alloy (Al-Si alloy) on the barrier metal 40 by PVD such as sputtering or evaporation.

[0032] Furthermore, a nickel alloy (Ni alloy) may be further formed on the aluminum silicon alloy by electroless plating or electrolytic plating to form the emitter electrode 41. Forming the emitter electrode 41 by plating makes it possible to easily form a thick metal film as the emitter electrode 41. This increases the heat capacity of the emitter electrode 41, thereby improving its heat resistance. Note that when forming the emitter electrode 41 made of an aluminum silicon alloy by PVD and then further forming a nickel alloy by plating, the plating to form the nickel alloy may be performed after processing the second main surface of the semiconductor substrate.

[0033] Next, the second main surface side of the semiconductor substrate is ground to thin the semiconductor substrate to a predetermined designed thickness, as shown in Fig. 13. The thickness of the semiconductor substrate after grinding is, for example, 60 µm to 200 µm.

[0034] Next, as shown in FIG. 14 , n-type impurities are implanted from the second main surface side of the semiconductor substrate to form an n-type buffer layer 15. Furthermore, p-type impurities are implanted from the second main surface side of the semiconductor substrate to form a p-type collector layer 16. The n-type buffer layer 15 is formed by implanting, for example, phosphorus (P) ions or protons (H+). The n-type buffer layer 15 may also be formed by implanting both protons and phosphorus. Protons can be implanted deep into the second main surface of the semiconductor substrate with low acceleration energy. Furthermore, the depth to which the protons are implanted can be easily changed by changing the acceleration energy. Therefore, by implanting protons multiple times while changing the acceleration energy, an n-type buffer layer 15 that is wider in the thickness direction of the semiconductor substrate than one formed with phosphorus can be formed.

[0035] Furthermore, phosphorus can have a higher activation rate as an n-type impurity than protons. By forming the n-type buffer layer 15 with phosphorus, punch-through of the depletion layer can be reliably suppressed even in a thinned semiconductor substrate. To further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 15 by implanting both protons and phosphorus. In this case, the protons are implanted deeper from the second main surface than the phosphorus.

[0036] The p-type collector layer 16 is formed by implanting, for example, boron (B). After ion implantation from the second main surface side of the semiconductor substrate, a laser is irradiated onto the second main surface for laser annealing. This activates the implanted boron, forming the p-type collector layer 16. At this time, phosphorus in the n-type buffer layer 15, which was implanted shallowly from the second main surface of the semiconductor substrate, is also activated at the same time. On the other hand, protons are activated at a relatively low annealing temperature of 350°C to 500°C. Therefore, after the proton implantation, care must be taken to ensure that the entire semiconductor substrate does not exceed a temperature of 350°C to 500°C, except during the process for activating the protons. Laser annealing can raise the temperature only near the second main surface of the semiconductor substrate. Therefore, even after the proton implantation, it can be used to activate n-type or p-type impurities.

[0037] 15, a collector electrode 42 is formed on the second main surface of the semiconductor substrate. The collector electrode 42 is formed by depositing an aluminum silicon alloy (Al-Si alloy), titanium (Ti), or the like by PVD, such as sputtering or vapor deposition. The collector electrode 42 may also be formed by laminating multiple metals, such as an aluminum silicon alloy, titanium, nickel, or gold. Furthermore, the collector electrode 42 may also be formed by forming another metal film by electroless plating or electrolytic plating on the metal film formed by PVD.

[0038] The semiconductor device 100 is manufactured through the above-described process. A plurality of semiconductor devices 100 are fabricated in a matrix on a single n-type wafer. The wafer is cut into individual semiconductor devices 100 by laser dicing or blade dicing, thereby completing the semiconductor devices 100.

[0039] As a modification of this embodiment, if the second portion 21b of the insulating film 21 is formed thicker toward the bottom, the center of the bottom surface of the upper electrode 24 does not need to be recessed. In this case, too, the gate-collector capacitance can be reduced. Also, if the center of the bottom surface of the upper electrode 24 is recessed, the second portion 21b of the insulating film 21 does not need to be formed thicker toward the bottom. In this case, too, the gate-emitter capacitance can be reduced. Also, the material, shape, and manufacturing method of each layer are as described above. Tamo Not limited to.

[0040] The semiconductor layer may be formed of a wide bandgap semiconductor. The wide bandgap semiconductor may be silicon carbide, a gallium nitride-based material, or diamond. According to this embodiment, the gate-collector capacitance can be reduced while suppressing an increase in threshold voltage, thereby making it possible to effectively utilize the performance of the semiconductor device 100 formed of the wide bandgap semiconductor.

[0041] These modifications can be applied as appropriate to the semiconductor devices and semiconductor device manufacturing methods according to the following embodiments. Note that the semiconductor devices and semiconductor device manufacturing methods according to the following embodiments have many points in common with the first embodiment, so the following description will focus on the differences from the first embodiment.

[0042] Embodiment 2 FIG. 16 is a cross-sectional view of a semiconductor device 200 according to a second embodiment. In this embodiment, the structures of the insulating film 21, the buried electrode 222, and the upper electrode 224 are different from those of the first embodiment. The other structures are the same as those of the first embodiment. In this embodiment, the first portion 21a of the insulating film 21 is thicker than the second portion 21b. This reduces the thickness of the upper electrode 224, which has a large effect on the gate-collector capacitance. 2 This allows the thickness of the insulating film 21 between the n-type carrier accumulation layer 12 and the gate electrode 24 to be further increased, thereby further reducing the gate-collector capacitance.

[0043] Embodiment 3 17 is an enlarged cross-sectional view of a semiconductor device according to a third embodiment. In this embodiment, the unevenness of the upper surface of the buried electrode 22 is smaller than the unevenness of the upper surface of the upper electrode 24. This makes it possible to prevent the third portion 21c of the insulating film 21 from becoming locally thin. This makes it possible to prevent the gate-emitter capacitance from becoming locally large, thereby improving the effect of reducing the gate-emitter capacitance. By using amorphous silicon doped with n-type or p-type impurities for the buried electrode 22, it is possible to reduce the unevenness of the upper surface of the buried electrode 22.

[0044] The technical features described in each embodiment may be used in appropriate combination.

[0045] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) a semiconductor layer having a trench formed therein; a buried electrode provided inside the trench; an upper electrode provided inside the trench above the buried electrode; an insulating film provided inside the trench; a first electrode provided on an upper surface of the semiconductor layer; a second electrode provided on a lower surface of the semiconductor layer; Equipped with the insulating film has a first portion between the buried electrode and a sidewall of the trench, a second portion between the upper electrode and a sidewall of the trench, and a third portion between the buried electrode and the upper electrode; The semiconductor device is characterized in that the lower surface of the upper electrode has a recess in the center. (Appendix 2) 2. The semiconductor device according to claim 1, wherein the second portion of the insulating film is thicker downward. (Appendix 3) 3. The semiconductor device according to claim 1, wherein the upper electrode has a side surface that is inclined toward the inside of the trench. (Appendix 4) the semiconductor layer includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type different from the first conductivity type provided on the first semiconductor layer; The semiconductor device described in any one of appendices 1 to 3, characterized in that the second portion of the insulating film, the portion adjacent to the first semiconductor layer, is thicker than the portion adjacent to the second semiconductor layer. (Appendix 5) 5. The semiconductor device according to claim 1, wherein the third portion is thicker than the second portion. (Appendix 6) 6. The semiconductor device according to claim 1, wherein the first portion is thicker than the second portion. (Appendix 7) 7. The semiconductor device according to claim 1, wherein the unevenness of the upper surface of the buried electrode is smaller than the unevenness of the upper surface of the upper electrode. (Appendix 8) 8. The semiconductor device according to claim 1, wherein the buried electrode is made of amorphous silicon. (Appendix 9) 9. The semiconductor device according to claim 1, wherein the semiconductor layer is formed of a wide bandgap semiconductor. (Appendix 10) 10. The semiconductor device according to claim 9, wherein the wide band gap semiconductor is silicon carbide, a gallium nitride-based material, or diamond. (Appendix 11) forming a trench in the semiconductor layer; forming a buried electrode inside the trench and a first oxide film separating the buried electrode from a sidewall of the trench; removing a portion of the first oxide film so that a portion of the first oxide film above the buried electrode is tapered; forming a second oxide film so as to cover the upper surface of the buried electrode, the sidewall of the trench, and the tapered portion; A method for manufacturing a semiconductor device, comprising forming an upper electrode on the second oxide film inside the trench. (Appendix 12) 12. The method for manufacturing a semiconductor device according to claim 11, wherein the portion of the second oxide film between the upper electrode and the sidewall of the trench is thicker toward the bottom. [Explanation of symbols]

[0046] 11 n-type drift layer, 12 n-type carrier accumulation layer, 13 p-type base layer, 14 n-type emitter layer, 15 n-type buffer layer, 16 p-type collector layer, 20 trench, 21 insulating film, 21a first portion, 21b second portion, 21c third portion, 22 buried electrode, 23a first oxide film, 23b second oxide film, 24 upper electrode 、3 0 interlayer insulating film, 40 barrier metal, 41 emitter electrode, 42 collector electrode, 100, 200 semiconductor device, 222 buried electrode, 224 upper electrode

Claims

1. a semiconductor layer having a trench formed therein; a buried electrode provided inside the trench; an upper electrode provided inside the trench above the buried electrode; an insulating film provided inside the trench; a first electrode provided on an upper surface of the semiconductor layer; a second electrode provided on a lower surface of the semiconductor layer; Equipped with the insulating film has a first portion between the buried electrode and a sidewall of the trench, a second portion between the upper electrode and a sidewall of the trench, and a third portion between the buried electrode and the upper electrode; The lower surface of the upper electrode has a recessed center, the third portion is thicker at a center of the trench than at a sidewall of the trench; The semiconductor device is characterized in that the second portion of the insulating film is thicker in the downward direction.

2. A semiconductor layer having a trench formed therein; a buried electrode provided inside the trench; an upper electrode provided inside the trench above the buried electrode; an insulating film provided inside the trench; a first electrode provided on an upper surface of the semiconductor layer; a second electrode provided on a lower surface of the semiconductor layer; Equipped with the insulating film has a first portion between the buried electrode and a sidewall of the trench, a second portion between the upper electrode and a sidewall of the trench, and a third portion between the buried electrode and the upper electrode; The lower surface of the upper electrode has a recessed center, the third portion is thicker at a center of the trench than at a sidewall of the trench; The upper electrode has a side surface that is inclined toward the inside of the trench.

3. A semiconductor layer having a trench formed therein; a buried electrode provided inside the trench; an upper electrode provided inside the trench above the buried electrode; an insulating film provided inside the trench; a first electrode provided on an upper surface of the semiconductor layer; a second electrode provided on a lower surface of the semiconductor layer; Equipped with the insulating film has a first portion between the buried electrode and a sidewall of the trench, a second portion between the upper electrode and a sidewall of the trench, and a third portion between the buried electrode and the upper electrode; The lower surface of the upper electrode has a recessed center, the third portion is thicker at a center of the trench than at a sidewall of the trench; the semiconductor layer includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type different from the first conductivity type provided on the first semiconductor layer; The semiconductor device according to claim 1, wherein the second portion of the insulating film is thicker in a portion adjacent to the first semiconductor layer than in a portion adjacent to the second semiconductor layer.

4. 2. The semiconductor device according to claim 1, wherein the third portion is thicker than the second portion.

5. 2. The semiconductor device according to claim 1, wherein the first portion is thicker than the second portion.

6. 2. The semiconductor device according to claim 1, wherein the unevenness of the upper surface of said buried electrode is smaller than the unevenness of the upper surface of said upper electrode.

7. 2. The semiconductor device according to claim 1, wherein the buried electrode is made of amorphous silicon.

8. 2. The semiconductor device according to claim 1, wherein the semiconductor layer is made of a wide bandgap semiconductor.

9. 9. The semiconductor device according to claim 8, wherein the wide band gap semiconductor is silicon carbide, a gallium nitride-based material, or diamond.

10. forming a trench in the semiconductor layer; forming a buried electrode inside the trench and a first oxide film separating the buried electrode from a sidewall of the trench; removing a portion of the first oxide film so that a portion of the first oxide film above the buried electrode is tapered; forming a second oxide film so as to cover the upper surface of the buried electrode, the sidewall of the trench, and the tapered portion; a second oxide film formed on the second insulating film in the trench;

11. 11. The method of manufacturing a semiconductor device according to claim 10, wherein a portion of the second oxide film between the upper electrode and the sidewall of the trench is thicker toward the bottom.

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