Isolation transformer

Abstract

This insulating transformer comprises: an insulating layer; a transformer including a first coil and a second coil, the first coil being embedded in the insulating layer, having a first signal end and a first ground end, and being configured to be able to apply a low voltage to the first signal end, the second coil being embedded in the insulating layer apart from the first coil in the thickness direction, having a second signal end and a second ground end, and being configured to be able to apply a high voltage to the second signal end; and a capacitor disposed between the first coil and the second coil and including a first capacitor electrode and a second capacitor electrode, the first capacitor electrode being connected to the first ground end, the second capacitor electrode disposed between the first capacitor electrode and the second coil and connected to the second ground end.

Description

[Technical Field]

[0001] The present disclosure relates to an isolation transformer. [Background technology]

[0002] An isolated gate driver is known as a gate driver that applies a gate voltage to the gate of a switching element such as a transistor. For example, Patent Document 1 describes a semiconductor integrated circuit as an isolated gate driver that includes a transformer having a first coil on the primary side and a second coil on the secondary side. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-78169 Summary of the Invention [Problem to be solved by the invention]

[0004] However, there is room for improvement in the influence on the signal transmitted through the transformer. [Means for solving the problem]

[0005] An isolation transformer according to one embodiment of the present disclosure includes: an insulating layer; a transformer having: a first coil embedded in the insulating layer, having a first signal end and a first ground end, and configured so that a low voltage can be applied to the first signal end; and a second coil embedded at a distance from the first coil in a thickness direction of the insulating layer, having a second signal end and a second ground end, and configured so that a high voltage can be applied to the second signal end; and a capacitor having a first capacitor electrode disposed between the first coil and the second coil and connected to the first ground end, and a second capacitor electrode disposed between the first capacitor electrode and the second coil and connected to the second ground end.

[0006] A gate driver according to one embodiment of the present disclosure is a gate driver that applies a drive voltage signal to the gate of a switching element, and includes: a low-voltage circuit chip configured to operate when a first voltage is applied thereto; a high-voltage circuit chip configured to operate when a second voltage higher than the first voltage is applied thereto; and a transformer chip connected between the low-voltage circuit chip and the high-voltage circuit chip, wherein the transformer chip includes: an insulating layer; a transformer having: a first coil embedded in the insulating layer and having a first ground end; and a second coil embedded at a distance from the first coil in the thickness direction of the insulating layer and having a second ground end; and a capacitor arranged between the first coil and the second coil and having a first capacitor electrode connected to the first ground end; and a second capacitor electrode arranged between the first capacitor electrode and the second coil and connected to the second ground end.

[0007] An isolation module according to one embodiment of the present disclosure is used to isolate a low-voltage circuit and a high-voltage circuit included in a gate driver that applies a drive voltage signal to the gate of a switching element, and includes a transformer chip connected between the low-voltage circuit and the high-voltage circuit, wherein the transformer chip includes: an insulating layer; a transformer having a first coil embedded in the insulating layer and having a first ground end; and a second coil embedded at a distance from the first coil in the thickness direction of the insulating layer and having a second ground end; and a capacitor having a first capacitor electrode disposed between the first coil and the second coil and connected to the first ground end, and a second capacitor electrode disposed between the first capacitor electrode and the second coil and connected to the second ground end. [Effects of the Invention]

[0008] According to one aspect of the present disclosure, it is possible to provide an isolation transformer that can reduce the influence on a signal to be transmitted. [Brief explanation of the drawings]

[0009] [Figure 1]FIG. 1 is a schematic circuit diagram of a gate driver according to an embodiment. [Figure 2] FIG. 2 is a plan view showing the internal configuration of a gate driver according to an embodiment. [Figure 3] FIG. 3 is a perspective view of a transformer chip of a gate driver according to an embodiment. [Figure 4] FIG. 4 is a plan view of the transformer chip of FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view showing a first coil of the transformer chip of FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a second coil of the transformer chip of FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a first capacitor electrode of the transformer chip of FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a second capacitor electrode of the transformer chip of FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line 9-9 in FIG. 4, showing a state in which the transformer chip is mounted on the low-voltage die pad. [Figure 10] FIG. 10 is a partially enlarged view of the transformer chip of FIG. [Figure 11] FIG. 11 is a circuit diagram showing the operation of a gate driver of a comparative example. [Figure 12] FIG. 12 is a circuit diagram showing the operation of the gate driver of this embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a first capacitor electrode of a transformer chip according to a modified example. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a first capacitor electrode of a transformer chip according to a modified example. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a first capacitor electrode of a transformer chip according to a modified example. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a first coil, a second coil, a dummy pattern, a first capacitor electrode, and a second capacitor electrode of a transformer chip according to a modified example. [Figure 17]FIG. 17 is a schematic cross-sectional view showing a first coil, a second coil, a dummy pattern, a first capacitor electrode, and a second capacitor electrode of a transformer chip according to a modified example. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a first coil, a second coil, a dummy pattern, a first capacitor electrode, and a second capacitor electrode of a transformer chip according to a modified example. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a first coil, a second coil, a dummy pattern, a first capacitor electrode, and a second capacitor electrode of a transformer chip according to a modified example. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a first coil, a second coil, a dummy pattern, a first capacitor electrode, and a second capacitor electrode of a transformer chip according to a modified example. [Figure 21] FIG. 21 is a schematic cross-sectional view showing a first coil, a second coil, a dummy pattern, a first capacitor electrode, and a second capacitor electrode of a transformer chip according to a modified example. [Figure 22] FIG. 22 is a schematic cross-sectional view showing a first coil, a second coil, a dummy pattern, a first capacitor electrode, and a second capacitor electrode of a transformer chip according to a modified example. [Figure 23] FIG. 23 is a schematic cross-sectional view showing a first coil, a second coil, a dummy pattern, a first capacitor electrode, and a second capacitor electrode of a transformer chip according to a modified example. [Figure 24] FIG. 24 is a schematic cross-sectional view showing a first coil, a second coil, a dummy pattern, a first capacitor electrode, and a second capacitor electrode of a transformer chip according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment of a gate driver will be described with reference to the drawings. The embodiments described below exemplify configurations and methods for embodying the technical ideas, and do not limit the materials, shapes, structures, arrangements, dimensions, etc. of each component to those described below. The accompanying drawings may show components enlarged to facilitate understanding. The dimensional ratios of the components may differ from the actual ones or from those in other drawings. In addition, in cross-sectional views, hatching of some components may be omitted to facilitate understanding.

[0011] [Gate driver] A gate driver 10 according to one embodiment will be described with reference to FIGS. FIG. 1 shows a simplified example of the circuit configuration of a gate driver 10. The gate driver 10 applies a drive voltage signal to the gate of a switching element and is applied, for example, to an inverter device 500 mounted on an electric vehicle or a hybrid vehicle. The inverter device 500 includes a pair of switching elements 501 and 502 connected in series, a gate driver 10, and an ECU (Electronic Control Unit) 503 that controls the gate driver 10. The switching element 501 is, for example, a high-side switching element connected to a drive power supply, and the switching element 502 is a low-side switching element. Examples of the switching elements 501 and 502 include transistors such as SiMOSFETs (Si Metal-Oxide-Semiconductor Field-Effect Transistors), SiCMOSFETs, and IGBTs (Insulated Gate Bipolar Transistors). The gate driver 10 of this embodiment applies a drive voltage signal to the gate of the switching element 501. In the following description, it is assumed that SiCMOSFETs are used for the switching elements 501 and 502.

[0012] A gate driver 10 is provided for each of the switching elements 501 and 502, and individually drives the switching elements 501 and 502. In this embodiment, for convenience of explanation, the gate driver 10 that drives the switching element 501 will be described.

[0013] The gate driver 10 includes a low-voltage circuit 20 to which a first voltage V1 is applied, a high-voltage circuit 30 to which a second voltage V2 higher than the first voltage V1 is applied, and a transformer 40 provided between the low-voltage circuit 20 and the high-voltage circuit 30. In other words, the low-voltage circuit 20 and the high-voltage circuit 30 are connected via the transformer 40. The first voltage V1 and the second voltage V2 are DC voltages.

[0014] The gate driver 10 of this embodiment is configured so that, based on a control signal from the ECU 503, a signal is transmitted from the low-voltage circuit 20 via the transformer 40 to the high-voltage circuit 30, and a drive voltage signal is output from the high-voltage circuit 30.

[0015] The signal transmitted from the low-voltage circuit 20 to the high-voltage circuit 30, i.e., the signal output from the low-voltage circuit 20, is, for example, a signal for driving the switching element 501, and examples thereof include a set signal and a reset signal. The set signal is a signal that transmits the rising edge of a control signal from the ECU 503, and the reset signal is a signal that transmits the falling edge of a control signal from the ECU 503. The set signal and the reset signal can also be said to be signals for generating a drive voltage signal for the switching element 501. For this reason, the set signal and the reset signal correspond to the "first signal."

[0016] More specifically, the low-voltage circuit 20 is configured to operate when a first voltage V1 is applied. The low-voltage circuit 20 is electrically connected to the ECU 503 and generates a set signal and a reset signal based on a control signal input from the ECU 503. For example, the low-voltage circuit 20 generates a set signal in response to a rising edge of the control signal, and generates a reset signal in response to a falling edge of the control signal. The low-voltage circuit 20 then transmits the generated set signal and reset signal to the high-voltage circuit 30.

[0017] The high-voltage circuit 30 is a circuit configured to operate when a second voltage V2 is applied. The high-voltage circuit 30 is electrically connected to the gate of the switching element 501. The high-voltage circuit 30 generates a drive voltage signal for driving the switching element 501 based on the set signal and reset signal received from the low-voltage circuit 20, and applies the drive voltage signal to the gate of the switching element 501. In other words, it can be said that the high-voltage circuit 30 generates a drive voltage signal to be applied to the gate of the switching element 501 based on the first signal output from the low-voltage circuit 20. More specifically, the high-voltage circuit 30 generates a drive voltage signal that turns on the switching element 501 based on the set signal, and applies the drive voltage signal to the gate of the switching element 501. On the other hand, the high-voltage circuit 30 generates a drive voltage signal that turns off the switching element 501 based on the reset signal, and applies the drive voltage signal to the gate of the switching element 501. In this way, the gate driver 10 controls the on / off of the switching element 501.

[0018] The high-voltage circuit 30 includes, for example, an RS flip-flop circuit to which a set signal and a reset signal are input, and a driver unit that generates a drive voltage signal based on the output signal of the RS flip-flop circuit. However, the specific circuit configuration of the high-voltage circuit 30 can be changed as desired.

[0019] In the gate driver 10 of this embodiment, the low-voltage circuit 20 and the high-voltage circuit 30 are insulated from each other by the transformer 40. More specifically, the transformer 40 restricts the transmission of DC voltage between the low-voltage circuit 20 and the high-voltage circuit 30, while allowing the transmission of various signals such as set signals and reset signals.

[0020] In other words, the state in which the low-voltage circuit 20 and the high-voltage circuit 30 are insulated means that the transmission of DC voltage is blocked between the low-voltage circuit 20 and the high-voltage circuit 30, while the transmission of signals between the low-voltage circuit 20 and the high-voltage circuit 30 is permitted.

[0021] The withstand voltage of the gate driver 10 is, for example, 2500 Vrms or more and 7500 Vrms or less. The withstand voltage of the gate driver 10 of this embodiment is approximately 5000 Vrms. However, the specific value of the withstand voltage of the gate driver 10 is not limited to this and can be any value.

[0022] In this embodiment, the ground GND1 of the low-voltage circuit 20 and the ground GND2 of the high-voltage circuit 30 are provided independently. Hereinafter, the potential of the ground GND1 of the low-voltage circuit 20 is referred to as a first reference potential, and the potential of the ground GND2 of the high-voltage circuit 30 is referred to as a second reference potential. In this case, the first voltage V1 is a voltage derived from the first reference potential, and the second voltage V2 is a voltage derived from the second reference potential. The first voltage V1 is, for example, 4.5 V or more and 5.5 V or less, and the second voltage V2 is, for example, 9 V or more and 24 V or less.

[0023] The transformer 40 will be described in detail below. The gate driver 10 of this embodiment includes two transformers 40 and two capacitors 50 corresponding to two signals transmitted from the low-voltage circuit 20 to the high-voltage circuit 30. More specifically, the gate driver 10 includes a transformer 40 and a capacitor 50 used to transmit a set signal (SET), and a transformer 40 and a capacitor 50 used to transmit a reset signal (RESET). For ease of explanation, the transformer 40 and the capacitor 50 used to transmit the set signal will be referred to as "transformer 40A" and "capacitor 50A" below. Furthermore, the transformer 40 and the capacitor 50 used to transmit the reset signal will be referred to as "transformer 40B" and "capacitor 50B" below.

[0024] The gate driver 10 includes a low-voltage signal line 21A that connects the low-voltage circuit 20 and the transformer 40A, and a low-voltage signal line 21B that connects the low-voltage circuit 20 and the transformer 40B. Therefore, the low-voltage signal line 21A transmits a set signal from the low-voltage circuit 20 to the transformer 40A. The low-voltage signal line 21B transmits a reset signal from the low-voltage circuit 20 to the transformer 40B.

[0025] The gate driver 10 includes a high-voltage signal line 31A that connects the transformer 40A and the high-voltage circuit 30, and a high-voltage signal line 31B that connects the transformer 40B and the high-voltage circuit 30. Therefore, the high-voltage signal line 31A transmits a set signal from the transformer 40A to the high-voltage circuit 30. The high-voltage signal line 31B transmits a reset signal from the transformer 40B to the high-voltage circuit 30.

[0026] The transformer 40A transmits a set signal from the low voltage circuit 20 to the high voltage circuit 30, while electrically insulating the low voltage circuit 20 from the high voltage circuit 30. The transformer 40A has a first coil 41A and a second coil 42A. The first coil 41A and the second coil 42A are electrically insulated from each other and configured to be magnetically coupled to each other.

[0027] The first coil 41A is connected to the low-voltage circuit 20 by a low-voltage signal line 21A, and is also connected to the ground GND1 of the low-voltage circuit 20. That is, a first end of the first coil 41A is electrically connected to the low-voltage circuit 20. The first coil 41A is configured so that a low voltage can be applied to the first end of the first coil 41A. A second end of the first coil 41A is electrically connected to the ground GND1 of the low-voltage circuit 20. Therefore, the potential of the second end of the first coil 41A becomes a first reference potential. The first reference potential is, for example, 0 V.

[0028] The second coil 42A is connected to the high-voltage circuit 30 by the high-voltage signal line 31A, and is also connected to the ground GND2 of the high-voltage circuit 30. That is, a first end of the second coil 42A is electrically connected to the high-voltage circuit 30. The second coil 42A is configured so that a high voltage can be applied to the first end of the second coil 42A. A second end of the second coil 42A is electrically connected to the ground GND2 of the high-voltage circuit 30. Therefore, the potential of the second end of the second coil 42A is the second reference potential. The ground GND2 of the high-voltage circuit 30 is connected to the source of the switching element 501. Therefore, the second reference potential fluctuates as the inverter device 500 is driven, and may reach, for example, 600 V or more.

[0029] The transformer 40B transmits a reset signal from the low-voltage circuit 20 to the high-voltage circuit 30, while electrically insulating the low-voltage circuit 20 from the high-voltage circuit 30. The transformer 40B has a first coil 41B and a second coil 42B. The first coil 41B and the second coil 42B are electrically insulated from each other and configured to be magnetically coupled. Note that the connection configuration of the transformer 40B is similar to that of the transformer 40A, and therefore a detailed description thereof will be omitted.

[0030] The capacitor 50A is connected to the transformer 40A. Specifically, the capacitor 50A is connected between the first coil 41A and the second coil 42A that constitute the transformer 40A.

[0031] The capacitor 50A has a first capacitor electrode 51A and a second capacitor electrode 52A. The first capacitor electrode 51A and the second capacitor electrode 52A are disposed between the first coil 41A and the second coil 42A that constitute the transformer 40A. The first capacitor electrode 51A is connected to the second end of the first coil 41A, and the second capacitor electrode 52A is connected to the second end of the second coil 42A. The second end of the first coil 41A is connected to the ground GND1 of the low-voltage circuit 20. That is, the second end of the first coil 41A is the ground end. Therefore, the first capacitor electrode 51A is connected to the ground end of the first coil 41A. The second end of the second coil 42A is connected to the ground GND2 of the high-voltage circuit 30. That is, the second end of the second coil 42A is the ground end. Therefore, the second capacitor electrode 52A is connected to the ground end of the second coil 42A.

[0032] The capacitor 50B is connected to the transformer 40B. Specifically, the capacitor 50B is connected between the first coil 41B and the second coil 42B that constitute the transformer 40B.

[0033] The capacitor 50B has a first capacitor electrode 51B and a second capacitor electrode 52B. The first capacitor electrode 51B and the second capacitor electrode 52B are arranged between the first coil 41B and the second coil 42B that constitute the transformer 40B. The first capacitor electrode 51B is connected to the ground end of the first coil 41B. The second capacitor electrode 52B is connected to the ground end of the second coil 42B.

[0034] Fig. 2 shows an example of a plan view illustrating the internal configuration of the gate driver 10. Note that Fig. 1 shows a simplified circuit configuration of the gate driver 10, and therefore the number of external terminals of the gate driver 10 in Fig. 2 is greater than the number of external terminals of the gate driver 10 in Fig. 1. Here, the number of external terminals of the gate driver 10 refers to the number of external electrodes that can connect the gate driver 10 to external electronic components of the gate driver 10, such as the ECU 503 and switching elements 501 (see Fig. 1). Furthermore, the number of signal lines (the number of wires W1 to W4, described later) that transmit signals from the low-voltage circuit 20 to the high-voltage circuit 30 in the gate driver 10 in Fig. 2 is greater than the number of signal lines in the gate driver 10 in Fig. 1.

[0035] 2, the gate driver 10 is a semiconductor device in which multiple semiconductor chips are packaged, and is mounted on, for example, a circuit board provided in an inverter device 500. Note that the switching elements 501 and 502 are mounted on a mounting board separate from the circuit board, and a cooler is attached to this mounting board.

[0036] The gate driver 10 is packaged in a small outline (SO) package, which is an SOP (Small Outline Package) in this embodiment. The gate driver 10 includes a low-voltage circuit chip 60, a high-voltage circuit chip 70, and a transformer chip 80 as semiconductor chips. The low-voltage circuit chip 60 is mounted on a low-voltage lead frame 90. The high-voltage circuit chip 70 is mounted on a high-voltage lead frame 100. A molded resin 110 seals a portion of each lead frame 90, 100 and each chip 60, 70, 80. In this embodiment, the transformer chip 80 corresponds to an "isolation transformer." The transformer chip 80 and molded resin 110 correspond to an "insulation module" that insulates the low-voltage circuit 20 from the high-voltage circuit 30. In FIG. 2, the molded resin 110 is indicated by a two-dot chain line for the convenience of explaining the internal structure of the gate driver 10. The package format of the gate driver 10 can be changed as desired.

[0037] The molded resin 110 is made of an electrically insulating material. This resin is, for example, a resin containing black epoxy resin. The molded resin 110 is formed in the shape of a rectangular plate with its thickness direction in the z direction. The molded resin 110 has four resin side surfaces 111 to 114. More specifically, the molded resin 110 has resin side surfaces 111 and 112 as both end surfaces in the x direction and resin side surfaces 113 and 114 as both end surfaces in the y direction. The x direction and the y direction are directions orthogonal to the z direction. The x direction and the y direction are orthogonal to each other. In the following description, a planar view means a view from the z direction.

[0038] The low-voltage lead frame 90 and the high-voltage lead frame 100 are each a conductor, and in this embodiment are made of a material containing Cu (copper), Fe (iron), etc. Each of the lead frames 90, 100 is provided straddling the inside and outside of the mold resin 110.

[0039] The low-voltage lead frame 90 has a low-voltage die pad 91 disposed within the molded resin 110, and a plurality of low-voltage leads 92 disposed across the inside and outside of the molded resin 110. Each low-voltage lead 92 constitutes an external terminal that electrically connects to an external electronic device such as an ECU 503 (see FIG. 1).

[0040] In this embodiment, both the low-voltage circuit chip 60 and the transformer chip 80 are mounted on the low-voltage die pad 91. In plan view, the low-voltage die pad 91 is arranged so that its center in the y direction is closer to the resin side surface 113 than the center in the y direction of the molded resin 110. In this embodiment, the low-voltage die pad 91 is not exposed from the molded resin 110. In plan view, the low-voltage die pad 91 has a rectangular shape with its longer side in the x direction and its shorter side in the y direction.

[0041] The plurality of low-voltage leads 92 are arranged spaced apart from one another in the x direction. Of the plurality of low-voltage leads 92, the low-voltage leads 92 arranged at both ends in the x direction are each integrated with the low-voltage die pad 91. A portion of each low-voltage lead 92 protrudes outward from the resin side surface 113 of the molded resin 110.

[0042] The high-voltage lead frame 100 has a high-voltage die pad 101 disposed within a molded resin 110, and a plurality of high-voltage leads 102 disposed across the inside and outside of the molded resin 110. Each high-voltage lead 102 constitutes an external terminal that electrically connects to an external electronic device such as the gate of a switching element 501 (see FIG. 1).

[0043] The high-voltage die pad 101 has a high-voltage circuit chip 70 mounted thereon. In plan view, the high-voltage die pad 101 is disposed closer to the resin side surface 114 in the y direction than the low-voltage die pad 91. In this embodiment, the high-voltage die pad 101 is not exposed from the molded resin 110. In plan view, the high-voltage die pad 101 has a rectangular shape with its longer side oriented in the x direction and its shorter side oriented in the y direction.

[0044] The low-voltage die pad 91 and the high-voltage die pad 101 are arranged apart from each other in the y direction. Therefore, the y direction can also be said to be the arrangement direction of both die pads 91, 101. The y-direction dimensions of the low-voltage die pad 91 and the high-voltage die pad 101 are set depending on the size and number of semiconductor chips to be mounted. In this embodiment, the low-voltage circuit chip 60 and the transformer chip 80 are mounted on the low-voltage die pad 91, and the high-voltage circuit chip 70 is mounted on the high-voltage die pad 101, so the y-direction dimension of the low-voltage die pad 91 is larger than the y-direction dimension of the high-voltage die pad 101.

[0045] The multiple high-voltage leads 102 are arranged spaced apart from each other in the x direction. Of the multiple high-voltage leads 102, a pair of high-voltage leads 102 are integrated with the high-voltage die pad 101. A portion of each high-voltage lead 102 protrudes outward from the resin side surface 114 of the molded resin 110.

[0046] In this embodiment, the number of high-voltage leads 102 is the same as the number of low-voltage leads 92. As can be seen from Fig. 2, the plurality of low-voltage leads 92 and the plurality of high-voltage leads 102 are arranged in a direction (x direction) perpendicular to the arrangement direction (y direction) of the low-voltage die pads 91 and the high-voltage die pads 101. Note that the number of high-voltage leads 102 and the number of low-voltage leads 92 can each be changed arbitrarily.

[0047] In this embodiment, the low-voltage die pad 91 is supported by a pair of low-voltage leads 92 that are integrated with the low-voltage die pad 91. The high-voltage die pad 101 is supported by a pair of high-voltage leads 102 that are integrated with the high-voltage die pad 101. Therefore, each die pad 91, 101 does not have a suspension lead that is exposed from the resin side surfaces 111, 112. This allows for a large insulation distance between the low-voltage lead frame 90 and the high-voltage lead frame 100.

[0048] The low-voltage circuit chip 60, the high-voltage circuit chip 70, and the transformer chip 80 are arranged spaced apart from one another in the y direction. In the y direction, the low-voltage circuit chip 60, the transformer chip 80, and the high-voltage circuit chip 70 are arranged in this order from the low-voltage lead 92 to the high-voltage lead 102.

[0049] The low-voltage circuit chip 60 includes the low-voltage circuit 20 shown in FIG. 1. In plan view, the low-voltage circuit chip 60 has a rectangular shape with short and long sides. In plan view, the low-voltage circuit chip 60 is mounted on the low-voltage die pad 91 with its long sides aligned along the x direction and its short sides aligned along the y direction. The low-voltage circuit chip 60 has a chip main surface 60s and a chip back surface (not shown) that face opposite each other in the z direction. The chip back surface of the low-voltage circuit chip 60 is bonded to the low-voltage die pad 91 with a conductive bonding material such as solder or Ag (silver) paste.

[0050] A plurality of first electrode pads 61, a plurality of second electrode pads 62, and a plurality of third electrode pads 63 are formed on a chip main surface 60s of the low-voltage circuit chip 60. Each of the electrode pads 61 to 63 is electrically connected to the low-voltage circuit 20.

[0051] The multiple first electrode pads 61 are arranged on the chip main surface 60s closer to the low-voltage leads 92 than to the center of the chip main surface 60s in the y direction. The multiple first electrode pads 61 are arranged in the x direction. The multiple second electrode pads 62 are arranged at one of both ends of the chip main surface 60s in the y direction that is closer to the transformer chip 80. The multiple second electrode pads 62 are arranged in the x direction. The multiple third electrode pads 63 are arranged at both ends of the chip main surface 60s in the x direction.

[0052] The high-voltage circuit chip 70 includes the high-voltage circuit 30 shown in FIG. 1. In plan view, the high-voltage circuit chip 70 has a rectangular shape with short and long sides. In plan view, the high-voltage circuit chip 70 is mounted on the high-voltage die pad 101 with the long sides aligned along the x direction and the short sides aligned along the y direction. The high-voltage circuit chip 70 has a chip main surface 70s and a chip back surface (not shown) facing opposite sides in the z direction. The chip back surface of the high-voltage circuit chip 70 is bonded to the high-voltage die pad 101 with a conductive bonding material.

[0053] A plurality of first electrode pads 71, a plurality of second electrode pads 72, and a plurality of third electrode pads 73 are formed on a chip main surface 70s of the high-voltage circuit chip 70. Each of the electrode pads 71 ​​to 73 is electrically connected to the high-voltage circuit 30.

[0054] The multiple first electrode pads 71 ​​are arranged at the end closer to the transformer chip 80 of both end portions in the y direction of the chip main surface 70s. The multiple first electrode pads 71 ​​are arranged in the x direction. The multiple second electrode pads 72 are arranged at the end farther from the transformer chip 80 of both end portions in the y direction of the chip main surface 70s. In other words, the multiple second electrode pads 72 are arranged at the end closer to the high-voltage lead 102 of both end portions in the y direction of the chip main surface 70s. The multiple second electrode pads 72 are arranged in the x direction. The multiple third electrode pads 73 are arranged at both end portions in the x direction of the chip main surface 70s.

[0055] The transformer chip 80 includes the transformer 40 (40A, 40B) and capacitor 50 (50A, 50B) shown in FIG. 1. The shape of the transformer chip 80 in plan view is a rectangle having short and long sides. In this embodiment, the transformer chip 80 is mounted on the low-voltage die pad 91 so that the long sides are aligned along the x direction and the short sides are aligned along the y direction in plan view.

[0056] The transformer chip 80 is disposed adjacent to the low-voltage circuit chip 60 in the y direction. The transformer chip 80 is disposed closer to the high-voltage circuit chip 70 than the low-voltage circuit chip 60. In other words, the transformer chip 80 is disposed between the low-voltage circuit chip 60 and the high-voltage circuit chip 70 in the y direction.

[0057] The transformer chip 80 has a chip main surface 80s and a chip back surface 80r (see FIG. 9) facing opposite sides in the z direction. The chip back surface 80r of the transformer chip 80 is bonded to a low-voltage die pad 91 by a conductive bonding material SD (see FIG. 9).

[0058] 2, a plurality of first electrode pads 81 and a plurality of second electrode pads 82 are formed on a chip main surface 80s of the transformer chip 80. Here, in this embodiment, each first electrode pad 81 corresponds to a "first electrode," and each second electrode pad 82 corresponds to a "second electrode."

[0059] The multiple first electrode pads 81 are arranged, for example, at one of both ends in the y direction of the chip main surface 80s, which is closer to the low-voltage circuit chip 60. The multiple first electrode pads 81 are arranged in the x direction. The multiple second electrode pads 82 are arranged, for example, near the center in the y direction of the chip main surface 80s. The multiple second electrode pads 82 are arranged in the x direction.

[0060] 4, the transformers 40A, 40B and the capacitors 50A, 50B are arranged near the center of the chip main surface 80s in the y direction in a plan view. In a plan view, the plurality of second electrode pads 82, the transformers 40A, 40B, and the capacitors 50A, 50B are arranged in positions where they do not overlap with each other. Each electrode pad 81, 82 is electrically connected to the transformers 40A, 40B and the capacitors 50A, 50B.

[0061] 2, in order to set the dielectric strength voltage of the gate driver 10 to a preset dielectric strength voltage, it is necessary to separate the low-voltage die pad 91 and the high-voltage die pad 101, which are closest to each other on the lead frames 90 and 100. Therefore, in a plan view, the distance between the high-voltage circuit chip 70 and the transformer chip 80 is greater than the distance between the low-voltage circuit chip 60 and the transformer chip 80.

[0062] A plurality of wires W1 to W4 are connected to each of the low-voltage circuit chip 60, the transformer chip 80, and the high-voltage circuit chip 70. Each of the wires W1 to W4 is a bonding wire formed by a wire bonding device, and is made of a conductor containing, for example, Au (gold), Al (aluminum), Cu, etc.

[0063] The low-voltage circuit chip 60 is electrically connected to the low-voltage lead frame 90 by wires W1. More specifically, the low-voltage circuit chip 60's first electrode pads 61 and third electrode pads 63 are connected to the low-voltage leads 92 by wires W1. The low-voltage circuit chip 60's third electrode pads 63 are connected to a pair of low-voltage leads 92, among the low-voltage leads 92, that are integrated with the low-voltage die pad 91, by wires W1. This electrically connects the low-voltage circuit 20 to the low-voltage leads 92 (external electrodes of the gate driver 10 that are electrically connected to the ECU 503). In this embodiment, the pair of low-voltage leads 92 that are integrated with the low-voltage die pad 91 form ground terminals, and the low-voltage circuit 20 and the low-voltage die pad 91 are electrically connected by wires W1. Therefore, the low-voltage die pad 91 has the same potential as the ground GND1 of the low-voltage circuit 20.

[0064] The high-voltage circuit chip 70 and the multiple high-voltage leads 102 of the high-voltage lead frame 100 are each electrically connected by a wire W4. More specifically, the multiple second electrode pads 72 and multiple third electrode pads 73 of the high-voltage circuit chip 70 are connected to the high-voltage leads 102 by the wire W4. This electrically connects the high-voltage circuit 30 and the multiple high-voltage leads 102 (external electrodes of the gate driver 10 that are electrically connected to the switching elements 501, etc.). In this embodiment, a pair of high-voltage leads 102 integrated with the high-voltage die pad 101 constitute ground terminals, and the high-voltage circuit 30 and the high-voltage die pad 101 are electrically connected by the wire W4. Therefore, the high-voltage die pad 101 has the same potential as the ground GND2 of the high-voltage circuit 30.

[0065] The transformer chip 80 is connected to the low-voltage circuit chip 60 by wires W2, and is connected to the high-voltage circuit chip 70 by wires W3. More specifically, the first electrode pads 81 of the transformer chip 80 are connected to the second electrode pads 62 of the low-voltage circuit chip 60 by wires W2. The second electrode pads 82 of the transformer chip 80 are connected to the first electrode pads 71 ​​of the high-voltage circuit chip 70 by wires W3.

[0066] Both the first coil 41A of the transformer 40A and the first coil 41B of the transformer 40B (see FIG. 1) are electrically connected to the ground GND1 of the low-voltage circuit 20 via the wire W2, the low-voltage circuit chip 60, etc. Both the second coil 42A of the transformer 40A and the second coil 42B of the transformer 40B (see FIG. 1) are electrically connected to the ground GND2 of the high-voltage circuit 30 via the wire W3, the high-voltage circuit chip 70, etc.

[0067] [Trans chip configuration] An example of the configuration of the transformer chip 80 will be described with reference to FIGS. In the following description, the direction from the chip back surface 80r of the transformer chip 80 toward the chip main surface 80s is referred to as "upward," and the direction from the chip main surface 80s toward the chip back surface 80r is referred to as "downward."

[0068] FIG. 3 is a perspective view showing the appearance of the transformer chip 80. As shown in FIG. FIG. 4 is a plan view of the transformer chip 80, and for convenience of explanation, the transformers 40A, 40B and capacitors 50A, 50B, as well as a shield electrode 86 and dummy patterns 120, 125, which will be described later, are indicated by dashed lines.

[0069] Fig. 5 is a cross-sectional view of the transformer chip 80 taken along the xy plane at the z-direction position of the first coils 41A and 41B, showing the connection relationship between the first coils 41A and 41B. Fig. 6 is a cross-sectional view of the transformer chip 80 taken along the xy plane at the z-direction position of the second coils 42A and 42B, showing the connection relationship between the second coils 42A and 42B. Note that hatching is omitted in Figs. 5 and 6 for convenience.

[0070] Fig. 7 is a cross-sectional view of the transformer chip 80 taken along the xy plane at the z-direction position of the first capacitor electrodes 51A and 51B. Fig. 8 is a cross-sectional view of the transformer chip 80 taken along the xy plane at the z-direction position of the second capacitor electrodes 52A and 52B. For convenience, hatching is omitted in Figs. 7 and 8.

[0071] 9 is a cross-sectional view of the transformer chip 80 taken along line 9-9 in FIG. 4, showing the cross-sectional structure of the transformer 40A and the capacitor. Note that in FIG. 9, some hatching has been omitted to make the drawing easier to read. FIG. 10 is an enlarged view of a portion of FIG. 9, and like FIG. 9, some hatching has been omitted.

[0072] As shown in Fig. 4, the transformer chip 80 of this embodiment includes two pairs of transformers 40A, 40B and capacitors 50A, 50B. More specifically, the transformer chip 80 is a semiconductor chip that integrates the transformers 40A, 40B and the capacitors 50A, 50B into a single chip. In other words, the transformer chip 80 is provided separately from the low-voltage circuit chip 60 and the high-voltage circuit chip 70 (both see Fig. 2).

[0073] Each pair of transformers 40A, 40B and capacitors 50A, 50B have the same configuration. Furthermore, transformer 40B has the same configuration as transformer 40A. Furthermore, capacitor 50B has the same configuration as capacitor 50A. Therefore, the detailed structures of transformer 40A and capacitor 50A will be described, and descriptions of transformer 40B and capacitor 50B will be omitted.

[0074] As shown in FIG. 4, the transformer chip 80 has four chip side surfaces 80a, 80b, 80c, and 80d that are perpendicular to both the chip main surface 80s and the chip back surface 80r. The chip side surfaces 80a to 80d are provided between the chip main surface 80s and the chip back surface 80r in the z direction. The chip side surfaces 80a and 80b form both end surfaces of the transformer chip 80 in the y direction, and the chip side surfaces 80c and 80d form both end surfaces of the transformer chip 80 in the x direction. In a plan view, the chip side surfaces 80a and 80b form the long sides of the transformer chip 80, and the chip side surfaces 80c and 80d form the short sides of the transformer chip 80. In this embodiment, the chip side surface 80a is closer to the high-voltage circuit chip 70 (see FIG. 2) than the chip side surface 80b, and the chip side surface 80b is closer to the low-voltage circuit chip 60 (see FIG. 2) than the chip side surface 80a.

[0075] As shown in FIGS. 4 and 9, the transformer chip 80 has a substrate 83 and an insulating layer 84 formed on the substrate 83. The substrate 83 is made of, for example, a semiconductor substrate. In this embodiment, the substrate 83 is a substrate formed from a material containing Si (silicon). Note that a wide band gap semiconductor or a compound semiconductor may be used as the semiconductor substrate for the substrate 83. Furthermore, instead of a semiconductor substrate, an insulating substrate formed from a material containing glass may be used as the substrate 83.

[0076] The wide bandgap semiconductor is a semiconductor substrate having a bandgap of 2.0 eV or more. The wide bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0077] The substrate 83 has a substrate main surface 83s and a substrate back surface 83r that face opposite to each other in the z direction. The substrate back surface 83r forms the chip back surface 80r of the transformer chip 80.

[0078] 9, the insulating layer 84 of this embodiment has a plurality of insulating films 85 stacked in the z direction from the substrate main surface 83s of the substrate 83. In other words, the z direction can also be said to be the thickness direction of the insulating layer 84. The z direction can also be said to be the stacking direction of the insulating films 85. The insulating layer 84 is formed on the substrate main surface 83s of the substrate 83.

[0079] The insulating film 85 includes a first insulating film 85A and a second insulating film 85B formed on the first insulating film 85A. The first insulating film 85A is a thin film, for example, an etching stopper layer. The first insulating film 85A is formed of a material containing SiN (silicon nitride), SiC, SiCN (nitrogen-doped silicon carbide), or the like. In this embodiment, the first insulating film 85A is formed of a material containing SiN. The second insulating film 85B is, for example, an interlayer insulating film. The second insulating film 85B is formed of a material containing SiO2 (silicon oxide). As shown in FIG. 9 , the thickness of the second insulating film 85B is thicker than the thickness of the first insulating film 85A. The thickness of the first insulating film 85A may be equal to or greater than 100 nm and less than 1000 nm. The thickness of the second insulating film 85B may be equal to or greater than 1000 nm and less than 3000 nm. In this embodiment, the thickness of the first insulating film 85A is, for example, approximately 300 nm, and the thickness of the second insulating film 85B is, for example, approximately 2000 nm.

[0080] Both the lowermost insulating film 85L in contact with the substrate main surface 83s of the substrate 83 and the uppermost insulating film 85U are composed of the second insulating film 85B. Therefore, the thicknesses of both the lowermost insulating film 85L and the uppermost insulating film 85U are thinner than the other insulating films 85. The thicknesses of both the lowermost insulating film 85L and the uppermost insulating film 85U are equal to or greater than the thickness of the first insulating film 85A and equal to or less than the thickness of the second insulating film 85B.

[0081] The thicknesses of both the lowermost insulating film 85L and the uppermost insulating film 85U can be changed as desired. For example, the thicknesses of both the lowermost insulating film 85L and the uppermost insulating film 85U may be greater than the thickness of the second insulating film 85B, or may be equal to or greater than the thickness of the insulating film 85 formed by the first insulating film 85A and the second insulating film 85B.

[0082] The transformer chip 80 includes a shield electrode 86 formed in the insulating layer 84. The shield electrode 86 prevents moisture from penetrating the insulating layer 84 and prevents cracks from occurring in the insulating layer 84. The shield electrode 86 is provided on the outer periphery of the insulating layer 84 (the outer periphery of the transformer chip 80) in a planar view. More specifically, as shown in FIGS. 4 to 8, the shield electrode 86 is provided spaced apart from the chip side surfaces 80a to 80d. In a planar view, the shield electrode 86 is formed in a strip shape and extends along the chip side surfaces 80a to 80d. In this embodiment, the shield electrode 86 has a rectangular ring shape in a planar view. The shield electrode 86 divides the insulating layer 84 into an inner region 87 and an outer region 88. In this embodiment, as shown in FIG. 9, the uppermost insulating film 85U is formed to straddle the shield electrode 86 in a planar view. In other words, it can be said that the uppermost insulating film 85U has the outer region 88.

[0083] As shown in FIG. 4, the inner region 87 is a region of the insulating layer 84 that is protected by the shield electrode 86. The inner region 87 has a rectangular shape in plan view, with its longer sides oriented in the x direction and its shorter sides oriented in the y direction. The outer region 88 is a rectangular ring-shaped region that surrounds the inner region 87 in plan view. The outer region 88 is a region between the shield electrode 86 and the chip side surfaces 80a to 80d in plan view. In other words, the outer region 88 is a rectangular ring-shaped region that includes the chip side surfaces 80a to 80d.

[0084] 9, the shield electrode 86 penetrates the insulating films 85 in the z direction. More specifically, the shield electrode 86 is provided so as to overlap with the coils 41A, 41B, 42A, and 42B of the transformers 40A and 40B and the capacitor electrodes 51A, 51B, 52A, and 52B of the capacitors 50A and 50B, respectively, when viewed from a direction perpendicular to the z direction. In this embodiment, the shield electrode 86 penetrates in the z direction from the insulating film 85 below the uppermost insulating film 85U to the insulating film 85 immediately above the lowermost insulating film 85L. The shield electrode 86 is formed of a material containing one or more appropriately selected from Ti (titanium), TiN (titanium nitride), Au, Ag, Cu, Al, and W (tungsten).

[0085] The lowermost insulating film 85L is provided with a via 89 that penetrates the lowermost insulating film 85L in the z-direction. The via 89 is disposed at a position that overlaps with the shield electrode 86 in a plan view, and connects the shield electrode 86 to the substrate 83. This electrically connects the shield electrode 86 to the substrate 83. The via 89 may be formed of, for example, the same material as the shield electrode 86.

[0086] As shown in FIG. 4, the transformers 40A, 40B and the capacitors 50A, 50B are embedded in an insulating layer 84. The transformers 40A, 40B and the capacitors 50A, 50B are arranged in an inner region 87. When viewed from the z direction, the capacitor 50A is arranged to overlap the transformer 40A, and the capacitor 50B is arranged to overlap the transformer 40B. The transformers 40A, 40B and the capacitors 50A, 50B are arranged aligned with each other in the y direction and spaced apart from each other in the x direction. In other words, the transformers 40A, 40B and the capacitors 50A, 50B are arranged in a direction perpendicular to the arrangement direction of the chips 60, 70, and 80 in a plan view.

[0087] As shown in FIG. 4, the transformer 40A and the capacitor 50A, and the transformer 40B and the capacitor 50B are arranged alternately in the x direction from the chip side surface 80c to the chip side surface 80d.

[0088] As shown in FIG. 5, the first coil 41A of the transformer 40A has a first coil wiring 43A, a first ground terminal 45 connected to one end of the first coil wiring 43A, and a first signal terminal 44A connected to the other end of the first coil wiring 43A. The first coil 41B of the transformer 40B has a first coil wiring 43B, a first ground terminal 45 connected to one end of the first coil wiring 43B, and a first signal terminal 44B connected to the other end of the first coil wiring 43B. The first ground terminal 45 is configured as a common terminal for the first coil 41A and the first coil 41B. Alternatively, the first coil 41A and the first coil 41B may each be provided with a first ground terminal.

[0089] The first coil wirings 43A and 43B have an elliptical spiral shape in a plan view. The first signal terminals 44A and 44B are disposed inside the first coil wirings 43A and 43B. The first ground terminal 45 is disposed between the first coil 41A of the transformer 40A and the first coil 41B of the transformer 40B. The first coils 41A and 41B are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0090] The first signal terminal 44A is connected to a first electrode pad 81A shown in Fig. 4 by a connection wiring 131A. The first signal terminal 44B is connected to a first electrode pad 81B shown in Fig. 4 by a connection wiring 131B. The first ground terminal 45 is connected to a first electrode pad 81C shown in Fig. 4 by a connection wiring 131C.

[0091] As shown in FIG. 6, the second coil 42A of the transformer 40A has a second coil wiring 46A, a second ground terminal 48 connected to one end of the second coil wiring 46A, and a second signal terminal 47A connected to the other end of the second coil wiring 46A. The second coil 42B of the transformer 40B has a second coil wiring 46B, a second ground terminal 48 connected to one end of the second coil wiring 46B, and a second signal terminal 47B connected to the other end of the second coil wiring 46B. The second ground terminal 48 is configured as a common terminal for the second coil 42A and the second coil 42B. Alternatively, the second coil 42A and the second coil 42B may each be provided with a second ground terminal.

[0092] The second coil wirings 46A and 46B have an elliptical spiral shape in a plan view. The second signal terminals 47A and 47B are disposed inside the second coil wirings 46A and 46B. The second ground terminal 48 is disposed between the second coil 42A of the transformer 40A and the second coil 42B of the transformer 40B. The second coils 42A and 42B are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0093] The second signal terminal 47A is connected to the second electrode pad 82A shown in Fig. 4. The second signal terminal 47B is connected to the second electrode pad 82B shown in Fig. 4. The second ground terminal 48 is connected to the second electrode pad 82C shown in Fig. 4.

[0094] In this embodiment, the second coil wiring 46A is formed in the same winding direction as the first coil wiring 43A shown in Fig. 5 in a plan view. The number of turns of the second coil wiring 46A is the same as the number of turns of the first coil wiring 43A. In this embodiment, the second coil wiring 46B is formed in the same winding direction as the first coil wiring 43B shown in Fig. 5 in a plan view. The number of turns of the second coil wiring 46B is the same as the number of turns of the first coil wiring 43B.

[0095] 9, the first coil 41A and the second coil 42A of the transformer 40A are arranged opposite to each other in the z direction via an insulating film 85. In this embodiment, the first coil 41A and the second coil 42A are arranged opposite to each other in the z direction via a plurality of insulating films 85.

[0096] The first coil 41A is configured as a conductive layer embedded in one insulating film 85. More specifically, the insulating film 851 in which the first coil 41A is embedded has a coil groove (first coil groove) 141 that penetrates both the first insulating film 85A and the second insulating film 85B in the z direction. The conductive layer that constitutes the first coil 41A is embedded in the coil groove 141 of the insulating film 851. The insulating film 851 in which the first coil 41A is embedded is covered by the insulating film 85 that is adjacent to the insulating film 851 in the z direction. As a result, it can be said that the first coil 41A is embedded in the insulating film 85.

[0097] The second coil 42A is configured as a conductive layer embedded in one insulating film 85. More specifically, the insulating film 854 in which the second coil 42A is embedded has a coil groove (second coil groove) 141 that penetrates both the first insulating film 85A and the second insulating film 85B in the z direction. The conductive layer that constitutes the second coil 42A is embedded in the coil groove 141 of the insulating film 854. The insulating film 854 in which the second coil 42A is embedded is covered by the insulating film 85 that is adjacent to the insulating film 854 in the z direction. As a result, it can be said that the second coil 42A is embedded in the insulating film 85.

[0098] In the z direction, the second coil 42A is located farther from the substrate 83 than the first coil 41A. In other words, the second coil 42A is located higher than the first coil 41A. Furthermore, the first coil 41A is located closer to the substrate 83 than the second coil 42A. In this embodiment, the distance between the first coil 41A and the second coil 42A in the z direction is greater than the distance between the first coil 41A and the substrate main surface 83s of the substrate 83.

[0099] The first capacitor electrode 51A of the capacitor 50A shown in FIG. 7 is formed so as to overlap the first coil 41A shown in FIG. 5 in a plan view. The first capacitor electrode 51A is formed of a conductive material. It is more preferable that the first capacitor electrode 51A be formed of a non-magnetic material. The non-magnetic material may be one or more of Ti, TiN, TiW (tungsten titanium), Ta (tantalum), TaN (tantalum nitride), Cr (chromium), CrSi (chromium silicide), Au, Ag, Cu, Al, and W. The first capacitor electrode 51A may also be formed of a conductive material other than the above materials.

[0100] The first capacitor electrode 51A has a first electrode wiring 53A, a first capacitor end 54A, and a first capacitor ground end 55. The first electrode wiring 53A is formed in an elliptical spiral shape, similar to the first coil wiring 43A shown in FIG. 5. The first electrode wiring 53A is formed in the same shape as the first coil wiring 43A of the first coil 41A shown in FIG. 5. In other words, the first electrode wiring 53A has the same line width / line spacing ratio as the first coil wiring 43A.

[0101] The first electrode wiring 53A has a first slit 51As formed along a direction from the center of the first electrode wiring 53A toward the outside of the first electrode wiring 53A. The first slit 51As forms the first electrode wiring 53A in an open ring shape. The first slit 51As suppresses the formation of a current loop in the first electrode wiring 53A.

[0102] The first capacitor end 54A is arranged to overlap the first signal end 44A of the first coil 41A shown in FIG. 5. The first capacitor end 54A is formed in the same shape as the first signal end 44A in a plan view. The first capacitor end 54A is arranged inside the first electrode wiring 53A and is connected to the first electrode wiring 53A. The shape of the first capacitor end 54A may be changed to any shape. Furthermore, the first capacitor end 54A may be omitted.

[0103] The first capacitor ground end 55 is arranged to overlap with the first ground end 45 of the first coil 41A shown in Fig. 5. The first capacitor ground end 55 is formed in the same shape as the first ground end 45 in a plan view. The first capacitor ground end 55 is arranged between the first capacitor electrode 51A of the capacitor 50A and the first capacitor electrode 51B of the capacitor 50B. The first capacitor ground end 55 is electrically connected to each wiring portion of the first electrode wiring 53A by a connection wiring 55A extending toward the center of the first electrode wiring 53A.

[0104] The first capacitor electrode 51B of the capacitor 50B shown in FIG. 7 is formed so as to overlap the first coil 41B shown in FIG. 5 in a plan view. The first capacitor electrode 51B is formed of a conductive material. It is more preferable that the first capacitor electrode 51B be formed of a non-magnetic material. As the non-magnetic material, one or more of Ti, TiN, TiW, Ta, TaN, Cr, CrSi, Au, Ag, Cu, Al, and W may be appropriately selected. Note that the first capacitor electrode 51B may also be formed of a conductive material other than the above materials.

[0105] The first capacitor electrode 51B has a first electrode wiring 53B, a first capacitor end 54B, and a first capacitor ground end 55. Therefore, the first capacitor electrodes 51A and 51B have the first capacitor ground end 55 as a common terminal, similar to the first coils 41A and 41B shown in FIG.

[0106] The first electrode wiring 53B is formed in an elliptical spiral shape, similar to the first coil wiring 43B shown in FIG. 5. The first electrode wiring 53B is formed in the same shape as the first coil wiring 43B of the first coil 41B shown in FIG. 5. In other words, the first electrode wiring 53B has the same line width / line spacing ratio as the first coil wiring 43B. The first electrode wiring 53B has first slits 51Bs formed in a direction from the center of the first electrode wiring 53B toward the outside of the first electrode wiring 53B. The first slits 51Bs form the first electrode wiring 53B in an open ring shape. The first slits 51Bs suppress the formation of a current loop in the first electrode wiring 53B.

[0107] The first capacitor end 54B is arranged to overlap the first signal end 44B of the first coil 41B shown in FIG. 5. The first capacitor end 54B is formed in the same shape as the first signal end 44B in a plan view. The first capacitor end 54B is arranged inside the first electrode wiring 53B and is connected to the first electrode wiring 53B. The shape of the first capacitor end 54B may be changed to any shape. Furthermore, the first capacitor end 54B may be omitted.

[0108] The first capacitor ground terminal 55 is electrically connected to each wiring portion of the first electrode wiring 53B by a connection wiring 55B that extends toward the center of the first electrode wiring 53B. The second capacitor electrode 52A of the capacitor 50A shown in FIG. 8 is formed so as to overlap the second coil 42A shown in FIG. 6 in plan view. The second capacitor electrode 52A is formed of a conductive material. It is more preferable that the second capacitor electrode 52A be formed of a non-magnetic material. As the non-magnetic material, one or more of Ti, TiN, TiW, Ta, TaN, Cr, CrSi, Au, Ag, Cu, Al, and W may be appropriately selected. Note that the second capacitor electrode 52A may also be formed of a conductive material other than the above materials.

[0109] The second capacitor electrode 52A has a second electrode wiring 56A, a second capacitor end 57A, and a second capacitor ground end 58. The second electrode wiring 56A is formed in an elliptical spiral shape, similar to the second coil wiring 46A shown in FIG. 6. The second electrode wiring 56A is formed in the same shape as the second coil wiring 46A of the second coil 42A shown in FIG. 6. In other words, the second electrode wiring 56A has the same line width / line spacing ratio as the second coil wiring 46A.

[0110] The second electrode wiring 56A has second slits 52As formed along a direction from the center of the second electrode wiring 56A toward the outside of the second electrode wiring 56A. The second slits 52As form the second electrode wiring 56A in an open ring shape. The second slits 52As suppress the formation of a current loop in the second electrode wiring 56A.

[0111] The second capacitor end 57A is arranged to overlap the second signal end 47A of the second coil 42A shown in FIG. 6. The second capacitor end 57A is formed in the same shape as the second signal end 47A in a plan view. The second capacitor end 57A is arranged inside the second electrode wiring 56A and is connected to the second electrode wiring 56A. The shape of the second capacitor end 57A may be changed to any shape. Furthermore, the second capacitor end 57A may be omitted.

[0112] The second capacitor ground end 58 is arranged to overlap with the second ground end 48 of the second coil 42A shown in Fig. 6. The second capacitor ground end 58 is formed in the same shape as the second ground end 48 in a plan view. The second capacitor ground end 58 is arranged between the second capacitor electrode 52A of the capacitor 50A and the second capacitor electrode 52B of the capacitor 50B. The second capacitor ground end 58 is electrically connected to each wiring portion of the second electrode wiring 56A by a connection wiring 58A extending toward the center of the second electrode wiring 56A.

[0113] The second capacitor electrode 52B of the capacitor 50B shown in FIG. 8 is formed so as to overlap the second coil 42B shown in FIG. 6 in plan view. The second capacitor electrode 52B is formed of a conductive material. It is more preferable that the second capacitor electrode 52B be formed of a non-magnetic material. As the non-magnetic material, one or more of Ti, TiN, TiW, Ta, TaN, Cr, CrSi, Au, Ag, Cu, Al, and W may be appropriately selected. Note that the second capacitor electrode 52B may also be formed of a conductive material other than the above materials.

[0114] The second capacitor electrode 52B has a second electrode wiring 56B, a second capacitor end 57B, and a second capacitor ground end 58. Therefore, the second capacitor electrodes 52A, 52B have the second capacitor ground end 58 as a common terminal, similar to the second coils 42A, 42B shown in FIG.

[0115] The second electrode wiring 56B is formed in an elliptical spiral shape, similar to the second coil wiring 46B shown in FIG. 6. The second electrode wiring 56B is formed in the same shape as the second coil wiring 46B of the second coil 42B shown in FIG. 6. In other words, the second electrode wiring 56B has the same line width / line spacing ratio as the second coil wiring 46B. The second electrode wiring 56B has second slits 52Bs formed in a direction from the center of the second electrode wiring 56B toward the outside of the second electrode wiring 56B. The second slits 52Bs form the second electrode wiring 56B in an open ring shape. The second slits 52Bs suppress the formation of a current loop in the second electrode wiring 56B.

[0116] The second capacitor end 57B is arranged to overlap the second signal end 47B of the second coil 42B shown in FIG. 6. The second capacitor end 57B is formed in the same shape as the second signal end 47B in a plan view. The second capacitor end 57B is arranged inside the second electrode wiring 56B and is connected to the second electrode wiring 56B. The shape of the second capacitor end 57B may be changed to any shape. Furthermore, the second capacitor end 57B may be omitted.

[0117] The second capacitor ground terminal 58 is electrically connected to each wiring portion of the second electrode wiring 56B by a connection wiring 58B that extends toward the center of the second electrode wiring 56B. 9, the first capacitor electrode 51A and the second capacitor electrode 52A of the capacitor 50A are disposed between the first coil 41A and the second coil 42A of the transformer 40A. The first capacitor electrode 51A and the second capacitor electrode 52A are disposed opposite to each other in the z direction with a plurality of insulating films 85 interposed therebetween.

[0118] At least one insulating film 85 is interposed between the first capacitor electrode 51A and the first coil 41A. In this embodiment, one insulating film 85 is interposed. At least one insulating film 85 is interposed between the second capacitor electrode 52A and the second coil 42A. In this embodiment, one insulating film 85 is interposed.

[0119] The first capacitor electrode 51A is configured as a conductive layer buried in one insulating film 85. More specifically, a capacitor groove (first capacitor groove) 144 penetrating both the first insulating film 85A and the second insulating film 85B in the z-direction is formed in the insulating film 852 in which the first capacitor electrode 51A is buried. The conductive layer constituting the first capacitor electrode 51A is buried in the capacitor groove 144 of the insulating film 852. The insulating film 852 in which the first capacitor electrode 51A is buried is covered by the insulating film 85 adjacent to the insulating film 852 in the z-direction. As a result, it can be said that the first capacitor electrode 51A is buried in the insulating film 85.

[0120] The second capacitor electrode 52A is configured as a conductive layer buried in one insulating film 85. More specifically, a capacitor groove (second capacitor groove) 144 penetrating both the first insulating film 85A and the second insulating film 85B in the z-direction is formed in the insulating film 853 in which the second capacitor electrode 52A is buried. The conductive layer constituting the second capacitor electrode 52A is buried in the capacitor groove 144 of the insulating film 853. The insulating film 853 in which the second capacitor electrode 52A is buried is covered by an insulating film 85 adjacent to the insulating film 853 in the z-direction. As a result, it can be said that the second capacitor electrode 52A is buried in the insulating film 85.

[0121] The distance between the first capacitor electrode 51A and the second capacitor electrode 52A is determined by the film thickness and the number of layers of the insulating film 85 interposed between the first capacitor electrode 51A and the second capacitor electrode 52A. This distance is set appropriately depending on the dielectric strength and electric field strength of the transformer chip 80.

[0122] As shown in FIG. 9, the first capacitor electrode 51A is electrically connected to the first coil 41A. The first coil 41A has a first coil wiring 43A, a first signal terminal 44A, and a first ground terminal 45. The first capacitor electrode 51A has a first electrode wiring 53A, a first capacitor terminal 54A, and a first capacitor ground terminal 55. The first electrode wiring 53A and the first coil wiring 43A overlap each other in the z direction. The first capacitor terminal 54A and the first signal terminal 44A overlap each other in the z direction. The first capacitor ground terminal 55 and the first ground terminal 45 overlap each other in the z direction.

[0123] The first capacitor ground end 55 of the first capacitor electrode 51A is connected to the first ground end 45 of the first coil 41A. A plurality of vias 137 that penetrate the insulating film 85 in the z-direction are formed in the insulating film 85 interposed between the first capacitor electrode 51A and the first coil 41A. The plurality of vias 137 connect the first capacitor ground end 55 of the first capacitor electrode 51A to the first ground end 45 of the first coil 41A. As a result, the first capacitor electrode 51A is connected to the first ground end 45 of the first coil 41A.

[0124] As shown in FIG. 9, the second capacitor electrode 52A is electrically connected to the second coil 42A. The second coil 42A has a second coil wiring 46A, a second signal terminal 47A, and a second ground terminal 48. The second capacitor electrode 52A has a second electrode wiring 56A, a second capacitor terminal 57A, and a second capacitor ground terminal 58. The second electrode wiring 56A and the second coil wiring 46A overlap each other in the z direction. The second capacitor terminal 57A and the second signal terminal 47A overlap each other in the z direction. The second capacitor ground terminal 58 and the second ground terminal 48 overlap each other in the z direction.

[0125] The second capacitor ground end 58 of the second capacitor electrode 52A is connected to the second ground end 48 of the second coil 42A. A plurality of vias 138 that penetrate the insulating film 85 in the z-direction are formed in the insulating film 85 interposed between the second capacitor electrode 52A and the second coil 42A. The plurality of vias 138 connect the second capacitor ground end 58 of the second capacitor electrode 52A to the second ground end 48 of the second coil 42A. As a result, the second capacitor electrode 52A is connected to the second ground end 48 of the second coil 42A.

[0126] As shown in FIG. 4, the plurality of first electrode pads 81 and the plurality of second electrode pads 82 are each disposed within an inner region 87 in a plan view. As shown in FIG. 9 , the electrode pads 81 and 82 are formed on an uppermost insulating film 85U. The uppermost insulating film 85U is formed in a position aligned with the electrode pads 81 and 82. In this embodiment, the electrode pads 81 and 82 are disposed at positions farther from the substrate 83 than the second coils 42A and 42B of the transformers 40A and 40B. In other words, the electrode pads 81 and 82 are positioned higher than the second coils 42A and 42B of the transformers 40A and 40B. In this embodiment, the distance between the first coil 41A and the second coil 42A is greater than the distance between the second coil 42A and the electrode pads 81 and 82 in the z direction.

[0127] 4, in a plan view, the multiple first electrode pads 81 are arranged at positions aligned with the two transformers 40A and the two transformers 40B in the x direction, and between the transformers 40A and 40B in the x direction. The multiple first electrode pads 81 are arranged closer to the chip side surface 80b in the y direction than the transformers 40A and 40B. In other words, the multiple first electrode pads 81 are arranged between the transformers 40A and 40B and the chip side surface 80b in the y direction. In other words, the multiple first electrode pads 81 are arranged closer to the low-voltage lead 92 (see FIG. 2) than the transformers 40A and 40B in a plan view.

[0128] Hereinafter, for convenience, the first electrode pad 81 arranged at a position aligned with the transformer 40A in the x direction will be referred to as the first electrode pad 81A. The first electrode pad 81 arranged at a position aligned with the transformer 40B in the x direction will be referred to as the first electrode pad 81B. The first electrode pad 81 arranged between the transformers 40A and 40B in the x direction will be referred to as the first electrode pad 81C. Note that when describing matters common to the first electrode pads 81A to 81C, they will be described as the first electrode pad 81.

[0129] The first electrode pad 81A is arranged at a position overlapping with the transformer 40A when viewed from the y direction. The first electrode pad 81B is arranged at a position overlapping with the transformer 40B when viewed from the y direction. The first electrode pad 81C is arranged at a position overlapping with a portion between the transformers 40A and 40B in the x direction when viewed from the y direction. The multiple first electrode pads 81A to 81C are arranged aligned with each other in the y direction and spaced apart from each other in the x direction.

[0130] 4, in a plan view, the multiple second electrode pads 82 are arranged in each of the transformers 40A and 40B and between the transformers 40A and 40B in the x direction. The multiple second electrode pads 82 are arranged at positions overlapping the transformers 40A and 40B when viewed from the x direction. For convenience, the second electrode pad 82 in the transformer 40A will be referred to as the second electrode pad 82A, the second electrode pad 82 in the transformer 40B will be referred to as the second electrode pad 82B, and the second electrode pad between the transformers 40A and 40B will be referred to as the second electrode pad 82C. Note that when describing matters common to the second electrode pads 82A to 82C, they will be described as the second electrode pad 82.

[0131] The second electrode pad 82A is arranged in the inner space formed in the elliptical spiral second coil 42A of the transformer 40A. The second electrode pad 82B is arranged in the inner space formed in the elliptical spiral second coil 42A of the transformer 40B. The second electrode pad 82C is arranged between the transformers 40A and 40B in the x direction. Each of the second electrode pads 82A to 82C includes a pair of electrode pads adjacent to each other in the x direction. The second electrode pads 82A to 82C are arranged spaced apart from each other in the x direction while being aligned with each other in the y direction.

[0132] As shown in FIGS. 4, 5, and 9, the first electrode pad 81A is electrically connected to the first coil 41A of the transformer 40A. The first electrode pad 81C is electrically connected to the first coil 41A of the transformer 40A. The first electrode pad 81B shown in FIGS. 4 and 5 is electrically connected to the first coil 41B of the transformer 40B. The first electrode pad 81C is electrically connected to the first coil 41B of the transformer 40B. In other words, the first electrode pad 81C is an electrode pad common to the transformers 40A and 40B.

[0133] As shown in FIGS. 4, 6, and 9, the second electrode pad 82A is electrically connected to the second coil 42A of the transformer 40A individually. The second electrode pad 82C is electrically connected to the second coil 42A of the transformer 40A. The second electrode pad 82B shown in FIGS. 4 and 6 is electrically connected to the second coil 42B of the transformer 40B. The second electrode pad 82C is electrically connected to the second coil 42B of the transformer 40B. In other words, the second electrode pad 82C is an electrode pad common to the transformers 40A and 40B.

[0134] 5 and 6, the transformer chip 80 includes connection wiring for individually connecting the electrode pads 81A-81C, 82A-82C to the coils 41A, 41B, 42A, 42B of the transformers 40A, 40B. In this embodiment, the connection wiring includes connection wiring 131A, 131B, 131C that connects the first electrode pads 81A-81C to the first coils 41A, 41B. The connection wiring 131A-131C is provided in the inner region 87. The connection wiring 131A-131C is formed from a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0135] As shown in FIG. 5, the connection wiring 131A is a wiring that connects the first electrode pad 81A and the first signal end 44A of the first coil 41A of the transformer 40A. The connection wiring 131B is a wiring that connects the first electrode pad 81B and the first signal end 44B of the first coil 41B of the transformer 40B. The connection wiring 131C is a wiring that connects the first electrode pad 81C and the second end of the first coil 41A of the transformer 40A and the second end of the first coil 41B of the transformer 40B. The connection wirings 131A to 131C have the same structure. Therefore, the following will describe the configuration of the connection wiring 131A, and detailed descriptions of the connection wirings 131B and 131C will be omitted.

[0136] As shown in FIG. 9, the connection wiring 131A has a first wiring portion 132A that extends in the z direction so as to penetrate a plurality of insulating films 85, and a second wiring portion 133A that extends in the y direction. The first wiring portion 132A is disposed at a position overlapping the first electrode pad 81A in a plan view and is connected to the first electrode pad 81A. The first wiring portion 132A penetrates from the insulating film 85 below the uppermost insulating film 85U among the plurality of insulating films 85 to the insulating film 85 that is two layers above the lowermost insulating film 85L. The first wiring portion 132A has a flat wiring portion and a plurality of vias. The wiring portions are provided at the same positions as the insulating films 851 and 854 on which the coils 41A and 42A are provided. Vias are provided between the two wiring portions in the z direction, between the upper wiring portion and the first electrode pad 81A, and between the lower wiring portion and the second wiring portion 133A.

[0137] The second wiring portion 133A is provided closer to the substrate 83 than the first wiring portion 132A. The second wiring portion 133A is provided closer to the substrate 83 than the first coil 41A. In this embodiment, the second wiring portion 133A is provided in an insulating film 85 that is one layer above the lowest insulating film 85L among the multiple insulating films 85. Of both ends of the second wiring portion 133A in the x direction, a first end that is closer to the chip side surface 80b of the transformer chip 80 is provided at a position overlapping with the first wiring portion 132A in a plan view. The second wiring portion 133A is connected to the first wiring portion 132A. A second end of the second wiring portion 133A, opposite to the first end, is provided at a position overlapping with the first coil 41A of the transformer 40A in a plan view. More specifically, the second end is provided at a position overlapping with the first signal terminal 44A included in the first coil 41A of the transformer 40A in a plan view. The second wiring portion 133A has a plurality of vias 134A that connect the second wiring portion 133A and the first signal end 44A.

[0138] As shown in FIG. 9, the connection wiring 131C has a first wiring portion 132C that extends in the z direction so as to penetrate a plurality of insulating films 85, and a second wiring portion 133C that extends in the y direction. The first wiring portion 132C is configured in the same manner as the first wiring portion 132A of the connection wiring 131A.

[0139] The first wiring portion 132C is disposed at a position overlapping the first electrode pad 81C in a plan view and is connected to the first electrode pad 81C. The first wiring portion 132C penetrates from the insulating film 85 below the uppermost insulating film 85U among the multiple insulating films 85 to the insulating film 85 that is two layers above the lowermost insulating film 85L. The first wiring portion 132C has a flat wiring portion and multiple vias. The wiring portions are provided at the same positions as the insulating films 851 and 854 on which the coils 41A and 42A are provided. Vias are provided between the two wiring portions in the z direction, between the upper wiring portion and the first electrode pad 81A, and between the lower wiring portion and the second wiring portion 133C.

[0140] The second wiring portion 133C is provided closer to the substrate 83 than the first wiring portion 132C. The second wiring portion 133C is provided closer to the substrate 83 than the first coil 41A. In this embodiment, the second wiring portion 133C is provided in an insulating film 85 one layer above the lowest insulating film 85L among the multiple insulating films 85. Of both ends of the second wiring portion 133C in the x direction, a first end closer to the chip side surface 80b of the transformer chip 80 is provided at a position overlapping with the first wiring portion 132C in a plan view. The second wiring portion 133C is connected to the first wiring portion 132C. A second end of the second wiring portion 133C opposite to the first end is provided at a position overlapping with the first coil 41A of the transformer 40A in a plan view. More specifically, the second end is provided at a position overlapping with the first ground terminal 45 included in the first coil 41A of the transformer 40A in a plan view. The second wiring portion 133C has a plurality of vias 134C that connect the second wiring portion 133C and the first signal end 44A. The second wiring portion 133C of the connection wiring 131C is electrically connected to the substrate 83 by vias 136 that penetrate the insulating film 85L of the lowest layer. Note that the vias 136 may be omitted.

[0141] As shown in FIG. 9, the second electrode pad 82A is electrically connected to the second signal terminal 47A of the second coil 42A by a via 135A that penetrates the uppermost insulating film 85U. The second electrode pad 82C is electrically connected to the second ground end 48 of the second coil 42A by a via 135C that penetrates the uppermost insulating film 85U.

[0142] 4 and 6, in this embodiment, the transformer chip 80 includes a dummy pattern 120 provided around the second coils 42A and 42B of the transformers 40A and 40B. The dummy pattern 120 is a dummy coil pattern.

[0143] The dummy pattern 120 is provided in the inner region 87 and includes a first dummy pattern 121, a second dummy pattern 122, and a third dummy pattern 123. Each of the dummy patterns 121 to 123 is formed from a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0144] The first dummy pattern 121 is provided in a region between the second coil 42A of the transformer 40A and the second coil 42B of the transformer 40B in the x-direction in a plan view. The first dummy pattern 121 is formed in a pattern different from the second coils 42A and 42B. The first dummy pattern 121 is electrically connected to the second ground end 48 of the second coil 42A. Note that the first dummy pattern 121 only needs to be electrically connected to at least one of the second ground ends 48 of the two second coils 42A. In this way, the first dummy pattern 121 has the same potential as the second coils 42A and 42B. Therefore, as the second reference potential of the second coils 42A and 42B changes, the voltage of the first dummy pattern 121 may become higher than that of the first coil 41B, similar to the second coil 42B.

[0145] Although not shown, the first dummy pattern 121 is arranged in a position aligned with the second coils 42A and 42B in the z direction. In other words, the first dummy pattern 121 is arranged in a position farther from the substrate 83 than the first coils 41A and 41B. In other words, it can be said that the dummy pattern 120 is provided around the coil of one of the transformers 40A and 40B that is closer to the chip main surface 80s of the transformer chip 80.

[0146] The first dummy pattern 121 has the same voltage as the second coils 42A, 42B, thereby suppressing a voltage drop between the second coils 42A, 42B and the first dummy pattern 121. Therefore, electric field concentration on the second coils 42A, 42B can be suppressed.

[0147] 6, the third dummy pattern 123 is formed to surround the second coils 42A and 42B of the transformers 40A and 40B in a plan view. The third dummy pattern 123 is electrically connected to the first dummy pattern 121. Therefore, similar to the first dummy pattern 121, the voltage of the third dummy pattern 123 may become higher than that of the first coil 41B as the second reference potential of the second coil 42B changes.

[0148] 9, the third dummy pattern 123 is arranged at a position aligned with the second coil 42A in the z direction. Although not shown, the third dummy pattern 123 is also arranged at a position aligned with the second coil 42B in the z direction. In other words, the third dummy pattern 123 is arranged at a position farther from the substrate 83 than the first coils 41A and 41B. In this way, the dummy patterns 121 to 123 are arranged at positions aligned with one another in the z direction.

[0149] The third dummy pattern 123 has the same voltage as the second coils 42A, 42B, thereby suppressing a voltage drop between the second coils 42A, 42B and the third dummy pattern 123. Therefore, electric field concentration on the second coils 42A, 42B can be suppressed.

[0150] 6, the second dummy pattern 122 is formed to surround the third dummy pattern 123 in a plan view. The second dummy pattern 122 is independent of the second coils 42A and 42B. In other words, the second dummy pattern 122 is not electrically connected to the second coils 42A and 42B.

[0151] 9, the second dummy pattern 122 is arranged in a position aligned with the second coil 42A in the z direction. Although not shown, the second dummy pattern 122 is also arranged in a position aligned with the second coil 42B in the z direction. In other words, the second dummy pattern 122 is arranged in a position farther from the substrate 83 than the first coils 41A and 41B. The second dummy pattern 122 can suppress an increase in the electric field strength around the second coils 42A and 42B and suppress electric field concentration on the second electrode pads 82A to 82C.

[0152] 8, in this embodiment, the transformer chip 80 includes a dummy pattern 125 provided around the second capacitor electrodes 52A and 52B of the capacitors 50A and 50B. The dummy pattern 125 is configured similarly to the above-described dummy pattern 120. The dummy pattern 125 is a dummy electrode pattern.

[0153] More specifically, the dummy pattern 125 is provided in the inner region 87 and includes a first dummy pattern 126, a second dummy pattern 127, and a third dummy pattern 128. Each of the dummy patterns 126 to 128 is formed of the same material as the second capacitor electrode 52A, for example. The dummy pattern 125 has a slit formed along a direction from the inside of the dummy pattern 125 to the outside of the dummy pattern 125. This slit suppresses the formation of a current loop in the dummy pattern 125. The dummy pattern 125 is a dummy electrode pattern.

[0154] The first dummy pattern 126 is provided in a region between the second capacitor electrode 52A of the capacitor 50A and the second capacitor electrode 52B of the capacitor 50B in the x-direction in a plan view. The first dummy pattern 126 is formed in a pattern different from that of the second capacitor electrodes 52A and 52B. The first dummy pattern 126 is electrically connected to the second capacitor ground terminal 58 of the second capacitor electrode 52A. Note that it is sufficient for the first dummy pattern 126 to be electrically connected to at least one of the second capacitor ground terminals 58 of the two second capacitor electrodes 52A. In this way, the first dummy pattern 126 has the same potential as the second capacitor electrodes 52A and 52B. Therefore, as the second reference potential of the second capacitor electrodes 52A and 52B changes, the voltage of the first dummy pattern 126 may become higher than that of the first capacitor electrode 51B, similar to that of the second capacitor electrode 52B.

[0155] Although not shown, the first dummy pattern 126 is arranged in a position aligned with the second capacitor electrodes 52A and 52B in the z direction. That is, the first dummy pattern 126 is arranged in a position farther from the substrate 83 than the first capacitor electrodes 51A and 51B. In other words, it can be said that the dummy pattern 125 is provided around the coil of one of the capacitors 50A and 50B that is closer to the chip main surface 80s of the transformer chip 80.

[0156] The first dummy pattern 126 has the same voltage as the second capacitor electrodes 52A, 52B, thereby suppressing a voltage drop between the second capacitor electrodes 52A, 52B and the first dummy pattern 126. This makes it possible to suppress electric field concentration on the second capacitor electrodes 52A, 52B.

[0157] 8, the third dummy pattern 128 is formed to surround the second capacitor electrodes 52A and 52B of the capacitors 50A and 50B in a plan view. The third dummy pattern 128 is electrically connected to the first dummy pattern 126. Therefore, similar to the first dummy pattern 126, the voltage of the third dummy pattern 128 may sometimes become higher than that of the first capacitor electrode 51B in accordance with a change in the second reference potential of the second capacitor electrode 52B.

[0158] 9, the third dummy pattern 128 is arranged at a position aligned with the second capacitor electrode 52A in the z direction. Although not shown, the third dummy pattern 128 is also arranged at a position aligned with the second capacitor electrode 52B in the z direction. In other words, the third dummy pattern 128 is arranged at a position farther from the substrate 83 than the first capacitor electrodes 51A and 51B. In this way, the dummy patterns 126 to 128 are arranged at positions aligned with one another in the z direction.

[0159] The third dummy pattern 128 has the same voltage as the second capacitor electrodes 52A, 52B, thereby suppressing a voltage drop between the second capacitor electrodes 52A, 52B and the third dummy pattern 128. This makes it possible to suppress electric field concentration on the second capacitor electrodes 52A, 52B.

[0160] 8, the second dummy pattern 127 is formed to surround the third dummy pattern 128 in a plan view. The second dummy pattern 127 is independent of the second capacitor electrodes 52A, 52B. In other words, the second dummy pattern 127 is not electrically connected to the second capacitor electrodes 52A, 52B.

[0161] 9, the second dummy pattern 127 is arranged at a position aligned with the second capacitor electrode 52A in the z direction. Although not shown, the second dummy pattern 127 is also arranged at a position aligned with the second capacitor electrode 52B in the z direction. In other words, the second dummy pattern 127 is arranged at a position farther from the substrate 83 than the first capacitor electrodes 51A, 51B. The second dummy pattern 127 can suppress an increase in the electric field strength around the second capacitor electrodes 52A, 52B and can suppress electric field concentration on the second electrode pads 82A to 82C.

[0162] 9, the transformer chip 80 includes a protective film 150 and a passivation film 160. The protective film 150 is formed on the surface 84s of the insulating layer 84. The protective film 150 is a film that protects the insulating layer 84. The protective film 150 is a film formed of a material containing, for example, silicon oxide.

[0163] The passivation film 160 is a surface protection film for the transformer chip 80. The passivation film 160 is formed of a material containing silicon nitride, for example. Examples of materials containing silicon nitride include SiN and SiCN. In this embodiment, the passivation film 160 is formed of a material containing SiN. The passivation film 160 constitutes the chip main surface 80s of the transformer chip 80.

[0164] The first electrode pad 81 and the second electrode pad 82 are covered with a protective film 150 and a passivation film 160. The protective film 150 and the passivation film 160 have openings that expose portions of the first electrode pad 81 and the second electrode pad 82. As a result, the first electrode pad 81 has an exposed surface for connecting a wire W2. In addition, the second electrode pad 82 has an exposed surface for connecting a wire W3.

[0165] As shown in FIGS. 3 and 4, the transformer chip 80 includes a resin layer 180 formed on a passivation film 160. The resin layer 180 is formed of a material containing, for example, polyimide (PI). The resin layer 180 is separated into an inner resin layer 181 and an outer resin layer 182 by a separation groove 183. As shown in FIG. 4, the separation groove 183 is formed so as to surround the transformers 40A and 40B in plan view. The resin layer 180 includes a first resin opening 184 exposing the first electrode pad 81 and a second resin opening 185 exposing the second electrode pad 82.

[0166] Fig. 10 is a partially enlarged view of Fig. 9, showing an example configuration of the second coil 42A and the second capacitor electrode 52A. In this configuration example, the second coil 42A and the second capacitor electrode 52A are made of Cu.

[0167] An elliptical spiral coil groove 141 is formed in the insulating film 854. The coil groove 141 is formed to penetrate the second insulating film 85B and the first insulating film 85A below it. As a result, the upper and lower ends of the coil groove 141 form surfaces that are open to the first insulating film 85A of the upper insulating film 85 and the second insulating film 85B of the lower insulating film 85, respectively.

[0168] A barrier film 142 is formed on the inner surfaces (side and bottom surfaces) of the coil groove 141. The barrier film 142 is formed in a film shape conforming to the side and bottom surfaces so as to form an upwardly open space in the coil groove 141. In this embodiment, the barrier film 142 is formed of a material including Ta, TaN, Ti, TiN, etc. Then, a main layer 143 is embedded inside the barrier film 142 in the coil groove 141, thereby forming a second coil 42A as an example of an embedded coil composed of the barrier film 142 and the main layer 143. The main layer 143 is formed of a material including one or more appropriately selected from Cu, Al, and W.

[0169] The second coil 42A is formed so that its upper surface is flush with the upper surface of the insulating film 85. As a result, the side, upper, and lower surfaces of the second coil 42A are in contact with different insulating films 85. Specifically, the first insulating film 85A and the second insulating film 85B of the insulating film 854 in which the second coil 42A is embedded are in contact with the side surfaces of the second coil 42A. Of the insulating film 85 formed above this insulating film 854, only the lower-layer first insulating film 85A is in contact with the upper surface of the second coil 42A. Furthermore, of the lower insulating film 85, only the upper-layer second insulating film 85B is in contact with the lower surface of the second coil 42A.

[0170] An elliptical spiral capacitor groove 144 is formed in the insulating film 853. The capacitor groove 144 is formed to penetrate the second insulating film 85B and the first insulating film 85A below it. As a result, the upper and lower ends of the capacitor groove 144 form surfaces that are open to the first insulating film 85A of the upper insulating film 85 and the second insulating film 85B of the lower insulating film 85, respectively.

[0171] A barrier film 145 is formed on the inner surface (side surface and bottom surface) of the capacitor groove 144. The barrier film 145 is formed in a film shape following the side surface and bottom surface so as to form an upwardly open space in the capacitor groove 144. In this embodiment, the barrier film 145 is formed of a material including Ta, TaN, Ti, TiN, etc. Then, a main layer 146 is embedded inside the barrier film 145 in the capacitor groove 144, thereby forming a second capacitor electrode 52A as an example of an embedded capacitor electrode composed of the barrier film 145 and the main layer 146. The main layer 146 is formed of a material including one or more appropriately selected from Cu, Al, and W.

[0172] The second capacitor electrode 52A is formed so that its upper surface is flush with the upper surface of the insulating film 85. As a result, the side, upper, and lower surfaces of the second capacitor electrode 52A are in contact with different insulating films 85. Specifically, the insulating film 853 in which the second capacitor electrode 52A is embedded has the first insulating film 85A and the second insulating film 85B in contact with the side surfaces of the second capacitor electrode 52A. Of the insulating film 85 formed above this insulating film 853, only the lower first insulating film 85A is in contact with the upper surface of the second capacitor electrode 52A. Furthermore, of the lower insulating film 85, only the upper second insulating film 85B is in contact with the lower surface of the second capacitor electrode 52A.

[0173] Although not explained or shown in the drawings, the first coil 41A is formed by embedding a barrier film and a main body layer in a coil groove, similar to the second coil 42A, and the first capacitor electrode 51A is formed by embedding a barrier film and a main body layer in a coil groove, similar to the second capacitor electrode 52A.

[0174] 9 are formed by embedding a barrier film and a main body layer in a groove that penetrates the insulating film 85, similar to the second coil 42A and the second capacitor electrode 52A. Although not shown in the drawings, the connection wiring 131B is formed by embedding a barrier film and a main body layer in a groove that penetrates the insulating film 85, similar to the second coil 42A and the second capacitor electrode 52A.

[0175] 10 also shows a dummy pattern 120 corresponding to the second coil 42A and a dummy pattern 125 corresponding to the second capacitor electrode 52A. These dummy patterns 120, 125 are formed of barrier films 142, 145 and main body layers 143, 146, similar to the second coil 42A and the second capacitor electrode 52A.

[0176] (action) The operation of the gate driver 10 of this embodiment will be described. (Comparative Example) First, a comparative example to the gate driver 10 of this embodiment will be described.

[0177] 11 shows a gate driver 10R of a comparative example. This gate driver 10R of the comparative example does not include the capacitor 50 (capacitors 50A and 50B) shown in FIG. 1. In this gate driver 10R, a current i C1 This may cause noise in the set signal transmitted from the low-voltage circuit 20 to the high-voltage circuit 30, resulting in malfunction. Similarly, the current I c2 This may cause noise in the reset signal transmitted from the low voltage circuit 20 to the high voltage circuit 30, resulting in malfunction.

[0178] This current i C1 ,i C2 As a method for preventing malfunction due to noise, the high-voltage circuit 30 is provided with a circuit for masking noise. The mask circuit masks the reception of signals for a certain period of time after receiving a reset signal (RESET), for example. This prevents the current i flowing through the second coils 42A and 42B due to the parasitic capacitances C1 and C2. C1 ,i C2 Prevents malfunctions caused by

[0179] However, the capacitance values ​​of the parasitic capacitances C1 and C2 may differ for each gate driver 10R and depending on the operating state. In other words, the capacitance values ​​of the parasitic capacitances C1 and C2 are indefinite. As a result, the position of noise superimposed on the set signal and reset signal may change. Therefore, in the high-voltage circuit 30, a long mask period must be set to match the position where noise may occur. Since signal transmission is not possible during the mask period, this becomes a factor that inhibits speeding up signal transmission from the low-voltage circuit 20 to the high-voltage circuit 30. Note that the same problem occurs when transmitting signals from the high-voltage circuit 30 to the low-voltage circuit 20. For this reason, the low-voltage circuit 20 also requires a mask circuit, just like the high-voltage circuit 30.

[0180] FIG. 12 shows the operation of the gate driver 10 of this embodiment. As described above, the gate driver 10 of this embodiment includes a transformer 40A having a first coil 41A and a second coil 42A, and a transformer 40B having a first coil 41B and a second coil 42B. The gate driver 10 of this embodiment also includes a capacitor 50A connected between the ground end of the first coil 41A and the ground end of the second coil 42A, and a capacitor 50B connected between the ground end of the first coil 41B and the ground end of the second coil 42B.

[0181] The first capacitor electrode 51A of the capacitor 50A is electrically connected to the first coil 41A and has the same potential. The second capacitor electrode 52A of the capacitor 50A is electrically connected to the second coil 42A and has the same potential. The first capacitor electrode 51B of the capacitor 50B is electrically connected to the first coil 41B and has the same potential. The second capacitor electrode 52B of the capacitor 50B is electrically connected to the second coil 42B and has the same potential.

[0182] For example, a set signal (SET) and a reset signal (RESET) are transmitted from the low voltage circuit 20 to the high voltage circuit 30 using the transformer 40A and the transformer 40B. At this time, the first coil 41A of the transformer 40A is supplied with a current i 1A A current i flows through the second coil 42A that is magnetically coupled to the first coil 41A. 2A The high voltage circuit 30 receives this current i 2A A pulse signal is generated by receiving a set signal.

[0183] A current i due to a set signal flows between the first capacitor electrode 51A and the second capacitor electrode 52A of the capacitor 50A. CA This current i CA flows from the second capacitor electrode 52A to the ground terminal of the second coil 42A, that is, to the ground GND2. Therefore, the current i 2AFor the current i flowing through the capacitor 50A, CA Therefore, the influence on the signal transmission between the low voltage circuit 20 and the high voltage circuit 30 can be reduced.

[0184] Similarly, a reset signal output from the low-voltage circuit 20 flows through the first coil 41B of the transformer 40B, causing a current i 1B A current i flows through the second coil 42B that is magnetically coupled to the first coil 41B. 2B The high voltage circuit 30 receives this current i 2B generates a pulse signal, i.e. receives a reset signal.

[0185] A current i due to a reset signal flows between the first capacitor electrode 51B and the second capacitor electrode 52B of the capacitor 50B. CB This current i CB flows from the second capacitor electrode 52B to the ground terminal of the second coil 42B, that is, to the ground GND2. Therefore, the current i 2B In response to this, the current i flowing through the capacitor 50B CB Therefore, the influence on the signal transmission between the low voltage circuit 20 and the high voltage circuit 30 can be reduced.

[0186] current i CA flows with a phase delay corresponding to the impedance value of transformer 40A and the capacitance value of capacitor 50A relative to the set signal current i. CB With respect to the current i of the reset signal, the current i flows with a phase delay according to the impedance value of the transformer 40B and the capacitance value of the capacitor 50B. CA ,i CB Even if the current i CA ,i CB The length of the mask period is shorter than that in the case of the parasitic capacitance C1, and therefore the effect on the speed of signal transmission can be reduced.

[0187] (effect) The gate driver 10 of this embodiment provides the following advantages. (1) The transformer chip 80 includes an insulating layer 84, a transformer 40A, and a capacitor 50A. The transformer 40A is embedded in the insulating layer 84 and has a first coil 41A and a second coil 42A that are spaced apart in the thickness direction of the insulating layer 84. The capacitor 50A has a first capacitor electrode 51A and a second capacitor electrode 52A that are arranged between the first coil 41A and the second coil 42A of the transformer 40A. The first capacitor electrode 51A is connected to a first ground terminal 45 of the first coil 41A. The second capacitor electrode 52A is connected to a second ground terminal 48 of the second coil 42A.

[0188] According to this configuration, the transformer 40A is used to transmit a set signal (SET), for example, from the low-voltage circuit 20 to the high-voltage circuit 30. The set signal causes a current i flowing through the capacitor 50A. CA flows from the second capacitor electrode 52A to the ground terminal of the second coil 42A, that is, to the ground GND2. Therefore, the current i 2A For the current i flowing through the capacitor 50A, CA Therefore, the influence on the signal transmission between the low voltage circuit 20 and the high voltage circuit 30 can be reduced.

[0189] The transformer chip 80 also includes an insulating layer 84, a transformer 40B, and a capacitor 50B. The transformer 40B is embedded in the insulating layer 84 and has a first coil 41B and a second coil 42B that are spaced apart in the thickness direction of the insulating layer 84. The capacitor 50B has a first capacitor electrode 51B and a second capacitor electrode 52B that are arranged between the first coil 41B and the second coil 42B of the transformer 40B. The first capacitor electrode 51B is connected to a first ground terminal 45 of the first coil 41B. The second capacitor electrode 52B is connected to a second ground terminal 48 of the second coil 42B.

[0190] A reset signal (RESET) is transmitted, for example, from the low-voltage circuit 20 to the high-voltage circuit 30 using the transformer 40B. The current i CB flows from the second capacitor electrode 52B to the ground terminal of the second coil 42B, that is, to the ground GND2. Therefore, the current i 2B In response to this, the current i flowing through the capacitor 50B CB Therefore, the influence on the signal transmission between the low voltage circuit 20 and the high voltage circuit 30 can be reduced.

[0191] (2) Current i flowing through the capacitor 50A CA The current i flows with a phase delay corresponding to the impedance value of transformer 40A and the capacitance value of capacitor 50A relative to the set signal current i. CB With respect to the current i of the reset signal, the current i flows with a phase delay according to the impedance value of the transformer 40B and the capacitance value of the capacitor 50B. CA ,i CB Even if the current i CA ,i CB This simplifies the design of the high-voltage circuit 30. The length of the mask period is shorter than in the case of the parasitic capacitance C1, and therefore the effect on the speed of signal transmission can be reduced.

[0192] (3) In plan view, the dummy patterns 120 are provided around the second coils 42A and 42B. This configuration can reduce the concentration of the electric field on the second coils 42A and 42B.

[0193] (4) In plan view, the dummy patterns 125 are provided around the second capacitor electrodes 52A and 52B. This configuration can reduce the concentration of the electric field on the second capacitor electrodes 52A and 52B.

[0194] (5) The gate driver 10 includes a low-voltage circuit 20 configured to operate when a first voltage V1 is applied, a high-voltage circuit 30 configured to operate when a second voltage V2 higher than the first voltage V1 is applied, and a transformer chip 80. The low-voltage circuit 20 and the high-voltage circuit 30 are connected via the transformer chip 80 and configured to transmit signals via the transformer chip 80. The transformer chip 80 includes a transformer 40A, a transformer 40B, and a capacitor 50A, a capacitor 50B. The capacitor 50A includes a first capacitor electrode 51A and a second capacitor electrode 52A arranged between the first coil 41A and the second coil 42A of the transformer 40A. The capacitor 50B includes a first capacitor electrode 51B and a second capacitor electrode 52B arranged between the first coil 41B and the second coil 42B of the transformer 40B. The first capacitor electrodes 51A and 51B are connected to first ground terminals 45 of the first coils 41A and 41B. The second capacitor electrodes 52A, 52B are connected to the second ground ends 48 of the second coils 42A, 42B. This configuration provides the same effect as in (1) above, thereby providing a gate driver 10 with reduced influence on transmitted signals.

[0195] (6) As a configuration in which the gate driver 10 includes the transformer 40 and the capacitor 50, for example, a low-voltage circuit chip including the low-voltage circuit 20, the transformer 40, and the capacitor 50 can be considered. Alternatively, a high-voltage circuit chip including the high-voltage circuit 30, the transformer 40, and the capacitor 50 can be considered. However, in these configurations, if the circuit configuration of the low-voltage circuit 20 or the high-voltage circuit 30 is to be changed, the entire chip must be changed, which increases the cost of manufacturing multiple types of gate drivers.

[0196] In this regard, in this embodiment, the transformer 40 and the capacitor 50 are included in a transformer chip 80, which is a chip independent of the low-voltage circuit chip 60 and the high-voltage circuit chip 70. In other words, a chip dedicated to the transformer 40 is provided. Therefore, a common transformer chip 80 can be used for different low-voltage circuits 20 and high-voltage circuits 30. This reduces costs when manufacturing multiple types of gate drivers 10 in which at least one of the low-voltage circuits 20 and the high-voltage circuits 30 is different.

[0197] (7) The first capacitor electrode 51A is formed in the same shape as the first coil 41A, and the second capacitor electrode 52A is formed in the same shape as the second coil 42A. Therefore, the first capacitor electrode 51A and the second capacitor electrode 52A can be easily formed by the same process as the process for forming the first coil 41A and the second coil 42A.

[0198] [Example of change] The above embodiments are examples of possible forms of the isolation module and gate driver according to the present disclosure and are not intended to limit the forms. The isolation module and gate driver according to the present disclosure may take forms different from those exemplified in the above embodiments. Examples include forms in which part of the configuration of the above embodiments is replaced, modified, or omitted, or forms in which new configurations are added to the above embodiments. Furthermore, the following modified examples can be combined with each other as long as there is no technical contradiction. In the following modified examples, parts common to the above embodiments are assigned the same reference numerals as the above embodiments, and their description will be omitted.

[0199] In the above embodiment, the shape of the capacitor 50 in plan view may be changed as appropriate. FIG. 13 shows first capacitor electrodes 51A and 51B according to a modified example. The first capacitor electrode 51A is formed in an elliptical ring shape so as to overlap the first coil wiring 43A of the first coil 41A shown in FIG. 5. The first electrode wiring 53A of the first capacitor electrode 51A according to this modified example is formed of a plurality of ring-shaped wirings arranged from the inner end 43i of the first coil wiring 43A shown in FIG. 5 to the outer end 43o of the first coil wiring 43A. The first capacitor electrode 51A has a slit 51AS extending from the center toward the outside. The slit 51As forms the first capacitor electrode 51A in an open ring shape.

[0200] The first capacitor electrode 51B is formed in an elliptical ring shape so as to overlap with the first coil wiring 43A of the first coil 41B shown in FIG. 5. The first capacitor electrode 51B of this modified example is formed by a plurality of ring-shaped wirings arranged from the inner end 43i of the first coil wiring 43B shown in FIG. 5 to the outer end 43o of the first coil wiring 43B. This first capacitor electrode 51B has first slits 51Bs extending from the center toward the outside. Due to these first slits 51Bs, the first capacitor electrode 51B is formed in an open ring shape.

[0201] FIG. 14 shows first capacitor electrodes 51A and 51B according to a modified example. The first capacitor electrode 51A is formed in an elliptical ring shape so as to overlap with the first coil wiring 43A of the first coil 41A shown in FIG. 5. The first electrode wiring 53A of the first capacitor electrode 51A according to this modified example is formed in a plate shape that continues from the inner end 43i of the first coil wiring 43A shown in FIG. 5 to the outer end 43o of the first coil wiring 43B. The first capacitor electrode 51A has a first slit 51As extending from the center toward the outside. The first slit 51As causes the first capacitor electrode 51A to be formed in an open ring shape.

[0202] The first capacitor electrode 51B is formed in an elliptical ring shape so as to overlap with the first coil wiring 43A of the first coil 41B shown in FIG. 5. The first electrode wiring 53B of the first capacitor electrode 51B in this modified example is formed in a plate shape that continues from the inner end 43i of the first coil wiring 43A shown in FIG. 5 to the outer end 43o of the first coil wiring 43B. This first capacitor electrode 51B has a first slit 51Bs extending from the center toward the outside. This first slit 51Bs causes the first capacitor electrode 51B to be formed in an open ring shape.

[0203] 15 shows first capacitor electrodes 51A and 51B according to a modified example. The first capacitor electrode 51A is formed in an elliptical plate shape so as to overlap with the first coil wiring 43A and the first signal terminal 44A of the first coil 41A shown in FIG. 5. The first electrode wiring 53A of the first capacitor electrode 51A according to this modified example is formed in a plate shape that continues from the center of the first coil 41A shown in FIG. 5 to the outer end 43o of the first coil wiring 43B. Therefore, the first electrode wiring 53A according to this modified example is formed so as to include the first signal terminal 44A shown in FIG. 5. The first capacitor electrode 51A has a first slit 51As extending from the center outward.

[0204] The first capacitor electrode 51B is formed in an elliptical plate shape so as to overlap the first coil wiring 43A and the first signal end 44B of the first coil 41B shown in Fig. 5. The first capacitor electrode 51B in this modified example is formed in a plate shape that continues from the center of the first coil 41B shown in Fig. 5 to the outer end 43o of the first coil wiring 43B. Therefore, the first electrode wiring 53B in this modified example is formed so as to include the first signal end 44B shown in Fig. 5. This first capacitor electrode 51B has a first slit 51Bs extending from the center outward.

[0205] In the above embodiment, the first coil 41A, the second coil 42A, the first capacitor electrode 51A, the second capacitor electrode 52A, and the dummy patterns 120, 125 may be changed as appropriate in the cross section in the z direction.

[0206] 16 to 24 show schematic views of a portion of the transformer chip 80 in cross section along the z direction. As shown in FIG. 16, a configuration may be adopted in which the dummy pattern 120 corresponding to the second coil 42A and the dummy pattern 125 (see FIG. 9) corresponding to the second capacitor electrode 52A are omitted.

[0207] 17, the dummy pattern 125 (see FIG. 9) corresponding to the second capacitor electrode 52A may be omitted, and only the dummy pattern 120 corresponding to the second coil wiring 46A of the second coil 42A may be provided. Note that the dummy pattern 120 corresponding to the second coil wiring 46A of the second coil 42A may be omitted, and only the dummy pattern 125 (see FIG. 9) corresponding to the second capacitor electrode 52A may be provided.

[0208] 18, the outer end 53o of the first electrode wiring 53A of the first capacitor electrode 51A is located outside the outer end 43o of the first coil wiring 43A of the first coil 41A. The inner end 53i of the first electrode wiring 53A of the first capacitor electrode 51A is located at the same position as the inner end 43i of the first coil wiring 43A of the first coil 41A. The outer end 56o of the second electrode wiring 56A of the second capacitor electrode 52A is located outside the outer end 46o of the second coil wiring 46A of the second coil 42A. The inner end 56i of the second electrode wiring 56A of the second capacitor electrode 52A is located at the same position as the inner end 46i of the second coil wiring 46A of the second coil 42A.

[0209] 19, the outer end 53o of the first electrode wiring 53A of the first capacitor electrode 51A is located outward from the outer end 43o of the first coil wiring 43A of the first coil 41A. The inner end 53i of the first electrode wiring 53A of the first capacitor electrode 51A is located inward from the inner end 43i of the first coil wiring 43A of the first coil 41A. The outer end 56o of the second electrode wiring 56A of the second capacitor electrode 52A is located outward from the outer end 46o of the second coil wiring 46A of the second coil 42A. The inner end 56i of the second electrode wiring 56A of the second capacitor electrode 52A is located inward from the inner end 46i of the second coil wiring 46A of the second coil 42A.

[0210] 20, the first electrode wiring 53A of the first capacitor electrode 51A and the second electrode wiring 56A of the second capacitor electrode 52A are formed to overlap the second coil wiring 46A of the second coil 42A and the dummy pattern 120. That is, the outer end 53o of the first electrode wiring 53A of the first capacitor electrode 51A is located at the same position as the outer end of the dummy pattern 120 formed outside the second coil wiring 46A of the second coil 42A. Similarly, the outer end 56o of the second electrode wiring 56A of the second capacitor electrode 52A is located at the same position as the outer end of the dummy pattern 120 formed outside the second coil wiring 46A of the second coil 42A. The inner end 53i of the first electrode wiring 53A of the first capacitor electrode 51A is located at the same position as the inner end 43i of the first coil wiring 43A of the first coil 41A. An inner end 56i of the second electrode wiring 56A of the second capacitor electrode 52A is disposed at the same position as an inner end 46i of the second coil wiring 46A of the second coil 42A.

[0211] 21, the first electrode wiring 53A of the first capacitor electrode 51A and the second electrode wiring 56A of the second capacitor electrode 52A are formed to overlap the second coil wiring 46A of the second coil 42A and the dummy pattern 120. That is, the outer end 53o of the first electrode wiring 53A of the first capacitor electrode 51A is located at the same position as the outer end of the dummy pattern 120 formed outside the second coil wiring 46A of the second coil 42A. Similarly, the outer end 56o of the second electrode wiring 56A of the second capacitor electrode 52A is located at the same position as the outer end of the dummy pattern 120 formed outside the second coil wiring 46A of the second coil 42A. The inner end 53i of the first electrode wiring 53A of the first capacitor electrode 51A is located more inward than the inner end 43i of the first coil wiring 43A of the first coil 41A. An inner end 56i of the second electrode wiring 56A of the second capacitor electrode 52A is disposed more inward than an inner end 46i of the second coil wiring 46A of the second coil 42A.

[0212] 22, the outer end 53o of the first electrode wiring 53A of the first capacitor electrode 51A is disposed inside the outer end 43o of the first coil wiring 43A of the first coil 41A. The inner end 53i of the first electrode wiring 53A of the first capacitor electrode 51A is disposed outside the inner end 43i of the first coil wiring 43A of the first coil 41A. The outer end 56o of the second electrode wiring 56A of the second capacitor electrode 52A is disposed inside the outer end 46o of the second coil wiring 46A of the second coil 42A. The inner end 56i of the second electrode wiring 56A of the second capacitor electrode 52A is disposed outside the inner end 46i of the second coil wiring 46A of the second coil 42A.

[0213] 23, the line width of the first electrode wiring 53A of the first capacitor electrode 51A is set to be narrower than the line width of the first coil wiring 43A of the first coil 41A. That is, the line width / line spacing ratio of the first electrode wiring 53A is set to be smaller than the line width / line spacing ratio of the first coil wiring 43A. The line width of the second electrode wiring 56A of the second capacitor electrode 52A is set to be narrower than the line width of the second coil wiring 46A of the second coil 42A. That is, the line width / line spacing ratio of the second electrode wiring 56A is set to be smaller than the line width / line spacing ratio of the second coil wiring 46A.

[0214] 24, the line width of the first electrode wiring 53A of the first capacitor electrode 51A is set wider than the line width of the first coil wiring 43A of the first coil 41A. That is, the line width / line spacing ratio of the first electrode wiring 53A is set larger than the line width / line spacing ratio of the first coil wiring 43A. The line width of the second electrode wiring 56A of the second capacitor electrode 52A is set wider than the line width of the second coil wiring 46A of the second coil 42A. That is, the line width / line spacing ratio of the second electrode wiring 56A is set larger than the line width / line spacing ratio of the second coil wiring 46A.

[0215] In this way, the shapes of the first coil wiring 43A (first coil 41A) and the second coil wiring 46A (second coil 42A) can be set arbitrarily. Furthermore, the shapes of the first electrode wiring 53A (first capacitor electrode 51A) and the second electrode wiring 56A (second capacitor electrode 52A) can be set arbitrarily. For example, in the z direction, the thickness of the first coil wiring 43A and the second coil wiring 46A can be made different from the thickness of the first electrode wiring 53A and the second electrode wiring 56A.

[0216] In the above embodiment, the passivation film 160 is not limited to a material containing silicon nitride, as long as it is a layer that can protect the insulating layer 84. In the above embodiment, the arrangement of the transformers 40A, 40B and the capacitors 50A, 50B can be changed as desired. For example, the transformers 40A, 40A, 40B, and 40B may be arranged in this order from the chip side surface 80c toward the chip side surface 80d of the transformer chip 80. The capacitors 50A, 50B are arranged according to the positions of the transformers 40A, 40B.

[0217] In the above embodiment, the first dummy pattern 121 of the dummy pattern 120 is electrically connected to the second coil 42B, but this is not limited to this. For example, the first dummy pattern 121 may be provided independently of the second coils 42A and 42B. That is, the first dummy pattern 121 does not have to be electrically connected to the second coils 42A and 42B. Also, in the above embodiment, the third dummy pattern 123 is electrically connected to the first dummy pattern 121, but this is not limited to this. For example, the third dummy pattern 123 does not have to be electrically connected to the first dummy pattern 121.

[0218] In the above embodiment, the first dummy pattern 126 of the dummy pattern 125 is electrically connected to the first capacitor electrode 51A, but this is not limited to this. For example, the first dummy pattern 126 may be provided independently of the first capacitor electrodes 51A and 51B. That is, the first dummy pattern 126 does not have to be electrically connected to the first capacitor electrodes 51A and 51B. Also, in the above embodiment, the third dummy pattern 128 is electrically connected to the first dummy pattern 126, but this is not limited to this. For example, the third dummy pattern 128 does not have to be electrically connected to the first dummy pattern 126.

[0219] In the above embodiment, the configuration of the dummy pattern 120 corresponding to the second coils 42A and 42B can be changed as desired. For example, in the dummy pattern 120, one or two of the first dummy pattern 121, the second dummy pattern 122, and the third dummy pattern 123 may be omitted. Also, the dummy pattern 120 may be omitted from the transformer chip 80.

[0220] In the above embodiment, the configuration of the dummy patterns 125 corresponding to the second capacitor electrodes 52A, 52B can be changed as desired. For example, in the dummy patterns 125, one or two of the first dummy pattern 126, the second dummy pattern 127, and the third dummy pattern 128 may be omitted. Also, the dummy pattern 125 may be omitted from the transformer chip 80.

[0221] In the above embodiment, the low-voltage circuit 20 and the transformer 40 are formed as separate chips, but this is not limiting. The transformer 40 and the low-voltage circuit 20 may be mounted on a single chip. In one example, the low-voltage circuit 20 may be formed on the substrate 83 of the transformer chip 80. The transformer chip 80 is covered with mold resin 110.

[0222] In the above embodiment, the high-voltage circuit 30 and the transformer 40 are formed as separate chips, but this is not limited to this. The transformer 40 and the high-voltage circuit 30 may be mounted on a single chip. In one example, the high-voltage circuit 30 may be formed on the substrate 83 of the transformer chip 80. In this case, the transformer chip 80 is mounted on the high-voltage die pad 101. The transformer chip 80 is covered with mold resin 110.

[0223] In the above embodiment, the gate driver 10 may include an insulating module that houses the transformer 40 in a single package. The insulating module includes a transformer chip 80 and a molded resin 110 that seals the transformer chip 80. The insulating module may further include a die pad on which the transformer chip 80 is mounted, multiple leads, and wires that connect the multiple leads to the transformer chip 80. The molded resin 110 seals at least the transformer chip 80, the die pad, and the wires. The multiple leads can be electrically connected to both the low-voltage circuit 20 and the high-voltage circuit 30.

[0224] In the above embodiment, the gate driver 10 may include a low-voltage circuit unit that houses the low-voltage circuit 20 and the transformer 40 in a single package. The low-voltage circuit unit may include a low-voltage circuit chip 60, a transformer chip 80, and a molding resin 110 that seals the low-voltage circuit chip 60 and the transformer chip 80. The low-voltage circuit unit may further include a die pad, a plurality of first leads, first wires that connect the plurality of first leads to the low-voltage circuit chip 60, a plurality of second leads, and second wires that connect the plurality of second leads to the transformer chip 80. The molding resin 110 seals at least the low-voltage circuit chip 60, the transformer chip 80, the die pad, and each wire. The plurality of first leads can be electrically connected to, for example, the ECU 503, and the plurality of second leads can be electrically connected to the high-voltage circuit 30.

[0225] In the above embodiment, the gate driver 10 may include a high-voltage circuit unit that houses the high-voltage circuit 30 and the transformer 40 in a single package. The high-voltage circuit unit may include a high-voltage circuit chip 70, a transformer chip 80, and a molded resin 110 that seals both the high-voltage circuit chip 70 and the transformer chip 80. The high-voltage circuit unit may further include a die pad, multiple first leads, first wires connecting the multiple first leads to the high-voltage circuit chip 70, multiple second leads, and second wires connecting the multiple second leads to the transformer chip 80. The molded resin 110 seals at least the high-voltage circuit chip 70, the transformer chip 80, the die pad, and each wire. The multiple first leads can be electrically connected to the source of the switching element 501, for example, and the multiple second leads can be electrically connected to the low-voltage circuit 20.

[0226] In the above embodiment, a configuration may be adopted in which a signal is transmitted from the high-voltage circuit 30 to the low-voltage circuit 20 via the transformer 40 and the capacitor 50. Also, a configuration may be adopted in which a signal is transmitted bidirectionally between the low-voltage circuit 20 and the high-voltage circuit 30 via the transformer 40 and the capacitor 50.

[0227] In the above embodiment, the first coil 41A and the second coil 42A, and the first coil 41B and the second coil 42B may have different numbers of turns. Also, the first coil 41A and the second coil 42A, and the first coil 41B and the second coil 42B may have different winding directions.

[0228] In the above embodiment, the positions of the slits 51As and 51Bs shown in FIG. 7 can be changed as desired. In FIG. 7, the slits 51As and 51Bs are formed along the x direction, but they may also be formed along the y direction. Furthermore, both slits 51As and 51Bs may be formed along the same direction, for example, the direction toward the chip side surface 80c. Similarly, the positions of the slits 52As and 52Bs shown in FIG. 8 can be changed as desired. Furthermore, the slit 51As shown in FIG. 7 and the slit 52As shown in FIG. 8 may be formed along different directions. Similarly, the slit 51Bs shown in FIG. 7 and the slit 52Bs shown in FIG. 8 may be formed along different directions.

[0229] The term "on" used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Therefore, the expression "A is formed on B" is intended to mean that, in this embodiment, A may be in contact with B and disposed directly on B, but as a variant, A may be disposed above B without contacting B. In other words, the term "on" does not exclude a structure in which another member is formed between A and B.

[0230] The z-direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the z-direction described herein being "up" and "down" of the vertical direction. For example, the x-direction may be the vertical direction, or the y-direction may be the vertical direction.

[0231] The statement "at least one of A and B" in this specification should be understood to mean "A only, or B only, or both A and B." [Explanation of symbols]

[0232] 10 Gate Drivers 20 Low-voltage circuit 21A, 21B Low voltage signal line 30 High-voltage circuit 31A, 31B High voltage signal line 40 Transformer 40A, 40B transformer 41A, 41B First coil 42A, 42B Second coil 43A, 43B First coil wiring 43i inner end 43o outer edge 44A,44B 1st signal end 45 1st ground terminal 46A, 46B Second coil wiring 46i inner end 46o outer edge 47A,47B 2nd signal end 48 2nd ground terminal 50 capacitors 50A, 50B capacitor 51A, 51B First capacitor electrodes 51As, 51Bs First slit 52A, 52B Second capacitor electrodes 52As, 52Bs Second slit 53A,53B 1st electrode wiring 53i inner end 53o outer edge 54A, 54B First capacitor end 55 First capacitor ground terminal 55A, 55B connection wiring 56A,56B 2nd electrode wiring 56i inner end 56o outer end 57A, 57B Second capacitor end 58 Second capacitor ground terminal 58A, 58B connection wiring 60 Low-voltage circuit chip 60s chip main surface 61 First electrode pad 62 Second electrode pad 63 Third electrode pad 70 High-voltage circuit chip 70s chip main surface 71 First electrode pad 72 Second electrode pad 73 Third electrode pad 80 Transformer Chip 80a~80d Chip side 80r chip backside 80s chip main surface 81 First electrode pad 81A~81C First electrode pad 82 Second electrode pad 82A~82C Second electrode pad 83 PCB 83r Back side of the board 83s Main surface of the board 84 Insulating layer 84s surface 85 insulating film 851~854 Insulating film 85A First insulating film 85B Second insulating film 85L insulating film 85U Insulating film 86 Shield electrode 87 Inner area 88 Outer area 89 Beer 90 Low voltage lead frame 91 Low voltage die pad 92 Low Voltage Lead 100 High voltage lead frame 101 High voltage die pad 102 High Voltage Lead 110 Molding resin 111~114 Resin side 120 dummy pattern 121 First dummy pattern 122 Second dummy pattern 123 Third Dummy Pattern 125 Dummy Pattern 126 First Dummy Pattern 127 Second Dummy Pattern 128 Third Dummy Pattern 131A~131C Connection wiring 132A, 132C First wiring section 133A,133C 2nd wiring section 134A, 134C via 135A, 135C via 136~138 Beer 141 Coil groove 142 Barrier membrane 143 Main Layer 144 Capacitor Groove 145 Barrier membrane 146 Main Layer 150 Protective film 160 Passivation Film 180 resin layer 181 Inner resin layer 182 Outer resin layer 183 Separation groove 184 First resin opening 185 Second resin opening 500 Inverter Device 501,502 Switching element 503 ECU GND1,GND2 Ground i current i 1A ,i 1B current i 2A ,i 2B current i CA ,i CB current SD conductive adhesive V1 First voltage V2 Second voltage W1~W4 wires

Claims

1. an insulating layer; a transformer including: a first coil embedded in the insulating layer, having a first signal end and a first ground end, and configured so that a low voltage can be applied to the first signal end; and a second coil embedded at a distance from the first coil in a thickness direction of the insulating layer, having a second signal end and a second ground end, and configured so that a high voltage can be applied to the second signal end; a capacitor having a first capacitor electrode disposed between the first coil and the second coil and connected to the first ground terminal, and a second capacitor electrode disposed between the first capacitor electrode and the second coil and connected to the second ground terminal; An isolation transformer equipped with

2. When viewed from the thickness direction, the first capacitor electrode is disposed so as to overlap the first coil; the second capacitor electrode is disposed so as to overlap the second coil; The isolation transformer according to claim 1 .

3. the insulating layer has a plurality of insulating films stacked in the thickness direction, the first coil, the second coil, the first capacitor electrode, and the second capacitor electrode are formed on the insulating film at different positions in the thickness direction, At least one insulating film is interposed between the first coil and the first capacitor electrode, At least one insulating film is interposed between the second coil and the second capacitor electrode, At least one insulating film is interposed between the first capacitor electrode and the second capacitor electrode. The isolation transformer according to claim 1 or 2.

4. the first coil is embedded in a first coil groove that penetrates the insulating film in the thickness direction, the second coil is embedded in a second coil groove that penetrates the insulating film in the thickness direction. The isolation transformer according to claim 3 .

5. the first capacitor electrode is embedded in a first capacitor groove that penetrates the insulating film in the thickness direction; the second capacitor electrode is embedded in a second capacitor groove that penetrates the insulating film in the thickness direction; The insulating transformer according to claim 3 or 4.

6. 6. The isolation transformer according to claim 1, wherein at least one of the first capacitor electrode and the second capacitor electrode is formed from a material containing a non-magnetic substance.

7. the first capacitor electrode is formed in an open annular shape having a first slit extending in a direction from a center of the first coil toward an outside of the first coil when viewed in the thickness direction, the second capacitor electrode is formed in an open annular shape having a second slit extending in a direction from the center of the second coil toward the outside of the second coil when viewed in the thickness direction; The isolation transformer according to any one of claims 1 to 6.

8. the first coil has a first coil wiring formed in a spiral shape, the first ground terminal to which one end of the first coil wiring is connected, and the first signal terminal to which the other end of the first coil wiring is connected, The second coil has a second coil wiring formed in a spiral shape, the second ground terminal to which one end of the second coil wiring is connected, and the second signal terminal to which the other end of the second coil wiring is connected. The isolation transformer according to any one of claims 1 to 6.

9. the first capacitor electrode has, when viewed in the thickness direction, a first electrode wiring formed to overlap the first coil wiring, a first capacitor end formed to overlap the first signal end, and a first capacitor ground end formed to overlap the first ground end; When viewed from the thickness direction, the second capacitor electrode has a second electrode wiring formed to overlap the second coil wiring, a second capacitor end formed to overlap the second signal end, and a second capacitor ground end formed to overlap the second ground end. The isolation transformer according to claim 8.

10. the first electrode wiring is set to the same line width / line spacing ratio as the first coil wiring, the second electrode wiring is set to the same line width / line spacing ratio as the second coil wiring; The isolation transformer according to claim 9.

11. the first capacitor electrode is formed in a plate shape that is continuous from an inner end portion to an outer end portion of the first coil wiring when viewed in the thickness direction, the second capacitor electrode is formed in a plate shape that is continuous from an inner end portion to an outer end portion of the second coil wiring when viewed in the thickness direction; The isolation transformer according to claim 8.

12. 11. The isolation transformer according to claim 9, wherein outer ends of the second electrode wiring are disposed outwardly of outer ends of the second coil wiring when viewed from the thickness direction.

13. 11. The isolation transformer according to claim 9, wherein an outer end of the second electrode wiring is disposed at the same position as an outer end of the second coil wiring when viewed from the thickness direction.

14. 14. The isolation transformer according to claim 12, wherein an inner end portion of the second electrode wiring is disposed at the same position as an inner end portion of the second coil wiring when viewed from the thickness direction.

15. 14. The isolation transformer according to claim 12, wherein an inner end portion of the second electrode wiring is disposed more inward than an inner end portion of the second coil wiring when viewed from the thickness direction.

16. 16. The isolation transformer according to claim 12, wherein outer ends of the first electrode wiring are disposed outwardly of outer ends of the first coil wiring when viewed from the thickness direction.

17. 16. The isolation transformer according to claim 12, wherein, when viewed from the thickness direction, an outer end of the second electrode wiring is disposed at the same position as an outer end of the second coil wiring.

18. 18. The isolation transformer according to claim 16, wherein an inner end portion of the first electrode wiring is disposed at the same position as an inner end portion of the first coil wiring when viewed from the thickness direction.

19. 18. The isolation transformer according to claim 16, wherein an inner end portion of the first electrode wiring is disposed more inward than an inner end portion of the first coil wiring when viewed from the thickness direction.

20. the isolation transformer has a chip main surface and a chip back surface facing opposite to each other in the thickness direction, the second coil is disposed near the main surface of the chip; 20. The isolation transformer according to claim 1, further comprising a dummy coil pattern disposed around the second coil and connected to the second coil.

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