Semiconductor device and manufacturing method thereof

Abstract

Even if an alignment mark is misread, the variations in the forward voltage and on-resistance can be reduced and stabilized. [Solution] The semiconductor device comprises an n-type SiC drift layer, a p-type base region 7, an n-type source region 8 selectively embedded in the upper part of the base region 7, p-type base contact regions 9a, 9b selectively embedded in the upper part of the base region 7 so as to form a first gap between the source region 8 along the <11-20> direction and the base region 7, a gate electrode 11 provided via a gate insulating film 10, and an n-type drain region. The upper surface of the drain region is <0001> The drift layer and base region 7 are epitaxially grown films, and the width wg of the first gap is set according to the misalignment of the alignment mark caused by the off-axis angle and epitaxial growth.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Photolithography is used in the manufacturing process of semiconductor devices such as field-effect transistors (MOSFETs) made from silicon carbide (SiC). In photolithography, alignment is important when fabricating various semiconductor layers on a semiconductor substrate, and alignment is often achieved by reading alignment marks formed on the semiconductor substrate by etching or other methods. Semiconductor substrates generally come in two types: epitaxial substrates, which have an epitaxially grown film, and bulk substrates, which do not. When epitaxial growth is performed only on the entire surface of a semiconductor substrate, alignment marks are not formed because an orientation flat already exists. Alignment marks are formed when alignment becomes necessary when fabricating various semiconductor layers on a semiconductor substrate during the semiconductor device manufacturing process.

[0003] To read alignment marks, a fixed-shape area on a semiconductor substrate containing the alignment marks is typically photographed, and the photographed image data is analyzed by a reading device using a predetermined technique such as brightness analysis. The position of the alignment mark is determined through the analysis, and the determined position information of the alignment mark is input into a semiconductor substrate positioning device. The input position information is combined with the design data for the semiconductor substrate to determine the ion implantation position and trench excavation position in subsequent processes.

[0004] When epitaxial growth is performed on a base semiconductor substrate, the shape of the alignment mark initially engraved on the top surface of the SiC semiconductor substrate is also transferred to the top surface of the epitaxially grown film deposited on the semiconductor substrate. Additionally, if the top surface of the semiconductor substrate has an off-axis angle, the initial alignment mark is transferred so that its pattern is distorted in the off-axis direction during epitaxial growth. Therefore, the position of the transferred upper alignment mark is shifted by a certain amount in the direction parallel to the main surface of the semiconductor substrate from the position of the initial lower alignment mark.

[0005] When misalignment of multiple alignment marks occurs due to the off-angle and epitaxial growth, the alignment marks appear to overlap in an image taken vertically from above the semiconductor substrate toward the top surface of the semiconductor substrate. Therefore, the alignment marks selected by the reading device during multiple reading operations on the same semiconductor substrate may not always be the same, and different alignment marks may be selected. If different alignment marks are selected in successive photolithography processes, there is a concern that misalignment (known as "lithographic misalignment") may occur between the semiconductor layers being fabricated.

[0006] For example, Patent Document 1 discloses a semiconductor device in which a base contact region is formed in an opening in the center of a source region. When these source and base contact regions are fabricated consecutively using photolithography, if the n-type impurity ion implanted region that forms the source region and the p-type impurity ion implanted region that forms the base contact region overlap, the conductivity types are offset in the overlapping region. In particular, if the source and base contact regions are implanted with approximately the same impurity concentration, the overlapping region of the implanted ions cannot fully achieve the contact performance of the base contact region. This increases the contact resistance, which in turn increases the forward voltage Vf and on-resistance Ron of the body diode, resulting in variations in the forward voltage Vf and on-resistance Ron.

[0007] One way to avoid this problem is to form alignment marks on the top surface of the semiconductor layer located at the top of the semiconductor substrate each time epitaxial growth is performed, and use these marks for reading, thereby preventing misreading of the alignment marks. However, this increases the number of photolithography processes required to form many alignment marks, which increases the manufacturing burden.

[0008] Another possible method is to place a separate reader on the underside of the semiconductor substrate and read the alignment marks from above and below separately, thereby avoiding interference with the shape of the alignment mark transferred to the upper side and reading the first alignment mark on the lower side.However, since the reading devices installed in existing manufacturing equipment are very often the type that photographs and reads the alignment mark positions from the upper side of the semiconductor substrate, installing a separate reading device would require new capital investment, which would increase costs. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-219161 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above-mentioned problems, the present invention aims to provide a semiconductor device and a manufacturing method thereof that can reduce variations in forward voltage Vf and on-resistance Ron and stabilize them even if misreading of an alignment mark occurs. [Means for solving the problem]

[0011] In one aspect of the present invention, a semiconductor chip is provided with a plurality of trenches on an upper surface thereof, a drift layer made of silicon carbide of a first conductivity type, a base region of a second conductivity type provided on the drift layer, and a semiconductor device comprising: By ion implantationa first main electrode region of a first conductivity type having a higher impurity concentration than the selectively provided drift layer; and a first main electrode region on the base region. By ion implantation a base contact region of a second conductivity type having a higher impurity concentration than the base region, which is selectively provided; a first main electrode electrically connecting to the first main electrode region and the base contact region; a step of forming a semiconductor layer from a drift layer to an upper surface of a semiconductor chip by epitaxial growth, and a step of forming a base contact region between first main electrode regions in a <11-20> direction as viewed from above, wherein the trenches extend along the <11-20> direction as viewed from above, and in the step of forming the base contact region, the base contact region is formed to have a first width in the <11-20> direction that is greater than t × tan θ, where t is a thickness of an epitaxially grown film formed by epitaxial growth and θ is an off-angle of the epitaxially grown film. In the step of forming the base contact region, the first main electrode region and the base contact region overlap, and a non-contact region is provided in at least a portion thereof, where impurities of respective conductivity types are offset by ion implantation into the first main electrode region and the base contact region, resulting in a low impurity density. The gist is that it is a method for manufacturing a semiconductor device.

[0012] Another aspect of the present invention is a semiconductor device having a plurality of trenches provided in an upper surface of a semiconductor chip, the semiconductor device including: a drift layer made of silicon carbide of a first conductivity type; a base region of a second conductivity type provided on the drift layer; a first main electrode region of the first conductivity type selectively provided on the base region and having a higher impurity concentration than the drift layer; and a base contact region of the second conductivity type selectively provided on the base region and having a higher impurity concentration than the base region. a first main electrode electrically connecting to the first main electrode region and the base contact region; a semiconductor layer from the drift layer to the top surface of the semiconductor chip is formed of an epitaxially grown film, The first main electrode region and the base contact region have an impurity density that decreases in a depth direction from the top surface of the semiconductor chip, The base contact region is provided between the first main electrode regions in the <11-20> direction in a top view, and the plurality of trenches extend along the <11-20> direction in a top view. When the thickness of an epitaxially grown film formed by epitaxial growth is t and the off-angle of the epitaxially grown film is θ, the base contact region has a first width in the <11-20> direction that is larger than t × tan θ. The first main electrode region and the base contact region overlap, and a non-contact region is provided in at least a portion thereof, where impurities of respective conductivity types in the first main electrode region and the base contact region cancel each other out, resulting in a low impurity density. The gist is that it is a semiconductor device. [Effects of the Invention]

[0013] According to the present invention, it is possible to provide a semiconductor device and a manufacturing method thereof that can reduce and stabilize variations in forward voltage Vf and on-resistance Ron even if misreading of an alignment mark occurs. [Brief explanation of the drawings]

[0014] [Figure 1] 3 is a cross-sectional view of a main part seen in the direction along line AA in FIG. 2, schematically illustrating an outline of the structure of the semiconductor device according to the first embodiment. [Figure 2] 1 is a plan view schematically illustrating the structure of a semiconductor device according to a first embodiment, excluding a region above an SiC semiconductor layer. [Figure 3] 3 is a cross-sectional view of a main part taken along the line BB in FIG. 2. [Figure 4] 1 is a plan view schematically illustrating an outline of the structure of a semiconductor wafer used in manufacturing a semiconductor device according to a first embodiment. [Figure 5] FIG. 2 is a plan view schematically showing the arrangement of trenches in the semiconductor device according to the first embodiment. [Figure 6] 5 is a cross-sectional view of a main part taken along line CC in FIG. 4, for schematically explaining a state of misalignment of an alignment mark caused by an off-angle and epitaxial growth. FIG. [Figure 7] FIG. 10 is a plan view schematically illustrating two alignment marks in which misalignment has occurred, as viewed from above. [Figure 8] 10A and 10B are cross-sectional views of essential parts for schematically explaining a method for setting the positional misalignment width of an alignment mark. [Figure 9] 10A to 10C are cross-sectional views for schematically explaining a method for setting alignment marks used for positioning. [Figure 10] FIG. 10(a) is a graph illustrating the positional deviation width in the <11-20> direction, and FIG. 10(b) is a graph illustrating the positional deviation width in the <1-100> direction. [Figure 11] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a first embodiment. [Figure 12] 12A to 12C are cross-sectional views illustrating steps in a semiconductor device manufacturing method, following FIG. [Figure 13] 13A to 13C are cross-sectional views illustrating steps in a semiconductor device manufacturing method, following FIG. [Figure 14] 14A to 14C are cross-sectional views illustrating steps in a semiconductor device manufacturing method, following FIG. [Figure 15] 15A to 15C are cross-sectional views illustrating steps in a semiconductor device manufacturing method, following FIG. [Figure 16] 16A to 16C are cross-sectional views illustrating steps in a semiconductor device manufacturing method, following FIG. [Figure 17] 15A to 15C are cross-sectional views illustrating steps in a semiconductor device manufacturing method when an alignment mark is misread. [Figure 18] 18A to 18D are cross-sectional views illustrating steps in a semiconductor device manufacturing method when an alignment mark is misread. [Figure 19] 19A to 19C are cross-sectional views illustrating steps in a semiconductor device manufacturing method when an alignment mark is misread. [Figure 20] 17A to 17C are cross-sectional views illustrating steps in a semiconductor device manufacturing method, following FIG. 16. [Figure 21] 21A to 21C are cross-sectional views illustrating steps in a semiconductor device manufacturing method, following FIG. 20. [Figure 22] 10A and 10B are diagrams for explaining the impurity density profiles of the source region and the base contact region in a semiconductor device having no gap; [Figure 23] 4A and 4B are diagrams illustrating the impurity density profiles of the source region and the base contact region in the semiconductor device according to the first embodiment in which a gap is provided. [Figure 24] 10 is a plan view schematically illustrating the structure of a semiconductor device according to a second embodiment, excluding a region above an SiC semiconductor layer. FIG. [Figure 25]FIG. 26 is a cross-sectional view of a main part as seen from the direction along the line DD in FIG. 25. [Figure 26] FIG. 10 is a graph diagram illustrating a profile of impurity density in a source region and a base contact region in the semiconductor device according to the second embodiment. [Figure 27] 10A to 10C are cross-sectional views illustrating the steps of a method for manufacturing a semiconductor device according to a second embodiment when an alignment mark is misread; [Figure 28] 28 is a process cross-sectional view following FIG. 27, which schematically shows an outline of the method for manufacturing a semiconductor device. [Figure 29] 10A to 10C are cross-sectional views illustrating the steps of a semiconductor device manufacturing method according to a comparative example when an alignment mark is misread; [Figure 30] 29A to 29C are cross-sectional views illustrating steps in a semiconductor device manufacturing method. [Figure 31] FIG. 10 is a plan view schematically illustrating the structure of a semiconductor device according to a modified example, excluding the region above an SiC semiconductor layer. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, first and second embodiments of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0016] In this specification, the term "first main electrode region" refers to a semiconductor region that becomes either the source region or the drain region in an insulated gate FET (MISFET) or an insulated gate static induction transistor (MISSIT). In an insulated gate bipolar transistor (IGBT), it refers to a semiconductor region that becomes either the emitter region or the collector region. In an MIS gate static induction thyristor (MIS gate SI thyristor), it refers to a semiconductor region that becomes either the anode region or the cathode region.

[0017] The "second main electrode region" means a semiconductor region that becomes either the source region or the drain region, not the first main electrode region, in a MISFET or MISSIT. In an IGBT, it means a region that becomes either the emitter region or the collector region, not the first main electrode region. In a MIS gate SI thyristor, it means a region that becomes either the anode region or the cathode region, not the first main electrode region. In other words, if the "first main electrode region" is the source region, the "second main electrode region" means the drain region. If the "first main electrode region" is the emitter region, the "second main electrode region" means the collector region. If the "first main electrode region" is the anode region, the "second main electrode region" means the cathode region.

[0018] In the following description of the embodiments, the first conductivity type is n-type and the second conductivity type is p-type. However, the conductivity types may be reversed, with the first conductivity type being p-type and the second conductivity type being n-type. In this specification and the accompanying drawings, the superscripts + and - attached to n and p indicate semiconductor regions with relatively higher or lower impurity densities, respectively, compared to semiconductor regions without the + or - designation. Furthermore, in the following description, it is technically and logically self-evident that components and regions designated with the designations "first conductivity type" and "second conductivity type" refer to components and regions made of semiconductor material, even without any explicit designation. In this specification, in Miller index notation, "-" refers to a bar attached to the index immediately following it, and adding "-" before an index indicates a negative index.

[0019] Furthermore, in the following explanation, the definitions of "upper" and "lower" in "upper surface" and "lower surface" are merely a matter of representation in the cross-sectional views shown. For example, if the orientation of the semiconductor device is changed by 90 degrees and observed, the terms "upper" and "lower" become "left" and "right," and of course, if the orientation is changed by 180 degrees and observed, the relationship between the terms "upper" and "lower" is reversed.

[0020] -First embodiment- <Structure of semiconductor device> As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention is a semiconductor device having a first conductivity type (n - The MOSFET is a trench gate type MOSFET having a drift layer 2 of a second conductivity type (p-type) and a base region 7 of a second conductivity type (p-type) arranged on the upper surface side of the drift layer 2. The upper part of the base region 7 is doped with n-type impurities having a higher impurity density than the drift layer 2. + A first main electrode region (source region) 8 of a silicon nitride type is provided. A trench 21 is provided penetrating the source region 8 and the base region 7, and a gate insulating film 10 is provided on the bottom and side surfaces of the trench 21.

[0021] A buried gate electrode 11 is buried in the trench 21 via a gate insulating film 10 provided so as to contact the base region 7. Since the semiconductor device according to the first embodiment is a MOSFET, an n-type electrode 11 is provided on the lower surface side of the drift layer 2. + A second main electrode region (drain region) 1 of the type is disposed in the trench 21. For convenience, Fig. 1 shows a cross section of a main part of a unit cell structure including one trench 21, but it is possible to pass a large current by periodically arranging a plurality of such unit cell structures to form a multi-channel structure.

[0022] The upper portion of the base region 7 is in contact with the source region 8, and a p + The upper portion of the drift layer 2 is provided with n-type base contact regions 9a and 9b, which are sandwiched between the lower portion of the drift layer 2 and the base region 7. +An n-type current spreading layer (CSL) 3 is formed on the drift layer 2. The current spreading layer 3 is formed by introducing n-type impurities into the upper part of the drift layer 2, and has the function of reducing the spreading resistance of carriers. Note that the current spreading layer 3 may be omitted, and the upper surface of the drift layer 2 may be in contact with the base region 7 at the upper surface of the current spreading layer 3.

[0023] In order to protect the gate insulating film 10 at the bottom of the trench 21 from a high voltage at the time of reverse bias, a p + On the other hand, a p type gate bottom protection region 4 is disposed on the bottom surface side of the base region 7 below the base contact regions 9a and 9b. + The mold base bottom buried regions (5a, 6a) and (5b, 6b) are respectively arranged in the mold base bottom buried regions (5a, 6a) and (5b, 6b). The cross-sectional shape of the base bottom buried regions (5a, 6a) and (5b, 6b) is approximately rectangular.

[0024] The base bottom buried region (5a, 6a) has a rectangular pattern including a first buried region 5a consisting of a first rectangle and a second buried region 6a consisting of a second rectangle that is disposed on the upper surface of the first buried region 5a and in contact with the lower surface of the base region 7. The base bottom buried region (5b, 6b) has a rectangular pattern including a first buried region 5b consisting of a first rectangle and a second buried region 6b consisting of a second rectangle that is disposed on the upper surface of the first buried region 5b and in contact with the lower surface of the base region 7. The upper surfaces of the first buried regions 5a, 5b are provided at the same depth as the upper surface of the gate bottom protection region 4.

[0025] The drain region 1 is made of a semiconductor substrate (SiC substrate) made of SiC, and the drift layer 2 is made of an epitaxial layer (SiC layer) made of SiC. In addition to SiC, semiconductor materials with a band gap wider than 1.1 eV of Si, such as gallium nitride (GaN), diamond, or aluminum nitride (AlN), can be used for the drain region 1 and the drift layer 2.

[0026] The reported bandgap widths at room temperature are 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, 3.02 eV for 6H-SiC, 3.4 eV for GaN, 5.5 eV for diamond, and 6.2 eV for AlN. Wide bandgap semiconductors with a bandgap width of 2.0 eV or more can be used for the drain region 1 and drift layer 2, etc., but in LEDs and the like, a bandgap width of 2.5 eV or more is often defined as a "wide bandgap." In this invention, the bandgap width of wide bandgap semiconductors will be explained based on the bandgap width of 2.23 eV for 3C-SiC at room temperature.

[0027] The bottom of the trench 21 that penetrates the source region 8 and the base region 7 in the depth direction reaches the current spreading layer 3. Although Fig. 1 illustrates an example in which the bottom surface of the trench 21 is flat, the bottom surface of the trench 21 may be curved. In terms of planar pattern, the trenches 21 of each unit cell structure are arranged in a stripe pattern as shown in Fig. 2, but may also have a rectangular planar pattern or a polygonal planar pattern such as a hexagon.

[0028] The gate insulating film 10 may be a silicon oxide film (SiO2 film), a silicon oxynitride (SiON) film, a single-layer film with a higher dielectric constant than SiO2 film, or a composite film made by laminating multiple layers of these. Specifically, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, an yttrium oxide (Y2O3) film, or the like may be used. Other possible films include a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, and a bismuth oxide (Bi2O3) film.

[0029] The buried gate electrode 11 may be made of, for example, a polysilicon layer (doped polysilicon layer) to which impurities are added at a high concentration. A first main electrode (source electrode) 16 is disposed on the buried gate electrode 11 via an interlayer insulating film 12, separated from a gate surface electrode (not shown) located at the back of the page. The source electrode 16 is electrically connected to the source region 8 and base contact regions 9a and 9b.

[0030] As shown in FIG. 1 , the source electrode 16 includes source contact layers 13a and 13b, a lower barrier metal layer 14, and an upper barrier metal layer 15 below it. The source contact layers 13a and 13b are disposed so as to be metallurgically in contact with the base contact regions 9a and 9b, respectively. The lower barrier metal layer 14 is disposed so as to be metallurgically in contact with the source region 8 and to cover the interlayer insulating film 12. The upper barrier metal layer 15 is disposed so as to cover the source contact layers 13a and 13b and the lower barrier metal layer 14, and the source electrode 16 is disposed so as to cover the upper barrier metal layer 15. For example, the source contact layers 13a and 13b may be nickel (Ni) silicide films, the lower barrier metal layer 14 may be a titanium nitride (TiN) film, and the upper barrier metal layer 15 may be a titanium (Ti) / TiN / Ti laminated structure. The source electrode 16 may be an aluminum (Al) film, and the gate surface electrode may be made of the same material as the source electrode 16.

[0031] A second main electrode (drain electrode) 17 is disposed on the lower surface of the drift layer 2 so as to contact the drift layer 2. The drain electrode 17 may be, for example, a single layer film made of gold (Au) or a metal film laminated in this order of Al, nickel (Ni), and Au, with a metal plate such as molybdenum (Mo) or tungsten (W) laminated on the bottom layer. Both the drift layer 2 and the base region 7 are epitaxially grown films.

[0032] During operation of the semiconductor device according to the first embodiment, when a positive voltage is applied to the drain electrode 17 and a positive voltage equal to or greater than a threshold value is applied to the buried gate electrode 11, an inversion layer (channel) is formed in the base region 7 on the side of the buried gate electrode 11, resulting in an ON state. In the ON state, a current flows from the drain electrode 17 to the source electrode 16 via the drain region 1, the drift layer 2, the inversion layer in the base region 7, and the source region 8. On the other hand, when the voltage applied to the buried gate electrode 11 is less than the threshold value, no inversion layer is formed in the base region 7, resulting in an OFF state and no current flowing from the drain electrode 17 to the source electrode 16.

[0033] As shown in FIG. 2, two first gaps with approximately the same width wg are provided at both ends in the <11-20> direction between the base contact regions 9a and 9b and the source region 8. The upper surface of the base region 7 is exposed inside the first gaps. The first gaps are provided to contact the upstream off-state end and downstream off-state end of the base contact regions 9a and 9b, respectively, located at the upper and lower ends in FIG. 2. The width of the first gaps in the <1-100> direction, which is perpendicular to the extension direction of the trench 21, is approximately the same as the width of the base contact regions 9a and 9b. The base contact regions 9a and 9b have a width wp along the <11-20> direction. As shown in FIG. 3, the base contact regions 9a and 9b are located in the central region inside the opening formed between adjacent source regions 8.

[0034] As shown in FIG. 4, the semiconductor device according to the first embodiment is fabricated based on a semiconductor wafer 100 made of SiC. An orientation flat 101 indicating the crystal orientation of the semiconductor wafer 100 is provided on the outer periphery of the semiconductor wafer 100. The semiconductor wafer 100 is sliced ​​along a direction that forms a plane inclined by a certain offset angle (off angle) θ relative to a specific crystal orientation, and the position of the orientation flat 101 is determined by the crystal orientation. Instead of the orientation flat 101, a notch may be provided on the outer periphery of the semiconductor wafer 100. A semiconductor chip 103 is illustrated on a surface 102 of the semiconductor wafer 100 shown in FIG. 4. Furthermore, as shown in FIG. 5, a trench 21 extends in a stripe shape on the top surface of the semiconductor chip 103 along the <11-20> direction. The crystal plane of the sidewall of the trench is the (11-20) a-plane or the (1-100) m-plane.

[0035] As shown in FIG. 6, in the semiconductor device according to the first embodiment, the upper surface of the drain region 1 is <0001> The drain region 1 has an off-axis angle θ of approximately 4° to 8° in the <11-20> direction with respect to the (c-axis) direction. The off-axis angle θ is the angle between a plane (basal plane) perpendicular to the c-axis, which is the (0001) Si-plane or the (000-1) C-plane, and the surface 102 of the semiconductor wafer 100. An alignment mark 104 for positioning is provided on the upper surface of the drain region 1. When the drift layer 2 is epitaxially grown on the drain region 1, an alignment mark 104a is formed on the upper surface of the drift layer 2, which is formed by transferring the initial alignment mark 104 on the upper surface toward the off-axis upstream side with a certain distance in a direction parallel to the main surface. While FIG. 6 shows the alignment mark 104 for positioning provided on the upper surface of the drain region 1, the epitaxial growth may be performed by providing the alignment mark 104 for positioning on the upper surface of the drift layer 2 of a semiconductor substrate on which the epitaxially grown drift layer 2 is provided on the drain region 1. Similarly, in other embodiments, alignment marks 104 for positioning may be provided on the upper surface of drift layer 2 of a semiconductor substrate having epitaxially grown drift layer 2 provided in drain region 1, and epitaxial growth may be performed.

[0036] <Setting the position offset width> Next, a method for setting the misalignment width will be described. Fig. 7 illustrates an example in which, for example, a single epitaxially grown film is formed as a drift layer 2 on the drain region 1 on which the initial alignment mark 104 is formed. When the initial alignment mark 104 and the transferred alignment mark 104a, which are misaligned as shown in Fig. 7, are viewed from the front of the main surface of the semiconductor device, two alignment marks of the same shape are observed.

[0037] 8, the height between the surface 102 of the drain region 1 and the surface 102a of the deposited drift layer 2 is set as the thickness of the epitaxially grown film. If an epitaxially grown film is further added on the drift layer 2, the sum of the thicknesses of all the epitaxially grown films including the additional epitaxially grown film is used to set the misalignment width as the "thickness t of the epitaxially grown film."

[0038] In the first embodiment, the misalignment width Δx of the alignment mark caused by the off-angle θ and the epitaxial growth is calculated by using the thickness t and the off-angle θ as follows: Δx=t×tanθ (1) It is set as follows.

[0039] For example, when the sum of the thicknesses t of all epitaxially grown films is 1.6 μm and the off-angle θ is 4°, the misalignment width Δx can be set to approximately 0.112 μm from equation (1). In the semiconductor device according to the first embodiment, the width wp of the base contact region 9 a in the <11-20> direction is set so that the width wg of the first gap is equal to or greater than the misalignment width Δx.

[0040] The upper limit of the misalignment width Δx is selected to be the smaller of the sum of the thicknesses t of the epitaxially grown films or the width of the base contact region 9a, because if the upper limit is larger than the width of the base contact region 9a, the proportion of the region that can effectively make contact becomes too low.

[0041] 9, the present inventors conducted an experiment to measure the width of misalignment when alignment was performed using different alignment marks AM1 to AM3. Specifically, first, alignment mark AM1 was formed on the upper surface of drain region 1, alignment mark AM2 was formed at the same height as the upper surfaces of first buried regions 5a and 5b, and alignment mark AM3 was formed at the same height as the upper surfaces of second buried regions 6a and 6b. Then, just before fabricating first buried regions 5a and 5b, second buried regions 6a and 6b, and trench 21, alignment was performed by changing alignment marks AM1 to AM3 read by a reading device under the following conditions (1) to (3):

[0042] (1) In the fabrication of the first buried regions 5a and 5b, the second buried regions 6a and 6b, and the trench 21, the alignment mark AM1 was commonly used. (2) The alignment mark AM1 was used to fabricate the first buried regions 5a and 5b, and the alignment mark AM2 was commonly used to fabricate the second buried regions 6a and 6b and the trench 21. (3) Alignment mark AM1 was used to form the first buried regions 5a and 5b, alignment mark AM2 was used to form the second buried regions 6a and 6b, and alignment mark AM3 was used to form the trench 21. The alignment marks were not shared.

[0043] Figure 10(a) shows the misalignment width (misalignment width) of trench 21 in the <11-20> direction measured under each of the above conditions, and Figure 10(b) shows the misalignment width (misalignment width) of trench 21 in the <1-100> direction. Also, in Figures 10(a) and 10(b), the case of p-type epitaxially grown film is shown by a solid line, and the case of n-type epitaxially grown film is shown by a dotted line. The thickness of the epitaxially grown film used in the experiment was approximately 1.1 μm.

[0044] As can be seen from comparing Figures 10(a) and 10(b), the misalignment width Δx in the <11-20> direction is much larger than that in the <1-100> direction. It can also be seen that the misalignment width Δx for the p-type epitaxially grown film, shown by the solid line, is larger than that for the n-type epitaxially grown film, shown by the dashed line. Considering the results shown in Figures 10(a) and 10(b), the inventors conducted research with the aim of continuing to use the initial alignment mark 104 on the top surface of the drain region 1 in subsequent processes. As a result, they completed the present invention, which realizes the common use of alignment marks by setting the misalignment width Δx defined by the above formula (1) and performing subsequent photolithography processes, thereby reducing the number of processes while suppressing the effects of lithography misalignment.

[0045] <Method of manufacturing a semiconductor device> Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to Figures 11 to 21. Note that the method for manufacturing the trench-gate MOSFET described below is one example, and it goes without saying that various other manufacturing methods can be used within the scope of the spirit of the claims.

[0046] First, n-type impurities such as nitrogen (N) are added. + A SiC substrate of this type is prepared. In the following description, the SiC substrate is a 4H—SiC substrate with an off-axis angle of 4°. + As shown in FIG. 11, a type SiC substrate is used as the drain region 1, and an n - The drift layer 2 of the mold is epitaxially grown. Due to the epitaxial growth, the top surface of the drift layer 2 also has an off-angle of 4°.

[0047] Next, n-type impurity ions such as nitrogen (N) are implanted into the entire surface of the drift layer 2 from the upper surface side of the drift layer 2 in multiple stages. After that, the implanted n-type impurity ions are activated by heat treatment, and as shown in FIG. +A current spreading layer 3 having a 4° off-angle is formed on the drift layer 2. The current spreading layer 3 may be epitaxially grown on the upper surface of the drift layer 2, and the epitaxial growth of the current spreading layer 3 also gives the upper surface of the current spreading layer 3 an off-angle of 4°. The current spreading layer 3 does not necessarily have to be formed, and the following steps may be performed on the drift layer 2.

[0048] Next, to form the first buried regions 5a and 5b shown in FIG. 1, a photoresist film is applied to the current spreading layer 3 and patterned using photolithography. Using the patterned photoresist film as an ion implantation mask, p-type impurity ions such as Al are implanted deep into the current spreading layer 3 in multiple stages. The photoresist film is then removed by wet processing or the like.

[0049] Furthermore, to form the gate bottom protection region 4 shown in Figure 1, a new photoresist film is applied to the current spreading layer 3 and patterned using photolithography. Using the patterned photoresist film as an ion implantation mask, p-type impurity ions such as Al are implanted in multiple stages perpendicular to the top surface of the current spreading layer 3, at positions shallower than the previous implantation. The photoresist film is then removed by wet processing or the like.

[0050] Furthermore, to form the second buried regions 6a and 6b shown in FIG. 1, a new photoresist film is applied to the current spreading layer 3 and patterned using photolithography. Using the patterned photoresist film as an ion implantation mask, p-type impurity ions such as Al are implanted in multiple stages. The photoresist film is then removed by wet processing or the like.

[0051] Subsequently, the implanted p-type impurity ions are activated by heat treatment, and p + The gate bottom protection region 4 is selectively formed. Furthermore, a p + The first buried regions 5a and 5b of the p-type are formed as rectangular regions. At the same time, the p-type first buried regions 5a and 5b are formed on the top of the current spreading layer 3.+ Since the second buried regions 6a, 6b of the mold are selectively formed as rectangular regions, the base bottom buried regions (5a, 6a), (5b, 6b) are formed in a pattern with rectangular units.

[0052] Next, as shown in Figure 13, a p-type base region 7 is epitaxially grown on the top surface of the current spreading layer 3. As a result of this epitaxial growth, the top surface of the base region 7 also has an off-angle of 4°. Next, the position of the alignment mark on the drain region 1 is read using a reading device, and the semiconductor substrate is positioned using the read position information. A photoresist film (not shown) is then applied to the base region 7, and the photoresist film is patterned using photolithography to have openings in a planar pattern.

[0053] 14, the patterned photoresist film is used as an ion implantation mask to perform multi-stage ion implantation of n-type impurity ions such as N to form a first planned region 8p that will become the source region 8. Because the n-type impurity ions are not implanted into the openings in the photoresist film, the first planned region 8p is selectively formed so that the region where the base region 7 will remain has an opening in the planar pattern. The photoresist film is then removed by wet processing or the like.

[0054] Next, the position of the alignment mark on the drain region 1 is read again using the reading device, and the semiconductor substrate is positioned using the read position information. Then, as shown in Fig. 15, a new photoresist film is applied to the upper surfaces of the base region 7 and the first planned region 8p, and the new photoresist film is patterned using photolithography to form an ion implantation mask 31.

[0055] The ion implantation mask 31 is formed by selectively patterning a photoresist film so that the edges of the openings in the <11-20> direction extend into the openings of the adjacent first planned regions 8p and cover the edges of the openings of the first planned regions 8p. The overhang widths w1 and w2 at both ends of the ion implantation mask 31 are controlled in advance so that the activated base contact region 9a extends beyond the edges of the openings of the source regions 8 by a predetermined misalignment width Δx or more. Multi-stage ion implantation of p-type impurity ions such as Al is performed from the upper surface of the drift layer 2 through the ion implantation mask 31 to form the second planned regions 9ap that will become the base contact regions. That is, the p-type impurity ions are implanted into the central regions of the openings of the adjacent first planned regions 8p, each having a width w8p in FIG. 15 , excluding the portions having the left overhang width w1 and the right overhang width w2.

[0056] Thereafter, the first planned region 8p and the second planned region 9ap are activated by heat treatment, and as shown in FIG. 16, n + Type source region 8 and p + The base contact region 9a is formed as shown in FIG. 16. + Type source region 8 and p + The state of the mold base contact region 9a is illustrated.

[0057] Next, a case where a misreading occurs between the reading of the alignment mark immediately before the formation of the first planned region 8p and the reading of the alignment mark immediately before the subsequent formation of the second planned region 9ap will be described with reference to FIGS. 17 to 19. As shown in FIG. 17, due to misalignment of the alignment mark, the opening of the ion implantation mask 31 formed on the base region 7 and the first planned region 8p is formed with a misalignment width Δx between it and the opening of the underlying first planned region 8p. However, as shown in the left portion of the opening in FIG. 17, even if the left edge of the opening of the ion implantation mask 31 is closer to the underlying first planned region 8p by the misalignment width Δx, the overhang width w1 is set to be equal to or greater than the misalignment width Δx. Therefore, even if p-type impurity ions such as Al are implanted from the upper surface of the drift layer 2 through the misaligned ion implantation mask 31, the ions will not overlap with the first planned region 8p and will not be implanted.

[0058] Therefore, by performing a heat treatment thereafter, it becomes possible to form the source region 8 and the base contact region 9a without overlapping each other, as shown in Fig. 18. A left first gap having a width wg1 and a right first gap having a width wg2 are formed at both ends of the base contact region 9a in the left-right direction in Fig. 18, and the width wg2 of the right first gap is equal to or greater than the misalignment width Δx.

[0059] 19, the base contact region 9a may be formed further to the left, up to the position where it contacts the source region 8, but the source region 8 and the base contact region 9a will not overlap. The width wg3 of the first gap on the right side of the base contact region 9a in FIG. 19 is equal to or greater than the misalignment width Δx. The following is an explanation of the subsequent steps following the state described with reference to FIG.

[0060] Next, n + Type source region 8 and p +A photoresist film is applied to the base contact regions 9a and 9b of the mold, and the applied photoresist film is patterned using photolithography. Using the patterned photoresist film 33 as an etching mask, a trench 21 is selectively formed by dry etching such as reactive ion etching (RIE) to penetrate the source region 8 and the base region 7 and reach the top of the current diffusion layer 3, as shown in FIG. 20. Thereafter, the photoresist film 33 is removed by wet processing or the like. Note that the source region 8 and the p + An oxide film may be formed on the base contact regions 9a and 9b of the mold, and the oxide film may be patterned with a photoresist film, and then the trench 21 may be formed by dry etching using the oxide film as an etching mask.

[0061] Next, as shown in FIG. 21, the bottom and side surfaces of the trench 21 and the source region 8 and p + A gate insulating film 10 such as an SiO2 film is formed on the upper surfaces of the mold base contact regions 9a and 9b. Next, a doped polysilicon layer containing a high concentration of impurities such as N is deposited on the gate insulating film 10 by a method such as CVD. The doped polysilicon layer is then etched back to embed the polysilicon layer within the trench 21 via the gate insulating film 10, thereby forming a buried gate electrode 11 made of the doped polysilicon layer.

[0062] Next, an interlayer insulating film such as an SiO2 film is deposited on the buried gate electrode 11 and the gate insulating film 10 by a CVD method or the like. A photoresist film (not shown) is then applied to the interlayer insulating film, and the photoresist film is patterned using photolithography. Using the patterned photoresist film as an etching mask, the interlayer insulating film 12 and the gate insulating film 10 are selectively removed by dry etching so that they remain on the buried gate electrode 11, as shown in FIG. 21, to open a source contact hole. Although not shown, a gate contact hole is also opened in the interlayer insulating film 12 and the gate insulating film 10 at a location different from the source contact hole so that a portion of the gate surface electrode connected to the buried gate electrode 11 is exposed. The photoresist film is then removed by a wet process or the like.

[0063] Next, a metal layer such as a Ni film is deposited by sputtering or vapor deposition, patterned using photolithography and RIE, and then heat-treated by RTA (rapid annealing) at, for example, 1000°C to form source contact layers 13a and 13b. Next, a metal layer such as a TiN film is deposited by sputtering, patterned using photolithography and RIE to form a lower barrier metal layer 14. Next, a metal layer such as a Ti / TiN / Ti / Al film is successively deposited by sputtering. The metal layer such as a Ti / TiN / Ti / Al film is patterned using photolithography and RIE to form a pattern of a source electrode 16 and a gate surface electrode (not shown) with an upper barrier metal layer 15 at the bottom. As a result, the patterns of the source electrode 16 and the gate surface electrode are separated. Next, a drain electrode 17 made of Au or the like is formed on the entire lower surface of the drain region 1 by sputtering or vapor deposition, as shown in FIG. 1. In this way, the semiconductor device according to the first embodiment is completed.

[0064] In the plan view in the middle row of FIG. 22 and the plan view in the middle row of FIG. 23, positions of the same impurity density are shown connected by lines like contour lines. Corresponding positions are shown by dashed lines between the plan view in the middle row and the cross-sectional view in the upper row and the graph in the lower row that sandwich the plan view in the middle row. If the first gap is not provided, as shown in FIG. 22, + The base contact regions 19a and n + The source region 8 of the mold is 3 × 10 inside and outside the boundary, respectively. 20 It is formed with an impurity density of about 1000 or more.

[0065] On the other hand, in the case of the first embodiment in which the first gap is provided, as shown in FIG. 20 p with impurity density of about + The base contact region 9a and n + A low impurity density p-type base region 7 is exposed in the first gap between the p-type source region 8 and the base region 7. The impurity density of the base region 7 is not shown in accordance with the scale of the vertical axis in FIG. 23, but it is 1×10 17 That's about it.

[0066] According to the semiconductor device manufacturing method of the first embodiment, the ion implantation mask 31 used when forming the base contact region 9a extends over the edge of the first planned region 8p, into which n-type impurity ions have been previously implanted, to become the source region 8. The width of the opening in the ion implantation mask 31 is controlled to be narrower than the width w8p of the opening in the first planned region 8p. This extension creates a first gap having widths wg1 and wg2 equal to or greater than the misalignment width Δx of the alignment mark in the <11-20> direction between the base contact region 9a and the source region 8 after activation. Then, p-type impurity ions are implanted through the ion implantation mask 31, thereby forming a small second planned region 9ap, which will become the base contact region 9a, so that the base contact region 9a remains inside the surrounding opening after activation.

[0067] Therefore, even if the alignment mark is misread and the second planned region 9ap is formed shifted from the originally designed position by the alignment mark misalignment width Δx, it is possible to reliably prevent the base contact region 9a and the source region 8 from overlapping after activation. Since there is no change in the forward voltage Vf and the on-resistance Ron due to the misalignment of the base contact region 9a, variations in the forward voltage Vf and the on-resistance Ron can be reduced and stabilized.

[0068] Furthermore, according to the method for manufacturing a semiconductor device according to the first embodiment, it is not necessary to repeatedly form alignment marks, and the initial alignment mark 104 formed on the semiconductor substrate can be used continuously. Therefore, the alignment marks can be shared, and the number of layers used in the photolithography process can be reduced, thereby simplifying the process.

[0069] The misalignment width Δx may be set by further adding a fluctuation range due to the positioning device that positions the semiconductor device. Empirically, a fluctuation range of approximately 0.2 μm is preferable. For example, if the misalignment width Δx due to the off-angle θ and epitaxial growth is approximately 0.112 μm, the misalignment width Δx can be set to approximately 0.312 μm by adding an additional fluctuation range of approximately 0.2 μm. Setting the width of the first gap to a value equal to or greater than this misalignment width Δx can more reliably prevent overlap due to misalignment.

[0070] -Second embodiment- <Structure of semiconductor device> 24, in the semiconductor device according to the second embodiment, a first gap is provided at one end of the lower side of the base contact region 9a in the <11-20> direction. A non-contact region 50 is further provided on the upper side of the base contact region 9a in the <11-20> direction, opposite to the first gap. The non-contact region 50 has a lower impurity concentration than both the base contact region 9a and the source region 8. The base contact region 9a is < 11-20 and the non-contact region 50 has a width wp in the < 11-20The width of the non-contact region 50 in the <1-100> direction is approximately the same as that of the base contact region 9a. As shown in FIG. 25, the top surface of the base region 7 is exposed in the first gap.

[0071] 26, the impurity density of the source region 8 and the impurity density of the base contact region 9a in SiC are approximately the same or close to each other from the surface to a depth of approximately 1.0 μm. Therefore, sufficient contact cannot be achieved in the non-contact region 50 where the source region 8 and the base contact region 9a overlap. The relationship between the impurity density and the penetration depth shown in FIG. 26 also applies to the semiconductor device according to the first embodiment.

[0072] In the second embodiment, the width wp of the base contact region 9a is set so that the sum of the width wp of the base contact region 9a and the width wa of the non-contact region 50 is larger than the misalignment width Δx of the alignment mark caused by the off-angle θ and epitaxial growth. The other configurations of the semiconductor device according to the second embodiment are equivalent to the components with the same names in the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0073] <Method of manufacturing a semiconductor device> The method for manufacturing a semiconductor device according to the second embodiment is the same as that of the first embodiment up to the step of forming the base region 7 above the drain region 1, which was described in the manufacturing method according to the first embodiment with reference to FIGS. 11 to 13. However, in the second embodiment, the step of forming an n-type first planned region 8p, which will become the source region 8, above the base region 7 is performed by controlling the implantation width of the n-type impurity ions so that the width of the opening of the source region 8 in the <11-20> direction after activation is larger than the misalignment width Δx. The second embodiment differs from the first embodiment in that a second planned region 9ap, which will become the base contact region 9a, is formed having an opening with the same width as the opening of the first planned region 8p.

[0074] If the position of the alignment mark read just before forming the first planned region 8p and the position of the alignment mark read just before forming the second planned region 9ap are the same, the first planned region 8p and the second planned region 9ap will not overlap, and no problems will occur. A method for manufacturing a semiconductor device when a misreading occurs and the alignment mark is misaligned will be described in detail below.

[0075] As shown in FIG. 27, if the alignment mark is misread, the opening of the ion implantation mask 35 formed on the base region 7 and the first planned region 8p is formed with a misalignment width Δx relative to the opening of the underlying first planned region 8p. The width of the opening of the first planned region 8p and the width of the opening of the ion implantation mask 35 are the same. Then, as shown in FIG. 28, p-type impurity ions such as Al are implanted toward the upper surface of the base region 7 exposed through the opening and toward a portion of the upper surface of the right end of the left-side first planned region 8p. Through the ion implantation, a p-type second planned region 9ap is formed above the base region 7, and a third planned region 50p, which becomes the non-contact region 50, is formed at the right end of the left-side first planned region 8p in FIG. 27. The p-type and n-type conductivity types cancel each other out within the third planned region 50p, resulting in a very low impurity density.

[0076] In the second embodiment, when forming the first planned region 8p, n-type impurity ions are implanted with a controlled implantation width so that the width of the opening in the source region 8 in the <11-20> direction after activation is greater than the misalignment width Δx. Therefore, even if some p-type impurity ions are implanted so as to overlap the left-side first planned region 8p, a high-concentration p-type second planned region 9ap can be formed between the right-side first planned region 8p, where the implanted ions do not overlap, and the low-impurity-concentration third planned region 50p. Therefore, by performing a subsequent heat treatment, the base contact region 9a can be reliably formed inside the opening in the source region 8. The semiconductor device according to the second embodiment can be completed by performing the subsequent processes similar to those of the manufacturing method according to the first embodiment described with reference to FIGS. 20 and 21 .

[0077] <Comparative Example> On the other hand, if the width of the opening in the source region 8 in the <11-20> direction after activation is equal to or less than the misalignment width Δx, the formation of the base contact region 9a is not guaranteed. Figure 29 illustrates an example in which the implantation width of n-type impurity ions is the same as the misalignment width Δx. In the comparative example, all p-type impurity ions are implanted so as to overlap the first planned region 8p. Therefore, as shown in Figure 30, after activation, only a non-contact region 50 with a width wa is formed in the portion sandwiched between adjacent source regions 8, and no base contact region is formed.

[0078] In the second embodiment, the first planned region 8p is patterned so that the width of the opening in the source region 8 after activation is larger than the misalignment width Δx of the alignment mark. The ion implantation mask 35a for forming the base contact region 9a is then patterned to match the width of the opening to form an opening. P-type impurity ions are then implanted through the ion implantation mask 35a with the opening to form the second planned region 9ap. Even if the second planned region 9ap is formed with a misalignment with the opening in the first planned region 8p, the base contact region 9a can be reliably formed inside the opening in the source region 8 after activation. Therefore, even if the alignment mark is misread, the forward voltage Vf and on-resistance Ron due to misalignment of the base contact region 9a do not change, thereby reducing and stabilizing variations in the forward voltage Vf and on-resistance Ron. Other advantages of the second embodiment are similar to those of the first embodiment.

[0079] <Modification> In the present invention, in addition to a first gap along the <11-20> direction, a second gap along the <1-100> direction may be provided, as shown in Fig. 31. Fig. 31 illustrates a case where, in addition to the first gap described in the first embodiment, a second gap having a width wg is provided between the base contact region 9a and the source region 8 along the <1-100> direction. The second gaps are provided on the left and right sides of the base contact region 9a in Fig. 31.

[0080] Like the first gap, the second gap formed along the <1-100> direction absorbs the misalignment width Δx of the alignment mark in the <1-100> direction due to the off-angle θ and epitaxial growth, and the fluctuation width in the <1-100> direction due to the alignment device. The provision of the second gap also reduces the overlap between the base contact region 9a and the source region 8 along the <1-100> direction. Note that FIG. 31 illustrates an example in which the second gap along the <1-100> direction is combined with the first gap along the <11-20> direction described in the first embodiment. However, this is not limiting; the second gap can also be combined with the configuration of the second embodiment in which the non-contact region 50 is formed.

[0081] <Other embodiments> Although the present invention has been described by the above disclosed embodiments, the descriptions and drawings forming part of this disclosure should not be understood as limiting the present invention. It should be understood that various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0082] For example, in the first embodiment, the width of the base contact region 9a was described as being narrower than the width of the opening of the source region 8. However, the present invention can also be implemented in a case where the base contact region has a predetermined desired width and the dimensions of the opening of the source region 8 are set so that a gap equal to or greater than the misalignment width Δx of the alignment mark is formed around the base contact region. Similarly, in the second embodiment, the width of the opening of the source region 8 was described as being greater than the misalignment width Δx of the alignment mark. However, the present invention can also be implemented by replacing the "width of the opening of the source region" with the "width of the base contact region." In other words, the region of interest can be changed and the dimensions of the changed region can be set according to the misalignment width Δx of the alignment mark.

[0083] Furthermore, for example, although the two first gaps shown in Fig. 2 have the same width wg, they may have different widths, and similarly, the two second gaps shown in Fig. 31 may have different widths. As described above, the present invention includes various embodiments not described above, and the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description. [Explanation of symbols]

[0084] 1...Drain region (second main electrode region) 2...Drift layer 3...Current diffusion layer 4...Gate bottom protection area 5a, 5b...base bottom buried region (first buried region) 6a, 6b...base bottom buried region (second buried region) 7...Base area 8...Source region (first main electrode region) 8p...First planned area 9a, 9b, 19a...base contact region 9ap...Second planned area 10...Gate insulating film 11...Gate buried electrode 12...Interlayer insulating film 13a, 13b...Source contact layer 14...Lower barrier metal layer 15...Upper barrier metal layer 16...Source electrode 17...Drain electrode 21...Trench 22...Contact groove 23...Base contact plug 33...Photoresist film 31, 35, 35a...Ion implantation mask 50, 50b...non-contact area 50p...Third planned area 100...Semiconductor wafer 101...Orientation Flat 102,102a…Surface 103...Semiconductor chip 104,104a...Alignment marks θ...off angle t: thickness of epitaxially grown film wg,wg1,wg2,wg3,wgy...gap width w1, w2...protrusion width of ion implantation mask w8p: Width of the opening in the first planned area wa: width of non-contact area wp: width of base contact region Δx: Alignment mark position deviation

Claims

1. a semiconductor device including a semiconductor chip having a plurality of trenches formed in an upper surface thereof, a drift layer made of silicon carbide of a first conductivity type, a base region of a second conductivity type provided on the drift layer, a first main electrode region of the first conductivity type selectively provided on the base region by ion implantation and having a higher impurity concentration than the drift layer, a base contact region of the second conductivity type selectively provided on the base region by ion implantation and having a higher impurity concentration than the base region, and a first main electrode electrically connected to the first main electrode region and the base contact region, forming a semiconductor layer from the drift layer to an upper surface of the semiconductor chip by epitaxial growth; forming the base contact region between the first main electrode regions in a <11-20> direction in a top view; Including, The plurality of trenches extend along the <11-20> direction in top view, In the step of forming the base contact region, the base contact region is formed to have a first width in a <11-20> direction that is larger than t×tan θ, where t is a thickness of an epitaxially grown film formed by the epitaxial growth and θ is an off-angle of the epitaxially grown film; In the step of forming the base contact region, the first main electrode region and the base contact region overlap, and a non-contact region is provided in at least a part thereof, in which impurities of respective conductivity types are offset by the ion implantation into the first main electrode region and the base contact region, resulting in a low impurity density; the non-contact region is provided at an end portion on the upstream side of the off-state of the base contact region, and each of the first main electrode region and the base contact region has an impurity concentration of 3×10 20 cm −3 or more; A second conductivity type base bottom buried region is provided on the drift layer in contact with a lower surface of the base region, and a lower end of the base bottom buried region is deeper than a bottom surface of the trench. A method for manufacturing a semiconductor device.

2. The crystal plane of the sidewall of the trench is the (11-20) a-plane or the (1-100) m-plane. The method for manufacturing a semiconductor device according to claim 1 .

3. The first width of the base contact region is smaller than a thickness t of the epitaxially grown film.

3. The method for manufacturing a semiconductor device according to claim 1.

4. In the step of forming the base contact region, the base contact region is formed between the first main electrode regions in a direction in which the plurality of trenches are arranged as viewed from above. The method for manufacturing a semiconductor device according to claim 1 .

5. forming a bottom region of a second conductivity type disposed at the bottom of the trench and having a higher impurity concentration than the base region; The method for manufacturing a semiconductor device according to claim 1 .

6. forming a gate electrode in the trench via an insulating film; The method for manufacturing a semiconductor device according to claim 1 .

7. In the step of epitaxially growing the semiconductor layer from the drift layer to the upper surface of the semiconductor chip, impurities of a first conductivity type are ion-implanted into the upper surface of the drift layer; Forming a current diffusion layer of the first conductivity type The method for manufacturing a semiconductor device according to claim 1 .

8. In the step of forming the semiconductor layer from the drift layer to the upper surface of the semiconductor chip by epitaxial growth, the base region is formed by epitaxial growth. The method for manufacturing a semiconductor device according to claim 1 .

9. In the step of forming the semiconductor layer from the drift layer to the upper surface of the semiconductor chip by epitaxial growth, an alignment mark is provided on the upper surface of the epitaxially grown film. The method for manufacturing a semiconductor device according to claim 1 .

10. The upper surface of the drift layer is in contact with the base region. The method for manufacturing a semiconductor device according to claim 1 .

11. A semiconductor device having a plurality of trenches formed on an upper surface of a semiconductor chip, a drift layer made of silicon carbide of a first conductivity type; a second conductivity type base region provided on the drift layer; a first main electrode region of a first conductivity type selectively provided on the base region and having a higher impurity concentration than the drift layer; a second conductivity type base contact region selectively provided on the base region and having a higher impurity concentration than the base region; a first main electrode electrically connected to the first main electrode region and the base contact region; Equipped with a semiconductor layer from the drift layer to an upper surface of the semiconductor chip is formed of an epitaxially grown film, and an impurity concentration in the first main electrode region and the base contact region decreases in a depth direction from the upper surface of the semiconductor chip; the base contact region is provided between the first main electrode regions in the <11-20> direction in a top view, The plurality of trenches extend along the <11-20> direction in top view, the base contact region has a first width in a <11-20> direction that is greater than t×tan θ, where t is a thickness of the epitaxially grown film formed by epitaxial growth and θ is an off-angle of the epitaxially grown film; the first main electrode region and the base contact region overlap, and a non-contact region is provided in at least a portion thereof, the non-contact region having a low impurity density due to cancellation of impurities of the respective conductivity types of the first main electrode region and the base contact region; the non-contact region is provided at an end portion on the upstream side of the off-state of the base contact region, and each of the first main electrode region and the base contact region has an impurity concentration of 3×10 20 cm −3 or more; A second conductivity type base bottom buried region is provided on the drift layer in contact with a lower surface of the base region, and a lower end of the base bottom buried region is deeper than a bottom surface of the trench. Semiconductor device.

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