Same level MRAM stack with different configurations

Abstract

A semiconductor device is provided that includes a base layer, a first MRAM device formed on the base layer, and a second MRAM device formed on the base layer, where the first MRAM device has different performance characteristics than the second MRAM device.

Description

[Technical Field]

[0001] The present disclosure relates to the fields of electricity, electronics, and computers. In particular, the present disclosure relates to cells of magnetoresistive random access memory ("MRAM") devices having different configurations. [Background technology]

[0002] A particular MRAM device may be fabricated to include a bottom electrode, an MRAM stack, and a top electrode. In general, MRAM devices can be used in a variety of applications. One exemplary application is embedded storage (e.g., replacing eFlash). Another example is cache (e.g., embedded dynamic random access memory (eDRAM) or static random access memory (SRAM)). A particular MRAM device may be embedded MRAM (eMRAM) at the 28 nm or 22 nm level. It may be necessary to provide both types of MRAM (e.g., embedded storage and cache) on the same chip, and this combination of different types of MRAM may provide benefits in terms of system performance. Summary of the Invention

[0003] According to one aspect of the present invention, there is provided a semiconductor device comprising a base layer, a first magnetoresistive random access memory (MRAM) device formed on the base layer, and a second MRAM device formed on the base layer, wherein the first MRAM device has different performance characteristics than the second MRAM device.

[0004] According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including forming a base layer, forming a first MRAM device on the base layer, and forming a second MRAM device on the base layer, wherein the first MRAM device has different performance characteristics than the second MRAM device.

[0005] Embodiments of the present disclosure relate to a semiconductor device including a base layer, a first MRAM device formed on the base layer, and a second MRAM device formed on the base layer, wherein the first MRAM device has different performance characteristics than the second MRAM device.

[0006] Certain embodiments of the present disclosure relate to a method of manufacturing a semiconductor device, the method including forming a base layer, forming a first MRAM device on the base layer, and forming a second MRAM device on the base layer, wherein the first MRAM device has different performance characteristics than the second MRAM device.

[0007] The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure.

[0008] The drawings included in this application are incorporated into and form a part of this specification. These drawings illustrate embodiments of the present disclosure and, together with the description, explain the principles of the disclosure. The drawings are merely illustrative of certain embodiments and are not intended to limit the disclosure. [Brief explanation of the drawings]

[0009] [Figure 1] 1A-1D are cross-sectional side views of a semiconductor device including an MRAM device at an intermediate stage of a manufacturing process, according to an embodiment. [Figure 2] 2 is a cross-sectional side view of the semiconductor device of FIG. 1 after additional manufacturing steps, according to an embodiment. [Figure 3] 3 is a cross-sectional side view of the semiconductor device of FIG. 2 after additional manufacturing steps, according to an embodiment. [Figure 4] 4 is a cross-sectional side view of the semiconductor device of FIG. 3 after additional manufacturing steps, according to an embodiment. [Figure 5] 5 is a cross-sectional side view of the semiconductor device of FIG. 4 after additional manufacturing steps, according to an embodiment. [Figure 6]6 is a cross-sectional side view of the semiconductor device of FIG. 5 after additional manufacturing steps, according to an embodiment. [Figure 7] 7 is a cross-sectional side view of the semiconductor device of FIG. 6 after additional manufacturing steps, according to an embodiment. [Figure 8] 8 is a cross-sectional side view of the semiconductor device of FIG. 7 after additional manufacturing steps, according to an embodiment. [Figure 9] 9 is a cross-sectional side view of the semiconductor device of FIG. 8 after additional fabrication steps, according to an embodiment. [Figure 10] 10 is a cross-sectional side view of the semiconductor device of FIG. 9 after additional manufacturing steps, according to an embodiment. [Figure 11] 11 is a cross-sectional side view of the semiconductor device of FIG. 10 after additional fabrication steps, according to an embodiment. [Figure 12] 3 is a cross-sectional side view of the semiconductor device of FIG. 2 including a chemical vapor deposited oxide refill layer after additional fabrication steps, according to an embodiment. [Figure 13] 1 is a flow diagram illustrating a method for fabricating multiple different types of MRAM stacks on the same level, according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] It should be understood that elements in the figures are shown for simplicity and clarity, and that well-understood elements that may be useful or necessary in a commercially feasible embodiment may not be shown for simplicity and to aid in understanding the illustrated embodiment.

[0011] This disclosure describes MRAM devices including magnetic tunnel junction ("MTJ") stacks and methods for fabricating MRAM devices. In particular, this disclosure describes MRAM devices that include different types of MRAM devices (e.g., embedded memory (e.g., persistent memory devices) and cache) at the same level (e.g., formed at the same level above a back-end-of-layer (BEOL) base layer). Each of the different types of MRAM devices may have different critical dimensions (CDs), different overall heights, different thicknesses relative to the constituent layers of the MRAM device, or different material compositions of one or more of the MRAM device layers, or combinations thereof.

[0012] Typically, storage bits may have larger CDs (60–80 nm) and high-retention stacks (high coercivity (Hc), high bias field (Eb), and high switching current (Ic)). Such devices can offer high retention and field tolerance, but may be slow to program (>100 ns) and require large currents. Cache bits may have smaller CDs (30–50 nm) and stacks optimized for fast switching. Hc and Eb are much lower, but programming speeds are 10–50 times faster. In terms of stack differences, the overall stack structure of storage and cache bits may be very similar, but the structural and compositional details may be quite different (e.g., tunnel barrier layer thickness and free layer composition).

[0013] According to certain embodiments of the present invention, fabrication costs can be reduced and the fabrication process can be simplified by forming different types of MRAM devices (e.g., cache and storage) on the same level. For example, if related MRAM devices are formed on different levels, it may be possible to form the cache bits and storage bits on two different metal levels, but additional inter-layer dielectric (ILD) deposition, planarization, and etching steps (as well as additional mask counts) may be required.

[0014] In general, one advantage of using MRAM devices compared to other non-volatile memory (NVM) technologies such as flash is that only a small number of additional masks are required (e.g., only 3-5). In this regard, doubling the number of masks required (i.e., to form different MRAM types on different levels) would undermine the value proposition of MRAM devices.

[0015] In this embodiment, cache-type MRAM devices can be integrated into the storage area (or vice versa) to reduce interconnect length and improve response time. In an exemplary layout, the cache array is surrounded by storage bits. Storage bits typically have a larger CD compared to cache bits, which have a relatively smaller CD, and typically offer a significantly larger process window. Thus, in this embodiment, this layout improves array uniformity of the cache bits, and therefore the process window. Therefore, as described above, this embodiment can achieve improved manufacturing process efficiency (i.e., fewer semiconductor processing steps and fewer masks) and associated cost savings.

[0016] Various embodiments of the present disclosure are described herein with reference to the associated drawings. Alternate embodiments may be devised without departing from the scope of the present disclosure. Note that in the following description and drawings, various connections and relationships (e.g., above, below, adjacent, etc.) between elements are described. These connections and / or relationships may be direct or indirect unless otherwise specified, and the present disclosure is not intended to be limited in this respect. Thus, coupling of entities may refer to either direct or indirect coupling, and relationship between entities may be direct or indirect. As an example of an indirect relationship, a reference herein to forming layer "A" on layer "B" includes a situation in which one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B," as long as the relevant properties and functionality of layer "A" and layer "B" are not substantially altered by the intermediate layer(s).

[0017] The following definitions and abbreviations are used for interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements and can include other elements not expressly listed or inherent in such composition, mixture, process, method, article, or device.

[0018] For purposes of the following description, the terms "above," "below," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives refer to the described structures and methods as oriented in the drawings. The terms "overlying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element, such as a first structure, resides on a second element, such as a second structure, and that an intervening element, such as an interfacial structure, may reside between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conductive, insulating, or semiconducting layer at the interface between the two elements. Note that the term "selective to," as in, for example, "a first element selective to a second element," means that the first element can be etched and the second element can act as an etch stop.

[0019] For the sake of brevity, conventional techniques related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Additionally, various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functions not described in detail herein. In particular, the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps are only briefly mentioned herein or omitted entirely without providing details of the well-known processes.

[0020] Generally, the various processes used to form the microchips that are packaged into ICs fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography.

[0021] Deposition is any process by which a material is grown, coated, or otherwise transferred onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD), among others. Another deposition technique is plasma-enhanced chemical vapor deposition (PECVD), a process that uses the energy of a plasma to induce reactions at the wafer surface that would otherwise require the higher temperatures associated with conventional CVD. Energetic ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0022] Removal / etching is any process that removes material from a wafer. Examples include etching processes (either wet or dry) and chemical mechanical planarization (CMP). One example of a removal process is ion beam etching (IBE). Generally, IBE (or milling) refers to dry plasma etching methods that utilize a remote broad-beam ion / plasma source to remove substrate material by physical inert gas means, chemically reactive gas means, or both. Like other dry plasma etching techniques, IBE offers advantages such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimal substrate damage. Another example of a dry removal process is reactive ion etching (RIE). Generally, RIE uses a chemically reactive plasma to remove material deposited on the wafer. In RIE, plasma is generated under low pressure (vacuum) by an electromagnetic field. High-energy ions from the RIE plasma attack the wafer surface and react with the wafer, removing material.

[0023] Semiconductor doping is the modification of electrical properties, typically by doping the source and drain of a transistor, typically through diffusion or ion implantation, or both. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). The annealing serves to activate the implanted dopants. Films, both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.), are used to connect and separate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the substrate's conductivity to be altered by the application of a voltage. By creating structures of these various components, millions of transistors can be constructed and wired together to form the complex circuits of modern microelectronic devices.

[0024] Semiconductor lithography is the creation of a three-dimensional relief image, or pattern, on a semiconductor substrate and the subsequent transfer of that pattern to the substrate. In semiconductor lithography, the pattern is formed with a light-sensitive polymer called photoresist. The lithography and etching pattern transfer steps are repeated multiple times to build the complex structures that make up transistors and the numerous wires that connect a circuit's millions of transistors. Each pattern printed on the wafer is aligned with previously formed patterns, and conductors, insulators, and selectively doped regions are gradually built up to form the final device.

[0025] Turning now to an overview of technologies more specifically related to embodiments of the present disclosure, embedded DRAM (eDRAM) is dynamic random access memory (DRAM) integrated onto the same die of an application-specific integrated circuit (ASIC) or microprocessor or on a multi-chip module (MCM). eDRAM has been implemented with silicon-on-insulator (SOI) technology, which refers to the use of a layered silicon-insulator-silicon substrate instead of the traditional silicon substrate in semiconductor manufacturing. While eDRAM technology has met with varying degrees of success, demand for SOI technology as a server memory option has declined in recent years.

[0026] Magnetoresistive Random Access Memory (MRAM) devices using magnetic tunnel junctions (MTJs) are one option to replace existing eDRAM technology. MRAM is a type of computer memory that is non-volatile, meaning that stored information can be retrieved even after power cycles. This advantage of being able to retain information even after power cycles is the driving force behind the accelerating development of this memory technology.

[0027] A magnetic tunnel junction (MTJ) device, the primary storage element of magnetic random access memory (MRAM), is a magnetic storage and switching device in which two ferromagnetic layers are separated by a thin insulating barrier (e.g., aluminum oxide) to form a stacked structure. One of the ferromagnetic layers is called the fixed, pinned, or reference layer because its magnetization is fixed. However, the other ferromagnetic layer is called the free layer because its magnetization can change. When a bias is applied to an MTJ device, electrons spin-polarized by the ferromagnetic layer cross the insulating barrier through a process known as quantum tunneling, generating a current whose magnitude depends on the orientation of the magnetization of the ferromagnetic layer. MTJ devices exhibit low resistance when the magnetic moment of the free layer is parallel to that of the fixed layer and high resistance when the magnetic moment of the free layer is oriented antiparallel to that of the fixed layer.

[0028] The materials and geometry used to construct the stack of different layers that form an MTJ device are factors that affect the device's characteristics in terms of speed (i.e., switching time) and power consumption (e.g., the voltage and / or current required to switch the device from one state to another). As briefly described above, certain MTJ devices have a pillar structure (i.e., a stack of materials) with a cylindrical shape, and current flows from the top layer to the bottom layer or vice versa to switch the magnetization of one ferromagnetic layer. These types of MTJ devices are generally referred to as spin-transfer torque (STT) MTJ devices. Certain STT MRAM devices may have limited switching speed and endurance compared to static random access memory (SRAM) devices (i.e., random access memories that retain data bits in memory as long as power is applied). Another type of MTJ device is called a spin-orbit torque (SOT) device. In SOT-type devices, the stacked pillar structure is also cylindrical, but the stack is deposited on a heavy metal conductor. In a SOT-type MTJ device, current flows horizontally through this conductor, switching the magnetization of the ferromagnetic layer at the interface.

[0029] In STT MRAM devices, device fabrication is often performed in conjunction with the formation of middle-of-the-line (MOL) or back-of-the-line (BEOL) layers. This is sometimes referred to as embedded MRAM, where the MRAM device is embedded in or formed with these layers. Front-of-the-line (FEOL) generally refers to the set of process steps used to form transistors and other circuit elements (such as resistors and capacitors) and subsequently electrically connect them to middle-of-the-line (MOL) and back-of-the-line (BEOL) layers. MOL generally refers to the set of wafer processing steps used to form structures that provide localized electrical connections between transistors (e.g., gate contact formation). MOL processing typically occurs after FEOL processes and before BEOL processes. BEOL is generally the part of IC fabrication where individual devices (such as transistors, capacitors, and resistors) are interconnected with wiring on the wafer.

[0030] As mentioned above, MRAM devices can be useful for a variety of different applications, such as embedded storage and cache. The embodiments described herein provide MRAM devices and methods for manufacturing MRAM devices in which multiple different types / configurations can exist on the same level of a chip.

[0031] Referring now to the drawings, in which like numerals represent the same or similar elements, and initially to FIG. 1 , a cross-sectional view is shown illustrating a particular semiconductor device 100 at an intermediate stage of a fabrication process, according to an embodiment. In FIG. 1 , a base layer 102 is provided. The base layer 102 may include certain electrical interconnects, wiring lines, or other devices. For example, the base layer 102 may include front-end (FEOL) elements (e.g., transistors, circuit elements, resistors, capacitors, etc.) or middle-of-line (MOL) elements (e.g., electrical connections between transistors, gate contact formation structures, etc.). It should be understood that the base layer 102 may include any suitable number of different components and may include multiple sub-layers having different components. In general, the base layer 102 is any suitable layer that can serve as a starting structure from which an embedded MRAM device can be formed.

[0032] As shown in FIG. 1 , the MRAM pillar includes a bottom electrode 106, an MRAM stack 108, and a top electrode 110. A bottom contact 104 is formed in contact with the base layer 102. For the MRAM pillar, the bottom electrode 106 is formed on the bottom contact 104 (and a portion of the base layer 102). Next, as shown in FIG. 1 , the MRAM stack 108 is formed on the bottom electrode 106. In a particular embodiment, the MRAM stack may include a reference layer, a tunnel barrier layer, a magnetic free layer, and a top electrode, which are not shown in FIG. 1 for simplicity and ease of explanation. The tunnel barrier layer may be formed on the reference layer. After forming the tunnel barrier layer, a magnetic free layer is formed on the tunnel barrier layer. Next, the top electrode 110 is formed on the magnetic free layer of the MRAM stack 108. It should be understood that this MRAM stack 108 structure is merely an example, and any other suitable MRAM stack structure known to those skilled in the art may be utilized. It should also be understood that this exemplary MRAM stack structure may include one or more additional layers, may include intervening layers, and any of the layers described with respect to the MRAM stack structure may include multiple sub-layers.

[0033] As shown in FIG. 1 , the MRAM stack structure (i.e., bottom electrode 106, MRAM stack 108, and top electrode 110) is patterned to form MRAM device pillars. As will be appreciated by those skilled in the art, the MRAM device pillars can be formed by any suitable patterning and etching technique (e.g., ion beam etching). In one particular embodiment, a dielectric liner layer 112 is formed to encapsulate the MRAM device pillars. The dielectric liner layer 112 can be composed of a SiN material or any other suitable dielectric material. As shown in FIG. 1 , the dielectric liner layer 112 covers at least a portion of the sidewall surfaces of the bottom electrode 106, MRAM stack 108, and top electrode 110. Although not shown in FIG. 1 , the dielectric liner layer 112 is first formed to conformally cover the entire surface of the wafer, after which a portion of the second interlayer dielectric layer (not shown) is optionally formed, and then the dielectric liner layer 112 and the top portion of the second interlayer dielectric layer are removed by a CMP process to expose the top surface of the top electrode 110. It should be understood that the semiconductor device 100 may not include the second interlayer dielectric layer or may include other suitable layers. One function of the dielectric liner layer 112 may be to protect the MRAM stack 108 from oxidation. Following the formation of the dielectric liner layer 112, an oxide layer 114 is provided to protect and / or cover the semiconductor device 100. The oxide layer 114 may first be provided over the entire surface of the base layer 102, and then a cut mask may be used to remove portions of the oxide layer 114 that are not adjacent to the two different MRAM stacks 108. 1, two different MRAM stacks 108 of the same first type are present next to each other. However, it should be understood that any other suitable number of MRAM stacks 108 may be present as appropriate for a given application or device. In one example, the two MRAM stacks 108 may be spaced apart by about 200 nm to about 1 μm. In another example, the spacing between adjacent MRAM stacks 108 may be about 10 times the total height of the MRAM pillar.

[0034] Referring now to FIG. 2, this figure is a cross-sectional view of the semiconductor device 100 of FIG. 1 after a subsequent fabrication process, according to an embodiment. As shown in FIG. 2, this is the point in the fabrication process where another MRAM pillar is added, having a different configuration than the two MRAM pillars shown in FIG. 1, with this additional MRAM pillar being formed at the same level (i.e., on the same base layer 102) as described above with respect to FIG. 1. A second bottom electrode 118 is formed on top of the contact 104, and a second MRAM stack 120 and a second top electrode 122 are conformally deposited over the entire surface of the semiconductor device 100. Thus, at least initially, the layers that form the second MRAM pillar (i.e., the second bottom electrode 118, the second MRAM stack 120, and the second top electrode 122) are formed on top of the MRAM stack 108.

[0035] 3, which is a cross-sectional view of the semiconductor device 100 of FIG. 2 after a subsequent manufacturing process, according to an embodiment. As shown in FIG. 3, an oxide layer 124 is formed on the second top electrode 122, and a mask 126 is formed on the oxide layer 124 in the area where the second MRAM pillar will be formed.

[0036] Referring now to FIG. 4, this figure illustrates a cross-sectional view of the semiconductor device 100 of FIG. 3 after a subsequent fabrication process, according to an embodiment. As shown in FIG. 4, an etching process is performed using a mask 126 to pattern the second MRAM pillars (the second bottom electrode 118, the second MRAM stack 120, and the second top electrode 122). However, in certain instances, as shown in FIG. 4, due to the height of the stacks in this particular region, some residual portions of the stacks (i.e., the residual portions of the second bottom electrode 118′, the residual portions of the second MRAM stack 120′, and the residual portions of the second top electrode 122′) may remain after the etching operation. In other words, where there is a step from the region near the edge of the MRAM stack 108, the height of the previously deposited layers (the second bottom electrode 118, the second MRAM stack 120, and the second top electrode 122) is, for example, two or three times thicker than in other regions. Theoretically, if the etching material has perfect (or near perfect) selectivity to the base layer 102 and bottom contact 104 compared to the second bottom electrode 118, second MRAM stack 120, and second top electrode 122 layers, it may be possible to remove the remaining portions without over-etching the base layer 102.

[0037] 5, which is a cross-sectional view of the semiconductor device 100 of FIG. 4 after a subsequent manufacturing process, according to an embodiment. As shown in FIG. 5, a second dielectric liner layer 128 is formed over the entire semiconductor device 100, covering the second MRAM stack 120. This second dielectric liner layer 128 (or second spacer layer) may be composed of a SiN material, and may be the same material as the dielectric liner layer 112, or may be a different material.

[0038] Referring now to FIG. 6, this figure is a cross-sectional view of the semiconductor device 100 of FIG. 5 after a subsequent fabrication process, according to an embodiment. As shown in FIG. 6, an etching process is performed to remove unwanted portions of the second dielectric liner layer 128. As shown in FIG. 6, remaining portions of the second dielectric liner layer 128 reside on the sidewalls of the second MRAM pillars. It should be understood that, in certain examples, remaining portions of the second dielectric liner layer 128′ may also still remain next to the remaining portions of the second bottom electrode 118′, the remaining portions of the second MRAM stack 120′, and the remaining portions of the second top electrode 122′.

[0039] 7, which is a cross-sectional view of the semiconductor device 100 of FIG. 6 after a subsequent fabrication process, according to an embodiment. At this stage in the fabrication process, it can be seen that the overall height of the first MRAM pillar H1 is different from the overall height of the second MRAM pillar H2. Also, the critical dimension (CD) (e.g., the diameter if the pillar is cylindrical) of the first MRAM pillar CD1 is different from the CD of the second MRAM pillar CD2. Thus, as described above, some of the MRAM devices can have structural characteristics suitable for one type of application (e.g., storage), while other of the MRAM devices can have structural characteristics suitable for a second type of application (e.g., cache). It should be understood that the material composition of the bottom electrode 106 may be the same as or different from the material composition of the second bottom electrode 118, the material composition of the MRAM stack 108 may be the same as or different from the material composition of the second MRAM stack 120, and the material composition of the top electrode 110 may be the same as or different from the material composition of the second top electrode 122. It should also be understood that the height (or thickness) of corresponding layers (e.g., the bottom electrode 106 and the second bottom electrode 118) may differ between the first and second MRAM pillars. In a broader sense, it may be sufficient to understand that the first and second MRAM devices (or pillars) have different performance characteristics from each other (i.e., due to one or more of the different physical or chemical properties described above).

[0040] Also, as shown in FIG. 7 , additional material of the oxide layer 114 can be added to fill all spaces between the MRAM devices, and the oxide layer 114 can function as a planarization layer. In a particular example, the oxide layer 114 may be subjected to CMP or some other planarization process. As shown in FIG. 7 , a second mask 132 is formed on the oxide layer 114. Specifically, the second mask 132 is formed in areas excluding the remaining portions (i.e., the remaining portions of the second dielectric liner layer 128′, the remaining portions of the second bottom electrode 118′, the remaining portions of the second MRAM stack 120′, and the remaining portions of the second top electrode 122′) so that these remaining portions can be removed in a subsequent etching operation.

[0041] Referring now to FIG. 8, this figure illustrates a cross-sectional view of the semiconductor device 100 of FIG. 7 after a subsequent fabrication process, according to an embodiment. As shown in FIG. 8, an etching process is performed to remove the remaining portions of the second dielectric liner layer 128′, the remaining portions of the second bottom electrode 118′, the remaining portions of the second MRAM stack 120′, and the remaining portions of the second top electrode 122′. The second mask 132 is then removed. It should be understood that, in certain instances, due to imperfect etch selectivity between the base layer 102 and the bottom contact 104 (if additional MRAM devices are formed) and the remaining portions, a certain amount of recession (i.e., depth D3 shown in FIG. 8, and depth D4 relative to the bottom contact 104 if additional MRAM devices are formed) may exist in the base layer 102 during these etching operations.

[0042] 9, which is a cross-sectional view of the semiconductor device 100 of FIG. 8 after a subsequent manufacturing process, according to an embodiment. As shown in FIG. 9, additional material of oxide layer 114 is added to fill all spaces between the MRAM devices, and oxide layer 114 can again function as a planarization layer. In one particular example, oxide layer 114 may be subjected to CMP or some other planarization process.

[0043] 10, which is a cross-sectional view of the semiconductor device 100 of FIG. 9 after a subsequent manufacturing process, according to an embodiment. As shown in FIG. 10, a meterization layer 134 is formed to electrically contact the first and second MRAM devices. It should be understood that the meterization layer 134 shown in FIG. 10 is only an example, and any other suitable configuration may be used.

[0044] 11 , which is a cross-sectional view of the semiconductor device 100 of FIG. 10 after subsequent fabrication processes, according to an embodiment. As shown in FIG. 11 , a third MRAM pillar can be formed in a manner similar to the process described above for the second MRAM pillar. The third MRAM pillar can include a third contact 104, a third bottom electrode 138, a third MRAM stack 140, a third top electrode 142, and a third dielectric liner layer 144. The process for forming the third MRAM pillar is similar to the process for forming the second MRAM pillar and will not be repeated here for the sake of brevity. It should be understood that the process of forming these different types of MRAM pillars on the base layer 102 and contacts 104 can be repeated any number of times to form as many types of MRAM pillars as desired for a particular application.

[0045] 12, which is a cross-sectional side view of the semiconductor device of FIG. 2 including a chemical vapor deposited oxide refill layer after additional fabrication steps, according to an embodiment. As shown in FIG. 12, unlike the conformal deposition (i.e., more like a liner layer) of oxide layer 124 shown in FIG. 3, here oxide layer 124 is formed following a CVD oxide refill process, followed by a CMP process to planarize the surface. Other than this difference, the remaining processes are similar to those described above with respect to FIGS. 3-11 and will not be repeated here for the sake of brevity.

[0046] FIG. 13 is a flow chart illustrating a method for fabricating multiple different types of MRAM stacks on the same level, according to an embodiment. As shown in FIG. 13, in operation 202, MRAM stack deposition is performed. This operation precedes the patterning of the first MRAM pillar shown in FIG. 1 and corresponds to the formation of the second bottom electrode 118 layer, the second MRAM stack 120 layer, and the second top electrode 122 shown in FIG. 2. In operation 204, MRAM stack patterning is performed, which corresponds to the process described above with reference to FIG. 3. In operation 206, etching is performed to form MRAM pillar structures, which corresponds to the process described above with reference to FIG. 4. In operation 208, MRAM pillar encapsulation is performed, which may correspond to the process described above with reference to FIGS. 5-9. In operation 210, if another MRAM device type (e.g., the third MRAM pillar shown in FIG. 10) is to be formed, the process returns to operation 202. If in operation 210 another MRAM device type is not being formed, the process proceeds to operation 212 for metal spacer removal, and then to operation 214 for additional downstream flow processes as known to those skilled in the art.

[0047] The description of various embodiments is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications or technical improvements to technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor device comprising: a base layer containing interconnect lines, front-end elements, or mid-end elements; a plurality of bottom contacts formed in the base layer; a first magnetoresistive random access memory (MRAM) device contacting one of the plurality of bottom contacts at a first region and being a cache bit formed on the base layer; a second MRAM device that is a persistent memory device formed on the base layer at the same level as the first MRAM device on the base layer and in contact with one of the plurality of bottom contacts in a second region surrounding the first region; Equipped with the first MRAM device has a critical dimension (CD) different from a critical dimension (CD) of the second MRAM device; the first MRAM device has a lower coercivity and bias field than the second MRAM device; the first MRAM device is capable of faster switching than the second MRAM device; the second MRAM device has a slower programming speed than the first MRAM device; and the first MRAM device has an overall height greater than an overall height of the second MRAM device; Semiconductor devices.

2. the first MRAM device includes a first bottom electrode, a first MRAM stack, and a first top electrode; the second MRAM device includes a second bottom electrode, a second MRAM stack, and a second top electrode; The semiconductor device of claim 1 .

3. The semiconductor device of claim 2 , wherein the thickness of the first bottom electrode is different from the thickness of the second bottom electrode.

4. 4. The semiconductor device of claim 2, wherein the thickness of the first top electrode is different from the thickness of the second top electrode.

5. the first MRAM device includes the first bottom electrode, the first MRAM stack, and a spacer layer formed on sidewalls of the first top electrode; the second MRAM device includes the second bottom electrode, the second MRAM stack, and a second spacer layer formed on sidewalls of the second top electrode. The semiconductor device according to any one of claims 2 to 4.

6. The semiconductor device of any one of claims 1 to 5, wherein the first MRAM device and the second MRAM device each include a fixed magnetic layer, an insulating barrier layer, and a free magnetic layer.

7. 1. A method for manufacturing a semiconductor device, comprising: forming a base layer including interconnect lines, front-end elements, or mid-end elements; forming a plurality of bottom contacts in the base layer; forming a first MRAM device in contact with one of the plurality of bottom contacts in a first region, the first MRAM device being a cache bit on the base layer; forming a second MRAM device, the second MRAM device being a persistent memory device on the base layer, at the same level as the first MRAM device on the base layer and in contact with one of the plurality of bottom contacts in a second region surrounding the first region; Including, the first MRAM device has a critical dimension (CD) different from a critical dimension (CD) of the second MRAM device; the first MRAM device has a lower coercivity and bias field than the second MRAM device; the first MRAM device is capable of faster switching than the second MRAM device; the second MRAM device has a slower programming speed than the first MRAM device; and the first MRAM device has an overall height greater than an overall height of the second MRAM device; method.

8. forming the first MRAM device includes forming a first bottom electrode, forming a first MRAM stack on the first bottom electrode, and forming a first top electrode on the first MRAM stack; forming the second MRAM device includes forming a second bottom electrode, forming a second MRAM stack on the second bottom electrode, and forming a second top electrode on the second MRAM stack. The method of claim 7.

9. The method of claim 8 , wherein the thickness of the first bottom electrode is different from the thickness of the second bottom electrode.

10. 10. The method of claim 8 or 9, wherein the thickness of the first top electrode is different from the thickness of the second top electrode.

11. the first MRAM device includes the first bottom electrode, the first MRAM stack, and a spacer layer formed on sidewalls of the first top electrode; the second MRAM device includes the second bottom electrode, the second MRAM stack, and a second spacer layer formed on sidewalls of the second top electrode. The method according to any one of claims 8 to 10.

12. The method of any one of claims 7 to 11, wherein the first MRAM device and the second MRAM device each include a fixed magnetic layer, an insulating barrier layer, and a free magnetic layer.

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