Semiconductor device inspection method and semiconductor device manufacturing method

Abstract

To provide a technique of detecting a SBD-incorporated MOSFET that has low current surge resistance.SOLUTION: An inspecting method for a semiconductor device regarding a technique disclosed herein includes measuring a first gate voltage applied to a gate electrode in accordance with a first drain current flowing from a drain electrode to a source electrode, measuring a second gate voltage applied to the gate electrode in accordance with a second drain current larger than the first drain current, and inspecting whether the difference between the first gate voltage and the second gate voltage is over a predetermined threshold.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a technology for inspecting semiconductor devices. [Background technology]

[0002] BACKGROUND ART In power electronics devices, insulated gate semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are widely used as switching elements that control the power supply to loads such as motors.

[0003] Meanwhile, MOSFETs or IGBTs using wide bandgap semiconductors such as silicon carbide (SiC) are attracting attention as next-generation switching elements, and are expected to be applied to technical fields that handle high voltages of about 1 kV or more. In addition to SiC, other wide bandgap semiconductors include gallium nitride (GaN)-based materials and diamond.

[0004] SiC has many polymorphic forms, which are based on differences in the atomic arrangement of the crystal, and SiC crystals with different atomic arrangements exhibit different physical properties.

[0005] 4H-SiC is generally used in semiconductor devices for power control. However, SiC crystals cannot be composed of only one crystal system, and other crystal polytypes may be mixed in during crystal growth. This is called stacking faults.

[0006] A pn diode called a body diode exists parasitic between the drain and source of a power control MOSFET, and in addition to forward operation when a positive voltage is applied to the drain terminal, it is also possible to operate in reverse when a positive voltage is applied to the source terminal. By using this body diode, it is possible to eliminate the freewheeling diode placed in parallel with the MOSFET, thereby reducing the number of circuit elements.

[0007] While MOSFETs are unipolar elements in which only electrons or holes flow, pn diodes are unipolar elements in which both flow simultaneously. It is known that when SiC operates in unipolar mode, the recombination energy of electron-hole pairs causes the above stacking faults to expand. Because stacking faults in 4H-SiC crystals behave as high-resistance bodies, the expansion of crystal defects leads to an increase in the element resistance.

[0008] Therefore, when connecting a MOSFET and an SBD (Schottky Barrier Diode) in parallel, the SBD must be designed so that the body diode of the MOSFET does not operate within the range of applied current; in other words, so that the generated voltage does not reach the turn-on voltage of the body diode.

[0009] To address this issue, SBD-integrated MOSFET technology has been developed, in which an SBD is embedded within a SiC-MOSFET, causing the reverse current to flow through the SBD rather than the body diode. Because the SBD is a unipolar element, stacking faults do not expand as they do in a body diode. Unlike regular SBDs, the embedded SBD shares a drift layer with the MOSFET. This makes the voltage applied to the SBD equal to the voltage applied to the body diode, so the turn-on voltage of the body diode in a MOSFET with an SBD is higher than the turn-on voltage of the body diode that is parasitic in a regular MOSFET. In other words, a MOSFET with an SBD can pass more SBD current than a regular MOSFET connected in parallel with an SBD.

[0010] Defects in semiconductor devices can be inspected using the method described in Patent Document 1, for example. However, defects in the drift layer can cause the SBD to behave differently from a normal SBD. For example, if a current surge occurs in the SBD (if a surge current flows), the SBD may heat up and be destroyed.

[0011] To increase the I2t capability, or resistance to current surges, a structure called JBS (Junction Barrier Schottky) is used, in which a pn diode is placed in parallel with the SBD. The SBD in a JBS has a low turn-on voltage and high parasitic resistance, while the pn diode is designed to have a high turn-on voltage and low parasitic resistance. This allows the SBD to operate during normal operation, and when a large current flows, the pn diode operates to reduce the generated voltage, preventing damage to the device. This difference in characteristics becomes particularly pronounced at high temperatures, making JBS more resistant to current surges than regular SBDs. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-23964 Summary of the Invention [Problem to be solved by the invention]

[0013] In a MOSFET with an SBD, the body diode functions in the same way as the pn diode in a JBS: when a certain current surge occurs, the body diode operates, the generated voltage drops, and the SBD current switches to the body diode current.

[0014] However, the inventors discovered that the histogram of the body diode operating voltage of an SBD-integrated MOSFET has multiple peaks. The crystal polytype mentioned above is cited as a possible cause. Some defects have already reached the surface of the drift layer after epitaxial growth, and this high-resistivity layer blocks the SBD portion, breaking the parallel connection between the body diode and the integrated SBD, lowering the body diode operating voltage. In particular, in modules with multiple SBD-integrated MOSFET chips connected in parallel, current concentrates in the SBD-integrated MOSFET chips with lower body diode operating voltages, causing them to be destroyed quickly, lowering the overall It capability.

[0015] Generally, methods for inspecting defects in semiconductor devices are disclosed, for example, in Patent Document 1, but there is no disclosure of an inspection method for the above-mentioned problem (i.e., crystal polytype) of a semiconductor device in which both a MOSFET region and a diode region are formed in an active region.

[0016] The technology disclosed in this specification has been made in consideration of the problems described above, and is a technology for detecting MOSFETs with built-in SBDs that have low current surge resistance. [Means for solving the problem]

[0017] A method for inspecting a semiconductor device, which is a first aspect of the technology disclosed in the present specification, is a method for inspecting a semiconductor device including an SBD region and a MOSFET region, the SBD region and the MOSFET region being provided on a first main surface side of a semiconductor substrate made of silicon carbide, a first conductivity type drift layer being provided on the first main surface of the semiconductor substrate, the MOSFET region including: a well region of a second conductivity type provided in a surface layer of the drift layer on the first main surface side; a source region of the first conductivity type provided in a surface layer of the well region; a gate insulating film provided in contact with the well region sandwiched between the source region and the drift layer; a gate electrode provided in contact with the gate insulating film; and an interlayer insulating film covering the gate electrode; a region of the semiconductor device that includes a Schottky electrode that forms a Schottky junction with the drift layer on the first main surface side of the drift layer; a source electrode that is connected to the Schottky electrode and covers the interlayer insulating film; and a drain electrode that is provided on a second main surface side of the semiconductor substrate that is the main surface opposite to the first main surface; and a method for inspecting the semiconductor device includes measuring a first gate voltage applied to the gate electrode corresponding to a first drain current flowing from the drain electrode to the source electrode, measuring a second gate voltage applied to the gate electrode corresponding to a second drain current that is larger than the first drain current, and inspecting whether a difference between the first gate voltage and the second gate voltage exceeds a predetermined threshold value. [Effects of the Invention]

[0018] According to at least the first aspect of the technique disclosed in the present specification, a MOSFET with a built-in SBD having low withstand capability can be detected based on the difference between corresponding gate voltages at different drain current values.

[0019] Furthermore, objects, features, aspects, and advantages associated with the technology disclosed herein will become more apparent from the detailed description set forth below and the accompanying drawings. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 1 is a plan view showing an example of a semiconductor device that is a SiC-MOSFET with an SBD, as viewed from above. [Figure 2] 2 is a plan view mainly showing a silicon carbide semiconductor portion in the structure shown in FIG. 1. FIG. [Figure 3] FIG. 2 is a cross-sectional view schematically showing an example of a cross section of a striped unit cell region extending from a source electrode to a gate wiring in the outer periphery of the silicon carbide semiconductor device shown in FIG. 1, as viewed in a direction perpendicular to the longitudinal direction of the unit cell region. [Figure 4] FIG. 10 is a plan view showing another example of the structure of a semiconductor device that is a SiC-MOSFET with an SBD. [Figure 5] 2 is a cross-sectional view schematically showing an example of a cross section from a source electrode to a gate wiring in the outer periphery of the silicon carbide semiconductor device shown in FIG. 1. FIG. [Figure 6] 1A and 1B are cross-sectional views illustrating a method for manufacturing an SiC-MOSFET with an SBD. [Figure 7] 1A and 1B are cross-sectional views illustrating a method for manufacturing an SiC-MOSFET with an SBD. [Figure 8] 1A and 1B are cross-sectional views illustrating a method for manufacturing an SiC-MOSFET with an SBD. [Figure 9] 1A and 1B are cross-sectional views illustrating a method for manufacturing an SiC-MOSFET with an SBD. [Figure 10] FIG. 1 is a diagram illustrating an example of the relationship between the gate voltage and the drain current of a semiconductor device. [Figure 11] FIG. 10 is a diagram illustrating an example of the relationship between the drain voltage and the drain current of a semiconductor device. [Figure 12] FIG. 1 is a cross-sectional view schematically illustrating an example of the structure of an SiC-MOSFET with an SBD. [Figure 13] FIG. 1 is a plan view showing an example of a part of a semiconductor device that is a SiC-MOSFET with an SBD, viewed from above. [Figure 14] 14 is an enlarged plan view of an active region of the semiconductor device, which is an SiC-MOSFET with an SBD shown in FIG. 13. FIG. [Figure 15]15 is a cross-sectional view of the semiconductor device at a location in the active region shown in FIG. 14 where a connection region is not formed. [Figure 16] 15 is a cross-sectional view of the semiconductor device at a location where a connection region is formed in the active region shown in FIG. 14. FIG. [Figure 17] 1A and 1B are cross-sectional views illustrating a method for manufacturing an SiC-MOSFET with an SBD. [Figure 18] 1A and 1B are cross-sectional views illustrating a method for manufacturing an SiC-MOSFET with an SBD. [Figure 19] 1A and 1B are cross-sectional views illustrating a method for manufacturing an SiC-MOSFET with an SBD. [Figure 20] 1A and 1B are cross-sectional views illustrating a method for manufacturing an SiC-MOSFET with an SBD. [Figure 21] 1A and 1B are cross-sectional views illustrating a method for manufacturing an SiC-MOSFET with an SBD. [Figure 22] 1A and 1B are cross-sectional views illustrating a method for manufacturing an SiC-MOSFET with an SBD. [Figure 23] FIG. 10 is a diagram illustrating an example of the effect of stacking faults on gate voltage. DETAILED DESCRIPTION OF THE INVENTION

[0021] First Embodiment A method for inspecting a semiconductor device and a method for manufacturing a semiconductor device according to this embodiment will be described.

[0022] First, an example of a silicon carbide semiconductor device incorporating an SBD, which is the target of the inspection method according to this embodiment, will be described.

[0023] In the following description, n and p indicate the conductivity type of the semiconductor. In this disclosure, the first conductivity type is described as n-type and the second conductivity type as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. Furthermore, n- indicates that the impurity concentration is lower than n, and n+ indicates that the impurity concentration is higher than n. Similarly, p- indicates that the impurity concentration is lower than p, and p+ indicates that the impurity concentration is higher than p.

[0024] Hereinafter, embodiments will be described with reference to the accompanying drawings. Note that the drawings are shown schematically, and the relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. In the following description, similar components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

[0025] Fig. 1 is a plan view showing an example of a semiconductor device that is a SiC-MOSFET with an SBD, viewed from the top. In Fig. 1, a gate pad 81 is formed on part of the top surface of the SiC-MOSFET with an SBD, and a source electrode 80 is formed adjacent to the gate pad 81. Gate wiring 82 is also formed so as to extend from the gate pad 81. Gate wiring 82 is formed on the outer periphery of the silicon carbide semiconductor device, surrounding the source electrode 80 in plan view.

[0026] <1. Planar type> <1-1. Stripe structure> Fig. 2 is a plan view mainly showing the silicon carbide semiconductor portion in the structure shown in Fig. 1. As shown in Fig. 2, semiconductor device 100 has unit cell regions, each having a MOSFET region formed on either side of an SBD region, arranged in a stripe pattern, and is called a "stripe type."

[0027] 2, unit cell regions each consisting of an n-type isolation region 21 that roughly corresponds to an SBD region where an SBD is formed and a p-type well region 30 that roughly corresponds to a MOSFET region where a MOSFET is formed are repeatedly arranged in one direction in a plan view. Also shown in FIG. 2 are drift layer 20 and isolation region 22, which will be described later.

[0028] The region where the SBD-integrated MOSFET is formed is called the active region, and the region formed around the active region is called the termination region. The termination region includes the region where the gate pad 81, in which the p-type well region 31 and the like are formed, is formed.

[0029] Fig. 3 is a cross-sectional view schematically illustrating an example of a cross section of a striped unit cell region extending from source electrode 80 to gate wiring 82 at the periphery of the silicon carbide semiconductor device, as viewed from a direction perpendicular to the longitudinal direction of the unit cell region, as shown in Fig. 1. As described above, an SBD region and a MOSFET region are formed in the unit cell region.

[0030] In FIG. 3, in a semiconductor device 100, a drift layer 20 made of n-type silicon carbide (SiC) is formed on the upper surface of a semiconductor substrate 10 made of n-type low-resistance silicon carbide.

[0031] Furthermore, a well region 31 made of p-type silicon carbide is provided in the surface layer of the drift layer 20 located in a position substantially corresponding to the region where the gate wiring 82 shown in FIG. 1 is formed.

[0032] 1, a plurality of well regions 30 made of p-type silicon carbide and formed in a stripe pattern are provided in the surface layer of drift layer 20. The well regions 30 formed in a stripe pattern may be connected to each other or may be a plurality of separated well regions 30.

[0033] In the surface layer of each well region 30, a source region 40 made of n-type silicon carbide is formed at a position inward from the periphery of the well region 30 by a predetermined distance.

[0034] Furthermore, a contact region 35 made of low-resistivity p-type silicon carbide is formed in the surface layer of the well region 30. Furthermore, a separation region 21 made of the same n-type silicon carbide as the drift layer 20 is formed in the striped well region 30 so as to penetrate the well region 30. The separation region 21 is formed in a striped shape along the striped well region 30. The n-type impurity concentration of the separation region 21 may be the same as the n-type impurity concentration of the drift layer 20, or may be higher or lower than the n-type impurity concentration of the drift layer 20. The contact region 35 is formed in the surface layer of the well region 30, closer to the separation region 21 than the source region 40.

[0035] A stripe-shaped Schottky electrode 71 that is Schottky-connected to the separation region 21 (drift layer 20) is formed on the upper surface of the separation region 21. Here, it is desirable that the Schottky electrode 71 is formed so as to include at least the corresponding separation region 21 in plan view (in FIG. 3, a part of the Schottky electrode 71 is formed so as to cover the well region 30).

[0036] An ohmic electrode 70 is formed to cover a part of the upper surface of the contact region 35 and a part of the upper surface of the source region 40. A source electrode 80 connected to the ohmic electrode 70, the Schottky electrode 71, and the contact region 35 is formed on the upper surfaces thereof.

[0037] The well region 30 can easily transfer electrons and holes between the ohmic electrode 70 and the well region 30 via the low-resistance contact region 35 .

[0038] An n-type separation region 22 is formed in the region where the drift layer 20 is formed between adjacent well regions 30. The n-type impurity concentration of the separation region 22 may be the same as the n-type impurity concentration of the drift layer 20, or may be higher or lower than the n-type impurity concentration of the drift layer 20.

[0039] A gate insulating film 50 made of silicon oxide is formed on a part of the upper surface of adjacent well regions 30, on the upper surface of the separation region 22 located therebetween, and on a part of the upper surface of the source region 40 in each well region 30. Furthermore, a gate electrode 60 made of polycrystalline silicon is formed on the upper surface of the gate insulating film 50 in a portion that overlaps at least the well region 30 (specifically, the well region 30 sandwiched between the source region 40 and the drift layer 20) in plan view.

[0040] Here, the surface layer of the well region 30 that overlaps in plan view with the region where the gate electrode 60 is formed and faces the region via the gate insulating film 50 is called a channel region.

[0041] A well region 31 is formed outside (in a termination region) the outermost well region 30 of the semiconductor device 100. A separation region 23, which has the same n-type as the drift layer 20, is formed between the well regions 30 and 31. The n-type impurity concentration of the separation region 23 may be the same as the n-type impurity concentration of the drift layer 20, or may be higher or lower than the n-type impurity concentration of the drift layer 20.

[0042] In addition, a gate insulating film 50 is also formed on the upper surface of the well region 31, and a gate electrode 60 electrically connected to the gate electrode 60 formed on the upper surface of the well region 30 is formed on top of the gate insulating film 50.

[0043] A silicon carbide conductive layer 45 made of silicon carbide is formed in a portion of the surface layer of the well region 31. The silicon carbide conductive layer 45 has a lower resistance and a higher n-type impurity concentration than the drift layer 20. The silicon carbide conductive layer 45 has a lower sheet resistance than the well region 31 and forms a pn junction with the p-type well region 31. The silicon carbide conductive layer 45 is formed across a width equal to or greater than half the lateral width of the well region 31 that surrounds the active region in a plan view. Note that the portion where the silicon carbide conductive layer 45 is formed across a width equal to or greater than half the lateral width of the well region 31 does not need to cover the entire longitudinal range of the well region 31, and may cover only a portion of the longitudinal range.

[0044] An interlayer insulating film 55 made of silicon oxide is formed between the gate electrode 60 and the source electrode 80. Furthermore, a gate wiring 82 provided above the well region 31 and the gate electrode 60 are connected via a gate contact hole 95 formed in the interlayer insulating film 55. A p-type junction termination extension (JTE) region 37 made of silicon carbide is formed on the outer periphery of the well region 31, i.e., on the opposite side to the well region 30. The p-type impurity concentration of the JTE region 37 is lower than the p-type impurity concentration of the well region 31. An FLR (Field Limiting Ring) may be formed instead of the JTE region 37. Alternatively, a combination of the JTE region 37 and an FLR may be formed.

[0045] A field insulating film 51 having a thickness thicker than the gate insulating film 50 or the gate insulating film 50 is formed on the upper surface of the well region 31 and the upper surface of the silicon carbide conductive layer 45. An opening, i.e., a termination region contact hole 91, is formed in a part of the gate insulating film 50 or the field insulating film 51 on the upper surface of the silicon carbide conductive layer 45, and the silicon carbide conductive layer 45 is ohmically connected to the source electrode 80 formed on its upper surface through the termination region contact hole 91 via the termination portion ohmic electrode 72.

[0046] Termination region contact hole 91 penetrates gate insulating film 50 (or field insulating film 51) and interlayer insulating film 55, and makes an ohmic connection between silicon carbide conductive layer 45 and source electrode 80, but does not connect silicon carbide conductive layer 45 and well region 31. Furthermore, silicon carbide conductive layer 45 has a width greater than the diameter of termination region contact hole 91. Here, well region 31 is not directly ohmically connected to source electrode 80.

[0047] In the active region, the upper surfaces of the ohmic electrode 70, the Schottky electrode 71, and the contact region 35 are connected to the source electrode 80 via an active region contact hole 90 formed through the interlayer insulating film 55 and the gate insulating film 50.

[0048] On the other hand, a drain electrode 84 is formed on the lower surface of the semiconductor substrate 10 .

[0049] When the plane orientation of the first main surface of the semiconductor substrate 10 is a (0001) plane having an off-angle in the <11-20> direction, the striped well region 30 may be formed along the <11-20> direction or along a direction perpendicular to the off-axis direction.

[0050] <1-2. Lattice structure> Fig. 4 is a plan view showing another example of the structure of a semiconductor device that is an SiC-MOSFET with an SBD. As shown in Fig. 4, semiconductor device 101 has unit cell regions, each formed with a MOSFET region surrounding an SBD region, repeatedly arranged vertically and horizontally in a plan view, and is called a "lattice type."

[0051] In FIG. 4, unit cell regions each consisting of an n-type isolation region 21A roughly corresponding to an SBD region and a p-type well region 30A roughly corresponding to a MOSFET region are repeatedly arranged in the vertical and horizontal directions in a plan view.

[0052] The region where the SBD-integrated MOSFET is formed is called the active region, and the region formed around the active region is called the termination region. The termination region includes the region where the gate pad 81, in which the p-type well region 31 and the like are formed, is formed.

[0053] FIG. 5 is a cross-sectional view schematically illustrating an example of a cross section extending from source electrode 80 to gate wiring 82 in the outer periphery of the silicon carbide semiconductor device shown in FIG.

[0054] In FIG. 5, in semiconductor device 101, drift layer 20 made of n-type silicon carbide is formed on the upper surface of semiconductor substrate 10 made of n-type low-resistance silicon carbide.

[0055] Furthermore, a well region 31 made of p-type silicon carbide is provided in the surface layer of the drift layer 20 located in a position substantially corresponding to the region where the gate wiring 82 shown in FIG. 1 is formed.

[0056] In the active region below the region where source electrode 80 shown in FIG. 1 is formed, a plurality of well regions 30A made of p-type silicon carbide and formed in a lattice pattern are provided in the surface layer of drift layer 20.

[0057] A source region 40 made of n-type silicon carbide is formed in the surface layer of each well region 30A at a position a predetermined distance inward from the outer periphery of the well region 30A.

[0058] Furthermore, a contact region 35 made of low-resistivity p-type silicon carbide is formed in the surface layer of the well region 30A. Furthermore, a separation region 21A made of the same n-type silicon carbide as the drift layer 20 is formed in the well region 30A so as to penetrate the well region 30A. The n-type impurity concentration of the separation region 21A may be the same as the n-type impurity concentration of the drift layer 20, or may be higher or lower than the n-type impurity concentration of the drift layer 20. The contact region 35 is formed in the surface layer of the well region 30A, closer to the separation region 21A than the source region 40.

[0059] A Schottky electrode 71 is formed on the upper surface of the separation region 21A, forming a Schottky connection with the separation region 21A. Here, it is desirable that the Schottky electrode 71 is formed so as to include at least the corresponding separation region 21A in plan view (in FIG. 5, a part of the Schottky electrode 71 is formed so as to cover the well region 30A).

[0060] An ohmic electrode 70 is formed to cover a part of the upper surface of the contact region 35 and a part of the upper surface of the source region 40. A source electrode 80 connected to the ohmic electrode 70, the Schottky electrode 71, and the contact region 35 is formed on the upper surfaces thereof.

[0061] The well region 30A can easily transfer electrons and holes between the ohmic electrode 70 and the well region 30A via the low-resistance contact region 35.

[0062] In the region where the drift layer 20 is formed between adjacent well regions 30A, an n-type separation region 22 is formed. The n-type impurity concentration of the separation region 22 may be the same as the n-type impurity concentration of the drift layer 20, or may be higher or lower than the n-type impurity concentration of the drift layer 20.

[0063] A gate insulating film 50 made of silicon oxide is formed on a part of the upper surface of adjacent well regions 30A, on the upper surface of the separation region 22 located therebetween, and on a part of the upper surface of the source region 40 in each well region 30A. Furthermore, a gate electrode 60 made of polycrystalline silicon is formed on at least a portion of the upper surface of the gate insulating film 50 that overlaps with the well region 30A in plan view.

[0064] Here, the surface layer of the well region 30A that overlaps in plan view with the region where the gate electrode 60 is formed and faces the region via the gate insulating film 50 is called a channel region.

[0065] A well region 31 is formed outside (in a termination region) the outermost well region 30A of the semiconductor device 100. A separation region 23, which has the same n-type as the drift layer 20, is formed between the well region 30A and the well region 31. The n-type impurity concentration of the separation region 23 may be the same as the n-type impurity concentration of the drift layer 20, or may be higher or lower than the n-type impurity concentration of the drift layer 20.

[0066] In addition, a gate insulating film 50 is also formed on the upper surface of the well region 31, and on top of the gate insulating film 50, a gate electrode 60 is formed that is electrically connected to the gate electrode 60 formed on the upper surface of the well region 30A.

[0067] A silicon carbide conductive layer 45 made of silicon carbide is formed in a portion of the surface layer of the well region 31. The silicon carbide conductive layer 45 has a lower resistance and a higher n-type impurity concentration than the drift layer 20. The silicon carbide conductive layer 45 has a lower sheet resistance than the well region 31 and forms a pn junction with the p-type well region 31. The silicon carbide conductive layer 45 is formed across a width equal to or greater than half the lateral width of the well region 31 that surrounds the active region in a plan view. Note that the portion where the silicon carbide conductive layer 45 is formed across a width equal to or greater than half the lateral width of the well region 31 does not need to cover the entire longitudinal range of the well region 31, and may cover only a portion of the longitudinal range.

[0068] An interlayer insulating film 55 made of silicon oxide is formed between the gate electrode 60 and the source electrode 80. The gate electrode 60 and the gate wiring 82 provided above the well region 31 are connected via a gate contact hole 95 formed in the interlayer insulating film 55. A p-type JTE region 37 made of silicon carbide is formed on the outer periphery of the well region 31, i.e., on the opposite side to the well region 30A. The p-type impurity concentration of the JTE region 37 is lower than the p-type impurity concentration of the well region 31. An FLR may be formed instead of the JTE region 37. Alternatively, a combination of the JTE region 37 and an FLR may be formed.

[0069] A field insulating film 51 having a thickness thicker than the gate insulating film 50 or the gate insulating film 50 is formed on the upper surface of the well region 31 and the upper surface of the silicon carbide conductive layer 45. An opening, i.e., a termination region contact hole 91, is formed in a part of the gate insulating film 50 or the field insulating film 51 on the upper surface of the silicon carbide conductive layer 45, and the silicon carbide conductive layer 45 is ohmically connected to the source electrode 80 formed on its upper surface through the termination region contact hole 91 via the termination portion ohmic electrode 72.

[0070] Termination region contact hole 91 penetrates gate insulating film 50 (or field insulating film 51) and interlayer insulating film 55, and makes an ohmic connection between silicon carbide conductive layer 45 and source electrode 80, but does not connect silicon carbide conductive layer 45 and well region 31. Furthermore, silicon carbide conductive layer 45 has a width greater than the diameter of termination region contact hole 91. Here, well region 31 is not directly ohmically connected to source electrode 80.

[0071] In the active region, the upper surfaces of the ohmic electrode 70, the Schottky electrode 71, and the contact region 35 are connected to the source electrode 80 via an active region contact hole 90 formed through the interlayer insulating film 55 and the gate insulating film 50.

[0072] On the other hand, a drain electrode 84 is formed on the lower surface of the semiconductor substrate 10 .

[0073] <1-3. Supplementary explanation common to stripe type and grid type> Here, a high SBD areal density structure (such as a folded structure) may be formed in the region of the active region closest to the termination region, and a high SBD areal density structure (such as a region with many SBDs, such as JBS) may also be formed in the region of the termination region closest to the active region.

[0074] A sense cell for sensing current may be provided inside the active region. The on-resistance can be reduced by making the n-type impurity concentration of the separation region 22 higher than the n-type impurity concentration of the drift layer 20.

[0075] <1-4. Planar type (common to stripe type and lattice type) manufacturing method> Next, a method for manufacturing a planar type SiC-MOSFET with built-in SBD, which is a silicon carbide semiconductor device according to this embodiment, will be described with reference to Fig. 6 to Fig. 9. Fig. 6 to Fig. 9 are cross-sectional views for explaining the method for manufacturing a SiC-MOSFET with built-in SBD. Although Fig. 6 to Fig. 9 use symbols representing a stripe type structure, they can be similarly applied to a lattice type structure.

[0076] First, as shown in FIG. 6, a 1×10 SiO 2 film was deposited by chemical vapor deposition (CVD) on the upper surface of a semiconductor substrate 10 made of n-type, low-resistance silicon carbide having a first main surface oriented in the (0001) plane with an off-axis angle and a polytype of 4H. 15 cm -3 Above and 1×10 17 cm -3 Drift layer 20 made of n-type silicon carbide having the following impurity concentration and a thickness of 5 μm or more and 50 μm or less is epitaxially grown.

[0077] Next, an implantation mask is formed on a part of the upper surface of the drift layer 20 using a photoresist or the like. Then, Al (aluminum), which is a p-type impurity, is ion-implanted through the implantation mask. At this time, the depth of the Al ion implantation does not exceed the thickness of the drift layer 20, for example, 0.5 μm or more and 3 μm or less. The impurity concentration of the implanted Al is 1×10 17 cm -3 Above and 1×10 19 cm -3 The impurity concentration is in the following range and is set higher than the impurity concentration of the drift layer 20. After that, the implantation mask is removed.

[0078] By the above process, the region into which Al is ion-implanted becomes well region 30 in the active region and well region 31 in the termination region.

[0079] Next, an implantation mask is formed on the upper surface of the drift layer 20 in the termination region using photoresist or the like, and Al ions, which are p-type impurities, are implanted. At this time, the depth of the Al ion implantation is set not to exceed the thickness of the drift layer 20, for example, to 0.5 μm or more and 3 μm or less. The impurity concentration of the implanted Al ions is set to 1×10 16 cm -3 Above and 1×10 18 cm -3 The impurity concentration is in the following range, which is higher than the impurity concentration of the drift layer 20 and lower than the impurity concentration of the well region 30. Thereafter, the implantation mask is removed.

[0080] The region into which Al ions have been implanted through the above process becomes the JTE region 37.

[0081] Similarly, a predetermined region is doped with 1×10 16 cm -3 Above and 1×10 18 cm -3 The contact region 35 is formed by ion implanting Al with an impurity concentration in the following range.

[0082] Next, an implantation mask is formed using photoresist or the like so that a predetermined location inside the well region 30 on the upper surface of the drift layer 20 is opened, and N (nitrogen) as an n-type impurity is ion-implanted. The depth of N ion implantation is shallower than the thickness of the well region 30. The impurity concentration of the ion-implanted N is 1×10 18 cm -3 Above and 1×10 21 cm -3 The range is as follows, and exceeds the p-type impurity concentration of the well region 30.

[0083] Through the above process, the region that exhibits n-type among the regions into which N is implanted becomes the source region 40.

[0084] Similarly, an implantation mask is formed using photoresist or the like so that a predetermined location inside the well region 31 of the termination region is opened, and N (nitrogen) as an n-type impurity is ion-implanted. The depth of N ion implantation is shallower than the thickness of the well region 30. The impurity concentration of the ion-implanted N is 1×10 18 cm -3 Above and 1×10 21 cm -3 The range is as follows, and exceeds the p-type impurity concentration of the well region 30.

[0085] Through the above steps, the region that exhibits n-type conductivity among the regions into which N has been implanted becomes silicon carbide conductive layer 45. The thickness of silicon carbide conductive layer 45 only needs to be smaller than the thickness of well region 31.

[0086] Silicon carbide conductive layer 45 and source region 40 may be formed in the same process with the same thickness and impurity concentration, or silicon carbide conductive layer 45 and source region 40 may be formed in different processes with different thicknesses and different impurity concentrations.

[0087] Next, the substrate is annealed in a heat treatment device in an inert gas atmosphere such as argon (Ar) gas at a temperature of, for example, 1300°C or higher and 1900°C or lower for, for example, 30 seconds or higher and 1 hour or shorter. This annealing electrically activates the implanted N and Al. The structure at this stage, up to the ion implantation stage, is shown in Figure 6.

[0088] Next, as shown in FIG. 7, using a CVD method, photolithography technology, or the like, a field insulating film 51 made of silicon oxide is formed on the upper surface of the semiconductor layer (including silicon carbide conductive layer 45, well region 31, JTE region 37, and drift layer 20) in a region excluding the active region (a region roughly corresponding to the region in which well region 30 is formed). The field insulating film 51 has a thickness of, for example, 0.5 μm or more and 2 μm or less and is larger than the thickness of gate insulating film 50.

[0089] Next, the upper surface of the semiconductor layer (including the silicon carbide conductive layer 45, well region 31, drift layer 20, well region 30, contact region 35, and source region 40) that is not covered with the field insulating film 51 is thermally oxidized to form a silicon oxide film that is a gate insulating film 50 of the desired thickness.

[0090] Next, a conductive polycrystalline silicon film is formed on the upper surface of the gate insulating film 50 and the upper surface of the field insulating film 51 by low pressure CVD, and is patterned to form the gate electrode 60.

[0091] Next, an interlayer insulating film 55 made of silicon oxide and having a thickness larger than that of the gate insulating film 50 is formed by low-pressure CVD so as to cover the gate insulating film 50, the field insulating film 51, and the gate electrode 60. The structure at the end of these steps is shown in FIG.

[0092] 8, active region contact holes 90A are formed that penetrate interlayer insulating film 55 and gate insulating film 50 and reach contact region 35 and source region 40 in the active region. Furthermore, termination region contact holes 91 are formed that penetrate interlayer insulating film 55 and gate insulating film 50 and reach silicon carbide conductive layer 45 in the termination region.

[0093] The active region contact hole 90A is the area of ​​the active region contact hole 90 excluding the area where the Schottky electrode 71 is to be formed.

[0094] Next, a metal film containing Ni as its main component is formed by a sputtering method or the like, and then heat treatment is performed at a temperature of, for example, 600°C or higher and 1100°C or lower, to react the metal film containing Ni as its main component with the silicon carbide layer in the active region contact hole 90A to form silicide between the silicon carbide layer and the metal film, and also to react the metal film containing Ni as its main component with the silicon carbide layer in the termination region contact hole 91 to form silicide between the silicon carbide layer and the metal film.

[0095] Next, the remaining metal film other than the silicide formed as described above is removed by wet etching. In this manner, ohmic electrode 70 is formed in active region contact hole 90A, and termination ohmic electrode 72 is formed in termination region contact hole 91. The structure after these steps are completed is shown in FIG.

[0096] Next, as shown in FIG. 9, a metal film mainly composed of Ni is formed on the lower surface (second main surface) of the semiconductor substrate 10, and then heat treatment is performed to form a backside ohmic electrode (not shown here) on the lower surface of the semiconductor substrate 10.

[0097] Next, a resist mask 99 is formed, and the interlayer insulating film 55 and the gate insulating film 50 on the upper surface of the separation region 21 are removed. A resist mask 99 is also formed, and the interlayer insulating film 55 is removed from a position that will become the gate contact hole 95. The removal method is wet etching that does not damage the upper surface of the silicon carbide layer that will become the Schottky interface. The structure at the stage where the processes up to this point have been completed is shown in FIG.

[0098] Next, after removing the resist mask 99, a metal film to be a Schottky electrode is deposited by a method such as sputtering, and then patterned with a photoresist or the like to form a Schottky electrode 71 on the upper surface of the separation region 21 in the active region contact hole 90. The material of the Schottky electrode 71 may be Ti, Mo, or the like.

[0099] Next, a wiring metal such as Al is formed by sputtering or vapor deposition on the upper surface of drift layer 20 that has been processed up to this point (including well region 30, well region 31, contact region 35, source region 40, silicon carbide conductive layer 45, JTE region 37, and interlayer insulating film 55 that have been formed), and the wiring metal is processed into a predetermined shape by photolithography to form ohmic electrode 70, termination ohmic electrode 72, and source electrode 80 that contacts Schottky electrode 71. Furthermore, by processing the wiring metal into a predetermined shape, a gate pad 81 and gate wiring 82 that contact gate electrode 60 are formed.

[0100] In this manner, the semiconductor device according to this embodiment having the structure shown in FIG. 5 can be manufactured.

[0101] <1-5. Operation explanation> Next, the operation of the SBD-integrated SiC-MOSFET, which is a semiconductor device according to this embodiment, will be described. In the following, a semiconductor device whose semiconductor material is 4H-type silicon carbide will be described as an example. In this case, the built-in potential of the pn junction is approximately 2 V.

[0102] The operation of the SBD-integrated MOSFET, which is the semiconductor device according to this embodiment, will be briefly explained in three states.

[0103] The first state is when a higher voltage than that applied to the source electrode 80 is applied to the drain electrode 84 and a positive voltage equal to or greater than the threshold is applied to the gate electrode 60, and is hereinafter referred to as the "on state."

[0104] In this on state, an inversion channel is formed in the channel region, and a path is formed through which electrons, which are carriers, flow between n-type source region 40 and n-type separation region 22. On the other hand, no current flows through the Schottky junction formed at the contact portion between separation region 21 and Schottky electrode 71 because an electric field (reverse bias) is applied in a direction that makes it difficult for a current to flow through the Schottky junction, that is, in the reverse direction.

[0105] Electrons flowing from the source electrode 80 to the drain electrode 84 travel from the source electrode 80 through the ohmic electrode 70, the source region 40, the channel region, the separation region 22, the drift layer 20, and the semiconductor substrate 10, according to the electric field formed by the positive voltage applied to the drain electrode 84. Therefore, by applying a positive voltage to the gate electrode 60, an on-current flows from the drain electrode 84 to the source electrode 80.

[0106] The voltage applied between the source electrode 80 and the drain electrode 84 at this time is called the on-voltage, and the value obtained by dividing the on-voltage by the density of the on-current is called the on-resistance. The on-resistance is equal to the total resistance of the paths through which the electrons flow. The product of the on-resistance and the square of the on-current is equal to the conduction loss consumed by the MOSFET when it is conducting, so a low on-resistance is preferable.

[0107] The second state is where a higher voltage is applied to the drain electrode 84 than to the source electrode 80, and a voltage below the threshold is applied to the gate electrode 60, and is hereinafter referred to as the "off state."

[0108] In this off state, no inversion carriers exist in the channel region, so no on-state current flows, and the high voltage that was applied to the load in the on state is applied between source electrode 80 and drain electrode 84 of the MOSFET. In addition, an electric field in the same direction as in the "on state" is applied to the Schottky junction formed at the contact portion between separation region 21 and Schottky electrode 71, so ideally no current flows. However, since an electric field much stronger than in the "on state" is applied, leakage current may occur.

[0109] A large leakage current increases the heat generated by the MOSFET, which can lead to thermal destruction of the MOSFET and the module that uses it. Therefore, to reduce the leakage current, it is preferable to keep the electric field across the Schottky junction low.

[0110] In the third state, a voltage lower than that applied to the source electrode 80 is applied to the drain electrode 84, i.e., a back electromotive force is applied to the MOSFET, and a reflux current flows from the source electrode 80 to the drain electrode 84. Hereinafter, this state will be referred to as the "reflux state."

[0111] In this freewheeling state, a forward electric field (forward bias) is applied to the Schottky junction formed at the contact between separation region 21 and Schottky electrode 71, causing a unipolar current consisting of an electron current to flow from Schottky electrode 71 toward n-type separation region 21. At this time, the freewheeling current component of the freewheeling diode is mainly this unipolar component. Note that source electrode 80 and well region 30 are at the same potential via ohmic electrode 70.

[0112] As a result, a forward bias is also applied to the pn junction between the p-type well region 30 and the drift layer 20. However, since the pn junction is formed in parallel with the Schottky junction, when the device changes from the off state to the reflux state, the Schottky junction, which has a lower threshold voltage, turns on before the pn junction. Therefore, most of the reflux current flows through the Schottky junction, and not through the pn junction.

[0113] In this way, by incorporating an SBD, it is possible to prevent a forward current, which is a bipolar current, from flowing through the pn junction even in a reflux state.

[0114] When a bipolar current flows through a pn junction and a basal plane dislocation or other origin exists at such a location, stacking faults expand, which can reduce the breakdown voltage of the transistor. Specifically, leakage current occurs when the transistor is off, and the heat generated by the leakage current can destroy the element or circuit.

[0115] However, by incorporating an SBD as described above, it is possible to prevent a bipolar current from flowing through the pn junction during reflux, thereby improving the reliability of the semiconductor device.

[0116] <1-6. Other structures> In the above, an example has been described in which a unit cell in which an SBD and a MOSFET are integrated is provided in the active region, but the SBD and the MOSFET may also be arranged in parallel within the unit cell formed in the active region.

[0117] Furthermore, the unit cell in the active region may have an n-type channel epitaxial layer 28 formed on the upper surface of the p-type well region 30. Specifically, the n-type channel epitaxial layer 28 may be formed in a portion that overlaps with the gate insulating film 50 in plan view. Fig. 12 is a cross-sectional view schematically showing an example of the structure of an SBD-integrated SiC-MOSFET.

[0118] As shown in an example in FIG. 12, the MOSFET may be designed so that the channel epitaxial layer 28 operates as a unipolar diode when a gate voltage lower than the threshold voltage is applied, and the turn-on voltage of this unipolar diode is lower than the operating voltage of the pn diode formed by the p-type well region 30 and the n-type drift layer 20.

[0119] In this way, even in the case of a MOSFET in which reverse current is passed through the channel region during reflux operation, the same effect as that of a MOSFET with an SBD can be obtained.

[0120] <2. Trench type> <2-1. Trench type structure> 13 is a plan view showing an example of a portion of a semiconductor device that is an SBD-integrated SiC-MOSFET, as viewed from above. As shown in the example in Fig. 13, in the active region of the semiconductor device 102, stripe-shaped gate trenches GT in which transistors are formed and stripe-shaped Schottky trenches ST in which Schottky electrodes are embedded are arranged parallel to each other and alternately.

[0121] In addition, a well region 31 is formed in a termination region provided around the active region.

[0122] FIG. 14 is an enlarged plan view of the active region of the semiconductor device, which is the SBD-integrated SiC-MOSFET shown in FIG.

[0123] 14, connection regions 36 made of p-type silicon carbide are formed at regular intervals on one side surface of the gate trench GT. Furthermore, connection regions 38 made of p-type silicon carbide are formed at regular intervals on the other side surface of the gate trench GT. Similarly, connection regions 36 made of p-type silicon carbide are formed at regular intervals on one side surface of the Schottky trench ST. Furthermore, connection regions 38 made of p-type silicon carbide are formed at regular intervals on the other side surface of the Schottky trench ST.

[0124] The termination region of the semiconductor device 102 may be formed in the same manner as a planar-type SBD-integrated MOSFET, or may have a different structure to suit the trench type. Here, the active region portion of the semiconductor device 102, which is a trench-type SBD-integrated SiC-MOSFET, will be described.

[0125] Fig. 15 is a cross-sectional view of the semiconductor device 102 at a portion of the active region shown in Fig. 14 where the connection region 36 and the connection region 38 are not formed. On the other hand, Fig. 16 is a cross-sectional view of the semiconductor device 102 at a portion of the active region shown in Fig. 14 where the connection region 36 and the connection region 38 are formed.

[0126] As shown in FIGS. 14, 15 and 16, in semiconductor device 102, drift layer 20 made of n-type silicon carbide is formed on the upper surface of semiconductor substrate 10 made of n-type low-resistance silicon carbide.

[0127] In addition, in the surface layer portion of the drift layer 20, a well region 30B made of p-type silicon carbide is formed.

[0128] A source region 40B made of n-type silicon carbide is formed in a part of the surface layer of the well region 30B. A low-resistance p-type contact region 35B is formed in a part of the surface layer of the well region 30B adjacent to the source region 40B.

[0129] Furthermore, a gate trench GT is formed in the active region, penetrating the source region 40B and the well region 30B to reach the drift layer 20. Furthermore, a Schottky trench ST is formed in a location in the active region different from the location where the gate trench GT is formed, penetrating the source region 40B and the well region 30B to reach the drift layer 20.

[0130] The gate trenches GT and the Schottky trenches ST are arranged alternately and parallel to each other. In Figures 15 and 16, the gate trenches GT and the Schottky trenches ST are formed to the same depth, but the depths of the two may be different. Furthermore, the gate trenches GT and the Schottky trenches ST may be formed to the same width, or the widths of the two may be different.

[0131] A gate electrode 60B is formed in the gate trench GT via a gate insulating film 50B made of silicon oxide. The gate insulating film 50B is provided in contact with the side surface of the well region 30B sandwiched between the source region 40B and the drift layer 20. The gate electrode 60B is made of low-resistance polycrystalline silicon with a high impurity concentration. An interlayer insulating film 55B made of silicon oxide is formed on the upper surface of the gate electrode 60B.

[0132] A Schottky electrode 71B and a source electrode 80 are formed in the Schottky trench ST. The Schottky electrode 71B is formed in contact with the drift layer 20 and forms a Schottky junction with the drift layer 20.

[0133] A p-type protection region 32 is formed on the drift layer 20 side of the lower surface of the gate trench GT. A p-type protection region 33 is formed on the drift layer 20 side of the lower surface of the Schottky trench ST. The protection region 32 and the protection region 33 have the same depth and the same impurity concentration.

[0134] 14 and 16, the protection region 32 and the well region 30B are connected by a p-type connection region 36. Also, in Figures 14 and 16, the protection region 33 and the well region 30B are connected by a p-type connection region 38.

[0135] An ohmic electrode 70 is formed across the upper surfaces of the source regions 40B and 35B. A source electrode 80 connected to the ohmic electrode 70, the Schottky electrode 71B, and the contact region 35B is formed to cover these.

[0136] The well region 30B can easily transfer electrons and holes between the ohmic electrode 70 and the well region 30B via the low-resistance contact region 35B.

[0137] The source electrode 80 is also connected to the Schottky electrode 71B in the Schottky trench ST.

[0138] A region of the well region 30B that faces the gate electrode 60B via the gate insulating film 50B on the side surface of the gate trench GT in which the gate electrode 60B is formed is called a channel region.

[0139] Furthermore, a Schottky diode is formed on the side surface of the Schottky trench ST at a location where the Schottky electrode 71B and the drift layer 20 are in contact with each other.

[0140] On the other hand, a drain electrode 84 is formed on the lower surface of the semiconductor substrate 10 .

[0141] The well region 31 in the termination region may be formed to the same depth as the well region 30B in the active region, or may be formed to the same depth as the protection region 32 and the protection region 33 in the active region, that is, to the depth of the bottoms of the gate trench GT and the Schottky trench ST. A low-resistance n-type silicon carbide conductive layer 45 may be formed in a surface layer portion of the well region 31.

[0142] Furthermore, the well region 31 may be formed so as not to be in direct ohmic contact with the source electrode 80 .

[0143] <2-2. Trench type manufacturing method> Next, a method for manufacturing a trench-type SiC-MOSFET with built-in SBD, which is a silicon carbide semiconductor device according to this embodiment, will be described with reference to Fig. 17 to Fig. 22. Fig. 17 to Fig. 22 are cross-sectional views for explaining the method for manufacturing a SiC-MOSFET with built-in SBD. Here, the description will be given using a cross section of a portion where connection region 36 and connection region 38 are not formed.

[0144] First, as shown in FIG. 17, a 1×10 SiO 2 film was deposited by chemical vapor deposition (CVD) on the upper surface of a semiconductor substrate 10 made of n-type, low-resistance silicon carbide having a first main surface with a plane orientation of (0001) having an off-angle and a polytype of 4H. 15 cm -3 Above and 1×10 17 cm -3 Drift layer 20 made of n-type silicon carbide having the following impurity concentration and a thickness of 5 μm or more and 50 μm or less is epitaxially grown.

[0145] Next, p-type impurity Al (aluminum) is ion-implanted into the upper surface of the drift layer 20. At this time, the depth of the Al ion implantation does not exceed the thickness of the drift layer 20, for example, 0.5 μm or more and 3 μm or less. The impurity concentration of the implanted Al is 1×10 17 cm -3 Above and 1×10 19 cm-3 The impurity concentration is in the range below, and is set higher than the impurity concentration of the drift layer 20.

[0146] Through the above process, the region into which Al is ion-implanted becomes well region 30B in the active region, and becomes well region 31 in the termination region. Note that well region 30B may be formed on the upper surface of drift layer 20 by an epitaxial method.

[0147] Next, a predetermined region in the surface layer of the well region 30B is doped with an impurity concentration higher than that of the well region 30B, for example, 1×10 16 cm -3 Above and 1×10 18 cm -3 The contact region 35B is formed by ion implanting Al with an impurity concentration in the following range.

[0148] Furthermore, N, an n-type impurity, is ion-implanted into a predetermined region in the surface layer of the well region 30B on the upper surface of the drift layer 20. The depth of the N ion implantation is shallower than the thickness of the well region 30B. The impurity concentration of the ion-implanted N is 1×10 18 cm -3 Above and 1×10 21 cm -3 The range is as follows, and is higher than the p-type impurity concentration of the well region 30B.

[0149] Through the above steps, the region that exhibits n-type conductivity among the regions into which N has been implanted becomes source region 40 B. The structure at the stage where the steps up to this point have been completed is shown in FIG.

[0150] 18, a gate trench GT is formed in the area where the source region 40B is formed, and a Schottky trench ST is formed in the area where the source region 40B and the contact region 35B are not formed. Then, a protection region 32 is formed at the bottom of the gate trench GT by ion-implanting Al, which is a p-type impurity, into the bottom of the gate trench GT. Similarly, a protection region 33 is formed at the bottom of the Schottky trench ST by ion-implanting Al, which is a p-type impurity, into the bottom of the Schottky trench ST. The impurity concentrations of the protection region 32 and the protection region 33 are, for example, 1×10 17 cm -3 Above and 1×10 19 cm -3 The following range is acceptable.

[0151] The connection regions 36 and 38 may be formed by obliquely implanting ions of p-type impurities such as Al from a direction perpendicular to the extension direction of the stripe-shaped trenches. The impurity concentration of the connection regions 36 and 38 is 1×10 17 cm -3 Above and 1×10 19 cm -3 It may be formed by ion implanting Al with an impurity concentration in the following range.

[0152] Here, if the plane orientation of the first main surface of the semiconductor substrate 10 is a (0001) plane having an off-axis angle in the <11-20> direction, the gate trench GT and the Schottky trench ST in the active region can both be formed parallel to the <11-20> direction. In this way, the side surfaces (trench sidewalls) on both sides of the Schottky trench ST are not affected by the off-axis direction of the semiconductor substrate 10. This reduces the variation in the barrier height of the Schottky interface of the Schottky trench ST. Furthermore, since the threshold voltage of the MOSFET in the gate trench GT is not affected by the off-axis direction of the semiconductor substrate 10, the variation in the threshold voltage of the MOSFET can be reduced.

[0153] Next, the substrate is annealed in a heat treatment device in an inert gas atmosphere such as Ar gas at a temperature of 1300°C to 1900°C for, for example, 30 seconds to 1 hour. This annealing electrically activates the implanted N and Al ions. The structure after these steps is shown in Figure 18.

[0154] Next, as shown in FIG. 19, the inside of the Schottky trench ST is filled with a protective insulating film 52 such as silicon oxide.

[0155] Next, as shown in FIG. 20, a gate insulating film 50B made of silicon oxide is formed in the gate trench GT, and further, inside the gate trench GT surrounded by the gate insulating film 50B, a gate electrode 60B made of a conductive, low-resistance polycrystalline silicon film is formed by low-pressure CVD and patterning.

[0156] Then, on the upper surface of the gate electrode 60B, an interlayer insulating film 55B made of silicon oxide or the like and having a thickness larger than that of the gate insulating film 50B is formed by low pressure CVD.

[0157] Next, the interlayer insulating film 55B and the gate insulating film 50B are removed by wet etching so as to expose the contact region 35B and the source region 40B in the active region. The structure after these steps are completed is shown in FIG.

[0158] 21 , a metal film mainly composed of Ni is formed by sputtering or the like on the upper surface where interlayer insulating film 55B and gate insulating film 50B have been removed to expose source region 40B and contact region 35B. Thereafter, a heat treatment is performed at a temperature of 600° C. or higher and 1100° C. or lower, for example, to react the metal film mainly composed of Ni with the silicon carbide layer, thereby forming a silicide between the silicon carbide layer and the metal film.

[0159] Next, the remaining metal film other than the silicide formed as described above is removed by wet etching, and the remaining silicide becomes the ohmic electrode 70. The structure after these steps are completed is shown in FIG.

[0160] 22, protective insulating film 52 in Schottky trench ST is removed with hydrofluoric acid or the like, and Schottky electrode 71B is formed in Schottky trench ST (specifically, on the bottom and side surfaces). Schottky electrode 71B may be made of Ti, Mo, or the like.

[0161] Next, a source electrode 80 mainly made of Al is formed so as to connect to the Schottky electrode 71B and the ohmic electrode 70. A gate pad 81 and a gate wiring 82 may be formed simultaneously with the source electrode 80. The structure of the active region after these steps have been completed is shown in FIG.

[0162] Furthermore, a drain electrode 84 made of a metal film is formed on the lower surface of a back surface ohmic electrode (not shown here) formed on the lower surface (back surface) of the semiconductor substrate 10. In this manner, the semiconductor device 102 according to this embodiment shown in FIG. 15 or 16 can be manufactured.

[0163] <2-3. Operational Description> The operation of the trench-type SiC-MOSFET with built-in SBD, which is the semiconductor device according to this embodiment, is similar to that of the planar-type SiC-MOSFET with built-in SBD.

[0164] In the freewheeling state, a freewheeling current flows from the source electrode 80 to the drain electrode 84 when a voltage lower than that of the source electrode 80 is applied to the drain electrode 84, that is, when a back electromotive force is applied to the MOSFET.

[0165] In this freewheeling state, a forward electric field (forward bias) is applied to the Schottky junction formed at the contact between the drift layer 20 and the Schottky electrode 71B, and a unipolar current consisting of an electron current flows from the Schottky electrode 71B toward the n-type drift layer 20. At this time, the freewheeling current component of the freewheeling diode is mainly this unipolar component. Note that the source electrode 80 and the well region 30B are at the same potential via the ohmic electrode 70.

[0166] As a result, a forward bias is also applied to the pn junction between the p-type well region 30B and the drift layer 20. However, since the pn junction is formed in parallel with the Schottky junction, when the device changes from the off state to the reflux state, the Schottky junction, which has a lower threshold voltage, turns on before the pn junction. Therefore, most of the reflux current flows through the Schottky junction, and not through the pn junction.

[0167] In this way, by incorporating an SBD, it is possible to prevent a forward current, which is a bipolar current, from flowing through the pn junction even in a reflux state.

[0168] When a bipolar current flows through a pn junction and a basal plane dislocation or other origin exists at such a location, stacking faults expand, which can reduce the breakdown voltage of the transistor. Specifically, leakage current occurs when the transistor is off, and the heat generated by the leakage current can destroy the element or circuit.

[0169] However, by incorporating an SBD as described above, it is possible to prevent a bipolar current from flowing through the pn junction during reflux, thereby improving the reliability of the semiconductor device.

[0170] <3. Supplementary explanation for the whole> In the above embodiment, aluminum (Al) is used as the p-type impurity, but the p-type impurity may be boron (B) or gallium (Ga). Also, the n-type impurity may be phosphorus (P) instead of nitrogen (N).

[0171] In the MOSFETs described in the above embodiments, the gate insulating film 50 does not necessarily have to be an oxide film such as SiO2, but may be an insulating film other than an oxide film, or a combination of an insulating film other than an oxide film and an oxide film. Furthermore, although silicon oxide obtained by thermally oxidizing silicon carbide is used as the gate insulating film 50, silicon oxide deposited by CVD may also be used.

[0172] Furthermore, in the above embodiment, specific examples of the crystal structure, the plane orientation of the main surface, the off-angle, and the respective implantation conditions are used, but the applicable range is not limited to these numerical ranges.

[0173] The semiconductor device may also be a MOSFET having a superjunction structure with an SBD built in.

[0174] <4. Testing Method> The inspection method according to this embodiment will be described below. Analysis by the inventors has revealed that MOSFETs with low I2t tolerance contain stacking faults.

[0175] The SBD built into a semiconductor device shares a drift layer with the MOSFET. Therefore, when a high-resistivity layer blocks the SBD portion due to stacking faults, the parallel connection between the body diode and the built-in SBD is broken, resulting in a drop in the operating voltage of the body diode. In particular, in modules with multiple MOSFET chips connected in parallel, current concentrates in the MOSFET chip with a lowered body diode operating voltage, causing it to break down quickly, further reducing the overall It capability.

[0176] Therefore, by removing (dropping) MOSFET chips that contain stacking faults, it is possible to screen out MOSFET chips with low I2t capability. However, there are many stacking faults in the SiC drift layer, and only a portion of them affect the I2t capability.

[0177] FIG. 23 shows an example of the effect of stacking faults (SF) on gate voltage. The horizontal axis of FIG. 23 shows the gate voltage Vgs value when the drain current Ids is 4.28 μA. The vertical axis of FIG. 23 shows the gate voltage Vgs value when the drain current Ids is 4.28 mA for the same device. In FIG. 23, MOSFET chips without stacking faults are indicated by white circles, and MOSFET chips with stacking faults are indicated by black circles.

[0178] As shown in Figure 23, the majority of MOSFET chips with stacking faults do not affect the I²t capability, i.e., the I²t capability is not significantly reduced. Therefore, it is unrealistic to reject all MOSFET chips containing stacking faults.

[0179] It would be ideal if the body diode could be activated and screening could be performed based on its operating voltage, but the nature of MOSFETs with built-in SBDs is such that the body diode is designed to operate as little as possible, making screening based on the electrical characteristics at the chip stage difficult.

[0180] On the other hand, if a module has many MOSFETs with built-in SBDs connected in parallel, it is possible to actually apply a current surge to screen them, but if any of the MOSFET chips in the module are removed by screening, all of the parallel-connected chips mounted on the module will have to be discarded, which will increase costs.

[0181] As a different approach, it is possible to identify the influence of stacking faults that reduce the operating voltage of the body diode on characteristics other than the body diode, and to remove MOSFET chips that have stacking faults based on this. Our analysis has shown that stacking faults that reduce the operating voltage of the body diode cause abnormalities in the drain current-gate voltage characteristics.

[0182] FIG. 10 is a diagram showing an example of the relationship between gate voltage and drain current of a semiconductor device. The stacking faults that reduce the operating voltage of the body diode have the effect of lowering the gate voltage in the rising region of the drain current, which is the current flowing from the drain electrode 84 to the source electrode 80. In the example of FIG. 10, the gate voltage Vg1a (see dotted line) at the drain current Id1, which is a low drain current, is lower than the gate voltage Vg1 (see solid line) at the drain current Id1 of a semiconductor device that does not have stacking faults that reduce the operating voltage of the body diode. This tendency is particularly pronounced when an n-type low-resistance layer (source region) is formed in the surface layer of a p-type well region in contact with the gate insulating film.

[0183] Therefore, by focusing on the amount of change in gate voltage as described above, it is possible to screen for MOSFET chips with low body diode operating voltages.

[0184] The above-mentioned decrease in gate voltage occurs in the low current region and disappears in the high current region. Therefore, for the MOSFET chip to be inspected, the difference between the gate voltage at a low drain current Id1 and the gate voltage at a high drain current Id2 is calculated at a constant drain voltage, and MOSFET chips for which this difference exceeds the threshold are eliminated (i.e., excluded), and MOSFET chips for which this difference does not exceed the threshold are selected.

[0185] Here, the combinations of gate voltage and drain current are not limited to the low current region and the high current region as described above, but may be compared with combinations of gate voltage and drain current in three or more regions.Furthermore, the above effect (i.e., the effect of lowering the gate voltage in the rising region of the drain current) may be detected by a calculation method other than a simple difference.

[0186] The larger the difference between the drain current values ​​used in the test, the better, and the ratio between the maximum and minimum drain currents is selected to be, for example, 100 times or more.

[0187] As described above, by applying the inspection method according to this embodiment to a semiconductor device incorporating an SBD, it is possible to screen for semiconductor devices with low I2t tolerance.

[0188] <Second embodiment> A method for inspecting a semiconductor device and a method for manufacturing a semiconductor device according to this embodiment will be described.

[0189] According to the analysis by the inventors, stacking faults that reduce the operating voltage of the body diode of a MOSFET with an SBD also affect the breakdown voltage characteristics (the relationship between drain voltage and drain current). Therefore, by focusing on the breakdown voltage characteristics, it is possible to screen for MOSFET chips that contain stacking faults that reduce the operating voltage of the body diode.

[0190] 11 is a diagram showing an example of the relationship between the drain voltage and the drain current of a semiconductor device. This diagram shows an example in which the gate voltage is changed under a drain voltage Vdm3, which is a drain voltage lower than the avalanche voltage. Here, the drain voltage is the voltage applied between the drain electrode 84 and the source electrode 80.

[0191] In the example of FIG. 11, the difference between the drain current Id3 (see the solid line) corresponding to the drain voltage Vdm3 when the gate voltage Vg3 is a low gate voltage and the drain current Id4 (see the dotted line) corresponding to the drain voltage Vdm3 when the gate voltage Vg4 is a high gate voltage is calculated, and MOSFET chips for which this difference exceeds a threshold value (i.e., when the gate voltage is increased, the drain current becomes greater than the reference value) are eliminated (i.e., excluded), and MOSFET chips for which this difference does not exceed the threshold value are selected.

[0192] Here, the combination of gate voltage and drain voltage is not limited to the above two, but may be three or more combinations. Furthermore, the above effect (i.e., the effect that the drain current becomes larger than the reference value when the gate voltage increases) may be detected by a calculation method other than a simple difference.

[0193] Among the gate voltages used for the inspection, the difference between the maximum and minimum voltages is selected to be, for example, 1 V or more.

[0194] <Effects Produced by the Multiple Embodiments Described Above> Next, examples of effects obtained by the above-described embodiments will be described. Note that in the following description, the effects will be described based on the specific configurations exemplified in the above-described embodiments, but these may be replaced with other specific configurations exemplified in this instruction manual to the extent that similar effects are obtained. In other words, for convenience, only one of the associated specific configurations may be described as a representative below, but the representatively described specific configuration may be replaced with another associated specific configuration.

[0195] Furthermore, the replacement may be made across multiple embodiments, i.e., configurations illustrated in different embodiments may be combined to produce the same effect.

[0196] According to the embodiment described above, the SBD region and the MOSFET region are provided on the first main surface side of the semiconductor substrate 10 made of silicon carbide. A drift layer 20 of a first conductivity type is provided on the first main surface of the semiconductor substrate 10. The MOSFET region includes a well region of a second conductivity type, a source region of the first conductivity type, a gate insulating film 50 (or a gate insulating film 50B), a gate electrode 60 (or a gate electrode 60B), and an interlayer insulating film 55 (or an interlayer insulating film 55B). The well region of the second conductivity type corresponds to, for example, the p-type well region 30 or the well region 30B. The source region of the first conductivity type corresponds to, for example, the n-type source region 40 or the source region 40B. The well region 30 is provided in a surface layer on the first main surface side of the drift layer 20. The source region 40 is provided in a surface layer of the well region 30. The gate insulating film 50 is provided in contact with the well region 30 sandwiched between the source region 40 and the drift layer 20. The gate electrode 60 is provided in contact with the gate insulating film 50. The interlayer insulating film 55 covers the gate electrode 60. The SBD region also includes a Schottky electrode 71 (or a Schottky electrode 71B) that forms a Schottky junction with the drift layer 20 on the first main surface side of the drift layer 20. The semiconductor device also includes a source electrode 80 and a drain electrode 84. The source electrode 80 is connected to the Schottky electrode 71. The source electrode 80 covers the interlayer insulating film 55. The drain electrode 84 is provided on the second main surface side, which is the main surface opposite to the first main surface of the semiconductor substrate 10. In a method for testing a semiconductor device including an SBD region and a MOSFET region, a first gate voltage applied to the gate electrode 60 corresponding to a first drain current flowing from the drain electrode 84 to the source electrode 80 is measured. Here, the first drain current corresponds to, for example, drain current Id1. The first gate voltage corresponds to, for example, gate voltage Vg1 or gate voltage Vg1a. Then, a second gate voltage applied to gate electrode 60 corresponding to a second drain current greater than drain current Id1 is measured. Here, the second drain current corresponds to, for example, drain current Id2.The second gate voltage corresponds to, for example, the gate voltage Vg2, etc. Then, it is checked whether the difference between the gate voltage Vg1a and the gate voltage Vg2 exceeds a predetermined threshold value (for example, a value based on the difference between the gate voltage Vg1 and the gate voltage Vg2).

[0197] With this configuration, a MOSFET with an SBD having a low I2t tolerance can be detected based on the difference in the corresponding gate voltage at different drain current values, taking advantage of the fact that a MOSFET with an SBD having a low I2t tolerance will have an abnormality in its drain current-gate voltage characteristics due to stacking faults.

[0198] Specifically, the above inspection method identifies, from the electrical characteristics, stacking faults that have reached the surface layer of the body diode.

[0199] Unless otherwise specified, the order in which the processes are performed can be changed.

[0200] Furthermore, if other configurations shown as examples in this instruction manual are added to the above configuration as appropriate, that is, if other configurations in this instruction manual that are not mentioned as the above configuration are added as appropriate, the same effect can be achieved.

[0201] Furthermore, according to the embodiment described above, the ratio of the drain current Id1 to the drain current Id2 is 100 times or more. With this configuration, the larger the ratio of the drain current values ​​used in the test, the larger the corresponding gate voltage deviation. This improves the test accuracy.

[0202] Furthermore, according to the above-described embodiment, in the semiconductor device testing method, a first drain current flowing from the drain electrode 84 to the source electrode 80 corresponding to a first gate voltage applied to the gate electrode 60 is measured while a first drain voltage applied between the drain electrode 84 and the source electrode 80 is kept constant. Here, the first drain voltage corresponds to, for example, a drain voltage Vdm3. The first gate voltage corresponds to, for example, a gate voltage Vg3. The first drain current corresponds to, for example, a drain current Id3. Then, the drain voltage Vdm3 is applied between the drain electrode 84 and the source electrode 80, and a drain current Id4 flowing from the drain electrode 84 to the source electrode 80 corresponding to a gate voltage Vg4 applied to the gate electrode 60 is measured. Here, the second gate voltage corresponds to, for example, a gate voltage Vg4. The second drain current corresponds to, for example, a drain current Id4. Here, the gate voltage Vg4 is a voltage different from the gate voltage Vg3. Then, it is checked whether the difference between the drain current Id3 and the drain current Id4 exceeds a predetermined threshold value (for example, a value based on the difference between the drain current corresponding to the gate voltage Vg3 and the drain current corresponding to the gate voltage Vg4 in a MOSFET chip that does not contain stacking faults).

[0203] With this configuration, a MOSFET with an SBD having a low I2t capability can be detected based on the difference in corresponding drain currents at different gate voltage values, taking advantage of the fact that a MOSFET with an SBD having a low I2t capability will have an abnormality in its drain current-drain voltage characteristics due to stacking faults.

[0204] Specifically, the above inspection method identifies, from the electrical characteristics, stacking faults that have reached the surface layer of the body diode.

[0205] Unless otherwise specified, the order in which the processes are performed can be changed.

[0206] Furthermore, if other configurations shown as examples in this instruction manual are added to the above configuration as appropriate, that is, if other configurations in this instruction manual that are not mentioned as the above configuration are added as appropriate, the same effect can be achieved.

[0207] Furthermore, according to the embodiment described above, the difference between the gate voltage Vg3 and the gate voltage Vg4 is 1 V or more. With this configuration, the difference in the gate voltages used in the test is sufficiently large, and the corresponding difference in drain current is also large. This improves the test accuracy.

[0208] According to the embodiment described above, in the method for manufacturing a semiconductor device, a first conductivity type drift layer 20 is formed on a first main surface of a semiconductor substrate 10 made of silicon carbide. Then, a second conductivity type well region 30 is formed on the surface layer on the first main surface side of the drift layer 20. A first conductivity type source region 40 is formed on the surface layer of the well region 30. A gate insulating film 50 is formed in contact with the well region 30 sandwiched between the source region 40 and the drift layer 20. A gate electrode 60 is formed in contact with the gate insulating film 50. An interlayer insulating film 55 is formed to cover the gate electrode 60, thereby forming a MOSFET region. Furthermore, an SBD region is formed by forming a Schottky electrode 71 on the first main surface side of the drift layer 20, the Schottky electrode 71 forming a Schottky junction with the drift layer 20. Then, a source electrode 80 is formed, connected to the Schottky electrode 71 and covering the interlayer insulating film 55. Then, a drain electrode 84 is formed on a second main surface side of the semiconductor substrate 10, which is the main surface opposite the first main surface. Then, a first gate voltage applied to the gate electrode 60 corresponding to the drain current Id1 flowing from the drain electrode 84 to the source electrode 80 is measured. Here, the first gate voltage corresponds to, for example, a gate voltage Vg1. Then, a second gate voltage applied to the gate electrode 60 corresponding to a drain current Id2 having a value greater than the drain current Id1 is measured. Here, the second gate voltage corresponds to, for example, a gate voltage Vg2. Then, a semiconductor device in which the difference between the gate voltages Vg1 and Vg2 does not exceed a predetermined threshold is selected.

[0209] With this configuration, MOSFETs with built-in SBDs that have low I2t tolerance can cause abnormalities in the drain current-gate voltage characteristics due to stacking faults. This can be utilized to detect and remove MOSFETs with built-in SBDs that have low I2t tolerance based on the difference in corresponding gate voltages at different drain current values.

[0210] Unless otherwise specified, the order in which the processes are performed can be changed.

[0211] Furthermore, if other configurations shown as examples in this instruction manual are added to the above configuration as appropriate, that is, if other configurations in this instruction manual that are not mentioned as the above configuration are added as appropriate, the same effect can be achieved.

[0212] Furthermore, according to the embodiment described above, the ratio of the drain current Id1 to the drain current Id2 is 100 times or more. With this configuration, the larger the ratio of the drain current values ​​used in the test, the larger the corresponding gate voltage deviation. This improves the test accuracy.

[0213] According to the above-described embodiment, in the method for manufacturing a semiconductor device, a drift layer 20 is formed on a first main surface of a semiconductor substrate 10 made of silicon carbide. Then, a well region 30 is formed on the surface layer of the first main surface of the drift layer 20, a source region 40 is formed on the surface layer of the well region 30, a gate insulating film 50 is formed in contact with the well region 30 sandwiched between the source region 40 and the drift layer 20, a gate electrode 60 is formed in contact with the gate insulating film 50, and an interlayer insulating film 55 is formed to cover the gate electrode 60, thereby forming a MOSFET region. Furthermore, a Schottky electrode 71 that forms a Schottky junction with the drift layer 20 is formed on the first main surface of the drift layer 20, thereby forming an SBD region. A source electrode 80 is formed that is connected to the Schottky electrode 71 and covers the interlayer insulating film 55. A drain electrode 84 is formed on a second main surface of the semiconductor substrate 10, which is the main surface opposite the first main surface. Then, a drain current Id3 flowing from the drain electrode 84 to the source electrode 80 corresponding to a gate voltage Vg3 applied to the gate electrode 60 is measured while a drain voltage Vdm3 applied between the drain electrode 84 and the source electrode 80 is kept constant. Furthermore, the drain voltage Vdm3 is applied between the drain electrode 84 and the source electrode 80, and a drain current Id4 flowing from the drain electrode 84 to the source electrode 80 corresponding to a gate voltage Vg4 applied to the gate electrode 60 is measured. Here, the gate voltage Vg4 is a voltage different from the gate voltage Vg3. Then, a semiconductor device is selected in which the difference between the drain current Id3 and the drain current Id4 does not exceed a predetermined threshold value.

[0214] With this configuration, MOSFETs with built-in SBDs that have low I2t tolerance can cause abnormalities in their drain current-drain voltage characteristics due to stacking faults. This can be utilized to detect and remove MOSFETs with built-in SBDs that have low I2t tolerance based on the difference in corresponding drain currents at different gate voltage values.

[0215] Unless otherwise specified, the order in which the processes are performed can be changed.

[0216] Furthermore, if other configurations shown as examples in this instruction manual are added to the above configuration as appropriate, that is, if other configurations in this instruction manual that are not mentioned as the above configuration are added as appropriate, the same effect can be achieved.

[0217] Furthermore, according to the embodiment described above, the difference between the gate voltage Vg3 and the gate voltage Vg4 is 1 V or more. With this configuration, the difference in the gate voltages used in the test is sufficiently large, and the corresponding difference in drain current is also large. This improves the test accuracy.

[0218] <Modifications of the above-described embodiments> In the multiple embodiments described above, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may also be described, but these are merely examples in all aspects and are not limiting.

[0219] Therefore, countless modifications and equivalents not shown as examples are contemplated within the scope of the technology disclosed in this specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component from at least one embodiment and combining it with a component from another embodiment.

[0220] Furthermore, in at least one of the embodiments described above, when a material name or the like is stated without being specifically specified, unless a contradiction arises, it is assumed that the material in question includes other additives, such as alloys.

[0221] Various aspects of the present disclosure are summarized below as appendices.

[0222] (Appendix 1) A method for testing a semiconductor device having an SBD region and a MOSFET region, the SBD region and the MOSFET region are provided on a first main surface side of a semiconductor substrate made of silicon carbide; a drift layer of a first conductivity type is provided on the first main surface of the semiconductor substrate; the MOSFET region a well region of a second conductivity type provided in a surface layer of the drift layer on the first main surface side; a first conductivity type source region provided in a surface layer of the well region; a gate insulating film provided in contact with the well region sandwiched between the source region and the drift layer; a gate electrode provided in contact with the gate insulating film; an interlayer insulating film covering the gate electrode; the SBD region includes a Schottky electrode that forms a Schottky junction with the drift layer on the first principal surface side of the drift layer, The semiconductor device is a source electrode connected to the Schottky electrode and covering the interlayer insulating film; a drain electrode provided on a second main surface of the semiconductor substrate opposite to the first main surface, The semiconductor device inspection method includes: measuring a first gate voltage applied to the gate electrode corresponding to a first drain current flowing from the drain electrode to the source electrode; measuring a second gate voltage applied to the gate electrode corresponding to a second drain current greater than the first drain current; checking whether a difference between the first gate voltage and the second gate voltage exceeds a predetermined threshold; A method for inspecting a semiconductor device.

[0223] (Appendix 2) A method for inspecting a semiconductor device according to claim 1, The ratio of the first drain current to the second drain current is 100 times or more. A method for inspecting a semiconductor device.

[0224] (Appendix 3) A method for testing a semiconductor device having an SBD region and a MOSFET region, the SBD region and the MOSFET region are provided on a first main surface side of a semiconductor substrate made of silicon carbide; a drift layer of a first conductivity type is provided on the first main surface of the semiconductor substrate; the MOSFET region a well region of a second conductivity type provided in a surface layer of the drift layer on the first main surface side; a first conductivity type source region provided in a surface layer of the well region; a gate insulating film provided in contact with the well region sandwiched between the source region and the drift layer; a gate electrode provided in contact with the gate insulating film; an interlayer insulating film covering the gate electrode; the SBD region includes a Schottky electrode that forms a Schottky junction with the drift layer on the first principal surface side of the drift layer, The semiconductor device is a source electrode connected to the Schottky electrode and covering the interlayer insulating film; a drain electrode provided on a second main surface of the semiconductor substrate opposite to the first main surface, The semiconductor device inspection method includes: measuring a first drain current flowing from the drain electrode to the source electrode corresponding to a first gate voltage applied to the gate electrode while maintaining a first drain voltage applied between the drain electrode and the source electrode constant; applying the first drain voltage between the drain electrode and the source electrode and measuring a second drain current flowing from the drain electrode to the source electrode corresponding to a second gate voltage applied to the gate electrode; the second gate voltage is different from the first gate voltage; checking whether a difference between the first drain current and the second drain current exceeds a predetermined threshold; A method for inspecting a semiconductor device.

[0225] (Appendix 4) A method for inspecting a semiconductor device according to Supplementary Note 3, The difference between the first gate voltage and the second gate voltage is 1 V or more. A method for inspecting a semiconductor device.

[0226] (Appendix 5) A method for manufacturing a semiconductor device including an SBD region and a MOSFET region, forming a drift layer of a first conductivity type on a first main surface of a semiconductor substrate made of silicon carbide; forming a well region of a second conductivity type in a surface layer on the first main surface side of the drift layer, forming a source region of a first conductivity type in a surface layer of the well region, forming a gate insulating film in contact with the well region sandwiched between the source region and the drift layer, forming a gate electrode in contact with the gate insulating film, and forming an interlayer insulating film covering the gate electrode, thereby forming the MOSFET region; forming a Schottky electrode on the first principal surface side of the drift layer to form a Schottky junction with the drift layer, thereby forming the SBD region; forming a source electrode connected to the Schottky electrode and covering the interlayer insulating film; forming a drain electrode on a second main surface of the semiconductor substrate, the second main surface being the main surface opposite to the first main surface; measuring a first gate voltage applied to the gate electrode corresponding to a first drain current flowing from the drain electrode to the source electrode; measuring a second gate voltage applied to the gate electrode corresponding to a second drain current greater than the first drain current; selecting the semiconductor device in which a difference between the first gate voltage and the second gate voltage does not exceed a predetermined threshold value; A method for manufacturing a semiconductor device.

[0227] (Appendix 6) A method for manufacturing a semiconductor device according to Supplementary Note 5, The ratio of the first drain current to the second drain current is 100 times or more. A method for manufacturing a semiconductor device.

[0228] (Appendix 7) A method for manufacturing a semiconductor device including an SBD region and a MOSFET region, forming a drift layer of a first conductivity type on a first main surface of a semiconductor substrate made of silicon carbide; forming a well region of a second conductivity type in a surface layer on the first main surface side of the drift layer, forming a source region of a first conductivity type in a surface layer of the well region, forming a gate insulating film in contact with the well region sandwiched between the source region and the drift layer, forming a gate electrode in contact with the gate insulating film, and forming an interlayer insulating film covering the gate electrode, thereby forming the MOSFET region; forming a Schottky electrode on the first principal surface side of the drift layer to form a Schottky junction with the drift layer, thereby forming the SBD region; forming a source electrode connected to the Schottky electrode and covering the interlayer insulating film; forming a drain electrode on a second main surface of the semiconductor substrate, the second main surface being the main surface opposite to the first main surface; measuring a first drain current flowing from the drain electrode to the source electrode corresponding to a first gate voltage applied to the gate electrode while maintaining a first drain voltage applied between the drain electrode and the source electrode constant; applying the first drain voltage between the drain electrode and the source electrode and measuring a second drain current flowing from the drain electrode to the source electrode corresponding to a second gate voltage applied to the gate electrode; the second gate voltage is different from the first gate voltage; selecting the semiconductor device in which a difference between the first drain current and the second drain current does not exceed a predetermined threshold value; A method for manufacturing a semiconductor device.

[0229] (Appendix 8) A method for manufacturing a semiconductor device according to claim 7, The difference between the first gate voltage and the second gate voltage is 1 V or more. A method for manufacturing a semiconductor device. [Explanation of symbols]

[0230] 10 semiconductor substrate, 20 drift layer, 30 well region, 30A well region, 30B well region, 31 well region, 40 source region, 40B source region, 50 gate insulating film, 50B gate insulating film, 55 interlayer insulating film, 55B interlayer insulating film, 60 gate electrode, 60B gate electrode, 71 Schottky electrode, 71B Schottky electrode, 80 source electrode, 84 drain electrode, 100 semiconductor device, 101 semiconductor device, 102 semiconductor device.

Claims

1. A method for testing a semiconductor device including an SBD region and a MOSFET region, the SBD region and the MOSFET region are provided on a first main surface side of a semiconductor substrate made of silicon carbide, a drift layer of a first conductivity type is provided on the first main surface of the semiconductor substrate; The MOSFET region is a well region of a second conductivity type provided in a surface layer of the drift layer on the first main surface side; a first conductivity type source region provided in a surface layer of the well region; a gate insulating film provided in contact with the well region sandwiched between the source region and the drift layer; a gate electrode provided in contact with the gate insulating film; an interlayer insulating film covering the gate electrode; the SBD region includes a Schottky electrode that forms a Schottky junction with the drift layer on the first main surface side of the drift layer, The semiconductor device is a source electrode connected to the Schottky electrode and covering the interlayer insulating film; a drain electrode provided on a second main surface of the semiconductor substrate opposite to the first main surface, The semiconductor device inspection method includes: measuring a first gate voltage applied to the gate electrode corresponding to a first drain current flowing from the drain electrode to the source electrode; measuring a second gate voltage applied to the gate electrode corresponding to a second drain current greater than the first drain current; checking whether a difference between the first gate voltage and the second gate voltage exceeds a predetermined threshold; A method for inspecting a semiconductor device.

2. 2. The semiconductor device inspection method according to claim 1, a ratio of the first drain current to the second drain current is 100 times or more; A method for inspecting a semiconductor device.

3. A method for testing a semiconductor device including an SBD region and a MOSFET region, the SBD region and the MOSFET region are provided on a first main surface side of a semiconductor substrate made of silicon carbide, a drift layer of a first conductivity type is provided on the first main surface of the semiconductor substrate; The MOSFET region is a well region of a second conductivity type provided in a surface layer of the drift layer on the first main surface side; a first conductivity type source region provided in a surface layer of the well region; a gate insulating film provided in contact with the well region sandwiched between the source region and the drift layer; a gate electrode provided in contact with the gate insulating film; an interlayer insulating film covering the gate electrode; the SBD region includes a Schottky electrode that forms a Schottky junction with the drift layer on the first main surface side of the drift layer, The semiconductor device is a source electrode connected to the Schottky electrode and covering the interlayer insulating film; a drain electrode provided on a second main surface of the semiconductor substrate opposite to the first main surface, The semiconductor device inspection method includes: a first drain current flowing from the drain electrode to the source electrode corresponding to a first gate voltage applied to the gate electrode is measured while a first drain voltage applied between the drain electrode and the source electrode is kept constant; applying the first drain voltage between the drain electrode and the source electrode and measuring a second drain current flowing from the drain electrode to the source electrode corresponding to a second gate voltage applied to the gate electrode; the second gate voltage is different from the first gate voltage; checking whether a difference between the first drain current and the second drain current exceeds a predetermined threshold; A method for inspecting a semiconductor device.

4. 4. The semiconductor device inspection method according to claim 3, a difference between the first gate voltage and the second gate voltage is 1 V or more; A method for inspecting a semiconductor device.

5. A method for manufacturing a semiconductor device including an SBD region and a MOSFET region, forming a drift layer of a first conductivity type on a first main surface of a semiconductor substrate made of silicon carbide; forming a well region of a second conductivity type in a surface layer on the first main surface side of the drift layer, forming a source region of a first conductivity type in a surface layer of the well region, forming a gate insulating film in contact with the well region sandwiched between the source region and the drift layer, forming a gate electrode in contact with the gate insulating film, and forming an interlayer insulating film covering the gate electrode, thereby forming the MOSFET region; forming a Schottky electrode on the first principal surface side of the drift layer to form a Schottky junction with the drift layer, thereby forming the SBD region; forming a source electrode connected to the Schottky electrode and covering the interlayer insulating film; forming a drain electrode on a second main surface of the semiconductor substrate, the second main surface being the main surface opposite to the first main surface; measuring a first gate voltage applied to the gate electrode corresponding to a first drain current flowing from the drain electrode to the source electrode; measuring a second gate voltage applied to the gate electrode corresponding to a second drain current greater than the first drain current; selecting the semiconductor device in which a difference between the first gate voltage and the second gate voltage does not exceed a predetermined threshold value; A method for manufacturing a semiconductor device.

6. 6. A method for manufacturing a semiconductor device according to claim 5, a ratio of the first drain current to the second drain current is 100 times or more; A method for manufacturing a semiconductor device.

7. A method for manufacturing a semiconductor device including an SBD region and a MOSFET region, forming a drift layer of a first conductivity type on a first main surface of a semiconductor substrate made of silicon carbide; forming a well region of a second conductivity type in a surface layer on the first main surface side of the drift layer, forming a source region of a first conductivity type in a surface layer of the well region, forming a gate insulating film in contact with the well region sandwiched between the source region and the drift layer, forming a gate electrode in contact with the gate insulating film, and forming an interlayer insulating film covering the gate electrode, thereby forming the MOSFET region; forming a Schottky electrode on the first principal surface side of the drift layer to form a Schottky junction with the drift layer, thereby forming the SBD region; forming a source electrode connected to the Schottky electrode and covering the interlayer insulating film; forming a drain electrode on a second main surface of the semiconductor substrate, the second main surface being the main surface opposite to the first main surface; a first drain current flowing from the drain electrode to the source electrode corresponding to a first gate voltage applied to the gate electrode is measured while a first drain voltage applied between the drain electrode and the source electrode is kept constant; applying the first drain voltage between the drain electrode and the source electrode and measuring a second drain current flowing from the drain electrode to the source electrode corresponding to a second gate voltage applied to the gate electrode; the second gate voltage is different from the first gate voltage; selecting the semiconductor device in which a difference between the first drain current and the second drain current does not exceed a predetermined threshold value; A method for manufacturing a semiconductor device.

8. 8. The method for manufacturing a semiconductor device according to claim 7, a difference between the first gate voltage and the second gate voltage is 1 V or more; A method for manufacturing a semiconductor device.

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