Semiconductor device and method for manufacturing the same

Abstract

To suppress damage during dicing in the manufacture of semiconductor devices.SOLUTION: It has a semiconductor substrate with an active portion and an edge-terminated structural portion surrounding the active portion, an interlayer insulating film provided above the semiconductor substrate, a protective film provided above the interlayer insulating film, and a protruding portion provided away from the active portion from the edge-terminated structural portion and protruding from the interlayer insulating film, and the protruding portion is not covered by the protective film and the protective film is provided on the active portion side from the protruding portion.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] In a conventional method for manufacturing a semiconductor device, dicing is performed on scribe regions, which are boundary regions between semiconductor devices, to separate the semiconductor devices into chips. Techniques for suppressing yield reductions due to damage during dicing are known (see, for example, Patent Documents 1 and 2). Patent Document 1: Japanese Patent Application Laid-Open No. 2007-67372 Patent Document 2: Japanese Patent Application Laid-Open No. 2007-335483 Summary of the Invention [Problem to be solved by the invention]

[0003] In the manufacture of semiconductor devices, it is preferable to suppress damage during dicing. [Means for solving the problem]

[0004] In order to solve the above problem, one aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate. The semiconductor substrate may be provided with an active portion. The semiconductor substrate may be provided with an edge termination structure surrounding the active portion in a top view. The semiconductor device may include an interlayer insulating film. The interlayer insulating film may be provided above the semiconductor substrate. The semiconductor device may include a protective film. The protective film may be provided above the interlayer insulating film. The semiconductor device may include a protruding portion. The protruding portion may be provided farther from the active portion than the edge termination structure. The protruding portion may protrude beyond the interlayer insulating film. The protruding portion may not be covered by the protective film. The protective film may be provided closer to the active portion than the protruding portion.

[0005] The protrusion may be a single layer film. The protrusion may be a metal film.

[0006] The protrusion may be a stacked film, may include a polysilicon film and a BPSG film, or may include a nitride film.

[0007] The width of the protrusion may be 4.5 μm or more and 6.0 μm or less. The protrusion may be provided at a position lower than the upper end of the protective film in the height direction.

[0008] The semiconductor device may include an alignment mark. The alignment mark may be provided farther from the active portion than the edge termination structure. The alignment mark may be provided farther from the active portion than the protrusion.

[0009] The protruding portion may have a first sidewall on the protective film side and a second sidewall provided farther from the active portion than the first sidewall, and the second sidewall may be steeper than the first sidewall.

[0010] A second aspect of the present invention provides a method for manufacturing a semiconductor device including a semiconductor substrate provided with an active portion and an edge termination structure surrounding the active portion. The method for manufacturing a semiconductor device may include an interlayer insulating film forming step. In the interlayer insulating film forming step, an interlayer insulating film may be formed above the semiconductor substrate. The method for manufacturing a semiconductor device may include a protrusion forming step. In the protrusion forming step, a protrusion may be formed that is located farther from the active portion than the edge termination structure and that protrudes beyond the interlayer insulating film. The method for manufacturing a semiconductor device may include a protective film forming step. In the protective film forming step, a protective film may be formed above the interlayer insulating film. The method for manufacturing a semiconductor device may include a protective film patterning step. In the protective film patterning step, the protective film may be patterned. In the protective film patterning step, the protrusion may not be covered by the protective film. In the protective film patterning step, the protective film may be provided on the active portion side of the protrusion.

[0011] The method for manufacturing a semiconductor device may include a resist formation step, in which a resist to be used in the protective film patterning step may be formed above the protective film, and at least a portion of the resist may be provided farther from the active portion than the protrusion.

[0012] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 2 is a top view showing a comparative example of the semiconductor device 100. [Figure 2] FIG. 1 is a diagram showing a wafer 1000 as viewed from above. [Figure 3] FIG. 10 is a flowchart illustrating a comparative example of a method for manufacturing the semiconductor device 100. [Figure 4] 10A and 10B are diagrams illustrating a comparative example of a method for manufacturing the semiconductor device 100 in the vicinity of the scribe region 140. FIG. [Figure 5] FIG. 2 is a flowchart illustrating an embodiment of a method for manufacturing the semiconductor device 100. [Figure 6] 1A to 1C are diagrams illustrating an embodiment of a method for manufacturing a semiconductor device 100 in the vicinity of a scribe region 140. [Figure 7] 10 is a diagram showing an example of a protrusion 98 as viewed from above. FIG. [Figure 8] 10A and 10B are diagrams illustrating other examples of the protrusion 98. FIG. [Figure 9] 10A and 10B are diagrams illustrating other examples of the protrusion 98. FIG. [Figure 10] 10A and 10B are diagrams illustrating other examples of the protrusion 98. FIG. [Figure 11] 10 is a diagram showing an example of the arrangement of protrusions 98 in the semiconductor device 100. FIG. [Figure 12] 1 is a diagram showing an example of a cross section of the semiconductor device 100 in an active portion 160. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification and drawings, elements having substantially the same function and configuration are designated by the same reference numerals to avoid redundant description, and elements not directly related to the present invention are not shown. Furthermore, in a single drawing, elements having the same function and configuration may be designated by the same reference numeral, and the reference numerals may be omitted for other elements.

[0015] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor module is mounted.

[0016] In this specification, technical matters may be described using orthogonal coordinate axes, i.e., the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. The +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is referred to without specifying positive or negative, it means a direction parallel to the +Z-axis and the -Z-axis. In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0017] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0018] FIG. 1 is a top view showing a comparative example of a semiconductor device 100. In FIG. 1, the positions of each component projected onto the top surface of a semiconductor substrate 10 are shown. In FIG. 1, only some components of the semiconductor device 100 are shown, and some components are omitted. The semiconductor device 100 is a semiconductor chip.

[0019] The semiconductor device 100 is provided on a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon.

[0020] The semiconductor substrate 10 has a first end edge 161 and a second end edge 162 in a top view. In this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two pairs of first end edges 161 that face each other in a top view. The semiconductor substrate 10 of this example also has two pairs of second end edges 162 that face each other in a top view. In FIG. 1, the first end edges 161 are parallel to the X-axis direction. The second end edges 162 are parallel to the Y-axis direction. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0021] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is not shown in FIG.

[0022] In this example, the active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT. In another example, the transistor section 70 and a diode section including a diode element such as an FWD (Free Wheel Diode) may be alternately arranged along a predetermined arrangement direction on the upper surface of the semiconductor substrate 10. The transistor section 70 may be provided with a reverse-blocking IGBT. In this example, two transistor sections 70 (transistor section 70-1 and transistor section 70-2) are provided along the Y-axis direction. A P+ type well region may be provided between each transistor section 70. A gate runner formed of polysilicon or the like may be provided between each transistor section 70.

[0023] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. The transistor section 70 also has a gate structure, which has an N++ type emitter region, a P- type base region, a gate conductive portion, and a gate insulating film, periodically arranged on the upper surface side of the semiconductor substrate 10.

[0024] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near a first edge 161. The vicinity of the first edge 161 refers to the region between the first edge 161 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0025] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring 130 that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring 130 is indicated by diagonal hatching.

[0026] The gate wiring 130 is disposed between the active portion 160 and the first end side 161 or the second end side 162 in a top view. The gate wiring 130 of this example surrounds the active portion 160 in a top view. The area surrounded by the gate wiring 130 in a top view may be the active portion 160. The gate wiring 130 is also connected to a gate pad 164. The gate wiring 130 is disposed above the semiconductor substrate 10. The gate wiring 130 may be a metal wiring containing aluminum or the like.

[0027] The peripheral well region 11 is provided so as to overlap with the gate wiring 130. In other words, like the gate wiring 130, the peripheral well region 11 surrounds the active section 160 in a top view. The peripheral well region 11 is also provided so as to extend with a predetermined width in an area where it does not overlap with the gate wiring 130. The peripheral well region 11 is a region of the second conductivity type. In this example, the peripheral well region 11 is of P+ type. The impurity concentration of the peripheral well region 11 is 5.0×10 17 atoms / cm 3 or more and 5.0 x 10 19 atoms / cm 3 The impurity concentration of the peripheral well region 11 may be 2.0×10 18 atoms / cm 3 or more and 2.0 x 10 19 atoms / cm 3 It may be the following:

[0028] The semiconductor device 100 may also include a temperature sensor (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detector (not shown) that simulates the operation of the transistor section 70 provided in the active section 160. The temperature sensor may be connected to the anode pad and the cathode pad via wiring. When a temperature sensor is provided, it is preferably provided in the center of the semiconductor substrate 10 in the X-axis direction and the Y-axis direction.

[0029] In this example, semiconductor device 100 includes an edge termination structure 90 between active section 160 and first edge 161 or second edge 162 in a top view. Edge termination structure 90 is provided on semiconductor substrate 10. [s1] In this example, edge termination structure 90 is disposed between peripheral gate wiring 130 and first edge 161 or second edge 162. Edge termination structure 90 surrounds active section 160 in a top view. [s2] Edge termination structure 90 relieves electric field concentration on the top surface side of semiconductor substrate 10. Edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf formed in an annular shape surrounding active section 160.

[0030] FIG. 2 is a diagram showing a wafer 1000 as viewed from above. The wafer 1000 has a plurality of semiconductor devices 100. In manufacturing the semiconductor devices 100, the wafer 1000 is diced to separate the semiconductor devices 100 into chips. In this example, the wafer 1000 has a substantially circular shape as viewed from above. The wafer 1000 may be diced by a known dicing method. For example, the wafer 1000 is diced by a dicing saw.

[0031] In the wafer 1000, scribe regions 140 are provided between the semiconductor devices 100. The scribe regions 140 are boundary regions between the semiconductor devices 100. FIG. 2 shows the semiconductor device 100 and the scribe regions 140 schematically. Therefore, the dimensions in FIG. 2 do not match the actual dimensions. When dicing the wafer 1000, the wafer 1000 may be diced based on the scribe regions 140. In other words, the wafer 1000 is diced along the scribe regions 140. Note that after dicing, part of the scribe regions 140 may remain on the semiconductor device 100.

[0032] 3 is a flowchart illustrating a comparative example of a method for manufacturing the semiconductor device 100. The method for manufacturing the semiconductor device 100 includes an interlayer insulating film forming step S101, a metal electrode forming step S102, a protective film forming step S103, a resist forming step S104, a protective film patterning step S105, a resist removing step S106, and a heat treatment step S107. First, the comparative example of the method for manufacturing the semiconductor device 100 will be described.

[0033] 4 is a diagram illustrating a comparative example of a manufacturing method for the semiconductor device 100 in the vicinity of the scribe region 140. Fig. 4 shows a cross section of the scribe region 140 and the semiconductor device 100. In Fig. 4, the boundary between the semiconductor device 100 and the scribe region 140 is indicated by a dotted line.

[0034] In the interlayer insulating film formation step S101, the interlayer insulating film 38 is formed above the semiconductor substrate 10. [s3] In this example, the interlayer insulating film 38 is formed on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. In this example, the interlayer insulating film 38 is a BPSG (Borophosphosilicate Glass) film. The interlayer insulating film 38 may also be provided above the semiconductor substrate 10 in the active section 160.

[0035] In metal electrode formation step S102, metal electrode 94 is formed above interlayer insulating film 38. Metal electrode 94 may be provided in edge termination structure 90. Metal electrode 94 may be a field plate provided in edge termination structure 90. Metal electrode 94 may be connected to a guard ring (not shown). One example of metal electrode 94 is AlSi.

[0036] In the protective film forming step S103, a protective film 150 is formed above the interlayer insulating film 38. [s4] The protective film 150 is, for example, a protective film that becomes a polyimide film by performing a heat treatment step S107. [s5] The protective film 150 may be a polyimide film in the protective film forming step S103. That is, a heat treatment may be performed in the protective film forming step S103. By providing the protective film 150, the semiconductor substrate 10 and the interlayer insulating film 38 can be protected. The protective film 150 may be provided over the entire semiconductor substrate 10 (wafer 1000).

[0037] In the resist formation step S104, a resist 170 is formed above the protective film 150. [s6] The resist 170 may be in contact with the upper surface of the protective film 150. The resist 170 may be patterned. By providing the resist 170, the protective film 150 can be patterned using the resist 170 in the protective film patterning step S105. [s7] The resist 170 is, for example, a photosensitive resist. The protective film 150 is, for example, a non-photosensitive polyimide.

[0038] In the protective film patterning step S105, the protective film 150 is patterned. [s8] The protective film 150 may be patterned by a known etching method. In this example, the protective film 150 is patterned by wet etching. The protective film 150 may be patterned in the same process as the patterning of the resist 170.

[0039] In the resist removal step S106, the resist 170 is removed. The resist 170 may be removed by a chemical solution. The chemical solution used in the resist removal step S106 may be an organic solvent.

[0040] In the heat treatment step S107, the wafer 1000 is heat treated. By performing the heat treatment step S107, a polyimide film is formed. The heat treatment step S107 may be performed by a known method. As an example, the heat treatment step S107 is performed in a thermal annealing furnace.

[0041] 4, the protective film 150 is also formed in the scribe region 140. In this case, dicing along the scribe region 140 may damage the protective film 150, resulting in a decrease in yield or defects. Therefore, it is preferable to design the semiconductor device 100 so that the protective film 150 is not formed in the scribe region 140. However, due to variations in the patterning of the protective film 150 by wet etching, the semiconductor device 100 must be set to a complex layer structure with a design margin, making it difficult to design the semiconductor device 100 so that the protective film 150 is not formed in the scribe region 140.

[0042] 5 is a diagram illustrating a flowchart of an embodiment of a method for manufacturing the semiconductor device 100. The method for manufacturing the semiconductor device 100 includes an interlayer insulating film forming step S201, a protrusion forming step S202, a protective film forming step S203, a resist forming step S204, a protective film patterning step S205, a resist removing step S206, and a heat treatment step S207. [s9] Next, an embodiment of the method for manufacturing the semiconductor device 100 will be described.

[0043] 6 is a diagram illustrating an embodiment of a method for manufacturing the semiconductor device 100 near the scribe region 140. Fig. 6 shows a cross section of the scribe region 140 and the semiconductor device 100. In Fig. 6, the boundary between the semiconductor device 100 and the scribe region 140 is indicated by a dotted line. Interlayer insulating film forming step S201 may be the same as interlayer insulating film forming step S101 in Fig. 4.

[0044] In protrusion formation step S202, protrusion 98 is formed. Protrusion 98 protrudes further than interlayer insulating film 38. Protrusion 98 is provided in semiconductor device 100. Protrusion 98 may be provided further from active section 160 than edge termination structure 90. [s10] In other words, protrusion 98 is provided closer to scribe region 140 than edge termination structure 90. Protrusion 98 may be provided in the peripheral region described below. Protrusion 98 does not have to be provided in scribe region 140. An end of protrusion 98 may be provided closer to active section 160 than the boundary between semiconductor device 100 and scribe region 140. The end of protrusion 98 may be at the boundary between semiconductor device 100 and scribe region 140.

[0045] In this example, the protrusion 98 is a single-layer film. [s11] The protrusion 98 may be a metal film. [s12] As an example, the protrusion 98 is AlSi. In the protrusion formation step S202, a metal electrode 94 may be formed above the interlayer insulating film 38. Since the protrusion 98 is a metal film, it can be formed in the same process as the metal electrode 94.

[0046] The protective film forming step S203, the resist forming step S204, the protective film patterning step S205, the resist removing step S206, and the heat treatment step S207 may be the same as the protective film forming step S103, the resist forming step S104, the protective film patterning step S105, the resist removing step S106, and the heat treatment step S107 in Figure 4, except that a protrusion 98 is formed.

[0047] After the protective film patterning step S205, the protruding portion 98 is not covered with the protective film 150. Furthermore, the protective film 150 is provided closer to the active portion 160 than the protruding portion 98. [s13] In other words, the protective film 150 is not formed in the scribe region 140. In this example, the protruding portion 98, which protrudes further than the interlayer insulating film 38, is provided on the scribe region 140 side of the semiconductor device 100, so that the protective film 150 can be prevented from being formed in the scribe region 140. Therefore, damage during dicing can be suppressed.

[0048] Furthermore, the patterning of the protrusions 98 varies less than the patterning of the protective film 150. Therefore, the positions at which the protrusions 98 are formed are less likely to vary and the protective film 150 is less likely to be formed in the scribe region 140, making it possible to suppress damage during dicing with a simple layer structure.

[0049] The protrusion 98 is provided at a position lower than the upper end of the protective film 150 in the height direction. [s14] In other words, the height H1 of the protrusion 98 (see heat treatment step S207) is smaller than the height H2 of the protective film 150 (see heat treatment step S207). The height H1 of the protrusion 98 may be the maximum height of the protrusion 98. The height H2 of the protective film 150 may be the maximum height of the protective film 150. The height H2 of the protective film 150 may be three times or more the height H1 of the protrusion 98. By providing the protrusion 98 at a position lower than the upper end of the protective film 150 in the height direction, the flatness of the semiconductor device 100 can be ensured. The height H1 of the protrusion 98 is, for example, about 5 μm. [s15]

[0050] Furthermore, the width L3 of the protrusion 98 (see heat treatment step S207) may be 4.5 μm or more. [s16] The width L3 of the protrusion 98 may be the width in the direction from the semiconductor device 100 toward the scribe region 140 (the X-axis direction in FIG. 6). The width L3 of the protrusion 98 may be 6.0 μm or less. The width of the scribe region 140 in the X-axis direction is defined as L1 (see interlayer insulating film formation step S201), and the opening width of the resist 170 in the X-axis direction is defined as L2 (see resist formation step S204). The width L3 of the protrusion 98 may be smaller than the width L1 of the scribe region 140. The width L3 of the protrusion 98 may be one-tenth or less of the width L1 of the scribe region 140. The width L1 of the scribe region 140 may be 70 μm or more and 90 μm or less. The width L3 of the protrusion 98 may be smaller than the opening width L2 of the resist 170. The width L3 of the protrusion 98 may be one tenth or less of the opening width L2 of the resist 170.

[0051] Furthermore, in resist formation step S204, at least a portion of resist 170 is provided farther from active portion 160 than protrusion 98. [s17] That is, at least a portion of resist 170 is provided closer to scribe region 140 than protrusion 98. By providing resist 170 closer to scribe region 140 than protrusion 98, protective film 150 can be provided above metal electrode 94 of edge termination structure 90.

[0052] The protrusion 98 has a first sidewall 112 and a second sidewall 114. The first sidewall 112 is provided on the protective film 150 side. [s18] In FIG. 6, the first sidewall 112 is in contact with the protective film 150. The first sidewall 112 may be provided closer to the active section 160 than the second sidewall 114. The second sidewall 114 is provided farther from the active section 160 than the first sidewall 112. [s19] The second sidewall 114 is provided farther from the protective film 150 than the first sidewall 112. The second sidewall 114 is not in contact with the protective film 150. The second sidewall 114 is provided closer to the scribe region 140 than the first sidewall 112.

[0053] 7 is a diagram showing an example of the protrusion 98 in a top view. The protrusion 98 may extend in the direction in which the scribe region 140 extends in a top view. In FIG. 7, the protrusion 98 extends in the Y-axis direction. The protrusion 98 has a longitudinal direction in the Y-axis direction. The protrusion 98 may be provided along the scribe region 140. The protrusion 98 has a width L3 in the X-axis direction.

[0054] Furthermore, alignment marks 120 are provided in the scribe region 140. That is, the alignment marks 120 are provided farther from the active section 160 than the edge termination structure section 90. [s20] The alignment marks 120 are marks that serve as a reference for alignment in photolithography and the like. That is, position adjustments may be performed using the alignment marks 120. The alignment marks 120 may be formed by etching the interlayer insulating film 38. The alignment marks 120 may be formed by providing a polysilicon film or the like above the interlayer insulating film 38.

[0055] In this example, the alignment mark 120 is provided farther from the active portion 160 (semiconductor device 100 in the figure) than the protruding portion 98. [s21] In other words, the alignment mark 120 is provided closer to the scribe region 140 than the protruding portion 98. By providing the protruding portion 98, it is possible to prevent the protective film 150 from being formed above the alignment mark 120.

[0056] Note that a portion of the alignment mark 120 is provided in the scribe region 140, and therefore may remain in the semiconductor device 100 after dicing. In other words, a portion of the alignment mark 120 may be provided in the semiconductor device 100. By controlling the dicing range, the alignment mark 120 can be left in the semiconductor device 100. The alignment mark 120 does not have to remain in the semiconductor device 100 after dicing.

[0057] 8 is a diagram illustrating another example of the protrusion 98. FIG. 8 shows a cross section of the scribe region 140 and the semiconductor device 100. In FIG. 8, the boundary between the semiconductor device 100 and the scribe region 140 is indicated by a dotted line. In this example, the configuration of the protrusion 98 differs from that in the heat treatment step S207 in FIG. 6. Other configurations in FIG. 8 may be the same as those in the heat treatment step S207 in FIG. 6.

[0058] In this example, the protruding portion 98 is a laminated film. [s22] In FIG. 8, the protruding portion 98 includes an interlayer insulating film 38 (BPSG film) and polysilicon 46. [s23] By forming the polysilicon 46 in the scribe region 140, the interlayer insulating film 38 on the polysilicon 46 can be made to protrude. The polysilicon 46 may be made of the same material as the gate runner. Therefore, the polysilicon 46 can be disposed in the same process as the formation of the gate runner.

[0059] 9 is a diagram illustrating another example of the protrusion 98. FIG. 9 shows a cross section of the scribe region 140 and the semiconductor device 100. In FIG. 9, the boundary between the semiconductor device 100 and the scribe region 140 is indicated by a dotted line. In this example, the configuration of the protrusion 98 differs from that in the heat treatment step S207 in FIG. 6. Other configurations in FIG. 9 may be the same as those in the heat treatment step S207 in FIG. 6.

[0060] In this example, the protruding portion 98 is a laminated film. [s24] In FIG. 9, the protruding portion 98 includes an interlayer insulating film 38 (BPSG film), polysilicon 46, and a nitride film 47. [s25] The nitride film 47 may be provided above the interlayer insulating film 38. By providing the nitride film 47 above the interlayer insulating film 38, the surface of the protruding portion 98 can be protected. Furthermore, by providing the nitride film 47 above the interlayer insulating film 38, the height of the protruding portion 98 can be increased. The nitride film 47 may be formed in the same process as the process for forming other nitride films.

[0061] FIG. 10 is a diagram illustrating another example of the protrusion 98. FIG. 10 shows a cross section of the scribe region 140 and the semiconductor device 100. In FIG. 10, the boundary between the semiconductor device 100 and the scribe region 140 is indicated by a dotted line. In this example, the configuration of the protrusion 98 differs from that in the heat treatment step S207 in FIG. 6. Other configurations in FIG. 10 may be the same as those in the heat treatment step S207 in FIG. 6. In FIG. 10, the protrusion 98 is a single-layer film (metal film) similar to that in FIG. 6.

[0062] In this example, the second side wall 114 is steeper than the first side wall 112. [s26] In other words, the slope of the second side wall 114 is greater than the slope of the first side wall 112. The slope of the second side wall 114 is approximately vertical. By making the second side wall 114 steeper than the first side wall 112, the width of the protrusion 98 can be narrowed. By making the slope of the first side wall 112 smaller than the slope of the second side wall 114, voids can be reduced when the protective film 150 is formed.

[0063] Fig. 11 is a diagram showing an example of the arrangement of the protrusions 98 in the semiconductor device 100. Fig. 11 is a top view showing an embodiment of the semiconductor device 100. In Fig. 11, the protrusions 98 are indicated by thick lines.

[0064] In a top view, semiconductor device 100 of this example includes periphery region 122 between edge termination structure 90 and first edge 161 or second edge 162. Periphery region 122 surrounds edge termination structure 90. In FIG. 11 , protrusion 98 is provided in periphery region 122. Protrusion 98 may also be provided in edge termination structure 90. The boundary between periphery region 122 and edge termination structure 90 is, for example, the end of the field plate or guard ring that is provided closest to first edge 161 or second edge 162.

[0065] 11, protrusion 98 is provided between edge termination structure 90 and first end edge 161 or second end edge 162. In other words, protrusion 98 is provided so as to surround edge termination structure 90. In the example of FIG. 11, protrusion 98 is provided continuously along first end edge 161 and second end edge 162, but some protrusions may not be provided. For example, protrusion 98 may not be provided near the corner connecting first end edge 161 and second end edge 162.

[0066] 12 is a diagram showing an example of a cross section of the semiconductor device 100 in the active portion 160. This cross section is an XZ plane passing through the emitter region 13 and the cathode region 82. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. In this example, a transistor section 70 and a diode section 80 are arranged on the semiconductor substrate 10.

[0067] The transistor section 70 has a P+ type collector region 22 in a region in contact with the lower surface of the semiconductor substrate 10. The transistor section 70 also has, on the upper surface side of the semiconductor substrate 10, a gate structure periodically arranged with an N++ type emitter region 13, a P- type base region 14, a P++ type contact region 15, a gate conductive portion, and a gate insulating film.

[0068] The diode section 80 has an N+ type cathode region 82 in a region that contacts the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region 22 may be provided on the lower surface of the semiconductor substrate 10 in a region other than the cathode region.

[0069] 12, the interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 has a contact hole 54 formed therein.

[0070] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 passes through a contact hole 54 in the interlayer insulating film 38 and is in contact with the upper surface 21 of the semiconductor substrate 10. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a metal material such as aluminum.

[0071] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction (the X-axis direction in this example). In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are periodically provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0072] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region inside the semiconductor substrate 10 that is sandwiched between the trench portions. As an example, the upper end of the mesa portion is the upper surface 21 of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench. In this example, the transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. In this specification, the mesa portion simply referred to as a mesa portion refers to both the mesa portion 60 and the mesa portion 61.

[0073] Each mesa portion is provided with a base region 14. The mesa portion 60 of the transistor portion 70 has an emitter region 13 exposed on the upper surface 21 of the semiconductor substrate 10. The emitter region 13 is provided in contact with the gate trench portion 40. Furthermore, the mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface 21 of the semiconductor substrate 10.

[0074] As an example, the contact region and emitter region 13 of the mesa portion 60 are provided in a stripe shape along the extension direction (Y-axis direction) of the trench portion. That is, the emitter region 13 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 13.

[0075] In another example, the contact regions 15 and the emitter regions 13 in the mesa portion 60 are each provided from one trench portion to the other trench portion in the X-axis direction. In this case, the contact regions 15 and the emitter regions 13 in the mesa portion 60 may be alternately arranged along the extension direction of the trench portions (the Y-axis direction).

[0076] The mesa portion 61 of the diode section 80 is not provided with the emitter region 13. The mesa portion 61 may have a base region 14 and a contact region 15 provided on its upper surface.

[0077] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60. The accumulation region 16 may also be provided only in the transistor portion 70.

[0078] In each of the transistor section 70 and the diode section 80, an N+ type buffer region 20 is provided on the lower surface 23 side of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0079] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0080] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as the donor and acceptor of each region are not limited to the examples described above.

[0081] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the top surface 21 of the semiconductor substrate 10. Each trench extends from the top surface 21 of the semiconductor substrate 10, penetrating the base region 14, and reaching the drift region 18. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed after the doped regions are formed. The trenches penetrating the doped regions also include trenches formed after the trenches are formed.

[0082] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and on the inner side of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0083] The gate conductive portion 44 may be provided to be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to a gate runner. The gate conductive portion 44 may be connected to a gate pad 164. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0084] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 may be connected to an electrode different from the gate pad 164. For example, the dummy conductive portion 34 may be connected to a dummy pad (not shown) that is connected to an external circuit different from the gate pad 164, and controlled differently from the gate conductive portion 44. The dummy conductive portion 34 may also be electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided more inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is made of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0085] The gate trench portion 40 and the dummy trench portion 30 in this example are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved and convex downward (curved in cross section).

[0086] The lifetime control portion 74 is a region in which a lifetime killer is intentionally formed by injecting impurities into the semiconductor substrate. The lifetime killer is a carrier recombination center, and may be a crystal defect, a vacancy, a divacancy, a complex defect of these with elements constituting the semiconductor substrate 10, a dislocation, a rare gas element such as helium or neon, or a metal element such as platinum. The lifetime control portion 74 can be formed by injecting helium or the like into the semiconductor substrate 10.

[0087] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. [Explanation of symbols]

[0088] 10 semiconductor substrate, 11 peripheral well region, 13 emitter region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 30 dummy trench portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 40 gate trench portion, 42 gate insulating film, 44 gate conductive portion, 46 polysilicon, 47 nitride film, 52 emitter electrode, 54 contact hole , 60··Mesa portion, 61··Mesa portion, 70··Transistor portion, 74··Lifetime control portion, 80··Diode portion, 82··Cathode region, 90··Edge termination structure portion, 94··Metal electrode, 98··Protrusion portion, 100··Semiconductor device, 112··First sidewall, 114··Second sidewall, 120··Alignment mark, 122··Periphery region, 130··Gate wiring, 140··Scribe region, 150··Protective film, 160··Active portion, 161··First edge, 162··Second edge, 164··Gate pad, 170··Resist, 1000··Wafer

Claims

1. a semiconductor substrate provided with an active portion and an edge termination structure surrounding the active portion in a top view; an interlayer insulating film provided above the semiconductor substrate; a protective film provided above the interlayer insulating film; a protruding portion that is provided farther from the active portion than the edge termination structure portion and protrudes above the interlayer insulating film that is provided in the edge termination structure portion; Equipped with At least a portion of the protrusion is not covered by the protective film, the protective film is provided on the active portion side of the protruding portion, an end position of the protrusion in the top view is the same as an end position of the semiconductor substrate; the edge termination structure has a field plate provided on the interlayer insulating film, The protruding portion protrudes beyond the interlayer insulating film covered by the field plate. Semiconductor device.

2. a semiconductor substrate provided with an active portion and an edge termination structure surrounding the active portion in a top view; an interlayer insulating film provided above the semiconductor substrate; a protective film provided above the interlayer insulating film; a protruding portion that is provided farther from the active portion than the edge termination structure portion and protrudes above the interlayer insulating film that is provided in the edge termination structure portion; Equipped with At least a portion of the protrusion is not covered by the protective film, the protective film is provided on the active portion side of the protruding portion, The uppermost surface of the protruding portion is the interlayer insulating film protruding upward. Semiconductor device.

3. a semiconductor substrate provided with an active portion and an edge termination structure surrounding the active portion in a top view; an interlayer insulating film provided above the semiconductor substrate; a protective film provided above the interlayer insulating film; a protruding portion that is provided farther from the active portion than the edge termination structure portion and protrudes above the interlayer insulating film that is provided in the edge termination structure portion; Equipped with At least a portion of the protrusion is not covered by the protective film, the protective film is provided on the active portion side of the protruding portion, The top surface of the protrusion is a nitride film. Semiconductor device.

4. a semiconductor substrate provided with an active portion and an edge termination structure surrounding the active portion in a top view; an interlayer insulating film provided above the semiconductor substrate; a protective film provided above the interlayer insulating film; a protruding portion that is provided farther from the active portion than the edge termination structure portion and protrudes above the interlayer insulating film that is provided in the edge termination structure portion; Equipped with At least a portion of the protrusion is not covered by the protective film, the protective film is provided on the active portion side of the protruding portion, The protruding portion includes a polysilicon film and a BPSG film. Semiconductor device.

5. The protrusion is a single layer film. The semiconductor device according to claim 1 .

6. The protrusion is a metal film. The semiconductor device according to claim 5 .

7. The protrusion is a laminated film. The semiconductor device according to claim 1 .

8. The protrusion further includes a nitride film. The semiconductor device according to claim 4 .

9. The width of the protrusion is 4.5 μm or more and 6.0 μm or less. The semiconductor device according to claim 1 .

10. The protrusion is provided at a position lower than the upper end of the protective film in the height direction. The semiconductor device according to claim 1 .

11. An alignment mark is provided at a distance from the active portion relative to the edge termination structure. Further preparation, The alignment mark is provided farther from the active portion than the protruding portion. The semiconductor device according to claim 2 .

12. a semiconductor substrate provided with an active portion and an edge termination structure surrounding the active portion in a top view; an interlayer insulating film provided above the semiconductor substrate; a protective film provided above the interlayer insulating film; a protruding portion that is provided farther from the active portion than the edge termination structure portion and protrudes above the interlayer insulating film that is provided in the edge termination structure portion; Equipped with At least a portion of the protrusion is not covered by the protective film, the protective film is provided on the active portion side of the protruding portion, The protrusion is a first sidewall on the protective film side; a second sidewall provided farther from the active portion than the first sidewall; and The second sidewall is steeper than the first sidewall. Semiconductor device.

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