Analog signal monitoring for functional safety

Abstract

A method of operating a memory device includes supplying one or more power supply voltages to a memory array and monitoring the one or more power supply voltages, the monitoring including selecting a selected power supply voltage from the one or more power supply voltages, converting an internal reference voltage of the memory device and a scaled version of the selected power supply voltage to one or more digital values ​​using an analog-to-digital converter (ADC), generating a calibrated measurement result using the one or more digital values, and determining whether the calibrated measurement result is within a predetermined range.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Patent Application No. 17 / 862,917, filed July 12, 2022, which application claims the benefit of U.S. Provisional Application No. 63 / 311,693, filed February 18, 2022, which application is incorporated herein by reference.

[0002] The present disclosure relates generally to electronic systems and methods, and in particular embodiments to circuits and methods for analog signal monitoring for functional safety. [Background technology]

[0003] Memory devices, such as random access memory (RAM), read-only memory (ROM), and flash memory, are widely used in electronic devices for storing application data and / or user data. To use a memory device, the electronic device can perform various memory access operations, such as read, write, and erase, on a memory array of the memory device.

[0004] Generally, in a memory device, one or more analog voltages and / or analog currents are provided or generated to drive circuits for performing various memory access operations. The signal level (e.g., voltage value or current value) of the analog signal is critical to the proper functioning of the memory device. For example, to program (e.g., write or erase) a memory array, a programming voltage at a nominal value or within a specified range from the nominal value is used to program the memory array. If the programming voltage deviates from the nominal value by more than an acceptable range (e.g., a predetermined range), the memory array may not be properly programmed. Similarly, during a read operation on the memory array, an electrical characteristic (e.g., current value or voltage value) indicative of the stored digital value is measured and compared to a threshold value to determine the digital value stored in the memory array. If the ready voltage for performing the read operation is outside the acceptable range, the digital value stored in the memory array may not be read correctly.

[0005] If analog signals (e.g., analog voltages and / or analog currents) used in performing memory access operations are not monitored and go out of range, the memory device may complete the memory access operation and report successful completion of the memory access operation without knowing that the analog signals are out of range. When analog signals used in memory access operations are out of range, a large number of data errors may occur. If the amount of data errors exceeds the error correction / error detection capabilities of the error correction code (ECC) used in the memory device, the uncorrected / undetected data errors may cause performance degradation at the system level. There is a need in the art for memory devices with built-in analog signal monitoring capabilities for improved system performance and efficient error mitigation / prevention capabilities. Summary of the Invention [Means for solving the problem]

[0006] According to one embodiment, a memory device includes a memory array including memory cells, and a power management circuit for the memory array, the power management circuit including: a voltage source configured to provide one or more power supply voltages to the memory array; an internal voltage reference configured to provide an internal reference voltage; a multiplexer configured to receive the one or more power supply voltages and to output a selected power supply voltage selected from the one or more power supply voltages; an analog-to-digital converter (ADC) configured to convert scaled versions of the internal reference voltage and the selected power supply voltage into one or more digital values; and a digital comparator. The digital comparator is configured to generate a calibrated measurement result using the one or more digital values, a first stored digital value of the internal reference voltage and a second stored digital value of the external reference voltage, compare the calibrated measurement result with a predetermined range, and set an error flag indicating a fault condition of the memory device in response to detecting that the calibrated measurement result is outside the predetermined range.

[0007] According to one embodiment, an integrated circuit (IC) device includes a memory array including memory cells, a controller coupled to the memory array, and a power management circuit coupled to the memory array and the controller, the power management circuit including: a voltage supply circuit configured to provide a power supply voltage to the memory array; a multiplexer coupled to the voltage supply circuit and configured to output a selected power supply voltage selected from the power supply voltage; an internal voltage reference configured to provide an internal reference voltage; an analog-to-digital converter (ADC) configured to convert scaled versions of the internal reference voltage and the selected power supply voltage into an ADC output; and a digital comparator configured to generate a calibrated measurement result using the ADC output, a first pre-stored digital value of the internal reference voltage, and a second pre-stored digital value of the external reference voltage, determine whether the calibrated measurement result is within a predetermined range, and set an error flag indicating a fault condition of the IC device in response to determining that the calibrated measurement result is outside the predetermined range.

[0008] According to one embodiment, a method of operating a memory device includes supplying one or more power supply voltages to a memory array and monitoring the one or more power supply voltages, the monitoring including selecting a selected power supply voltage from the one or more power supply voltages, converting an internal reference voltage of the memory device and a scaled version of the selected power supply voltage(s) using an analog-to-digital converter (ADC) to one or more digital values, generating a calibrated measurement result using the one or more digital values, and determining whether the calibrated measurement result is within a predetermined range.

[0009] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 illustrates a memory device incorporating analog signal monitoring functionality in one embodiment. [Figure 2] FIG. 2 is a block diagram of an analog signal monitoring circuit in one embodiment. [Figure 3] FIG. 3 is a timing diagram of the analog signal monitoring circuit of FIG. 2 in one embodiment. [Figure 4] 1 is a flowchart of a method for monitoring an analog signal, in one embodiment. [Figure 5] 1 is a flowchart of a method for operating a memory device, according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Making and using examples of the present disclosure are described in detail below. However, it should be appreciated that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The illustrated examples are merely illustrative of specific ways to make and use the invention and do not limit the scope of the invention. Throughout this description, unless otherwise specified, the same or similar reference numbers in different figures refer to the same or similar components.

[0012] While the present disclosure is described with reference to an example in a particular context, namely, analog signal monitoring in a memory device, those skilled in the art will readily appreciate that the principles disclosed herein may be applied to analog signal monitoring for other types of systems or applications.

[0013] 1 illustrates a memory device 100 incorporating analog signal monitoring functionality in one embodiment. As shown in FIG. 1, memory device 100 includes a memory array 101 and a memory control circuit 110. Memory control circuit 110 further includes, among other circuits, a power management circuit 120, a controller 103, a system clock circuit 115, and an input / output (I / O) driver circuit 111. Details are described below.

[0014] The memory array 101 includes multiple memory cells (e.g., multi-bit, multi-level memory cells) for storing digital values ​​(e.g., 0s and 1s) or analog values. The memory array 101 may comprise any suitable type of memory cell, such as one-transistor, one-capacitor (1T1C) memory cells, split-gate (1.5T) memory cells, two-transistor memory cells, etc. Each of the memory cells of the memory array 101 can store one or more bits of digital data. The memory cells may be organized into rows and columns and may be individually addressable by address lines (e.g., bit lines, word lines) of the memory array 101. Addressing of the memory cells and data transfer (e.g., read / write) between the memory cells may be controlled by the controller 103, for example, via control signal / data paths 114 between the controller 103 and the memory array 101. Memory arrays are known in the art, so details will not be repeated here.

[0015] The controller 103 may be a microcontroller, a processor, a digital logic circuit, an application-specific integrated circuit (ASIC), etc. FIG. 1 shows a ROM module 107 and a static random access memory (SRAM) module 109 coupled to the controller 103. The ROM module 107 and the SRAM module 109 are used to store programs (e.g., computer code) executed by the controller 103 and / or program or user data used by the controller 103. The controller 103 may have multiple registers 105 or other types of memory components that may be used to store target values ​​(e.g., target nominal values ​​or ranges around nominal values) of analog signals (e.g., voltages or currents) used in memory access operations, or to store pass / fail results for analog signal monitoring. A system clock circuit 115 generates one or more system clocks used to drive the controller 103 and the power management circuit 120.

[0016] 1 further shows an I / O driver circuit 111 coupled between the controller 103 and an I / O pad 113 of the memory device 100. The I / O driver circuit 111 may be used to improve the drive capability of the controller 103 and / or to convert signal levels (e.g., voltage levels) between an I / O voltage of the controller 103 and an I / O voltage applied to the I / O pad 113. The I / O pad 113 enables communication between the controller 103 and an external device (e.g., another processor or another device). In some embodiments, a target value for an analog signal (e.g., voltage or current) used for memory access operations is received by the controller 103 via the I / O pad 113. In some embodiments, a pass / fail result for the analog signal monitoring is output at the I / O pad 113.

[0017] 1 , memory device 100 includes a power management circuit 120 coupled to controller 103, for example, via control signal / data paths 116 and 118. In some embodiments, power management circuit 120 includes circuitry for generating one or more power supply voltages (or power supply currents) used in memory access operations. In addition, power management circuit 120 includes circuitry for monitoring the power supply voltages (or power supply currents). In the description herein, monitoring a power supply voltage (or power supply current) may be referred to as analog signal monitoring. While the description herein uses an example in which the analog signal being monitored is a power supply voltage, it will be understood that the principles disclosed therein can be readily applied to monitoring any power supply current, for example, by monitoring the voltage drop across a fixed (e.g., known) resistor through which the power supply current flows.

[0018] 1, power management circuit 120 includes a voltage supply circuit 121 that generates one or more power supply voltages (e.g., having different voltage values ​​such as +1V, +1.5V, +3V, etc.) used, for example, for memory access operations or for operation of other circuits in memory device 100. Voltage supply circuit 121 may include, for example, a DC-DC power converter, a low-drop power regulator, etc. In some embodiments, the DC-DC power converter of voltage supply circuit 121 converts an analog voltage VDD1 into one or more different DC voltages for use in memory access operations. Analog voltage VDD1, in an exemplary embodiment, is an external input voltage signal to memory device 100. FIG. 1 further shows a charge pump 123 coupled to memory array 101 and / or voltage supply circuit 121. In some embodiments, using an analog voltage VDD1 (e.g., an external voltage signal of +3 V), charge pump 123 generates one or more high voltages (e.g., +10 V), and voltage supply circuit 121 generates one or more low voltages (e.g., +1 V, +1.5 V, +3 V) for use by memory device 100. In the description herein, unless otherwise specified, the voltages provided by charge pump 123 are not distinguished from the power supply voltages provided by voltage supply circuit 121, and all voltages supplied to memory array 101 are collectively referred to as one or more power supply voltages for memory array 101 (or for memory access operations). Note that in embodiments in which power supply currents are used to drive memory array 101 for memory access operations, voltage supply circuit 121 may be replaced by a current supply circuit that generates one or more power supply currents. Thus, voltage supply circuit 121 may also be collectively referred to as a power supply circuit.

[0019] The voltage used for memory access operations is sent to analog signal monitoring circuit 130 of power management circuit 120. As shown in FIG. 1 , analog signal monitoring circuit 130 includes MUX & voltage divider circuit 131, internal voltage reference 135, and analog functional safety circuit 133. Internal voltage reference 135 is a circuit that provides an internal reference voltage (e.g., a fixed, known voltage). In one embodiment, internal voltage reference 135 is a bandgap voltage reference that provides a reference voltage of, for example, 1.25 V. In some embodiments, MUX & voltage divider circuit 131 includes a multiplexer (MUX) 132 (see FIG. 2 ) that selects (e.g., selects) a selected power supply voltage for monitoring from one or more power supply voltages. MUX & voltage divider circuit 131 further includes scaling circuit 134 (see FIG. 2 ) that scales the selected power supply voltage by a scaling factor so that the voltage at the output of the scaling circuit is within the measurement range of a subsequent analog-to-digital converter (ADC). The analog functional safety circuit 133 includes an ADC 137 (see FIG. 2) and a digital comparator 139 (see FIG. 2). Details of the analog signal monitoring circuit 130 are described below with reference to FIG.

[0020] In some embodiments, control signal / data path 118 is used to transfer control signals and data between controller 103 and voltage supply circuit 121. For example, depending on the type / structure of memory array 101, controller 103 may use control signal / data path 118 to control the voltage levels and dynamic behavior (e.g., timing sequence) of the power supply voltages generated by voltage supply circuit 121. In some embodiments, control signal / data path 116 is used to transfer control signals and data between controller 103 and analog signal monitoring circuit 130. Various control signals and data transferred between controller 103 and analog signal monitoring circuit 130 are described below.

[0021] 2 illustrates a block diagram of the analog signal monitoring circuit 130 of FIG. 1 in one embodiment. In the example of FIG. 2, the analog signal monitoring circuit 130 includes an internal voltage reference 135, a MUX 132 (e.g., an analog MUX), a scaling circuit 134 (sometimes called a voltage divider), an ADC 137, and a digital comparator 139. An enable signal (labeled "fusa_en" in FIG. 2) serves as an enable signal for the analog signal monitoring circuit 130. The MUX 132 selects one or more power supply voltages (e.g., analog_in <1> ,...,analog_in <n>, and N analog signals). In the example of FIG. 2, MUX 132 further accepts an external reference signal (labeled “External Reference” in FIG. 2) as an input signal. The external reference signal may be used to generate a pre-stored digital value of an external reference voltage during factory testing, as described in more detail below. MUX 132 may also accept other analog signals of memory device 100 for monitoring. MUX 132 is controlled by a control signal (labeled “Input Selector” in FIG. 2) to select which analog signal is sent to the output of MUX 132 as the selected analog signal (e.g., the selected power supply voltage). The control signal for MUX 132 may be generated by controller 103 and sent to analog signal monitoring circuit 130 via control signal / data path 116, as shown in FIG. 1.

[0022] The output of MUX 132 is sent to the input terminal of scaling circuit 134, which scales (e.g., divides or multiplies) the output of MUX 132 by a scaling factor. The scaling factor of scaling circuit 134 is selected by a control signal (labeled “Division Coefficient” in FIG. 2 ), which may be generated by controller 103 and sent to analog signal monitoring circuit 130 via control signal / data path 116. Because the input analog signal to MUX 132 may cover a wide range of signal levels (e.g., voltage or current values), an appropriate scaling factor is selected by controller 103 according to the signal level of the selected analog signal at the output of MUX 132, such that the signal level of the selected analog signal at the output of scaling circuit 134 is within the input range of ADC 137. In some embodiments, the scaling factor is selected so that the scaled selected analog signal at the output of the scaling circuit 134 is at an optimal or near-optimal level for the ADC 137, e.g., about 80% of the maximum input signal level of the ADC 137, maximizing the signal-to-noise ratio (SNR) of the ADC output while leaving some headroom to avoid saturation of the ADC output.

[0023] In FIG. 2 , ADC 137 accepts the output of internal voltage reference 135 as a first measurement input (labeled “refer_in” in FIG. 2 ) and the scaled selected analog signal from scaling circuit 134 as a second measurement input (labeled “meas_in” in FIG. 2 ). In some embodiments, a multiplexer (not shown) may be included in ADC 137 to, for example, select the first measurement input and then the second measurement input as inputs to ADC 137, such that the first and second measurement inputs are sequentially converted to digital values ​​by ADC 137. In some embodiments, the first and second measurement inputs are used as a pair of differential input signals to ADC 137, and the pair of differential signals is converted to digital values ​​by ADC 137. In some embodiments, ADC 137 may include two parallel ADC circuits, each coupled to the first and second measurement inputs, such that the first and second measurement inputs are converted to digital values ​​in parallel. These and other variations are possible and are fully intended to be within the scope of the present disclosure. As a non-limiting example, the following description uses an example in which each of the first and second measurement inputs is converted to a respective digital value, it being understood that the principles disclosed herein may be modified for other variations.

[0024] To monitor a selected analog signal, ADC 137 converts a first measurement input to a first digital value (also referred to as a first ADC output) and a second measurement input to a second digital value (also referred to as a second ADC output). The first and second digital values ​​from ADC 137 are, for example, 16-bit binary digital words for a 16-bit ADC. The first and second digital values ​​are sent to digital comparator 139 for processing. FIG. 2 shows a clock signal (labeled “clk” in FIG. 2) for driving ADC 137 and a control signal (labeled “start” in FIG. 2) for starting (e.g., enabling) ADC 137. The clock signal may be generated by system clock circuit 115 and sent to analog signal monitoring circuit 130, and the control signal for ADC 137 may be generated by controller 103 and sent to analog signal monitoring circuit 130 via control signal / data path 116.

[0025] The output of ADC 137 (e.g., the first digital value and the second digital value) is sent to digital comparator 139 via a data path (labeled "Data" in FIG. 2) between the output of ADC 137 and the input of digital comparator 139. FIG. 2 further shows an enable signal (labeled "Compare Enable" in FIG. 2) generated by ADC 137 and sent to digital comparator 139 to enable a comparison of the measurement result generated by digital comparator 139 with a target value.

[0026] Digital comparator 139 includes data processing circuitry 141 that generates a calibrated measurement result using the output (e.g., the first digital value and the second digital value) of ADC 137, a first pre-stored digital value of the internal reference voltage, and a second pre-stored digital value of the external reference voltage. The first pre-stored digital value and the second pre-stored digital value may be stored in registers of digital comparator 139 during factory testing of memory device 100. Details for generating the calibrated measurement result are described below with reference to FIG. 4.

[0027] The calibrated measurement corresponds to a metric that indicates the value (e.g., voltage value) of the selected analog signal. As a non-limiting example, the calibrated measurement may correspond to (e.g., be proportional to) the difference between the value of the selected analog signal and the value of the internal reference voltage, or may correspond to the ratio between the value of the selected analog signal and the value of the internal reference voltage.

[0028] Digital comparator 139 compares the calibrated measurement result with a target value (labeled "Target" in FIG. 2 ), and the comparison result is used to set an error flag indicating a "pass" or "fail" of the monitored analog signal, where "pass" means that the monitored analog signal is at the target value (or within a predetermined range from the target value), and "fail" means that the monitored analog signal is not at the target value (or not within a predetermined range from the target value). The target value (which may be a predetermined value or a range around the predetermined value) may be sent from controller 103 to analog signal monitoring circuit 130 via control signal / data path 116. Note that in some embodiments, the target value takes into account the scaling factor of scaling circuit 134. The output of digital comparator 139 (e.g., a pass / fail result) may, in some embodiments, be sent back to controller 103 via control signal / data path 116 and stored in register 105 of controller 103.

[0029] In some embodiments, after a first analog signal is selected and monitored (e.g., converted by ADC 137 and processed by digital comparator 139 to find a "pass / fail" result), controller 103 selects a second analog signal as the output of MUX 132 to monitor the second analog signal. In some embodiments, the process is repeated until all, or at least all, of the analog signal selections at the inputs of MUX 132 have been monitored.

[0030] 3 illustrates a timing diagram of the analog signal monitoring circuit 130 of FIG. 2 in one embodiment. As shown in FIG. 3, at time t1, the control signal fusa_en (corresponding to the control signal "fusa_en" of FIG. 2) rises from low to high, enabling the analog signal monitoring circuit 130. After the control signal fusa_en rises high, a period of time (e.g., a predetermined duration), at time t2, the control signal fusa_start (corresponding to the control signal "start" of FIG. 2) rises from low to high, thus enabling the ADC 137. The ADC 137 begins outputting digital samples after time t2. The ADC output is the M-bit data signal fusa_data of FIG. 3, which corresponds to the data signal "data" of FIG. 2. <m-1:0>Depending on the type / architecture of the ADC 137, after a certain period of time (e.g., a predetermined duration), at time t3, the control signal fusa_data_ready (corresponding to the control signal "compare enable" in FIG. 2) rises from low to high, and the ADC output signal fusa_data <m-1:0>is valid and ready to be used for comparison, and digital comparator 139 begins processing the ADC output signal. At time t4, the output signal PASS / FAIL of digital comparator 139 (corresponding to the "RESULT" signal in FIG. 2) is ready. Next, at time t5, the control signal fusa_start falls from high to low, signaling the end of monitoring the currently selected analog signal. The falling edge of control signal fusa_start causes control signal fusa_en to fall from high to low, and the ADC output signal fusa_data <m-1:0>and the output signal fusa_data_ready is reset. The analog signal monitoring circuit 130 is now ready to process the next selected analog signal.

[0031] 1 is implemented as an integrated circuit (IC) formed on a semiconductor substrate (e.g., silicon) using semiconductor fabrication techniques. An IC device may also be referred to as a semiconductor die or semiconductor chip. In some embodiments, portions of memory device 100, such as memory array 101 and power management circuitry 120, are integrated into the IC device, while controller 103 is not, thereby allowing user selection of a different controller 103 within semiconductor device 100. Different levels of integration for IC devices are possible and are fully intended to be within the scope of this disclosure.

[0032] 4 shows a flowchart of a method 1000 for monitoring an analog signal, according to one embodiment. At block 1010, voltage monitoring begins. At block 1020, during factory testing of memory device 100, an internal reference voltage provided by internal voltage reference 135 is measured and converted to a digital value A, e.g., by ADC 137. sort and the external reference voltage is also measured and converted to a digital value K sort In block 1030, the measurement result (e.g., digital value A sort and K. sort ) is a pre-stored digital value (e.g., the first pre-stored digital value A of the internal reference voltage sort and a second pre-stored digital value K of the external reference voltage sort ) in memory device 100 (e.g., in a register of digital comparator 139). These pre-stored digital values ​​are used in calculating the calibrated measurement results in later processing.

[0033] Note that in some embodiments, the processing of blocks 1020 and 1030 may be performed only once during factory testing (sometimes referred to as a sorting process) of memory device 100. Here, factory testing refers to a device testing / qualification process (e.g., a quality control process) performed at a factory where memory device 100 is manufactured before memory device 100 is shipped and deployed in the field (e.g., for use in an electronic device comprising memory device 100). During the processing of block 1020, an external reference voltage is generated by a high-precision external voltage reference (e.g., laboratory testing equipment used during factory testing that provides a known, calibrated, high-precision reference voltage). The external reference voltage, which has higher precision (e.g., does not deviate much from its nominal value) than the internal reference voltage, is applied to input terminal 117 (see FIG. 1) of memory device 100 and transmitted to MUX 132 as an external reference signal (see the label “External Reference” in FIG. 2). MUX132 selects the external reference signal under factory test as the output signal to ADC137, which converts the external reference voltage into a digital value, K sort Convert to.

[0034] In some embodiments, the digital value K sort is used to calculate the actual internal reference voltage V provided by internal voltage reference 135. As a non-limiting example, consider a scenario in which internal voltage reference 135 is designed to generate an internal reference voltage having a nominal value of, say, 1.25 V. However, due to manufacturing limitations and other non-ideal conditions, the actual internal reference voltage V provided by internal voltage reference 135 may be INT The actual internal reference voltage V deviates from this nominal value and is unknown. INT To find an estimate of V, we use an external reference voltage provided during factory testing. EXT The actual internal reference voltage V INT teeth,

number

[0035] The processing of blocks 1040-1090 is performed after memory device 100 is deployed in the field, for example, when an electronic device including memory device 100 is monitoring analog signals during operation. In block 1040, one of the analog signals at the input of MUX 132 is selected and sent to ADC 137 for measurement. In block 1050, the selected analog signal from MUX 132 (e.g., the power supply voltage provided by voltage supply circuit 121) is scaled by scaling circuit 134 and then converted to digital value B by ADC 137, and the internal reference voltage provided by internal voltage reference 135 is converted to digital value A by ADC 137. Note that the internal reference voltage is measured again to compensate for various factors, such as component aging and temperature-induced drift, that may cause the internal reference voltage to drift over time. Details are described in the processing of block 1060.

[0036] Next, in block 1060, a transformation function f(A, B, A) is calculated as follows: sort ,K sort ) a digital value A of the internal reference voltage, a digital value B of the selected analog signal (e.g., a scaled selected power supply voltage), a first pre-stored digital value A of the internal reference voltage, sort and a second pre-stored digital value K of the external reference voltage sort The calibrated measurement is calculated using:

[0037] The digital values ​​A and B measured during operation of memory device 100 may contain uncontrolled / unpredictable errors caused by factors such as component aging, temperature-induced measurement drift, etc. In addition, the internal voltage reference may not be perfect (e.g., the internal reference voltage is not exactly at the nominal value of 1.25V), and the internal reference voltage may or may not drift over time. To eliminate or reduce the uncontrolled / unpredictable errors, the digital values ​​A and B are converted to a conversion function f(A,B,A) to calculate a calibrated measurement result. sort ,K sort ) the first pre-stored digital value A sort and a second pre-stored digital value K sort It is used together with the transformation function f(A,B,A sort ,K sort An example of this is given in equation (4) below.

[0038] In some embodiments, the first pre-stored digital value A sort and a second pre-stored digital value K sort is used to reduce errors in the digital values ​​A and B, or other related values ​​(e.g., calibrated measurements). As an example, given the digital value A of the internal reference voltage (which may or may not drift over time) measured when the nth analog signal is selected by MUX 132, the calibrated value V of the internal reference voltage is INT (n) is

number

[0039] Similarly, the calibration value V of a selected analog signal (e.g., a selected supply voltage) B teeth,

number

[0040] As previously mentioned, the calibrated measurement corresponds to a metric that indicates the value (e.g., voltage value) of a selected analog signal, such as, by way of example, the difference or ratio between the value of the selected analog signal and the value of an internal reference voltage. For example, depending on the structure / implementation of various circuits within IC device 100, different methods of calculating the calibrated measurement are possible, as will be readily appreciated by those skilled in the art. As a non-limiting example, a calibrated measurement expressed as CMR may be:

number

[0041] Next, in block 1070, the calibrated measurement result CMR calculated in block 1060 is compared to an expected range to determine whether the signal level (e.g., voltage value) of the selected analog signal is within the expected range. The expected range of the selected analog signal may be stored as a target value in register 105 of controller 103 and transmitted by controller 103 to analog signal monitoring circuit 130. For example, digital comparator 139 may compare the calibrated measurement result CMR with the expected range and determine whether the calibrated measurement result CMR is within the expected range (Range low ≦CMR≦Range high ), the digital comparator 139 declares a "pass" state for the selected analog signal; otherwise, the digital comparator 139 declares a "fail" state for the selected analog signal; low and Range high are the lower and upper bounds of the expected range. In other words, the digital comparator 139 sets an error flag to "1" if the calibrated measurement result is outside the expected range.

[0042] A "pass" or "fail" result is then reported to controller 103 by digital comparator 139, e.g., via control signal / data path 116, in block 1080. In some embodiments, controller 103 initiates error recovery action in response to receiving the error flag, e.g., by repeating the last memory access operation, monitoring the analog signal to ensure that the analog signal level is within a target range, or by resetting memory device 100 or resetting power management circuit 120.

[0043] Next, in block 1090, controller 103 checks whether all analog signals at the input of MUX 132 have been examined (e.g., monitored). If not, processing returns to block 1040, where controller 103 selects the next analog signal at the input of MUX 132 as the analog signal selected for examination. Processing continues until all analog signals at the input of MUX 132 have been examined. Then, in block 1010, monitoring is stopped. Processing between blocks 1040 and 1090 may begin again when controller 103 instructs power management circuit 120 to do so.

[0044] The analog signal monitoring disclosed herein reduces or prevents data errors in low-level processing of an electronic device, for example, during memory access operations. This advantageously provides early detection of data errors, reduces or prevents catastrophic data errors (e.g., a long sequence of data errors during memory access), and enables early error recovery operations, improving system performance and reducing latency. Data stored in a memory array is typically protected by an error correction code (ECC). The ECC provides some degree of protection against data errors. For example, the ECC may be designed to detect / correct a specific number of bit errors for a specific data size. However, when a burst error (e.g., a long sequence of bit errors) occurs, which is likely due to the analog signal (e.g., power supply voltage) used for memory access being outside a specified range, the ECC is unable to detect or correct the error. In fact, without the disclosed analog signal monitoring, an electronic device may believe that a memory access operation completed successfully, when in fact the analog signal (e.g., power supply voltage) used for memory access is outside a specified range, causing a long sequence of errors in the data being read or written. When data having a long sequence of errors is used by an application running on an electronic device, serious performance degradation or system failure may occur. For example, even if a data error is detected at a high level of processing, such as in an application running on an electronic device, data recovery operations (e.g., rewriting, rereading, or retransmitting) initiated by the application may cause longer processing delays, higher computational complexity, or higher power consumption. In contrast, the disclosed analog signal monitoring enables early detection of data errors and early error recovery operations by monitoring analog signals at the memory access level, thereby reducing the processing delays, computational complexity, and power consumption of the electronic device.

[0045] The circuits and methods for analog signal monitoring disclosed herein may be performed at different stages of operation of memory device 100. For example, analog signal monitoring may be performed during a dedicated calibration process or during a test mode when no memory access operations are being performed. As another example, analog signal monitoring may be performed periodically at a lower frequency, such as every 10 ms or every 100 ms, to periodically check the signal level of the analog signal. As another example, analog signal monitoring may be performed when controller 103 issues a command to power management circuit 120 to perform analog signal monitoring. As yet another example, analog signal monitoring may be performed as a built-in operation that is automatically executed in parallel with all memory access operations, for example. These and other variations are fully intended to be within the scope of the present disclosure.

[0046] 5 illustrates a flowchart of a method 2000 of operating a memory device, according to some embodiments. It should be understood that the exemplary method illustrated in FIG. 5 is merely an example of many possible exemplary methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, various steps illustrated in FIG. 5 may be added, removed, substituted, rearranged, or repeated.

[0047] 5, one or more power supply voltages are provided to a memory array in block 2010. In block 2020, the one or more power supply voltages are monitored, where the monitoring includes selecting a selected power supply voltage from the one or more power supply voltages, converting an internal reference voltage of the memory device and a scaled version of the selected power supply voltage(s) into one or more digital values ​​using an analog-to-digital converter (ADC), generating a calibrated measurement result using the one or more digital values, and determining whether the calibrated measurement result is within a predetermined range.

[0048] Embodiments may achieve the following advantages: In the disclosed embodiments, analog signals used in memory access operations are checked (e.g., monitored) to determine whether the signal level of the analog signals is within a specified range. If the analog signals are outside the specified range, a corresponding error flag is set. A memory device incorporating analog signal monitoring functionality can detect data errors early in the processing chain and reduce or prevent data errors by initiating error recovery operations early, if necessary, thereby reducing processing delays, processing complexity, and power consumption of the memory device. In addition, the disclosed method generates calibrated measurement results using pre-stored values ​​of the external and internal reference voltages stored during factory testing, thereby improving measurement accuracy and achieving better analog signal monitoring results.

[0049] Examples of the present invention are summarized here. Other examples can be seen throughout the specification and claims appended hereto.

[0050] Example 1. In one embodiment, a memory device comprises a memory array comprising memory cells, and power management circuitry for the memory array, the power management circuitry comprising: a voltage source configured to provide one or more power supply voltages to the memory array; an internal voltage reference configured to provide an internal reference voltage; a multiplexer configured to receive the one or more power supply voltages and to output a selected power supply voltage selected from the one or more power supply voltages; an analog-to-digital converter (ADC) configured to convert scaled versions of the internal reference voltage and the selected power supply voltage into one or more digital values; and a digital comparator. The digital comparator is configured to generate a calibrated measurement result using the one or more digital values, a first stored digital value of the internal reference voltage and a second stored digital value of the external reference voltage, compare the calibrated measurement result with a predetermined range, and set an error flag indicating a fault condition of the memory device in response to detecting that the calibrated measurement result is outside the predetermined range.

[0051] Example 2. The memory device of Example 1, wherein the first stored digital value and the second stored digital value are ADC outputs for an internal reference voltage and an external reference voltage, respectively, that were generated during factory testing of the memory device and stored in the memory device before the memory device was deployed in the field.

[0052] Example 3. The memory device of example 2, wherein the external reference voltage has a higher accuracy than the internal reference voltage.

[0053] Example 4. The memory device of Example 2, wherein the power management circuitry comprises an input terminal configured to receive an external reference voltage during factory testing of the memory device.

[0054] Example 5. The memory device of example 4, wherein the internal voltage reference is a bandgap voltage reference.

[0055] Example 6. The memory device of Example 1, further comprising a controller, the controller configured to send the predetermined range to the power management circuitry and receive the error flag from the power management circuitry.

[0056] Example 7. The memory device of Example 6, wherein the controller is further configured to, in response to receiving the error flag, instruct the memory device to repeat a previous memory access operation of the memory array.

[0057] Example 8. The memory device of Example 6, wherein the controller is further configured to reset the power management circuitry in response to receiving the error flag.

[0058] Example 9. The memory device of Example 6, further comprising an input / output (I / O) driver circuit coupled to the controller, and an I / O pad coupled to the I / O driver circuit for communication between the controller and an external device.

[0059] Example 10. The memory device of Example 1, wherein the power management circuitry further comprises a scaling circuit coupled between the multiplexer and the ADC and configured to scale the selected power supply voltage by a scaling factor.

[0060] Example 11. In one embodiment, an integrated circuit (IC) device includes a memory array including memory cells, a controller coupled to the memory array, and a power management circuit coupled to the memory array and the controller, the power management circuit including a voltage supply circuit configured to provide a power supply voltage to the memory array, a multiplexer coupled to the voltage supply circuit and configured to output a selected power supply voltage selected from the power supply voltage, an internal voltage reference configured to provide an internal reference voltage, an analog-to-digital converter (ADC) configured to convert scaled versions of the internal reference voltage and the selected power supply voltage into an ADC output, and a digital comparator. The digital comparator is configured to generate a calibrated measurement result using the ADC output, a first pre-stored digital value of the internal reference voltage, and a second pre-stored digital value of the external reference voltage, determine whether the calibrated measurement result is within a predetermined range, and set an error flag indicating a fault condition of the IC device in response to determining that the calibrated measurement result is outside the predetermined range.

[0061] Example 12. The IC device of Example 11, wherein the power management circuitry is configured to send an error flag to the controller.

[0062] Example 13. The IC device of Example 12, wherein the controller is configured to initiate an error recovery action for the IC device in response to the error flag.

[0063] Example 14. The IC device of Example 13, wherein initiating the error recovery operation includes resetting the power management circuitry or repeating a previous memory access operation of the memory array.

[0064] Example 15. A digital comparator is used to calculate the transfer function f(A,B,A sort ,K sort ), where A is a first ADC output for an internal reference voltage, B is a second ADC output for a scaled version of a selected supply voltage, and A sort is the first pre-stored digital value of the internal reference voltage, and K sort is a second pre-stored digital value of the external reference voltage, the external reference voltage having a higher accuracy than the internal reference voltage.

[0065] Example 16. The IC device of Example 15, wherein the first pre-stored digital value and the second pre-stored digital value are ADC outputs for an internal reference voltage and an external reference voltage, respectively, that were generated during factory testing of the IC device and stored in the IC device before the IC device was deployed in the field.

[0066] Example 17. In one embodiment, a method of operating a memory device includes supplying one or more power supply voltages to a memory array and monitoring the one or more power supply voltages, the monitoring including selecting a selected power supply voltage from the one or more power supply voltages, converting an internal reference voltage of the memory device and a scaled version of the selected power supply voltage(s) using an analog-to-digital converter (ADC) to one or more digital values, generating a calibrated measurement result using the one or more digital values, and determining whether the calibrated measurement result is within a predetermined range.

[0067] Example 18. The method of Example 17, further comprising setting an error flag indicating a fault condition of the memory device in response to determining that the calibrated measurement is outside a predetermined range.

[0068] Example 19. The method of Example 18, further comprising initiating a recovery operation in response to the error flag being set, wherein initiating the recovery operation comprises repeating a previous memory access operation of the memory array or resetting power management circuitry of the memory device.

[0069] Example 20. Producing a calibrated measurement result is a transformation function f(A,B,A sort ,K sort ), where A is a first digital value of the internal reference voltage converted by the ADC, and B is a second digital value of the scaled version of the selected power supply voltage converted by the ADC, and A sort is the first pre-stored digital value of the internal reference voltage, and K sort 18. The method of example 17, wherein: ≡(x,y) is a second pre-stored digital value of the external reference voltage, the external reference voltage having a higher accuracy than the internal reference voltage.

[0070] Example 21. The method of Example 20, wherein the first pre-stored digital value and the second pre-stored digital value are ADC outputs for an internal reference voltage and an external reference voltage, respectively, that were generated during factory testing of the memory device and stored in the memory device before the memory device was deployed in the field.

[0071] While the present invention has been described with reference to illustrative examples, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative examples, as well as other examples of the invention, will be apparent to those skilled in the art upon reference to the description. It is therefore intended that the appended claims cover any such modifications or examples. < / n>

Claims

1. a memory array comprising memory cells; a power management circuit for the memory array; A memory device comprising: The power management circuitry includes: a voltage source configured to provide one or more power supply voltages to the memory array; an internal voltage reference configured to provide an internal reference voltage; a multiplexer configured to receive the one or more power supply voltages and to output a selected power supply voltage selected from the one or more power supply voltages; an analog-to-digital converter (ADC) configured to convert scaled versions of the internal reference voltage and the selected power supply voltage into one or more digital values; A digital comparator; Equipped with The digital comparator generating a calibrated measurement result using the one or more digital values, the first stored digital value of the internal reference voltage, and the second stored digital value of the external reference voltage; comparing the calibrated measurement result with a predetermined range; configured to set an error flag indicating a fault condition of the memory device in response to detecting that the calibrated measurement is outside the predetermined range. Memory device.

2. the first stored digital value and the second stored digital value are ADC outputs for the internal reference voltage and the external reference voltage, respectively, the ADC outputs being generated during factory testing of the memory device and stored in the memory device before the memory device is deployed in the field; The memory device of claim 1 .

3. the external reference voltage has a higher accuracy than the internal reference voltage; The memory device of claim 2 .

4. the power management circuit comprises an input terminal configured to receive the external reference voltage during the factory testing of the memory device. The memory device of claim 2 .

5. the internal voltage reference is a bandgap voltage reference; The memory device of claim 4 .

6. The memory device further comprises a controller, the controller comprising: transmitting the predetermined range to the power management circuit; configured to receive the error flag from the power management circuit; The memory device of claim 1 .

7. The controller and further configured, in response to receiving the error flag, to instruct the memory device to repeat a previous memory access operation of the memory array. The memory device of claim 6.

8. The controller further configured to reset the power management circuitry in response to receiving the error flag. The memory device of claim 6.

9. The memory device is an input / output (I / O) driver circuit coupled to the controller; an I / O pad coupled to the I / O driver circuit for communication between the controller and an external device; Further provided with The memory device of claim 6.

10. the power management circuit further comprising a scaling circuit coupled between the multiplexer and the ADC, the scaling circuit configured to scale the selected power supply voltage by a scaling factor. The memory device of claim 1 .

11. a memory array comprising memory cells; a controller coupled to the memory array; a power management circuit coupled to the memory array and the controller; 1. An integrated circuit (IC) device comprising: The power management circuitry includes: a voltage supply circuit configured to provide a power supply voltage to the memory array; a multiplexer coupled to the voltage supply circuit and configured to output a selected power supply voltage selected from the power supply voltages; an internal voltage reference circuit configured to provide an internal reference voltage; an analog-to-digital converter (ADC) configured to convert scaled versions of the internal reference voltage and the selected power supply voltage into an ADC output; A digital comparator; Equipped with The digital comparator generating a calibrated measurement result using the ADC output, a first pre-stored digital value of the internal reference voltage, and a second pre-stored digital value of an external reference voltage; determining whether the calibrated measurement is within a predetermined range; configured to set an error flag indicating a fault condition of the IC device in response to determining that the calibrated measurement is outside the predetermined range. IC device.

12. the power management circuit is configured to send the error flag to the controller; The IC device of claim 11.

13. the controller is configured to initiate an error recovery action for the IC device in response to the error flag.

13. The IC device of claim 12.

14. Initiating the error recovery operation includes resetting the power management circuitry or repeating a previous memory access operation of the memory array.

14. The IC device of claim 13.

15. The digital comparator is a conversion function f(A, B, A ｓｏｒｔ , K ｓｏｒｔ ) to generate the calibrated measurement; A is the first ADC output for the internal reference voltage; B is a second ADC output for the scaled version of the selected power supply voltage; A ｓｏｒｔ is the first pre-stored digital value of the internal reference voltage; K ｓｏｒｔ is the second pre-stored digital value of the external reference voltage; the external reference voltage has a higher accuracy than the internal reference voltage; The IC device of claim 11.

16. the first pre-stored digital value and the second pre-stored digital value are ADC outputs for the internal reference voltage and the external reference voltage, respectively, the ADC outputs being generated during factory testing of the IC device and stored in the IC device before the IC device is deployed in the field; 16. The IC device of claim 15.

17. 1. A method of operating a memory device, the method comprising: providing one or more power supply voltages to the memory array; monitoring the one or more power supply voltages; Including, The monitoring steps are: selecting a selected power supply voltage from the one or more power supply voltages; converting an internal reference voltage of the memory device and a scaled version of the selected power supply voltage into one or more digital values ​​using an analog-to-digital converter (ADC); generating a calibrated measurement using the one or more digital values; determining whether the calibrated measurement is within a predetermined range; Including, The step of generating a calibrated measurement result comprises: generating said calibrated measurement using a transformation function f(A, B, A sort , K sort ); A is a first digital value of the internal reference voltage converted by the ADC; B is a second digital value of the scaled version of the selected power supply voltage converted by the ADC; A sort is a first pre-stored digital value of the internal reference voltage; K sort is a second pre-stored digital value of the external reference voltage; the external reference voltage has a higher accuracy than the internal reference voltage; method.

18. The method comprises: and, in response to determining that the calibrated measurement is outside the predetermined range, setting an error flag indicating a fault condition of the memory device.

18. The method of claim 17.

19. The method further includes initiating a recovery action in response to the error flag being set; Initiating the recovery operation includes repeating a previous memory access operation of the memory array or resetting power management circuitry of the memory device.

20. The method of claim 18.

20. the first pre-stored digital value and the second pre-stored digital value are ADC outputs for the internal reference voltage and the external reference voltage, respectively, the ADC outputs being generated during factory testing of the memory device and stored in the memory device before the memory device is deployed in the field; 18. The method of claim 17.

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