Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

To provide a SiC semiconductor device that can have a trench inner wall cleaned to improve the mobility, and to provide a method of manufacturing the same.SOLUTION: A SiC semiconductor device comprises: an n type drift region 2; a p type base region 3 arranged on the drift region 2; an n type main electrode region 4 embedded selectively on the base region 3, and having higher impurity density than the drift region 2; a trench 5 penetrating the base region 3 from the main electrode region 4 to reach the drift region 2; and an insulation gate structure (6, 7) provided inside the trench 5. An inner wall surface of the trench 5 has a first terrace defined with a first step in a depth direction of the trench 5 and a second terrace defined with a second step in a direction crossing the depth direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a silicon carbide (SiC) semiconductor device and a manufacturing method thereof, and more particularly to a trench gate type SiC semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In trench-gate MOS field-effect transistors (FETs) using SiC, trenches are generally excavated by RIE, followed by trench rounding, sacrificial oxide layer formation and removal, or isotropic plasma etching to form a gate oxide film. However, even after these processes, the surface of the trench sidewalls that form the MOSFET channel still suffers from surface precipitated carbon due to SiC oxidation or plasma etching damage, which leads to problems such as reduced field-effect mobility due to carrier scattering caused by interface states and surface roughness at the gate oxide / SiC interface.

[0003] Patent Document 1 describes that hydrogen annealing is performed followed by nitrogen-addition annealing to set the arithmetic mean roughness of the terrace portion of the trench sidewall surface to 0.1 nm or less, thereby reducing interfacial roughness scattering. In Patent Document 1, hydrogen annealing after trench formation is performed at a high pressure of 40,000 Pa. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2021-44355 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a SiC semiconductor device that can clean the inner walls of trenches and improve mobility, and a method for manufacturing the SiC semiconductor device. [Means for solving the problem]

[0006] In order to achieve the above object, one aspect of the present invention is a SiC semiconductor device comprising: (a) a drift region of a first conductivity type; (b) a base region of a second conductivity type disposed on the drift region; (c) a main electrode region of the first conductivity type selectively embedded in an upper portion of the base region and having a higher impurity concentration than the drift region; (d) a trench extending from the main electrode region through the base region to reach the drift region; and (e) an insulated gate structure provided inside the trench, wherein the inner wall surface of the trench has a first terrace defined by a first step in the depth direction of the trench and a second terrace defined by a second step in a direction intersecting the depth direction.

[0007] Another aspect of the present invention is a method for manufacturing a SiC semiconductor device, comprising: (a) forming a base region of a second conductivity type on an upper surface of a drift region of a first conductivity type; (b) forming a main electrode region of the first conductivity type, the main electrode region having a higher impurity density than the drift region, on top of the base region; (c) forming a trench from the upper surface of the main electrode region through the base region to reach the drift region; (d) hydrogen-etching the inner wall surface of the trench by heating in a hydrogen-containing atmosphere having a pressure of 67 Pa (0.5 Torr) or more and 4000 Pa (30 Torr) or less; (e) forming a gate insulating film inside the trench; and (f) forming a gate electrode on the gate insulating film to control the surface potential of the channel formation region. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a SiC semiconductor device and a method for manufacturing a SiC semiconductor device that can clean the inner walls of trenches and improve mobility. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic cross-sectional view showing an example of a SiC semiconductor device according to an embodiment of the present invention. [Figure 2] 2A to 2C are schematic cross-sectional views illustrating an example of a process of a method for manufacturing a SiC semiconductor device according to an embodiment. [Figure 3] 3 is a schematic cross-sectional view continuing from FIG. 2 for explaining an example of a process of the method for manufacturing the SiC semiconductor device according to the embodiment. [Figure 4] 4 is a schematic cross-sectional view continuing from FIG. 3 for explaining an example of a process of the method for manufacturing the SiC semiconductor device according to the embodiment. [Figure 5] 5 is a schematic cross-sectional view continuing from FIG. 4 for explaining an example of a process of the method for manufacturing the SiC semiconductor device according to the embodiment. [Figure 6] 6 is a schematic cross-sectional view continuing from FIG. 5 for explaining an example of a process of the method for manufacturing the SiC semiconductor device according to the embodiment. [Figure 7] 7 is a schematic cross-sectional view continuing from FIG. 6 for explaining an example of a process of the method for manufacturing the SiC semiconductor device according to the embodiment. [Figure 8] 1 is a schematic cross-sectional view showing an example of a trench sidewall of a SiC semiconductor device. [Figure 9] FIG. 10 is a diagram showing an example of an AFM image of the inner wall surface of a trench according to an embodiment. [Figure 10] FIG. 10 is a diagram showing an example of an AFM image of the inner wall surface of a trench according to a comparative example. [Figure 11] FIG. 10 is a diagram showing another example of an AFM image of the inner wall surface of a trench according to a comparative example. [Figure 12] 1 is a table showing evaluation results of the mobility of the SiC semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the embodiments shown below are examples of devices and methods for embodying the technical concept of the present invention, and the technical concept of the present invention does not specify the materials, shapes, structures, arrangements, etc. of component parts to those described below.

[0011] In this specification, the source region of an MIS transistor is "one of the main regions (first main region)" that can be selected as the emitter region of an insulated gate bipolar transistor (IGBT). In addition, in a thyristor such as an MIS-controlled static induction thyristor (SI thyristor), one of the main regions can be selected as the cathode region. The drain region of an MIS transistor is "the other main region (second main region)" of the semiconductor device that can be selected as the collector region in an IGBT or as the anode region in a thyristor. In this specification, the term "main region" simply refers to either the first or second main region, as appropriate from the common technical knowledge of a person skilled in the art.

[0012] Furthermore, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical concept of the present invention. For example, if an object is rotated 90 degrees and observed, up and down are read as being converted to left and right, and if it is rotated 180 degrees and observed, up and down are read as being reversed. The following description will exemplify a case in which the first conductivity type is n-type and the opposite second conductivity type is p-type. However, the conductivity types may be selected in reverse, with the first conductivity type being p-type and the second conductivity type being n-type. Furthermore, the + or - appended to n or p indicates a semiconductor region with a relatively higher or lower impurity density, respectively, compared to a semiconductor region without the + or - appended. However, semiconductor regions with the same n and n appended do not necessarily have the same impurity density. Furthermore, in this specification, in the Miller index notation, "-" refers to a bar immediately following the index, and adding "-" before an index indicates a negative index.

[0013] (SiC semiconductor device structure) As shown in FIG. 1, the SiC semiconductor device according to the embodiment of the present invention has a first conductivity type (n - A second conductivity type (p - The base region 3 is a trench gate type MOSFET. The lower surface of the drift region 2 is covered with an n-type impurity layer having a higher impurity density than the drift region 2. + A drain region (first main region) 1 of the n-type is provided above the base region 3. The n-type drain region (first main region) 1 has a higher impurity density than the drift region 2. + A second main region (source region) 4 of a silicon nitride type is provided on the upper surface of the source region 4. A front surface electrode (source electrode) 8 is provided on the lower surface of the drain region 1. A back surface electrode (drain electrode) 9 is provided on the lower surface of the drain region 1.

[0014] The source electrode 8 and the drain electrode 9 are ohmically connected to the source region 4 and the drain region 1, respectively. The source electrode 8 and the drain electrode 9 are made of, for example, a single layer film made of Al or nickel silicide (NiSi xA metal film in which a metal film including titanium nitride (TiN) and Al is laminated in this order can be used. Although not shown in the figure, a p + A type base contact region may be disposed adjacent to the source region 4 .

[0015] A trench 5 is provided from the top surface of the source region 4 in the depth direction, penetrating the base region 3 and having its bottom reaching the drift region 2. An insulated gate structure (6, 7) is provided inside the trench 5. The insulated gate structure (6, 7) has a gate insulating film 6 provided on the bottom and side surfaces of the trench 5, and a gate electrode (control electrode) 7 buried in the trench 5 with the gate insulating film 6 interposed therebetween.

[0016] In an embodiment of the present invention, the drain region 1 is composed of a semiconductor substrate (SiC substrate) made of SiC, and the drift region 2 and base region 3 are composed of epitaxial layers (SiC layers) made of SiC. SiC crystals have crystal polymorphs, the main ones being cubic 3C, hexagonal 4H, 6H, and cubic. The band gaps at room temperature have been reported to be 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. In the embodiment of the present invention, 4H-SiC will be used for explanation.

[0017] In the SiC semiconductor device according to the embodiment, the upper surface of the drain region 1 is a (0001) plane (Si plane) or a (000-1) plane (C plane), <0001> The off-angle θ is approximately 1° to 8°, for example 4°, in the <11-20> (a-axis) direction relative to the (c-axis) direction. The off-angle θ is the angle between the top surface of the drain region 1 and a plane (basal plane) perpendicular to the c-axis, which is the (0001) plane (Si plane) or the (000-1) plane (C-plane). The description will be given using the Si plane as the top surface of the drain region 1 and the (1-100) m-plane as the side surface of the trench 5 that serves as the channel. The top surface of the drain region 1 may be the C-plane, and the side surface of the trench 5 may be the (11-20) a-plane.

[0018] The gate insulating film 6 can be a silicon oxide film (SiO2 film), a silicon oxynitride (SiON) film, a single-layer film with a higher dielectric constant than SiO2 film, or a composite film made by laminating multiple layers of these. Specifically, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, an yttrium oxide (Y2O3) film, or the like can be used. Other usable materials include a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, and a bismuth oxide (Bi2O3) film. The gate electrode 7 can be made of a polysilicon layer (doped polysilicon layer) doped with a high concentration of impurities such as phosphorus (P) or boron (B).

[0019] 1, in the SiC semiconductor device according to the embodiment, a voltage is applied to the gate electrode 7 to form an inversion layer that serves as a channel at the interface between the gate insulating film 6 and the base region 3. At this time, a voltage is applied between the source electrode 8 and the drain electrode 9, so that carriers (electrons) are injected into the channel from the source region 4. The injected carriers travel through the drift region 2 and flow into the drain region 1.

[0020] As will be described later, the semiconductor device according to the embodiment uses trenches 5 whose inner wall surfaces have been subjected to hydrogen etching treatment at low pressure and high temperature in a hydrogen-containing atmosphere. By performing hydrogen etching treatment at low pressure and high temperature, damaged layers and carbon deposits on the inner walls of trenches 5 can be removed and cleaned, making it possible to reduce scattering of electrons traveling through the channel.

[0021] (SiC semiconductor device manufacturing method) Next, a method for manufacturing a trench-gate SiC semiconductor device according to an embodiment will be described with reference to the process diagrams shown in Figures 2 to 7. Note that the method for manufacturing a MOSFET described below is one example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be implemented within the scope of the spirit of the claims.

[0022] First, n-type impurities such as nitrogen (N) are added. + A 4H—SiC substrate (substrate) 1s is prepared. The substrate 1s has a Si surface with an off-angle on the top surface, tilted in the range of 0° to 8°, for example, about 4°, toward the a-axis with respect to the c-axis. An n-type impurity such as N is added to the top surface of the substrate 1s. - A p-type drift region 2 is epitaxially grown. Subsequently, a base region 3 doped with p-type impurities such as aluminum (Al) is epitaxially grown on the upper surface of the drift region 2. An n-type impurity such as phosphorus (P) is implanted into the upper part of the base region 3 using a multi-stage ion implantation technique or the like. The implanted n-type impurity ions are activated by heat treatment, and as shown in Figure 2, n-type impurity ions are formed in the upper part of the base region 3. + A p-type source region 4 is formed. + When a p-type base contact region is provided, p-type impurities such as aluminum (Al) are ion-implanted before heat treatment. + A base contact region of the mold is formed.

[0023] Next, an oxide film such as SiO2 is formed on the top surface of the source region 4 by chemical vapor deposition (CVD) or other methods. A photoresist film is applied to the top surface of the formed oxide film and patterned using photolithography or other techniques. The patterned photoresist film has openings extending in the <11-20> direction, which is the direction in which the top surface of the substrate 1s is tilted at an off-angle in plan view. Using the patterned photoresist film as an etching mask, the oxide film is patterned by dry etching using a trifluoromethane (CHF3), tetrafluoromethane (CF4), and argon (Ar) gas mixture. Then, using the patterned oxide film as an etching mask, a trench 5s is selectively formed that penetrates the source region 4 and base region 3 and reaches the drift region 2, as shown in Figure 3, by dry etching using a sulfur hexafluoride (SF6), oxygen (O2), and Ar gas mixture, such as inductively coupled reactive ion etching (ICP-RIE). The trench 5s extends in the a-axis direction in plan view, but the extension direction includes an error of about ±5° from the a-axis direction due to wafer orientation error.

[0024] The oxide film used as an etching mask is removed by wet etching using hydrofluoric acid (HF) or the like. Then, a hydrogen etching process is performed in a hydrogen (H2)-containing gas atmosphere at a pressure of 67 Pa to 4000 Pa and a temperature of 1300°C to 1600°C. This low-pressure hydrogen etching process cleans the surface layers of the top surface of the source region 4 and the sidewalls and bottom surface of the trench 5s, forming the trench 5, as shown in FIG. 4. The hydrogen-containing gas atmosphere contains hydrogen (H2) in the range of 3% to 100% and a rare gas such as Ar, neon (Ne), or krypton (Kr). The hydrogen-containing gas preferably has a flow rate of 100 sccm or more, depending on the exhaust capacity of the low-pressure hydrogen etching equipment.

[0025] Next, as shown in FIG. 5, an insulating film 6s, such as a high-temperature silicon dioxide (HTO) film, is deposited on the inner surface of the trench 5 and the upper surface of the source region 4 by low-pressure (LP) thermal chemical vapor deposition (CVD) or other methods. LP thermal CVD can employ deposition conditions of approximately 600°C at a pressure of approximately 0.2 Pa using a mixture of silane (SiH4) and oxygen (O2). Subsequently, nitridation is performed at a temperature of 1150°C to 1300°C in an atmospheric pressure gas atmosphere containing approximately 10% nitric oxide (NO) gas in nitrogen (N2) gas. Nitrous oxide (NO) gas may be used instead of NO for the nitridation. The nitridation process forms a termination layer in which N atoms replace vacancies at the interface between the HTO film and SiC.

[0026] After the nitridation process, a doped polysilicon layer containing a high concentration of impurities such as P is deposited on the upper surface of the insulating film 6s by LP-CVD or the like. The doped polysilicon layer is selectively removed by photolithography and dry etching to form a gate electrode 7 so as to fill the trench 5 covered with the insulating film 6s, as shown in FIG. 6. Subsequently, the insulating film 6s is selectively removed by photolithography and dry etching or the like. As a result, an insulated gate structure (6, 7) consisting of the gate insulating film 6 and the gate electrode 7 is formed, as shown in FIG. 7. After forming the gate electrode 7, an interlayer insulating film may be provided to cover the gate electrode 7, and the interlayer insulating film and the insulating film 6s may be selectively removed simultaneously. Next, a metal film such as aluminum deposited by sputtering or evaporation or the like is selectively removed by photolithography and dry etching or the like to form a source electrode 8 on the upper surface of the exposed source region 4.

[0027] Next, the lower surface of the substrate 1s is polished by chemical mechanical polishing (CMP) or the like to adjust the thickness, thereby forming the drain region 1. Thereafter, a back surface electrode (drain electrode) 9 made of a metal film such as Al is formed on the lower surface of the drain region 1 by sputtering or vacuum deposition or the like. In this manner, the SiC semiconductor device according to the embodiment shown in FIG. 1 is completed.

[0028] <Hydrogen etching treatment> Typically, when a trench is formed in a SiC substrate, the trench sidewalls are not perpendicular to the main surface but tilted by approximately 5° from the perpendicular. Because the top surface of a SiC substrate is generally tilted by approximately 4° to 8° toward the <11-20> direction relative to the (0001) Si surface, when a trench-gate MOSFET is fabricated using a Si substrate with an m-plane as the channel formation surface, the actual channel formation surface tilts not only in the c-axis direction but also in the a-axis direction from the m-plane. Furthermore, if the wafer's orientation flat formation surface deviates from the expected m-plane, the extension direction of the trench formed by aligning the orientation flat may deviate by approximately 5° from the a-axis direction, resulting in the channel formation surface tilting not only in the c-axis direction but also in the a-axis direction from the m-plane. When a clean trench inner wall surface is formed by trench annealing using hydrogen gas, a step-terrace structure is formed, with steps appearing in two different directions and terraces between the steps, depending on the inclination in the a-axis and c-axis directions. Figure 8 is an enlarged cross-sectional view of a trench cut in the c-axis or a-axis direction. The trench sidewall Lc is inclined at an inclination angle α due to dry etching or the off-angle of the SiC substrate, and has a step-terrace structure consisting of steps St and terraces Te defined between adjacent steps St. In Figure 8, "e" represents electrons, which are carriers. If the spacing between steps St is too short and the width of the terraces Te is narrow, the electrons "e" traveling through the channel will be scattered more by the steps St. This reduces the field-effect mobility, so a wide step spacing is preferable.

[0029] Because the etching rate in hydrogen etching is proportional to the amount of silicon evaporated, improving the etching rate requires high temperatures and low gas pressures to efficiently evaporate silicon. At gas pressures of 10,640 Pa to 13,333 Pa, which are typically used in trench annealing, the etching rate of the trench inner wall is nearly zero. On the other hand, at low gas pressures of around 400 Pa, the etching rate increases, and an etching rate of several nanometers per minute is achieved at around 1,500°C. The damaged layer on the trench inner wall caused by dry etching during trench formation is thought to be several nanometers thick. Therefore, performing hydrogen etching at low pressures removes and cleans the damaged layer and carbon deposits on the trench inner wall, reducing roughness scattering.

[0030] In addition, the Si surface on the top surface of the SiC substrate exposed to the hydrogen atmosphere is etched at a faster rate than the m surface on the inner wall surface of the trench. This is thought to be because the supply of hydrogen gas is stagnant inside the trench, effectively slowing down the gas flow rate. + The upper surface of the source region 4 of the mold is etched away, which tends to increase the resistance of the semiconductor device. To prevent the resistance of the semiconductor device from increasing, the depth of the source region 4 must be set to about 400 nm to 800 nm, and the hydrogen etching process must remove a damaged layer of several nanometers from the inner wall surface of the trench 5 while limiting the amount of etching of the upper surface of the source region 4 to 150 nm or less. Considering the amount of etching of the source region 4, the hydrogen etching process is preferably performed for 2 to 3 minutes at a gas pressure of about 400 Pa and a temperature of about 1500°C.

[0031] The temperature conditions for the hydrogen etching treatment are preferably in the range of 1300°C to 1600°C, and more preferably in the range of 1400°C to 1500°C. If the temperature is less than 1300°C, hydrogen etching of the inner wall surface of the trench 5 is hardly possible. If the temperature exceeds 1600°C, step bunching occurs on the inner wall surface of the trench 5, which is undesirable. The pressure conditions are preferably in the range of 67 Pa to 4000 Pa, and more preferably in the range of 67 Pa to 1333 Pa. If the pressure is less than 67 Pa, the supply of hydrogen molecules is reduced, resulting in significant carbon deposition. Furthermore, if the pressure exceeds 4000 Pa, hydrogen etching of the inner wall surface of the trench 5 becomes difficult.

[0032] Furthermore, etching for a short period of a few minutes can result in uneven etching due to the temperature distribution within the surface of the SiC substrate. In this case, it is necessary to control the processing time by reducing the etching rate. The etching rate can be reduced by using a relatively low temperature range of 1300°C to 1500°C, which reduces Si evaporation, or by using an atmospheric pressure range of 400 Pa to 4000 Pa. It is preferable to adjust the etching rate by the temperature and atmospheric pressure of the hydrogen etching process and set the processing time to at least 5 minutes. The etching rate can also be reduced by reducing the hydrogen concentration in the atmospheric gas. In this case, if the hydrogen concentration is less than 3%, the etching rate will be too low, causing problems with the reproducibility of the etching process, so a hydrogen concentration of 3% or more in the atmospheric gas is preferred.

[0033] <Evaluation of semiconductor devices> SiC semiconductor devices according to the embodiment were fabricated, and their field-effect mobility was evaluated. The trench inner wall surfaces were also observed with an atomic force microscope (AFM). For the samples of Examples 1 to 4 and Comparative Examples 1 to 3, hydrogen etching after trench formation was performed in a 100% hydrogen atmosphere, with the etching conditions of temperature, gas pressure, and time varied. In Example 1, the treatment temperature was 1500°C, the gas pressure was 400 Pa, and the treatment time was 2 minutes. In Example 2, the treatment temperature was lowered to 1300°C than in Example 1, and the gas pressure was lowered to 133 Pa to compensate for the reduced etching rate, and the treatment time was extended to 19 minutes. In Example 3, the treatment temperature was the same as in Example 1 at 1500°C, but the gas pressure was increased to 4000 Pa to reduce the etching rate, and the treatment time was extended to 45 minutes. In Example 4, the treatment temperature was increased to 1550°C, the gas pressure was 1333 Pa, and the treatment time was 5 minutes. In Comparative Example 1, the treatment temperature was 1500°C, as in Examples 1 and 2, the gas pressure was 5333 Pa, which was higher than in Example 3, and the treatment time was 68 minutes, which was longer. In Comparative Example 2, the treatment temperature was 1550°C, as in Example 4, the gas pressure was 6666 Pa, which was higher than in Example 4, and the treatment time was 40 minutes, which was longer. In Comparative Example 3, the treatment temperature was 1500°C, the gas pressure was 4000 Pa, as in Example 3, and the treatment time was 2 minutes, which was shorter. In addition, Comparative Example 4 was a sample prepared without performing hydrogen etching treatment.

[0034] For each sample of Examples 1 to 4 and Comparative Examples 1 to 4, an evaluation element such as a TEG was cut out, and the insulated gate structure (6, 7) embedded in the trench 5 was removed using a wet etching agent such as phosphoric acid or dilute hydrofluoric acid to expose the inner wall surface of the trench 5, followed by AFM observation. Figure 9 shows AFM images of Examples 1 to 4, Figure 10 shows AFM images of Comparative Examples 1 to 3, and Figure 11 shows an AFM image of Comparative Example 4. In the AFM images of the trench inner wall surface of Examples 1 to 4, as shown in Figure 9, a step-terrace structure consisting of steps and terraces defined between the steps can be confirmed in two different directions, the c-axis and the a-axis. Thus, for each of Examples 1 to 4, it is believed that the surface was sufficiently cleaned by hydrogen etching, and a two-directional step-terrace structure was formed due to the tilt of the SiC crystal axis in the c-axis and a-axis directions. The two-way step-terrace structure has a terrace width of 10 nm or more and 500 nm or less in the c-axis and a-axis directions, and a step height (step depth) of 0.5 nm or more and 10 nm or less.

[0035] In the AFM images of the trench inner wall surfaces of Comparative Examples 1 to 3, as shown in FIG. 10, a uniaxial step-terrace structure resulting from the tilt in the c-axis direction is confirmed. When the surface is cleaned by hydrogen etching, a step-terrace structure is formed due to the tilt from the m-plane, which is the crystal plane of the surface. However, the AFM image in FIG. 10 does not confirm the step-terrace structure in the a-axis direction. In Comparative Examples 1 to 3, the step height and terrace width formed due to the tilt in the a-axis direction are thought to be small. Alternatively, the gas pressure in Comparative Examples 1 and 2 is higher than that in Examples 3 and 4, which have the same treatment temperature, exceeding 30 Pa. In Comparative Example 3, the treatment time is shorter (2 minutes compared to 45 minutes in Example 3), which is thought to be insufficient hydrogen etching. Thus, the surface was not sufficiently cleaned, and steps and terraces could not be clearly seen in the a-axis direction in the AFM images, and only the step-terrace structure in the c-axis direction was confirmed. Furthermore, in Comparative Example 4, which did not undergo hydrogen etching, no clear step-terrace structure was observed, as shown in FIG. 11. This is thought to be due to the effect of the SiC natural oxide film or carbon deposits generated during the formation of the gate insulating film irregularly covering the surface on the inner wall surface of the trench.

[0036] 12 is a table showing the conditions of the hydrogen etching treatment and the results of AFM image observation, as well as the measurement results of the field-effect mobility of the MOSFET. As shown in the table in FIG. 12, the samples of Examples 1 to 4 have a field-effect mobility of 68 cm 2 / Vs~72cm 2 / Vs, whereas the samples of Comparative Examples 1 to 4 were 50 cm 2 / Vs~54cm 2 Thus, in the samples of Examples 1 to 4 having a two-way step-terrace structure on the inner wall surface of the trench, the field-effect mobility was 70 cm 2 On the other hand, in the samples of Comparative Examples 1 to 4, which have no step-terrace structure or have a one-directional step-terrace structure on the inner wall surface of the trench, the field-effect mobility is 50 cm 2 / Vs. In this way, it was confirmed that the AFM image of the trench inner wall surface can be used as an indicator of surface cleanliness. In the SiC semiconductor device according to the embodiment, by appropriately adjusting the processing temperature and processing time in the low gas pressure hydrogen etching process, it is possible to clean the trench inner wall and improve the channel mobility.

[0037] (Other embodiments) As described above, the insulated gate semiconductor device according to the first to third embodiments of the present invention has been described, but the descriptions and drawings that form part of this disclosure should not be construed as limiting the present invention. Various alternative embodiments, examples, and application techniques will be apparent to those skilled in the art from this disclosure.

[0038] As described above, in the embodiments, 100% hydrogen gas or a mixture of 3% or more hydrogen and a rare gas is used as the atmospheric gas for the hydrogen etching process. However, trace amounts of oxidizing gases, such as oxygen (O), in the range of 0.5 ppm to 50 ppm may also be added to the atmospheric gas. Generally, even when a step-terrace structure is formed on the inner wall surface of a trench by hydrogen etching, clustered carbon precipitates may form at the step edges (kinks) of the trench. Because carbon precipitates are not removed during the semiconductor device manufacturing process, they act as excess carbon at the MOS interface in the final MOSFET, causing defects and surface roughness. Etching with hydrogen alone is difficult to remove clustered carbon precipitates. Oxygen, other than hydrogen, is a gas that efficiently reacts with carbon. While oxygen is generally thought to react with hydrogen, it is difficult to react with hydrogen at low oxygen concentrations, and some oxygen remains. It has been confirmed that adding trace amounts of oxygen, in the range of 0.5 ppm to 50 ppm, to the hydrogen etching atmosphere improves the ability to remove carbon precipitates and increases the hydrogen etching rate. In MOSFET samples that were subjected to hydrogen etching with the addition of a small amount of oxygen, it was confirmed that the field-effect mobility was improved and carbon deposits were removed. No increase in the etching rate was observed when the oxygen concentration was less than 0.5 ppm, but when the oxygen concentration exceeded 50 ppm, numerous pits formed on the inner wall surface of the trench, resulting in increased surface roughness. While oxygen was used as the oxidizing gas in this example, other oxidizing gases such as ozone (O3), nitric oxide (NO), and nitrous oxide (N2O) can also be used.

[0039] Although the above embodiment has been described as an example of a MOSFET, the semiconductor device to which the present invention is applicable is not limited to a MOSFET. The semiconductor device of the present invention can be applied to semiconductor devices having various trench structures, such as an IGBT having a trench structure in which an electrode is disposed on a semiconductor layer via an insulating film.

[0040] As such, the present invention naturally includes various embodiments not described herein, such as configurations in which the configurations described in the above embodiments and modifications are arbitrarily applied, etc. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0041] 1...Drain region (second main region) 1s...board 2...Drift region 3...Base area 4...Source region (first main region) 5...Trench 6...Gate insulating film 7...Gate electrode (control electrode) 8...Source electrode (surface electrode) 9...Drain electrode (rear electrode)

Claims

1. a drift region of a first conductivity type; a base region of a second conductivity type disposed on the drift region; a first conductivity type main electrode region selectively embedded in an upper portion of the base region and having a higher impurity concentration than the drift region; a trench extending from the main electrode region through the base region to the drift region; an insulated gate structure disposed inside the trench; Equipped with an inner wall surface of the trench having a first terrace defined by a first step in a depth direction of the trench and a second terrace defined by a second step in a direction intersecting the depth direction.

2. 2 . The silicon carbide semiconductor device according to claim 1 , wherein the width of each of the first terrace and the second terrace is not less than 10 nm and not more than 500 nm.

3. 3. The silicon carbide semiconductor device according to claim 2, wherein the depth of each of the first step and the second step is not less than 0.5 nm and not more than 10 nm.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the upper surface of the main electrode region is a surface having an off angle in the <11-20> direction with respect to the <0001> direction, and the plane orientation of the inner wall surface of the trench is a (11-20) plane or a (1-100) plane.

5. 5. The silicon carbide semiconductor device according to claim 4, wherein the plane orientation of the inner wall surface is a (11-20) plane, the depth direction is a <0001> direction, and the intersecting direction is a <1-100> direction.

6. forming a base region of a second conductivity type on an upper surface of a drift region of a first conductivity type; forming a first conductivity type main electrode region having a higher impurity concentration than the drift region above the base region; forming a trench extending from an upper surface of the main electrode region through the base region to the drift region; a step of hydrogen-etching the inner wall surface of the trench by heating in a hydrogen-containing atmosphere having a pressure of 67 Pa or more and 4000 Pa or less; forming a gate insulating film inside the trench; forming a gate electrode on the gate insulating film to control a surface potential of the base region; Including, A method for manufacturing a silicon carbide semiconductor device, wherein when the gas pressure is set to 4000 Pa, the treatment time is set to 5 minutes or more.

7. 7. The method for manufacturing a silicon carbide semiconductor device according to claim 6, wherein the hydrogen etching step comprises heating at a temperature of 1300°C or higher and 1600°C or lower.

8. 8. The method for manufacturing a silicon carbide semiconductor device according to claim 6, wherein the hydrogen-containing atmosphere in said hydrogen etching step contains hydrogen at a concentration of 3% or more and 100% or less.

9. A step of forming a base region of a second conductivity type on an upper surface of a drift region of a first conductivity type; forming a first conductivity type main electrode region having a higher impurity concentration than the drift region above the base region; forming a trench extending from an upper surface of the main electrode region through the base region to the drift region; a step of hydrogen-etching the inner wall surface of the trench by heating in a hydrogen-containing atmosphere having a pressure of 67 Pa or more and 4000 Pa or less; forming a gate insulating film inside the trench; forming a gate electrode on the gate insulating film to control a surface potential of the base region; Including, the hydrogen-containing atmosphere in the hydrogen etching step contains hydrogen at a concentration of 3% or more and 100% or less; a hydrogen-containing atmosphere containing an oxidizing gas at a concentration of 0.5 ppm to 50 ppm;

Images