Back-contact battery, its manufacturing method and photovoltaic assembly

Abstract

The present disclosure relates to the technical field of back-contact batteries, and more particularly to a back-contact battery, its manufacturing method, and a photovoltaic assembly. The back-contact battery includes a silicon substrate having a front and a back surface, a first semiconductor layer on the back surface, the first semiconductor layer having a second semiconductor opening region, and a second semiconductor layer. The back surface further includes a plurality of insulating layers spaced apart along the X-axis direction, the insulating layers being disposed on the outer surfaces of the second semiconductor layer and each extending across a side edge of the second semiconductor opening region in the X-axis direction. The insulating layer's spanning length W12 in the second semiconductor opening region and its spanning length W11 in the first semiconductor layer satisfy a ratio W12:W11 = 0.1 to 10:1. The back-contact battery of the present disclosure effectively prevents leakage current from occurring at the side edge of the second semiconductor opening region, while simultaneously achieving excellent cell efficiency, a high cell pass rate, and a simple manufacturing process.

Description

[Technical Field]

[0001] This application claims priority based on a Chinese patent application bearing application number 2023103322311 and entitled "Back-contact battery, its manufacturing method and photovoltaic assembly," filed with the State Intellectual Property Office of the People's Republic of China on March 31, 2023, the entire contents of which are incorporated herein by reference.

[0002] FIELD OF THE INVENTION This application relates to the field of back-contact batteries, and more particularly to back-contact batteries, their manufacturing methods, and photovoltaic assemblies. [Background technology]

[0003] Conventional back-contact batteries include those with a conventional heterojunction passivation structure and those with a composite passivation structure. The composite passivation structure uses a tunnel oxide film passivation for the first passivation layer of the first semiconductor layer and an intrinsic silicon layer passivation for the second passivation layer of the second semiconductor layer, resulting in superior battery performance compared to conventional heterojunction passivation. Furthermore, conventional back-contact batteries have a second semiconductor opening region in the first semiconductor layer to accommodate a portion of the second semiconductor layer, and a first semiconductor opening region in the second semiconductor layer to expose a portion of the first semiconductor layer, each of which is coupled to a metal electrode to form two emitters. Specifically, a composite passivation structure is a back-contact battery formed by combining a second semiconductor layer of a conventional heterojunction passivation structure with a first semiconductor layer of a TOPCON passivation structure. The first semiconductor layer uses a tunnel oxide layer (TOPCON passivation layer) and an N-type doped polycrystalline silicon layer, and the second semiconductor layer uses a conventional heterojunction intrinsic amorphous silicon passivation layer. That is, the term "composite" here means combining two passivation structures. Those skilled in the art will understand that the specific meaning is "combining two passivation structures."

[0004] However, serious leakage and short circuits are likely to occur at the side edges of the second semiconductor opening region (i.e., the contact boundary between the first and second semiconductor layers in the Z-axis direction), which reduces the parallel resistance of the battery, and ultimately reduces the battery efficiency and battery pass rate.

[0005] CN115588698A provides a back-contact solar cell, its manufacturing method, and a photovoltaic assembly. The back-contact solar cell includes a silicon substrate, a first semiconductor layer located on a first surface of the silicon substrate, a second semiconductor layer, and a first insulating layer. A first portion of the second semiconductor layer and the first semiconductor layer are alternately arranged with a gap therebetween, and a second portion of the second semiconductor layer is continuous with the first portion and extends along a second direction perpendicular to the first surface to the side of the first semiconductor layer away from the silicon substrate. The first insulating layer is located at least within the gap and adjacent to an end of the first conductive semiconductor layer. Between the first and second conductive semiconductor layers, there is a second intrinsic semiconductor layer that serves as passivation and insulation. The first insulating layer also provides excellent insulation reinforcement for the first and second conductive semiconductor layers, reducing the probability of electrical leakage between different types of conductive semiconductor layers. In this application, a first insulating layer is provided between a first semiconductor layer and a second semiconductor layer under the condition of having a mask layer, and a part of the first insulating layer in the width direction directly contacts the silicon substrate and also serves as a passivation layer, which affects the battery efficiency and battery pass rate and makes the manufacturing process complicated.

[0006] Therefore, there is a need in the art for a back-contact type battery that can effectively avoid leakage current that occurs at the side edges of the second semiconductor opening region, has excellent battery efficiency and battery pass rate, and is simple to manufacture. Summary of the Invention

[0007] The present disclosure aims to overcome the deficiencies in the prior art, such as the inability to effectively avoid leakage current occurring at the side edges of the second semiconductor opening region, to simultaneously achieve excellent cell efficiency and a cell pass rate, and a simple manufacturing process, by providing a back-contact type battery, a manufacturing method thereof, and a photovoltaic assembly, which can simultaneously achieve excellent cell efficiency and a cell pass rate, and a simple manufacturing process, while effectively avoiding leakage current occurring at the side edges of the second semiconductor opening region.

[0008] To achieve the above object, a first aspect of the present disclosure provides a back-contact battery, the back-contact battery including a silicon substrate having a front surface and a back surface, a first semiconductor layer provided on the back surface and having a second semiconductor opening region, a second semiconductor layer provided on an outer surface of the first semiconductor layer and within the second semiconductor opening region, and further including a plurality of insulating layers spaced apart along the X-axis direction on the back surface, the insulating layers provided on the outer surface of the second semiconductor layer, and both ends of the insulating layers extending across side edges of the second semiconductor opening region in the X-axis direction, wherein a spanning length W12 of the insulating layer in the second semiconductor opening region and a spanning length W11 of the insulating layer in the first semiconductor layer satisfy a ratio W12:W11=0.1 to 10:1.

[0009] In some preferred embodiments, the insulating layer has a length W1 in the X-axis direction of 20 to 200 μm, and a length W12 of 10 μm or more.

[0010] In some preferred embodiments, the material of the insulating layer includes at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0011] In some preferred embodiments, the back-contact battery further includes a conductive film layer disposed on the outer surface of the insulating layer, and the conductive film layer has an isolation groove formed on the outer surface of the insulating layer in the Z-axis direction.

[0012] In some preferred embodiments, the width W3 of the isolation groove in the X-axis direction is 10 to 190 μm.

[0013] In some preferred embodiments, the ratio of the length W1 of the insulating layer in the X-axis direction to the width W3 of the isolating groove is 0.3 to 10:1.

[0014] In some preferred embodiments, the isolation trench is located directly above a side edge of the second semiconductor opening region.

[0015] In some preferred embodiments, the back-contact battery further includes an insulating protective layer covering an outer surface of the insulating layer, the insulating protective layer being located between the insulating layer and the conductive film layer, and the isolation groove being located on the outer surface of the insulating protective layer in the Z-axis direction.

[0016] In some preferred embodiments, the insulating protective layer has a thickness of 5 to 30 μm.

[0017] In some preferred embodiments, the material of the insulating protective layer includes at least one of an epoxy resin, an acrylic resin, and a polyurethane resin.

[0018] In some preferred embodiments, the first semiconductor layer includes a first passivation layer and a first conductive semiconductor film layer, the first passivation layer being a tunnel oxide layer or an intrinsic silicon layer, the second semiconductor layer includes a second passivation layer and a second conductive semiconductor film layer, the second passivation layer being an intrinsic silicon layer, and one of the first conductive semiconductor film layer and the second conductive semiconductor film layer is N-type (preferably an N-type doped polycrystalline silicon layer), and the other is P-type (preferably a P-type doped amorphous or microcrystalline silicon layer).

[0019] More preferably, the first passivation layer is a tunnel oxide layer, the first conductive semiconductor film layer is a polycrystalline silicon doped layer, and the second conductive semiconductor film layer is an amorphous silicon or microcrystalline silicon doped layer.

[0020] More preferably, the first conductive semiconductor film layer is N-type, and the second conductive semiconductor film layer is P-type.

[0021] In some preferred embodiments, no mask layer is provided between the first semiconductor layer and the second semiconductor layer.

[0022] In some preferred embodiments, the front surface of the silicon substrate is a textured surface and the entire back surface of the silicon substrate is a polished surface, or alternatively, a second semiconductor opening region on the back surface is a textured surface and another region on the back surface is a polished region.

[0023] In some preferred embodiments, first semiconductor opening regions are formed in the second semiconductor layer at intervals along the X-axis direction to expose the first semiconductor layer, the first semiconductor opening regions are located between adjacent second semiconductor opening regions, and a portion of the conductive film layer is accommodated within the first semiconductor opening regions.

[0024] More preferably, in the X-axis direction, the length W4 of the first semiconductor opening region is 100 to 300 μm, the length W2 of the second semiconductor opening region is 300 to 700 μm, and the distance Wg between the first semiconductor opening region and the second semiconductor opening region is 50 to 400 μm.

[0025] More preferably, W12:W2 is 1:3-55, and W11:Wg is 1:1-10.

[0026] In some preferred embodiments, the back-contact cell further includes metal electrodes disposed on the outer surfaces of the first and second semiconductor aperture regions, respectively, a front passivation layer disposed on the front surface of the silicon substrate, and a front anti-reflection layer disposed on the outer surface of the front passivation layer.

[0027] A second aspect of the present disclosure provides a method for manufacturing the back-contact battery according to the first aspect. This manufacturing method includes the steps of: providing a silicon substrate having a first semiconductor layer, a second semiconductor layer, and an insulating film formed on its back surface in this order along the Z-axis direction; opening second semiconductor opening regions in the first semiconductor layer at intervals to accommodate portions of the second semiconductor layer; applying a protective ink to a portion of the outer surface of the insulating film on the back surface obtained in step S101, so that the protective ink covers the outer surface of the portion of the insulating film to be left, and setting the size of the protective ink according to the insulating layer to be formed; and removing the portion of the insulating film not covered by the protective ink from the back surface obtained in step S102, and forming an insulating layer using the portion of the insulating film to be left.

[0028] In some preferred embodiments, step S103 further includes removing the protective ink after removing the insulating film from the portion not covered by the protective ink.

[0029] In some other preferred embodiments, the protective ink is an insulating protective layer in step S102, and the protective ink is not removed in step S103.

[0030] In some preferred embodiments, the manufacturing method includes step S104 of depositing a conductive film layer on the back surface obtained in step S103, and step S105 of opening a separation tank in the conductive film layer on the back surface obtained in step S104.

[0031] More preferably, the method of opening the separation reservoir comprises laser etching, printing, or inkjet printing a protective ink followed by etching.

[0032] In some preferred embodiments, step S101 further includes forming a front passivation layer and a front anti-reflection layer on the front side of the silicon substrate, and forming a first semiconductor aperture region in the second semiconductor layer.

[0033] More preferably, the manufacturing method further includes step S106 of providing metal electrodes on the outer surface of the first semiconductor opening region and the outer surface of the second semiconductor opening region on the back surface obtained in step S105.

[0034] In a third aspect of the present disclosure, there is provided a photovoltaic assembly including a back-contact cell according to the first aspect.

[0035] Beneficial effects

[0036] The present disclosure provides an insulating layer on the outer surface of the second semiconductor layer, with the insulating layer spanning the side edges of the second semiconductor opening region in the X-axis direction, with both ends extending at the appropriate rate. This significantly reduces leakage current and avoids short circuits without the need for a mask layer, thereby increasing the battery's parallel resistance and improving battery conversion efficiency and battery pass rate. Compared to CN115588698A, in which the first insulating layer is located within the gap at the side edges of the second semiconductor opening region, with a portion of the insulating layer directly contacting the silicon substrate, the present disclosure provides an insulating layer that is completely located on the outer surface of the second semiconductor layer and covers its outer surface at an appropriate length. This insulating layer is independent of the two semiconductor layers, is not doped, and does not simultaneously contact the first and second semiconductor layers, thereby not weakening the passivation effect of the dual semiconductor layer. This eliminates the need to consider passivation and achieve both passivation and insulation. Furthermore, the insulating effect is better, the passivation effect can be improved without the need for a mask layer, and the manufacturing process is simple.

[0037] Preferably, the applicant's prior application relates to a back-contact battery and its manufacturing method, in which a specially formed separation groove is located above the contact boundary between the first and second semiconductor layers in the Z-axis direction, spanning the textured and polished surfaces, with no protection by a mask layer between the separation groove and the second semiconductor layer. Laser etching of the textured surface would significantly damage the underlying second semiconductor layer, so the only way to ensure battery reliability is to use a mask etching method. In contrast, in a preferred embodiment of the present disclosure, the separation groove is located on the outer surface of the insulating layer in the Z-axis direction, and the insulating layer (or the insulating layer and the insulating protective layer) serves as a mask layer for forming the separation groove, with the entire separation groove being located on the outer surface of the polished region or the insulating protective layer. This allows for openings in the polished region or the insulating protective layer, enabling laser isolation without damaging the second semiconductor layer. Furthermore, the process is simplified, further contributing to improved battery reliability. Furthermore, the insulating layer of the present disclosure can be made of at least one of silicon nitride, silicon oxynitride, and silicon oxide, which significantly improves waterproofing compared to the applicant's previous application (in which the insulating layer printed or sprayed inside the separator is made of a polymer material), resulting in higher battery reliability. [Brief explanation of the drawings]

[0038] In order to more clearly explain the technical solutions of the embodiments of the present application, the following will briefly explain the drawings necessary for describing the embodiments. The following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope. It should be understood that those skilled in the art can obtain other related drawings based on these drawings without using inventive ability.

[0039] [Figure 1] 1 is a schematic diagram of a battery structure in which a front film layer, a first semiconductor layer on the back surface, a second semiconductor layer, and an insulating film are formed according to Example 1 of the present disclosure. [Figure 2] FIG. 10 is a structural schematic diagram of a silicon substrate in Example 1 of the present disclosure when a protective ink is formed on the rear surface of the silicon substrate. [Figure 3] FIG. 2 is a structural schematic diagram of the protective ink outer insulating film in Example 1 of the present disclosure after etching. [Figure 4] FIG. 10 is a structural schematic diagram of Example 1 of the present disclosure after the protective ink has been removed and the device has been cleaned. [Figure 5] FIG. 1 is a structural schematic diagram showing a conductive film layer deposited on the back surface in Example 1 of the present disclosure. [Figure 6] FIG. 10 is a structural schematic diagram of a case where an isolation groove is formed directly above an insulating film on the rear surface in Example 1 of the present disclosure. [Figure 7] FIG. 1 is a structural schematic diagram of a case where a metal electrode is formed on the back surface of Example 1 of the present disclosure. [Figure 8] FIG. 10 is a structural schematic diagram showing a conductive film layer deposited on the rear surface in Example 3 of the present disclosure. [Figure 9] FIG. 11 is a structural schematic diagram of a case where an isolation groove is formed directly above insulating ink on the back surface in Example 3 of the present disclosure. [Figure 10] FIG. 10 is a structural schematic diagram of a case where a metal electrode is formed on the back surface in Example 3 of the present disclosure. [Figure 11] FIG. 2 is a schematic diagram of a battery structure of Comparative Example 1. DETAILED DESCRIPTION OF THE INVENTION

[0040] In the description of this disclosure, the direction toward the silicon substrate is referred to as the inward direction, and the direction away from the silicon substrate is referred to as the outward direction. Additionally, the terms "first" and "second" are for descriptive purposes only and do not express or imply relative importance or the number of technical features. Thus, a feature qualified by "first" or "second" may expressly or imply the inclusion of one or more of the feature. In the description of this application, unless specifically limited otherwise, "plurality" means two or more.

[0041] In this application, unless otherwise clearly specified or limited, a first feature being located "above" or "below" a second feature may mean that the first and second features are in direct contact with each other, or that the first and second features are in indirect contact with each other via an intermediate object. Furthermore, a first feature being located "above" a second feature may mean that the first feature is located directly above or diagonally above the second feature, or may simply mean that the horizontal height of the first feature is higher than the horizontal height of the second feature. A first feature being located "below" a second feature may mean that the first feature is located directly below or diagonally below the second feature, or may simply mean that the horizontal height of the first feature is smaller than the horizontal height of the second feature.

[0042] The endpoints of ranges and any value disclosed herein should be understood not to be limited to that exact range or value, but to include values ​​close to those ranges or values. For numerical ranges, the endpoints of each range, the endpoints of each range and individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, and these numerical ranges should be considered to be specifically disclosed herein. Here, the terms "preferably" and "optionally" mean either inclusive or exclusive (or may or may not be present).

[0043] A first aspect of the present disclosure provides a back-contact battery as follows. The back-contact battery includes a silicon substrate having a front surface and a back surface, a first semiconductor layer provided on the back surface and having a second semiconductor opening region, and a second semiconductor layer provided on the outer surface of the first semiconductor layer and within the second semiconductor opening region. The back-contact battery further includes a plurality of insulating layers arranged at intervals along the X-axis direction on the back surface, the insulating layers being provided on the outer surface of the second semiconductor layer. In the X-axis direction, both ends of the insulating layer extend across side edges of the second semiconductor opening region, and when the spanning length of the insulating layer in the second semiconductor opening region is defined as W12 and the spanning length of the insulating layer in the first semiconductor layer is defined as W11, the ratio W12:W11=0.1 to 10:1 is satisfied. For example, it may be 0.1:1, 0.5:1, 1:1, 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1, and is preferably 1 to 5:1.

[0044] In the back-contact type battery of the present disclosure, by providing an insulating layer with the above-mentioned specific spanning length ratio, it is possible to significantly improve leakage current and avoid short circuits without the need for a mask layer, thereby increasing the parallel resistance of the battery and improving the battery conversion efficiency and battery pass rate.On the other hand, under the same conditions, if W12:W11 is too large or too small, the edge of the insulating layer will be too close to the side edge of the second semiconductor opening region, resulting in poor insulation effect and affecting the battery pass rate and battery conversion efficiency.

[0045] In some preferred embodiments, the length W1 of the insulating layer in the X-axis direction is 20 to 200 μm.

[0046] More preferably, W12≧10 μm. In this preferred embodiment, the covering width of the insulating layer exceeds the side edge of the second semiconductor opening region by 10 μm or more. This is advantageous in improving leakage current, preventing short circuits, and improving the parallel resistance and battery conversion efficiency of the battery.

[0047] In some preferred embodiments, the insulating layer is made of at least one of silicon nitride, silicon oxynitride, and silicon oxide, which is advantageous in that it has better waterproofing properties, improves the reliability of the battery, and increases the pass rate and conversion efficiency of the battery.

[0048] In some preferred embodiments, the back-contact battery further includes a conductive film layer disposed on an outer surface of the insulating layer, the conductive film layer having an isolation groove located on the outer surface of the insulating layer in the Z-axis direction.

[0049] In some preferred embodiments, the width W3 of the isolation groove in the X-axis direction is 10 to 190 μm, preferably 50 to 190 μm. The isolation groove of the present disclosure mainly serves to insulate the first semiconductor layer from the conductive film layer on the surface of the second semiconductor layer. By keeping W3 within an appropriate range, short circuits can be minimized to improve the pass rate of the battery, and the transport length of carriers on the conductive film layer can be increased to improve battery efficiency.

[0050] Those skilled in the art can select the thickness of the insulating layer according to actual needs, for example, the thickness of the insulating layer may be 30 to 100 nm.

[0051] In some preferred embodiments, the ratio of the length W1 of the insulating layer in the X-axis direction to the width W3 of the isolating groove is 0.3 to 10:1.

[0052] More preferably, the ratio of the length W1 of the insulating layer in the X-axis direction to the width W3 of the isolation groove is 1.1 to 10:1, and even more preferably 1.1 to 6:1. In this preferred embodiment, the width W1 is greater than the width of the isolation groove, and the isolation groove does not extend beyond the area of ​​W1, so that the isolation groove W3 is completely formed on the upper surface of the insulating layer. In this way, the area below the isolation groove is protected by the insulating layer, improving the reliability of the battery. This avoids the lack of protection of the mask layer from the semiconductor layer due to the presence of the isolation groove.

[0053] The isolation groove of the present disclosure only needs to satisfy the requirement that it does not exceed the area of ​​W1. In some preferred embodiments, the isolation groove is located directly above the side edge of the second semiconductor opening region to further improve the reliability of the battery.

[0054] In some preferred embodiments, the back-contact battery further includes an insulating protective layer covering an outer surface of the insulating layer, the insulating protective layer being located between the insulating layer and the conductive film layer, and the isolation groove being located on the outer surface of the insulating protective layer in the Z-axis direction.

[0055] In the present disclosure, the insulating protective layer preferably has a thickness of 5 to 30 μm.

[0056] In some preferred embodiments, the material of the insulating protective layer includes at least one of epoxy resin, acrylic resin, and polyurethane resin, which cannot be washed or removed with hot water or acid-alkali solution.

[0057] The conductive film layer of the present disclosure may be, for example, a transparent conductive film layer or a composite layer of a transparent conductive film and a metal film. The transparent conductive film layer is a thin film based on indium oxide, such as tin-doped, zinc-doped, tungsten-doped, or titanium-doped, and the metal film is a thin film of one or more of gold, silver, copper, aluminum, nickel, or a nickel alloy. Those skilled in the art can select the appropriate film layer according to their needs.

[0058] In some preferred embodiments, the first semiconductor layer includes a first passivation layer and a first conductive semiconductor film layer, and the first passivation layer is a tunnel oxide layer or an intrinsic silicon layer. The second semiconductor layer includes a second passivation layer and a second conductive semiconductor film layer, and the second passivation layer is an intrinsic silicon layer. One of the first conductive semiconductor film layer and the second conductive semiconductor film layer is N-type, and the other is P-type.

[0059] The first passivation layer may be an intrinsic silicon layer, for example, intrinsic amorphous silicon. In this case, the back-contact battery of the present disclosure is a conventional heterojunction battery, and the first conductive semiconductor film layer and the second conductive semiconductor film layer are doped amorphous silicon or microcrystalline silicon layers, respectively. In some specific embodiments of the conventional heterojunction battery structure, the thickness of the intrinsic silicon layer is, for example, 5 to 10 nm. The thickness of the first conductive semiconductor film layer is 10 to 15 nm, and the doping concentration is 8e18 to 8e20 cm. -3 The thickness of the second passivation layer is 5 to 15 nm, the thickness of the second conductive semiconductor film layer is 5 to 25 nm, and the doping concentration is 8e18 to 8e20 cm -3 is.

[0060] More preferably, the first passivation layer is a tunnel oxide layer, the first conductive semiconductor film layer is a layer doped with polycrystalline silicon, and the second conductive semiconductor film layer is a layer doped with amorphous silicon or microcrystalline silicon.

[0061] Those skilled in the art can select the thickness of the first passivation layer, the thickness of the first conductive semiconductor film layer, the thickness of the second conductive semiconductor film layer, the thickness of the second passivation layer, and the doping concentration of the first conductive semiconductor film layer and the doping concentration of the second conductive semiconductor film layer according to actual needs. For example, the thicknesses and doping concentrations of the corresponding layers disclosed in the applicant's previous applications of the present disclosure or other common ranges can be adopted. In some specific embodiments of back-contact type batteries with a composite passivation structure, the thickness of the first passivation layer is 0.5 to 5 nm, and the doping concentration of the first conductive semiconductor film layer is 8x18 to 8x20 cm. -3 and the thickness is 100-200 nm, the thickness of the second passivation layer is 5-15 nm, the thickness of the second conductive semiconductor film layer is 5-25 nm, and the doping concentration is 8e18-8e20 cm -3 is.

[0062] More preferably, the first conductive semiconductor film layer is N-type and the second conductive semiconductor film layer is P-type. In this preferred solution, the bottom of the gap Wg between the first semiconductor opening region and the second semiconductor opening region is an N-type semiconductor, which has better passivation effect and conductivity than a P-type semiconductor, thereby improving the passivation effect of the battery and reducing the electrical loss of carrier transport, which is more advantageous for improving the conversion efficiency of the battery.

[0063] In some preferred embodiments, no mask layer is provided between the first semiconductor layer and the second semiconductor layer.

[0064] In this disclosure, those skilled in the art can choose to polish or texture the front and back surfaces of the silicon substrate, respectively, depending on the light reflectance of the front and back surfaces, and the effect on conversion efficiency or the effect on the manufacturing process. In some preferred embodiments, the front surface of the silicon substrate is textured and the back surface of the silicon substrate is polished, or the second semiconductor opening region on the back surface is textured and the other regions on the back surface are polished. This can significantly reduce light reflection and improve cell conversion efficiency.

[0065] In some preferred embodiments, the second semiconductor layer has first semiconductor opening regions spaced apart along the X-axis direction to expose the first semiconductor layer, the first semiconductor opening regions are located between adjacent second semiconductor opening regions, and a portion of the conductive film layer is accommodated within the first semiconductor opening regions.

[0066] More preferably, in the X-axis direction, the length W4 of the first semiconductor opening region is 100 to 300 μm, the length W2 of the second semiconductor opening region is 300 to 700 μm, and the distance Wg between the first semiconductor opening region and the second semiconductor opening region is 50 to 400 μm.

[0067] More preferably, W12 / W2 is 1:3-55, and W11 / Wg is 1:1-10.

[0068] More preferably, W12 / W2 is 1:3 to 35, more preferably 1:9 to 25, and W11 / Wg is 1:1 to 10, more preferably 1:1 to 5. In this preferred solution, the insulating layer-covered region is located at a certain appropriate safe distance from the side edge of the second semiconductor opening region, thereby increasing the carrier transport distance in the conductive film layer and appropriately reducing the carrier transport distance in the semiconductor layer. Since the resistivity of the semiconductor layer is higher than that of the conductive film layer, carrier transport loss can be significantly reduced. Furthermore, since the isolation grooves are completely formed in the insulating layer-covered region by etching, the requirement for alignment accuracy is relatively low, which is advantageous for efficient mass production. This contributes to improving the pass rate and conversion efficiency of batteries.

[0069] In some preferred embodiments, the back-contact cell further includes metal electrodes disposed on the outer surface of the first semiconductor aperture region and the outer surface of the second semiconductor aperture region, respectively.

[0070] In some preferred embodiments, the back-contact cell further comprises a front passivation layer disposed on the front side of the silicon substrate.

[0071] More preferably, the front passivation layer is a silicon medium passivation layer, which is a tunnel silicon oxide layer and a polycrystalline silicon layer, or an intrinsic amorphous silicon layer and an N-type doped amorphous / microcrystalline silicon layer.

[0072] In some preferred embodiments, the back-contact cell further comprises a front anti-reflective layer disposed on the outer surface of the front passivation layer.

[0073] More preferably, the front anti-reflection layer is a silicon media anti-reflection layer. Those skilled in the art can use any conventional material in the prior art to form the silicon media anti-reflection layer, and the description thereof is omitted here.

[0074] In a second aspect of the present disclosure, there is provided a method for manufacturing the back-contact battery according to the first aspect, the method comprising the steps of:

[0075] S101: A silicon substrate is provided having a first semiconductor layer, a second semiconductor layer, and an insulating film formed on the back surface thereof in this order along the Z-axis direction, and second semiconductor opening regions are formed in the first semiconductor layer at intervals to accommodate portions of the second semiconductor layer.

[0076] S102: A protective ink is applied to a portion of the outer surface of the insulating film on the back surface obtained in S101, and the protective ink covers the outer surface of the portion of the insulating film that is to be left behind, and the size of the protective ink is set according to the insulating layer to be formed.

[0077] S103: On the back surface obtained in S102, the insulating film in the portion not covered with the protective ink is removed, and the remaining insulating film forms an insulating layer.

[0078] In S103, the insulating film is removed from the portions not covered with the protective ink. The insulating film is removed using, for example, an etching solution. The etching solution is, for example, a solution containing HF (HF mass concentration, for example, 1 wt % to 10 wt %).

[0079] In some preferred embodiments, step S103 further includes removing the protective ink after removing the insulating film from the portion not covered by the protective ink. In this embodiment, the protective ink may be, for example, hot melt wax or other resin that can be removed and washed with alkaline. The protective ink may be removed using, for example, hot water or a weak alkaline solution, as long as it can be removed cleanly.

[0080] In some preferred embodiments, the protective ink in S102 is an insulating protective layer, and the protective ink is not removed in S103.

[0081] In some preferred embodiments, the manufacturing method further comprises the following steps:

[0082] S104: A conductive film layer is deposited on the back surface obtained in S103.

[0083] S105: A separation tank is opened on the backside conductive film layer obtained in S104.

[0084] In S104, the deposition method of the conductive film layer may be, for example, physical vapor deposition (PVD) or reactive plasma deposition (RPD).

[0085] More preferably, the method for opening the separation tank can be laser etching, printing, or inkjet printing a protective ink followed by etching. The laser etching method is more preferred because it is a simpler process.

[0086] In a preferred embodiment of the present disclosure, the separation pits are located on the outer surface of the insulating layer in the Z-axis direction, and the insulating layer (or the insulating layer and the insulating protective layer) can be used as a mask layer to form the separation pits. Furthermore, since the entire separation pits are located on the outer surface of the polished area or the insulating protective layer, openings can be formed in the polished area or the insulating protective layer, and laser isolation can be used without damaging the second semiconductor layer. This simplifies the process and contributes to improving the reliability of the battery.

[0087] In some preferred embodiments, S101 further includes forming a front passivation layer and a front anti-reflection layer on the front side of the silicon substrate, and forming a first semiconductor aperture region in the second semiconductor layer.

[0088] More preferably, the manufacturing method further includes step S106 of providing metal electrodes on the outer surface of the first semiconductor opening region and the outer surface of the second semiconductor opening region on the back surface obtained in S105.

[0089] The metal electrodes are formed by printing silver paste to form silver paste grid line electrodes, and then electroplating to form copper grid line electrodes.

[0090] In a third aspect of the present disclosure, there is provided a photovoltaic assembly including a back-contact cell according to the first aspect.

[0091] The following detailed description of the embodiments of the present application is given with reference to the drawings, and the embodiments are illustrated by the drawings, and the same or similar elements or elements having the same or similar functions are represented by the same or similar reference numerals in all the drawings. The following embodiments described with reference to the drawings are illustrative and are only for explaining the present invention, but are not intended to limit the present invention.

[0092] Example 1

[0093] The back-contact type battery is manufactured as follows.

[0094] S101: As shown in Figure 1, a silicon substrate 1 was provided with a first semiconductor layer, a second semiconductor layer, and an insulating film 6 (silicon nitride) formed on the backside. The first semiconductor layer consisted of a first passivation layer 2 (tunnel oxide layer, thickness 1.5 nm) and a first conductive semiconductor film layer 3 (N-type polycrystalline layer, doping concentration 8e20 cm3). -3 The second semiconductor layer is a second passivation layer 4 (intrinsic amorphous silicon layer, thickness 10 nm), a second conductive semiconductor film layer 5 (P-type doped amorphous silicon layer, thickness 20 nm, doping concentration 8e19 cm -3) A cell structure of a front film layer 7 is formed on the front surface of the silicon substrate 1. The front film layer 7 includes a silicon medium passivation layer and a silicon medium anti-reflection layer. A second semiconductor opening region is opened in the first conductive semiconductor film layer 3, and the width W2 of the second semiconductor opening region is 500 μm. The silicon substrate surface located in the horizontal region 101 of the second semiconductor opening region is a polished surface. A first semiconductor opening region is opened in the second semiconductor layer to expose the first semiconductor layer. The length W4 of the first semiconductor opening region is 200 μm. The distance Wg between the first semiconductor opening region and the second semiconductor opening region is 100 μm.

[0095] S102: As shown in Figure 2, protective ink 8 (hot melt wax) was inkjet printed on the outer surface directly above the side edge 102 of the second semiconductor opening region on the back surface of silicon substrate 1. The protective ink 8 spans the side edge 102 of the second semiconductor opening region, and the width W1 of the protective ink 8 is 100 μm. The length W12 of the protective ink 8 spanning above the second semiconductor opening region is 10 μm or more, the length W11 of the protective ink 8 spanning over the first semiconductor layer is 10 μm or more, and W12:W11 = 1:1. W12:W2 is 1:10, and W11:Wg is 1:2.

[0096] S103: As shown in Fig. 3, the insulating film 6 on the outside of the protective ink 8 was etched using a solution with a concentration of 5 wt% HF to form an insulating layer. Also, as shown in Fig. 4, the protective ink 8 was removed and washed with hot water.

[0097] S104: As shown in FIG. 5, a conductive film layer 9 is deposited on the rear surface of the silicon substrate 1 by physical vapor deposition (PVD), and the conductive film layer 9 is a transparent conductive film layer, and the transparent conductive film layer is a tin-doped indium oxide film.

[0098] S105: As shown in Figure 6, an isolation trench was formed directly above the insulating film 6 on the back surface of the silicon substrate 1. The width W3 of the isolation trench was 50 μm, and the isolation trench was directly etched using a laser. The ratio of W1 to the width of the isolation trench was 2:1.

[0099] In S106, a metal electrode 10 was formed on the back surface of the silicon substrate 1, as shown in FIG.

[0100] The test results of the parallel resistance, the battery pass rate, and the battery conversion efficiency of the back-contact type battery of this example are shown in Table 1 below.

[0101] Example 2

[0102] Example 2 was carried out by following the method of Example 1. The difference is that the P / N types of the two semiconductor layers are different, specifically, the first conductive semiconductor film layer 3 is a P-type polycrystalline silicon layer, and the second conductive semiconductor film layer 5 is an N-type doped amorphous silicon layer. Corresponding tests were carried out, and the results are shown in Table 1.

[0103] Example 3

[0104] Example 3 was carried out with reference to the method of Example 1. The difference is that the protective ink 8 is an insulating ink and is not removed afterwards. Specifically, it includes the following steps:

[0105] S102: The printed protective ink 8 is an insulating ink (i.e., an insulating protective layer) made of epoxy resin, and cannot be washed or removed with hot water or acid / alkali solutions. The thickness of the insulating ink is 10 μm.

[0106] S103: As shown in FIG. 3, the insulating film 6 outside the insulating ink was etched with a solution containing HF.

[0107] S104: As shown in FIG. 8, a conductive film layer 9 was deposited on the rear surface of the silicon substrate 1 by physical vapor deposition (PVD).

[0108] S105: As shown in FIG. 9, an isolation groove was formed on the rear surface of the silicon substrate 1 directly above the insulating ink.

[0109] S106: As shown in FIG. 10, a metal electrode 10 was formed on the back surface of the silicon substrate 1.

[0110] The corresponding tests were carried out and the results are shown in Table 1.

[0111] Example 4

[0112] Example 4 was carried out by following the method of Example 1. The differences are that W12:W11 is the same as in Example 1, W1 is changed to 30 μm, and by calculation, the ratio of W1 to the width W3 of the separation tank is 0.6:1, W12:W2 is 1:33, and W11:Wg is 1:6.7.

[0113] The corresponding tests were carried out and the results are shown in Table 1.

[0114] Example 5 Example 5 was carried out by referring to the method of Example 1. The difference is that W1 was the same as in Example 1, but W12:W11 was changed to 9:1, and by calculation, W12:W2 was 1:5.6, and W11:Wg was 1:10.

[0115] The corresponding tests were carried out and the results are shown in Table 1.

[0116] Example 6 Example 6 was carried out by following the method of Example 1. The difference is that W1 was the same as in Example 1, but W12:W11 was changed to 0.1:1, and by calculation, W12:W2 was 1:55, and W11:Wg was 1:1.1.

[0117] The corresponding tests were carried out and the results are shown in Table 1.

[0118] Example 7 Example 7 was carried out with reference to the method of Example 1. The difference is that the width of the separation tank was changed so that the ratio of the length W1 of the insulating layer in the X-axis direction to the width W3 of the separation tank was 10:1.

[0119] The corresponding tests were carried out and the results are shown in Table 1.

[0120] Example 8

[0121] Example 8 was carried out using the method of Example 1. The difference is that a conventional heterojunction passivation structure is used. Specifically, the first passivation layer is an intrinsic amorphous silicon layer with a thickness of 10 nm, and the first conductive semiconductor layer is an N-type microcrystalline silicon layer with a thickness of 10 nm, with the same doping concentration as Example 1.

[0122] The corresponding tests were carried out and the results are shown in Table 1.

[0123] Comparative Example 1

[0124] Comparative Example 1 was carried out with reference to the method of Example 1. The difference is that a composite passivation cell structure without an insulating film 6 is adopted, and a mask layer 11 is further deposited in the gap Wg between the first semiconductor opening region and the second semiconductor opening region, as shown in Figure 11, the mask layer 11 is located between the first semiconductor layer and the second semiconductor layer, and the insulating groove is located above the outer surface of the mask layer 11 and away from the side edge 102 of the second semiconductor opening region.

[0125] The corresponding tests were carried out and the results are shown in Table 1.

[0126] Comparative Example 2

[0127] Comparative Example 2 was carried out by referring to the method of Example 1. The difference is that W1 was the same as in Example 1, but W12:W11 was changed to 20:1, and by calculation, W12:W2 was 1:5.3, and W11:Wg was 1:21.

[0128] The corresponding tests were carried out and the results are shown in Table 1.

[0129] Comparative Example 3

[0130] Comparative Example 3 was carried out by referring to the method of Example 1. The difference is that W1 was the same as in Example 1, but W12:W11 was changed to 0.05:1, and by calculation, W12:W2 was 1:105, and W11:Wg was 1:1.1.

[0131] The corresponding tests were carried out and the results are shown in Table 1.

[0132] Comparative Example 4

[0133] Comparative Example 4 was carried out with reference to the method of Example 8. The difference is that a normal heterojunction passivation cell structure without an insulating film 6 is adopted, a mask layer 11 is further deposited within the gap Wg between the first semiconductor opening region and the second semiconductor opening region, the mask layer 11 is located between the first semiconductor layer and the second semiconductor layer, and an insulating groove is provided above the outer surface of the mask layer 11 and away from the side edge 102 of the second semiconductor opening region.

[0134] The corresponding tests were carried out and the results are shown in Table 1. TIFF0007809248000001.tif136170

[0135] As can be seen from the above examples and comparative examples, by adopting the examples of the present disclosure, the leakage phenomenon can be significantly improved without providing a mask layer, and at the same time, the passivation effect is not affected, so the parallel resistance of the battery can be increased, and the battery conversion efficiency and pass rate can be further improved. Comparative Example 1, which has a conventional structure, and Comparative Examples 2 to 4, which are outside the scope of the present disclosure, all failed to achieve the overall effect of the present disclosure.

[0136] Preferably, as can be seen from Examples 1 and 2 of the present disclosure, the first semiconductor layer is an N-type semiconductor layer and the second semiconductor layer is a P-type semiconductor layer, which contributes to improving battery conversion efficiency. As can be seen from Examples 1 and 3 of the present disclosure, removing the insulating ink on the top surface of the insulating layer contributes to improving the pass rate of battery production. As can be seen from Examples 1 and 4 to 7 of the present disclosure, providing an insulating layer of appropriate width and an isolation groove of appropriate width on both outer surfaces of the side edges of the second semiconductor opening region contributes to improving the parallel resistance of the battery, the pass rate of the battery, and the conversion efficiency. As can be seen from Examples 1 and 8 of the present disclosure, adopting a composite passivation structure contributes to improving the pass rate of battery production and the conversion efficiency, compared to a conventional heterojunction structure.

[0137] Although the preferred embodiments of the present disclosure have been described in detail above, the present disclosure is not limited thereto, and various simple modifications can be made to the technical solutions of the present disclosure within the scope of the technical concept of the present disclosure, including the combination of each technical feature in any other suitable manner, and these simple modifications and combinations should also be considered as the disclosure content of the present disclosure, and all fall within the protection scope of the present disclosure.

[0138] Industrial Applicability

[0139] In the back-contact battery of the present disclosure, an insulating layer is provided on the outer surface of the second semiconductor layer, and in the X-axis direction, the insulating layer spans the side edges of the second semiconductor opening region, with both ends extending at the above-mentioned appropriate ratio. This eliminates the need for a mask layer, thereby significantly improving leakage current and avoiding short circuits, thereby increasing the parallel resistance of the battery and further improving the battery conversion efficiency and battery pass rate. [Explanation of symbols]

[0140] 1...Silicon substrate 2...First passivation layer 3...First conductive semiconductor film layer 4...Second passivation layer 5...Second conductive semiconductor film layer 6...Insulating film 7…Front membrane layer 8...Protective ink 9...Conductive film layer 10...Metal electrode 11...Mask layer 101... horizontal region of second semiconductor opening region 102...side edge of second semiconductor opening region

Claims

1. 1. A back-contact cell comprising: a silicon substrate having a front surface and a back surface; a first semiconductor layer disposed on the back surface and having a second semiconductor opening region; and a second semiconductor layer disposed on an outer surface of the first semiconductor layer and within the second semiconductor opening region; Further comprising a plurality of insulating layers arranged at intervals along the X-axis direction on the rear surface; the insulating layer is provided on an outer surface of the second semiconductor layer, and both ends of the insulating layer extend across side edges of the second semiconductor opening region in the X-axis direction; a spanning length W12 of the insulating layer in the second semiconductor opening region and a spanning length W11 of the insulating layer in the first semiconductor layer satisfy a relationship W12:W11=0.1 to 10:1; The length W1 of the insulating layer in the X-axis direction is 20 to 200 μm, and W12 is 10 μm or more, a conductive film layer provided on an outer surface of the insulating layer; an insulating protective layer covering an outer surface of the insulating layer; The insulating protection layer is located between the insulating layer and the conductive film layer. The conductive film layer has an isolation groove formed on an outer surface of the insulating layer in the Z-axis direction. A back-contact battery characterized by:

2. the material of the insulating layer includes at least one of silicon nitride, silicon oxynitride, and silicon oxide; 2. The back-contact battery of claim 1.

3. the width W3 of the isolation trench in the X-axis direction is 10 to 190 μm, and the ratio of the length W1 of the insulating layer in the X-axis direction to the width W3 of the isolation trench is 0.3 to 10:1; and / or the isolation trench is located directly above a side edge of the second semiconductor opening region; 2. The back-contact battery of claim 1.

4. The insulating protection layer has a thickness of 5 to 30 μm, and / or the material of the insulating protection layer includes at least one of an epoxy resin, an acrylic resin, and a polyurethane resin.

2. The back-contact battery of claim 1.

5. The first semiconductor layer includes a first passivation layer and a first conductive semiconductor film layer, and the first passivation layer is a tunnel oxide layer or an intrinsic silicon layer; the second semiconductor layer includes a second passivation layer and a second conductive semiconductor film layer, the second passivation layer being an intrinsic silicon layer; one of the first conductive semiconductor film layer and the second conductive semiconductor film layer is N-type, and the other is P-type; 2. The back-contact battery of claim 1.

6. the first passivation layer is a tunnel oxide layer, the first conductive semiconductor film layer is a polycrystalline silicon doped layer, and the second conductive semiconductor film layer is an amorphous silicon or microcrystalline silicon doped layer; 6. The back-contact battery of claim 5.

7. The first conductive semiconductor film layer is N-type, and the second conductive semiconductor film layer is P-type.

7. The back-contact battery of claim 6.

8. No mask layer is provided between the first semiconductor layer and the second semiconductor layer, and / or the front surface of the silicon substrate is a textured surface and the entire back surface of the silicon substrate is a polished surface, or the second semiconductor opening region of the back surface is a textured surface and another region of the back surface is a polished region; 2. The back-contact battery of claim 1.

9. First semiconductor opening regions are opened in the second semiconductor layer at intervals along the X-axis direction so as to expose the first semiconductor layer, the first semiconductor opening regions are located between adjacent second semiconductor opening regions, and a portion of the conductive film layer is accommodated in the first semiconductor opening regions; In the X-axis direction, the length W4 of the first semiconductor opening region is 100 to 300 μm, the length W2 of the second semiconductor opening region is 300 to 700 μm, and the interval Wg between the first semiconductor opening region and the second semiconductor opening region is 50 to 400 μm; and / or W12:W2 is 1:3-55, and W11:Wg is 1:1-10.

2. The back-contact battery of claim 1.

10. a metal electrode provided on an outer surface of the first semiconductor opening region and an outer surface of the second semiconductor opening region; a front passivation layer disposed on the front side of the silicon substrate; a front anti-reflective layer disposed on the outer surface of the front passivation layer.

10. The back-contact battery of claim 9.

11. A method for producing the back-contact battery according to any one of claims 1 to 10, comprising: Step S101: providing a silicon substrate having a first semiconductor layer, a second semiconductor layer, and an insulating film formed on a back surface thereof in this order along a Z-axis direction; and opening a second semiconductor opening region in the first semiconductor layer at an interval to accommodate a portion of the second semiconductor layer; Step S102: providing a protective ink as an insulating protective layer on a part of the outer surface of the insulating film on the back surface obtained in step S101, so that the protective ink covers the outer surface of the part of the insulating film to be left, and setting the size of the protective ink according to the insulating layer to be formed; Step S103: removing the insulating film from the back surface obtained in step S102 in a portion not covered with the protective ink, and forming an insulating layer using the remaining insulating film; Step S104: depositing a conductive film layer on the back surface obtained in step S103; Step S105 includes opening a separation hole in the backside conductive film layer obtained in step S104, and the method for opening the separation hole includes laser etching, printing, or inkjet printing a protective ink and then etching; A method for manufacturing a back-contact type battery.

12. Step S101 further includes forming a front passivation layer and a front anti-reflection layer on the front surface of the silicon substrate, and forming a first semiconductor opening region in the second semiconductor layer, and the manufacturing method further includes step S106 of providing metal electrodes on the outer surface of the first semiconductor opening region and the outer surface of the second semiconductor opening region on the back surface obtained in step S105, respectively. The method of claim 11 .

13. A photovoltaic assembly comprising a back-contact cell according to any one of claims 1 to 10.

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