Nitride semiconductor device manufacturing method and nitride semiconductor device

Abstract

To provide a method for manufacturing a nitride semiconductor device and a nitride semiconductor device capable of reducing the GaOx layer and suppressing Ga diffusion from the GaOx layer into the insulating film.SOLUTION: A method for manufacturing a nitride semiconductor device includes the following processes: forming an oxide thin film on the surface of a gallium nitride layer by a plasma CVD, thermal CVD, or thermal sputtering method; irradiating the oxide thin film and the interface area between the oxide thin film and the gallium nitride layer with plasma in an atmosphere containing nitrogen to dope the oxide thin film and the interface area with nitrogen; and forming an insulating film on the nitrogen-doped oxide thin film.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a nitride semiconductor device and a nitride semiconductor device. [Background technology]

[0002] To realize GaN-MOSFETs with excellent electrical characteristics, it is important to suppress the fluctuation of the threshold voltage.

[0003] When forming a gate insulating film using conventional plasma CVD, oxygen gas is introduced into the equipment to generate an oxygen plasma. The oxygen plasma oxidizes the gallium nitride (GaN) surface in a short time of a few seconds, forming a GaOx layer. The GaOx layer may generate interface traps, which can reduce the mobility of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0004] Furthermore, the GaOx layer may act as a source of Ga diffusion into the gate insulating film, resulting in fixed charges in the gate insulating film, which may lead to a decrease in the threshold voltage of the MOSFET. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-143842 Summary of the Invention [Problem to be solved by the invention]

[0006] A technology that can reduce the GaOx layer and suppress Ga diffusion from the GaOx layer into the insulating film is desired.

[0007] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a nitride semiconductor device, and a nitride semiconductor device, which can reduce the GaOx layer and suppress Ga diffusion from the GaOx layer into the insulating film. [Means for solving the problem]

[0008] In order to solve the above-described problems, a method for manufacturing a nitride semiconductor device according to one aspect of the present invention includes the steps of: forming an oxide thin film on a surface of a gallium nitride layer by plasma CVD, thermal CVD, or thermal sputtering; irradiating the oxide thin film and an interface between the oxide thin film and the gallium nitride layer with plasma in an atmosphere containing nitrogen to dope the oxide thin film and the interface with nitrogen; and forming an insulating film on the nitrogen-doped oxide thin film.

[0009] A nitride semiconductor device according to one aspect of the present invention includes a gallium nitride layer, an insulating film provided on the gallium nitride layer, and a nitride layer between the gallium nitride layer and the insulating film, the nitride layer having a GaOxNy layer located closer to the gallium nitride layer and an oxynitride thin film located closer to the insulating film. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a method for manufacturing a nitride semiconductor device and a nitride semiconductor device that can reduce the GaOx layer and suppress Ga diffusion from the GaOx layer into the insulating film. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view showing a configuration example of a GaN semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view showing an example of the configuration of the GaN semiconductor device according to the first embodiment of the present invention. [Figure 3] 3A to 3C are cross-sectional views showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of steps. [Figure 4] 4A to 4C are cross-sectional views showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of steps. [Figure 5] 5A to 5C are cross-sectional views showing the manufacturing method of a GaN semiconductor device according to the second embodiment of the present invention in the order of steps. [Figure 6] 6A to 6C are cross-sectional views showing the manufacturing method of a GaN semiconductor device according to the second embodiment of the present invention in the order of steps. [Figure 7] 7A to 7C are cross-sectional views showing the manufacturing method of a GaN semiconductor device according to the third embodiment of the present invention in the order of steps. [Figure 8] 8A to 8C are cross-sectional views showing the manufacturing method of a GaN semiconductor device according to the third embodiment of the present invention in the order of steps. [Figure 9] FIG. 9 is a graph showing the relationship between the amount of nitrogen and the nitriding time due to nitrogen plasma. [Figure 10] FIG. 10 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] An embodiment of the present invention will be described below. In the following description of the drawings, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each component, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0013] In the following description, directions may be described using the terms X-axis, Y-axis, and Z-axis. For example, the X-axis or Y-axis direction is a direction parallel to the surface 12a of the GaN layer 12. The X-axis, Y-axis, or both the X-axis and Y-axis directions may be referred to as horizontal directions. The Z-axis direction is a normal direction to the surface 12a of the GaN layer 12. The Z-axis direction is also the thickness direction of the GaN layer 12. The X-axis, Y-axis, and Z-axis directions are perpendicular to each other.

[0014] In the following description, the direction of the Z-axis arrow may be referred to as "up" and the opposite direction of the Z-axis arrow may be referred to as "down." "Up" and "down" do not necessarily refer to the vertical direction relative to the ground. In other words, the "up" and "down" directions are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship of regions, layers, films, substrates, etc., and do not limit the technical concept of the present invention. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up."

[0015] In the following explanation, p and n mean that holes and electrons are the majority carriers, respectively. The + and - symbols attached to p and n mean that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without the + or - symbol. However, even if the same p and p (or n and n) are attached to semiconductor regions, this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0016] <Embodiment 1> (Configuration example) Fig. 1 is a plan view showing an example of the configuration of a GaN semiconductor device 100 according to embodiment 1 of the present invention. Fig. 2 is a cross-sectional view showing an example of the configuration of a GaN semiconductor device 100 according to embodiment 1 of the present invention. Fig. 2 shows a cross section taken along line X1-X'1 in the plan view of Fig. 1.

[0017] 1 and 2 is, for example, a power semiconductor device, and includes a gallium nitride substrate (hereinafter, referred to as GaN substrate) 10 and a plurality of vertical MOSFETs 1 provided on the GaN substrate 10. In the GaN semiconductor device 100, the vertical MOSFETs 1 are repeatedly provided in one direction (for example, the X-axis direction). One vertical MOSFET 1 is a repeated unit structure, and this unit structure is arranged side by side in one direction (for example, the X-axis direction).

[0018] The region where multiple unit structures are provided is called the active region. Although not shown, an edge termination structure that functions to prevent electric field concentration in the active region is provided around the active region. The edge termination structure may include one or more of a guard ring structure, a field plate structure, and a JTE (JunctiOn Termination ExtentSiOn) structure.

[0019] As shown in FIGS. 1 and 2, the vertical MOSFET 1 has a gate insulating film 5 provided on a GaN substrate 10, a gate electrode 6 provided on the gate insulating film 5, and a source electrode 7 and a drain electrode 8 provided on the GaN substrate 10.

[0020] GaN substrate 10 has, for example, a GaN single crystal substrate 11 and a GaN layer 12 (an example of a "gallium nitride layer" of the present invention) provided on GaN single crystal substrate 11. As shown in FIG. 2 , front surface 12a of GaN layer 12 is also front surface 10a of GaN substrate 10. A back surface 12b of GaN layer 12, located opposite front surface 12a, is in contact with GaN single crystal substrate 11. Back surface 11b of GaN single crystal substrate 11 is also back surface 10b of GaN substrate 10.

[0021] The conductivity type of the GaN single crystal substrate 11 is, for example, n+ type. The n-type dopant contained in the GaN single crystal substrate 11 is one or more elements selected from the group consisting of Si (silicon), O (oxygen), and Ge (germanium), and one example is O. The impurity concentration of O in the GaN single crystal substrate 11 is 2×10 18 / cm 3 That's all.

[0022] The GaN single crystal substrate 11 has a dislocation density of 1E+7 / cm 2 The GaN single crystal substrate 11 may be a low-dislocation freestanding substrate having a dislocation density of less than 1000 nm. When the GaN single crystal substrate 11 is a low-dislocation freestanding substrate, the dislocation density of the GaN layer 12 formed on the GaN single crystal substrate 11 is also low. Furthermore, by using a low-dislocation freestanding substrate for the GaN single crystal substrate 11, it is possible to reduce leakage current in the power device even when a large-area power device is formed on the GaN single crystal substrate 11. This allows the manufacturing equipment to manufacture power devices with a high yield rate. Furthermore, it is possible to prevent ion-implanted impurities from diffusing deeply along dislocations during heat treatment. Note that E+ is an exponential notation. For example, 1E+7 is 1×10 7 means.

[0023] GaN layer 12 is provided on GaN single crystal substrate 11. GaN layer 12 is an n-type GaN single crystal layer, and is a layer formed by epitaxial growth on GaN single crystal substrate 11. The n-type dopant (n-type impurity) contained in GaN layer 12 is one or more elements selected from Si (silicon), O (oxygen), and Ge (germanium), and one example is O.

[0024] A p-type well region 13, an n+ type source region 14, a p+ type contact region 16, and a p+ type base region 18 are provided on the surface 12a side of the GaN layer 12. A region of the GaN layer 12 that does not include the well region 13, the source region 14, the contact region 16, and the base region 18 may be called a drift region. The drift region functions as a current path between the GaN single crystal substrate 11 and the well region 13.

[0025] The well region 13 is formed by ion-implanting a p-type dopant (p-type impurity) from the surface 12a side of the GaN layer 12 and activating the p-type dopant by heat treatment. The p-type dopant is, for example, magnesium (Mg). The well region 13 faces the surface 12a of the GaN layer 12. The well region 13 has, in the horizontal direction, a first side surface adjacent to the source region 14 and a second side surface in contact with the drift region directly below the gate insulating film 5. In the well region 13, a channel of the vertical MOSFET 1 is formed between the first and second side surfaces, at and near the contact interface with the gate insulating film 5. Hereinafter, the region in the well region 13 where the channel is formed will be referred to as the channel region.

[0026] For example, the channel region is located within a range of 20 nm from the front surface 12a in contact with the gate insulating film 5 to the rear surface 12b side. The concentration of the p-type dopant (for example, Mg) in the channel region is higher than the concentration of the n-type dopant contained in the channel region, and for example, is 1E+16 / cm 3 That's all.

[0027] The source region 14 is formed by ion-implanting an n-type dopant from the surface 12a side of the GaN layer 12 and activating the n-type dopant by heat treatment. The n-type dopant is, for example, one or more elements selected from the group consisting of Si, O, and Ge. The source region 14 faces the surface 12a of the GaN layer 12 and is located inside the well region 13. The sides and bottom of the source region 14 are in contact with the well region 13. The source region 14 and the well region 13 are in contact with each other in the X-axis, Y-axis, and Z-axis directions.

[0028] The p+ type contact region 16 is formed by ion-implanting a p-type dopant from the surface 12a side of the GaN layer 12 and activating the p-type dopant by heat treatment. The p-type dopant is, for example, Mg. The contact region 16 faces the surface 12a of the GaN layer 12 and is located inside the well region 13. At least the bottom of the contact region 16 is in contact with the p+ type base region 18. In the Z-axis direction, the contact region 16 and the base region 18 are in contact with each other.

[0029] The p+ type base region 18 is formed by ion-implanting a p-type dopant from the surface 12a side of the GaN layer 12 and activating the p-type dopant by heat treatment. The p-type dopant is, for example, Mg. For example, at least a portion of the top of the base region 18 is in contact with the p- type well region 13. At least a portion of the side of the base region 18 is in contact with the well region 13. The bottom of the base region 18 is in contact with the n- type drift region.

[0030] 2, the gate insulating film 5 has an insulating film 52 provided on the GaN layer 12, and a nitride layer 51 present between the insulating film 52 and the GaN layer 12. The nitride layer 51 is in contact with a surface 12a of the GaN layer 12 including the well region 13. The insulating film 52 is located between the nitride layer 51 and the gate electrode 6, and is in contact with the surface of the nitride layer 51. The nitride layer 51 and the insulating film 52 are stacked in this order to form the gate insulating film 5.

[0031] As will be described later with reference to FIG. 4 and the like, the nitride layer 51 has a GaOxNy layer 511 located closer to the GaN layer 12 and a SiON thin film 513 (an example of an "oxynitride thin film" according to the present invention) located closer to the insulating film 52. The SiON thin film 513 contains, for example, nitrogen at a higher concentration than the insulating film 52. The GaOxNy layer 511 is, for example, a GaON layer. That is, in the GaOxNy layer 511, the values ​​of x and y are, for example, 1. However, in the embodiment of the present invention, the values ​​of x and y are not limited to 1. The thickness of the nitride layer 51 is, for example, 0.2 nm or more and 3 nm or less.

[0032] The insulating film 52 is, for example, a silicon oxide film (SiO2 film), an aluminum oxide film (Al2O3 film), an AlSiO film, or a hafnium oxide film (HfO film). The insulating film 52 may be a single-layer film or a multilayer film including one or more of a SiO2 film, an Al2O3 film, an AlSiO film, and a HfO film. The thickness of the insulating film 52 is, for example, 30 nm or more and 100 nm or less.

[0033] The gate electrode 6 is provided on the gate insulating film 5. The gate electrode 6 is a planar electrode provided on the flat gate insulating film 5. The gate electrode 6 is made of, for example, Al or an Al-Si alloy. Alternatively, the gate electrode 6 may be made of polysilicon doped with impurities.

[0034] The source electrode 7 is provided continuously from above the n+ type source region 14 to above the p+ type contact region 16, and is electrically connected to both the source region 14 and the contact region 16. Although not shown, the source electrode 7 may be provided so as to cover the gate electrode 6 via an interlayer insulating film. The source electrode 7 is made of, for example, Al or an Al-Si alloy.

[0035] Drain electrode 8 is provided on the back surface 11b side of GaN single crystal substrate 11 and is electrically connected to GaN single crystal substrate 11. Drain electrode 8 is made of, for example, Al or an Al—Si alloy.

[0036] (Manufacturing method) Next, a method for manufacturing GaN semiconductor device 100 will be described. Figures 3 and 4 are cross-sectional views showing the manufacturing method for GaN semiconductor device 100 according to embodiment 1 of the present invention in the order of steps. GaN semiconductor device 100 is manufactured using various types of equipment, such as a cleaning equipment, a film-forming equipment, a heat treatment equipment, an exposure equipment, and an etching equipment. Hereinafter, these equipments will be collectively referred to as manufacturing equipment.

[0037] In step ST1 of FIG. 3, a manufacturing apparatus (not shown) forms a p-type well region 13 (see FIG. 2), an n+ type source region 14 (see FIG. 2), a p+ type contact region 16 (see FIG. 2), and a p+ type base region 18 on the surface 12a side of the GaN layer 12. The p- type well region 13 is formed by partially ion-implanting magnesium (Mg) as a p-type impurity into the surface 12a side of the GaN layer 12 and activating the Mg by performing a heat treatment on the entire substrate including the GaN layer 12. The n+ type source region 14 is formed by partially ion-implanting silicon (Si) as an n-type impurity into the surface side of the well region 13 and activating the Si by performing a heat treatment on the entire substrate including the well region 13. The p+ type contact region 16 and the p+ type base region 18 are formed by partially ion-implanting Mg as a p-type impurity into the surface side of the well region 13 and activating the Si by performing a heat treatment on the entire substrate including the well region 13. The heat treatment for forming the n+ type source region 14 and the heat treatment for forming the p+ type contact region 16 and the p+ type base region 18 are, for example, the same process.

[0038] 3, the manufacturing equipment forms an SiO thin film 512 (an example of the "oxide thin film" of the present invention) by plasma CVD, thermal CVD, or thermal sputtering on the surface 12a of the GaN layer 12 on which the well region 13, the source region 14, the contact region 16, and the base region 18 are formed. The thickness of the SiO thin film 512 is, for example, 0.5 nm or more and 3 nm or less.

[0039] Furthermore, during the formation of the SiO2 thin film 512, the surface 12a of the GaN layer 12 is oxidized, naturally forming a gallium oxide (GaOx) layer 510. For example, when the SiO2 thin film 512 is formed by plasma CVD, oxygen gas is introduced into the apparatus to generate oxygen plasma. The oxygen plasma oxidizes the surface of the GaN layer 12 in a short time of several seconds, forming the GaOx layer 510. The GaOx layer 510 is formed at the interface between the GaN layer 12 and the SiO2 thin film 512. The thickness of the GaOx layer 510 is, for example, not less than 0.2 nm and not more than 1 nm.

[0040] Next, the manufacturing equipment irradiates the SiO2 thin film 512 and the interface between the SiO2 thin film 512 and the GaN layer 12 (i.e., the GaOx layer 510) with plasma in an atmosphere containing nitrogen, thereby doping the SiO2 thin film 512 and the interface (i.e., the GaOx layer 510) with nitrogen. For example, the SiO2 thin film 512 and the GaOx layer 510 are irradiated with plasma containing nitrogen molecules (N2) or ammonia (NH3) as nitrogen, thereby doping the SiO2 thin film 512 and the GaOx layer 510 with nitrogen. Hereinafter, the plasma in an atmosphere containing nitrogen will also be referred to as nitrogen plasma. The concentration of nitrogen doped in the GaOx layer 510 by the nitrogen plasma is, for example, 1×10 21 cm -3 More than 1×10 23 cm -3 The following is the result.

[0041] As a result, the SiO2 thin film 512 and the GaOx layer 510 are nitrided, and as shown in step ST3 in Fig. 4, the GaOx layer 510 becomes a GaOxNy layer 511, and the SiO2 thin film 512 becomes a SiON thin film 513. A nitride layer 51 including the GaOxNy layer 511 and the SiON thin film 513 is formed.

[0042] 4, the manufacturing equipment forms an insulating film 52 on the nitride layer 51. The insulating film 52 is formed by, for example, thermal CVD or plasma CVD.

[0043] 3, the step of forming the SiO 2 thin film 512, the step of irradiating the SiO 2 thin film 512 and the GaO x layer 510 with nitrogen plasma to dope them with nitrogen (nitriding step), and the step ST 4 The steps of forming the insulating film 52 shown in 1) may be performed in separate apparatuses, or may be performed consecutively in the same apparatus. For example, the above three steps may be performed consecutively in the same apparatus. Furthermore, of the above three steps, the step of forming the SiO2 thin film 512 and the nitrogen doping step may be performed consecutively in the same apparatus, or the nitrogen doping step and the step of forming the insulating film 52 may be performed consecutively in the same apparatus.

[0044] The method for manufacturing the GaN semiconductor device 100 according to the first embodiment includes the steps of forming the gate insulating film 5 of the vertical MOSFET 1, including the steps of forming the SiO thin film 512, doping the SiO thin film 512 and the GaO layer 510 with nitrogen plasma, and forming the insulating film 52.

[0045] Next, the manufacturing equipment applies heat treatment to the entire substrate on which the insulating film 52 has been formed. The temperature of this heat treatment is, for example, 800° C. or higher.

[0046] Next, the manufacturing equipment forms a gate electrode 6 (see FIG. 2) on the insulating film 52. For example, the manufacturing equipment deposits a gate electrode film on the insulating film 52. The gate electrode film is made of Al or an Al-Si alloy, and the deposition method thereof is a vapor deposition method. Alternatively, the gate electrode film may be made of polysilicon doped with impurities, and the deposition method thereof may be a CVD method. Next, the manufacturing equipment forms the gate electrode 6 by patterning the gate electrode film.

[0047] Next, the manufacturing equipment forms source electrode 7 (see FIG. 2) on surface 12a of GaN layer 12. Source electrode 7 is formed by depositing Al or an Al—Si alloy by vapor deposition and patterning the deposited Al or Al—Si alloy.

[0048] Next, the manufacturing equipment forms a drain electrode 8 (see FIG. 2) on the back surface 10b side of the GaN substrate 10. The drain electrode 8 is formed by depositing an Al or Al-Si alloy film by vapor deposition and patterning it as necessary. Through the above steps, the GaN semiconductor device 100 shown in FIGS. 1 and 2 is completed.

[0049] (Effects of the First Embodiment) As described above, the method for manufacturing GaN semiconductor device 100 according to the first embodiment of the present invention includes the steps of forming SiO thin film 512 on surface 12a of GaN layer 12 by plasma CVD, thermal CVD, or thermal sputtering, irradiating SiO thin film 512 and the interface between SiO thin film 512 and GaN layer 12 with plasma in a nitrogen-containing atmosphere to dope SiO thin film 512 and the interface with nitrogen, and forming insulating film 52 on nitrogen-doped SiO thin film 512.

[0050] This allows nitrogen to be doped into the SiO2 thin film 512 and the GaOx layer 510 formed at the interface between the SiO2 thin film 512 and the GaN layer 12, thereby nitriding the SiO2 thin film 512 and the GaOx layer 510. This reduces the GaOx layer 510, making it possible to suppress interface traps and a decrease in mobility caused by the GaOx layer 510. Furthermore, it is possible to suppress gallium (Ga) diffusion from the GaOx layer 510 to the insulating film 52. This reduces the fixed charge in the insulating film 52, making it possible to suppress a decrease in the threshold voltage of the MOSFET.

[0051] 9, in the method of nitrogen doping using nitrogen plasma described in the first embodiment of the present invention, the amount of nitrogen doped is approximately proportional to the irradiation time of the nitrogen plasma (nitridation time). Therefore, the amount of nitrogen doped is easily controlled, and the SiO2 thin film 512 and the GaOx layer 510 can be nitrided with good reproducibility.

[0052] GaN semiconductor device 100 according to embodiment 1 of the present invention includes GaN layer 12, insulating film 52 provided on GaN layer 12, and nitride layer 51 present between GaN layer 12 and insulating film 52. Nitride layer 51 includes GaOxNy layer 511 located closer to GaN layer 12 and SiON thin film 513 located closer to insulating film 52. GaN semiconductor device 100 having such a configuration can be manufactured by the manufacturing method including the nitrogen doping step using nitrogen plasma described above.

[0053] In addition, when nitrogen doping is performed by flowing nitrogen gas into a chamber instead of by irradiating nitrogen plasma, it is difficult to control the amount of nitrogen doping, and therefore it is difficult to form the GaOxNy layer 511 so as to be in contact with the GaN layer 12.

[0054] <Embodiment 2> In the above-described first embodiment, the oxide thin film of the present invention is described as being formed on the surface 12a of the GaN layer 12. However, in the embodiments of the present invention, the oxide thin film is not limited to being an SiO thin film, and may be, for example, an AlO thin film.

[0055] 5 and 6 are cross-sectional views illustrating the process sequence of a method for manufacturing GaN semiconductor device 100 according to embodiment 2 of the present invention. In step ST11 of Fig. 5, similar to step ST1 of Fig. 3 described in embodiment 1, the manufacturing equipment forms p-type well region 13 (see Fig. 2), n+ type source region 14 (see Fig. 2), and p+ type contact region 16 (see Fig. 2) on the surface 12a side of GaN layer 12.

[0056] 5, the manufacturing equipment forms an Al2O3 thin film 512A (an example of the "oxide thin film" of the present invention) by plasma CVD, thermal CVD, or thermal sputtering on the surface 12a of the GaN layer 12 on which the well region 13, the source region 14, and the contact region 16 are formed. The thickness of the Al2O3 thin film 512A is, for example, 0.5 nm or more and 3 nm or less.

[0057] Also in the second embodiment, when the Al2O3 thin film 512A is formed, the surface 12a of the GaN layer 12 is oxidized, and the GaOx layer 510 is naturally formed. For example, when the Al2O3 thin film 512A is formed by the plasma CVD method, oxygen gas is introduced into the apparatus to generate plasma in an oxygen-containing atmosphere (oxygen plasma). The oxygen plasma oxidizes the surface of the GaN layer 12 in a short time of several seconds, forming the GaOx layer 510. The GaOx layer 510 is formed at the interface between the GaN layer 12 and the Al2O3 thin film 512A.

[0058] Next, the manufacturing equipment irradiates nitrogen plasma onto the Al2O3 thin film 512A and the interface between the Al2O3 thin film 512A and the GaN layer 12 (i.e., the GaOx layer 510) to dope nitrogen into the Al2O3 thin film 512A and the interface (i.e., the GaOx layer 510). For example, nitrogen molecules (N2) or ammonia (NH3) are used as nitrogen, and 1×10 21 cm -3 More than 1×10 23 cm -3 The Al2O3 thin film 512A and the GaOx layer 510 are irradiated with plasma containing nitrogen at the following concentrations, thereby doping the Al2O3 thin film 512A and the GaOx layer 510 with nitrogen.

[0059] As a result, the Al2O3 thin film 512A and the GaOx layer 510 are nitrided, and as shown in step ST13 of Figure 6, the GaOx layer 510 becomes a GaOxNy layer 511, and the Al2O3 thin film 512A becomes an AlON thin film 513A (an example of the "oxynitride thin film" of the present invention). A nitride layer 51 including the GaOxNy layer 511 and the AlON thin film 513A is formed. The AlON thin film 513A contains, for example, a higher concentration of nitrogen than the insulating film 52 to be formed next.

[0060] The subsequent steps are the same as those in embodiment 1. As shown in step ST14 of Fig. 6, the manufacturing equipment forms an insulating film 52 on the nitride layer 51. The insulating film 52 is formed by, for example, thermal CVD or plasma CVD.

[0061] In the second embodiment, as in the first embodiment, the steps of forming the Al2O3 thin film 512A shown in step ST12 of FIG. 5, the step of doping the Al2O3 thin film 512A and the GaOx layer 510 with nitrogen by irradiating them with nitrogen plasma (nitriding step), and the steps of forming the Al2O3 thin film 512A and the GaOx layer 510 with nitrogen plasma (nitriding step) shown in step ST1 of FIG. 4 The steps of forming the insulating film 52 shown in 1) may be performed in separate apparatuses, or may be performed consecutively in the same apparatus.

[0062] The method for manufacturing the GaN semiconductor device 100 according to the second embodiment includes the steps of forming the gate insulating film 5 of the vertical MOSFET 1, including the steps of forming the Al2O3 thin film 512A, doping the Al2O3 thin film 512A and the GaOx layer 510 with nitrogen plasma, and forming the insulating film 52.

[0063] Next, the manufacturing equipment applies heat treatment to the entire substrate on which the insulating film 52 has been formed. The temperature of this heat treatment is, for example, 800° C. or higher.

[0064] Next, the manufacturing equipment sequentially forms gate electrode 6 (see FIG. 2), source electrode 7 (see FIG. 2), and drain electrode 8 (see FIG. 2). Through the above steps, GaN semiconductor device 100 shown in FIG. 1 is completed.

[0065] As described above, the method for manufacturing GaN semiconductor device 100 according to the second embodiment of the present invention makes it possible to dope Al2O3 thin film 512A and GaOx layer 510 formed at the interface between Al2O3 thin film 512A and GaN layer 12 with nitrogen, thereby nitriding Al2O3 thin film 512A and GaOx layer 510. As a result, similar to the first embodiment, GaOx layer 510 can be reduced, and Ga diffusion from GaOx layer 510 into insulating film 52 can be suppressed.

[0066] Also in the second embodiment, nitrogen doping is performed using nitrogen plasma, as in the first embodiment. This makes it easy to control the amount of nitrogen doping, and the Al2O3 thin film 512A and the GaOx layer 510 can be nitrided with good reproducibility.

[0067] <Embodiment 3> In an embodiment of the present invention, the step of forming the SiO2 thin film 512 (or the Al2O3 thin film 512) and the nitrogen doping step (nitriding step) may be repeated. This allows multiple SiON thin films 513 (or AlON thin films 513A) to be stacked, thereby making the nitride layer 51 thicker.

[0068] 7 and 8 are cross-sectional views showing the order of steps in a method for manufacturing GaN semiconductor device 100 according to embodiment 3 of the present invention. In step ST21 of Fig. 7, similar to step ST1 of Fig. 3 described in embodiment 1, the manufacturing equipment forms p-type well region 13 (see Fig. 2), n+ type source region 14 (see Fig. 2), and p+ type contact region 16 (see Fig. 2) on the surface 12a side of GaN layer 12.

[0069] 7, the manufacturing equipment forms an SiO2 thin film 512 by plasma CVD, thermal CVD, or thermal sputtering on the surface 12a of the GaN layer 12 on which the well region 13, the source region 14, and the contact region 16 have been formed. During the formation of the SiO2 thin film 512, the surface 12a of the GaN layer 12 is oxidized, and a GaOx layer 510 is naturally formed. The GaOx layer 510 is formed at the interface between the GaN layer 12 and the SiO2 thin film 512.

[0070] Next, the manufacturing equipment irradiates nitrogen plasma onto SiO2 thin film 512 and the interface between SiO2 thin film 512 and GaN layer 12 (i.e., GaOx layer 510), thereby doping nitrogen into SiO2 thin film 512 and GaOx layer 510. As a result, SiO2 thin film 512 and GaOx layer 510 are nitrided, and GaOxNy layer 511 and SiON thin film 513 are formed, as shown in step ST23 of FIG.

[0071] In the third embodiment, the manufacturing equipment repeatedly performs the step of forming the SiO thin film 512 and the nitrogen doping step (nitriding step) shown in step ST22. The number of repetitions is arbitrary. As a result, as shown in step ST24 of FIG. 8, it is possible to stack multiple SiON thin films 513, and to thicken the nitride layer 51 including the SiON thin films 513.

[0072] To prevent Ga diffusion from the GaN layer 12 side to the insulating film 52 side, it is preferable to form the SiON thin film 513 thick. However, when nitrogen is doped using nitrogen plasma, nitrogen penetrates only a depth of about several nm from the surface of the SiO2 thin film 512. Therefore, as described above, the formation of the SiO2 thin film 512 and nitrogen doping using nitrogen plasma are repeated. In other words, nitrogen doping is performed in several steps. This allows multiple SiON thin films 513 to be stacked, and the total thickness of the SiON thin films 513 can be increased.

[0073] The subsequent steps are the same as those in embodiment 1. As shown in step ST25 of FIG.

[0074] The method for manufacturing the GaN semiconductor device 100 according to the third embodiment includes, as steps for forming the gate insulating film 5 of the vertical MOSFET 1, a step of forming a SiO thin film 512, a step of irradiating the SiO thin film 512 and the GaO layer 510 with nitrogen plasma to dope them with nitrogen, a step of repeating these two steps, and a step of forming an insulating film 52 after the repetition.

[0075] Next, the manufacturing equipment applies heat treatment to the entire substrate on which the insulating film 52 has been formed. The temperature of this heat treatment is, for example, 800° C. or higher.

[0076] Next, the manufacturing equipment sequentially forms gate electrode 6 (see FIG. 2), source electrode 7 (see FIG. 2), and drain electrode 8 (see FIG. 2). Through the above steps, GaN semiconductor device 100 shown in FIG. 1 is completed.

[0077] As described above, the method for manufacturing GaN semiconductor device 100 according to the third embodiment of the present invention makes it possible to thicken nitride layer 51 including SiON thin film 513. This makes it possible to further prevent Ga diffusion from GaN layer 12 to insulating film 52.

[0078] <Relationship between nitrogen amount and nitriding time using nitrogen plasma> The inventors investigated the relationship between the amount of nitrogen and the nitriding time using nitrogen plasma. In this investigation, a SiO2 thin film was placed in a chamber, the vacuum level in the chamber was set to 200 mTorr, the gas atmosphere was set to NH3 / Ar = 10 / 400 (a mixture of NH3 and Ar gases with a mixing ratio of 10:400), and the plasma power was set to 400 W, and nitrogen plasma was generated in the chamber. Under these conditions, nitrogen doping was performed multiple times with varying nitriding times to obtain multiple samples with different nitriding times. The amount of nitrogen on the surface of the SiO2 thin film was then measured for each sample using X-ray photoelectron spectroscopy (XPS). The results are shown in Figure 9.

[0079] Figure 9 is a graph showing the relationship between the amount of nitrogen produced by nitrogen plasma and the nitriding time. The vertical axis of Figure 9 shows the amount of nitrogen (at.%) on the surface of the SiO2 thin film, and the horizontal axis shows the nitriding time (minutes). In Figure 9, the amount of nitrogen on the surface of the SiO2 thin film can also be rephrased as the amount of nitrogen doping or the composition ratio of nitrogen atoms. As shown in Figure 9, it was confirmed that the amount of nitrogen on the surface of the SiO2 thin film increases in almost proportion to the nitriding time produced by nitrogen plasma. This result shows that the amount of nitrogen can be controlled by the nitriding time.

[0080] For example, in a method of nitrogen doping by flowing nitrogen gas into a chamber rather than by irradiating nitrogen plasma, the amount of nitrogen incorporated into the film (i.e., the nitrogen doping amount) is hardly dependent on the nitrogen gas flow rate, making it difficult to control the nitrogen doping amount. In contrast, in the method of nitrogen doping using nitrogen plasma described in embodiments 1 to 3 of the present invention, as shown in Figure 9, the amount of nitrogen on the SiO2 thin film surface is approximately proportional to the irradiation time of nitrogen plasma (i.e., the nitriding time), making it easy to control the nitrogen doping amount.

[0081] <Embodiment 4> In the above-described first embodiment, the vertical MOSFET 1 included in the GaN semiconductor device 100 is of a planar type. However, in each embodiment of the present invention, the vertical MOSFET included in the GaN semiconductor device 100 is not limited to a planar type, and may be a trench gate type.

[0082] Fig. 10 is a cross-sectional view showing a configuration example of a GaN semiconductor device 100A according to embodiment 4 of the present invention. As shown in Fig. 10, the GaN semiconductor device 100A according to embodiment 4 has a trench H provided in a GaN substrate 10. The trench H opens to the surface 10a side of the GaN substrate 10. The trench H is formed deeper than the p-type well region 13, and the bottom of the trench H reaches the n-type GaN layer 12 (drift region).

[0083] A gate insulating film 5 and a gate electrode 6 are disposed inside the trench H. The inner side and bottom surfaces of the trench H are covered with a nitride layer 51 of the gate insulating film 5. The gate electrode 6 is buried in the trench H via the gate insulating film 5. In a trench-gate vertical MOSFET, the well region 13, which faces the gate electrode 6 via the gate insulating film 5 provided on the side surface of the trench H, serves as a channel region.

[0084] The GaN semiconductor device 100A according to the second embodiment has, as the gate insulating film 5, a nitride layer 51 that covers the inner side and bottom surfaces of the trench H, and an insulating film 52 provided on the nitride layer 51. The nitride layer 51 and the insulating film 52 are stacked in this order to form the gate insulating film 5. The configurations of the nitride layer 51 and the insulating film 52 are as described in the first to third embodiments.

[0085] GaN semiconductor device 100A can be manufactured by a manufacturing method including the nitrogen doping step using nitrogen plasma described above, similar to GaN semiconductor device 100. Furthermore, in GaN semiconductor device 100A, the vertical MOSFET employs a trench gate structure, which allows channel regions to be arranged more densely, facilitating element miniaturization.

[0086] <Other embodiments> As described above, the present invention has been described by the embodiments and modifications, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present invention. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure.

[0087] For example, the p-type dopant used in the vertical MOSFET 1 is not limited to magnesium (Mg). The p-type dopant may be beryllium (Be), zinc (Zn), or cadmium (Cd). For example, the channel region may contain one or more of Mg, Be, Zn, and Cd as p-type dopants at a concentration of 1E+16 / cm. 3 It may be contained at a concentration of 100 or more.

[0088] 2, an n-type JFET region may be provided in the drift region directly below the gate insulating film 5. The JFET region has a higher concentration of n-type dopants and a lower electrical resistance than the other drift regions. The provision of the JFET region may reduce the on-resistance of the vertical MOSFET 1.

[0089] In the above embodiment, the GaN layer 12 is exemplified as the "gallium nitride layer" of the present invention, but the "gallium nitride layer" is not limited to a GaN layer. For example, the "gallium nitride layer" may be a bulk GaN substrate. Furthermore, the "gallium nitride layer" may contain GaN as a main component and further contain one or more elements selected from aluminum (Al) and indium (In).

[0090] As such, the present invention naturally includes various embodiments not described herein. Various omissions, substitutions, and modifications of components may be made without departing from the spirit of the above-described embodiments and modifications. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present. The technical scope of the present invention is defined solely by the invention-specifying matters pertaining to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0091] 1 Vertical MOSFET 5 Gate insulating film 6 gate electrode 7. Source electrode 8 Drain electrode 10 GaN substrate 10a, 12a surface 10b, 11b, 12b back side 11 GaN single crystal substrate 12 GaN layers 13 well area 14 Source Region 16 Contact Area 18 Base Area 51 Nitrided layer 52 insulating film 100, 100A GaN semiconductor device 510 GaOx layer 511 GaOxNy layer 512 SiO2 thin film 512A Al2O3 thin film 513 SiON thin film 513A AlON thin film H Trench

Claims

1. forming an oxide thin film on the surface of the gallium nitride layer by plasma CVD, thermal CVD, or thermal sputtering; a step of irradiating the oxide thin film and the interface between the oxide thin film and the gallium nitride layer with plasma in an atmosphere containing nitrogen to dope the oxide thin film and the interface with nitrogen; forming an insulating film on the nitrogen-doped oxide thin film in contact with the oxide thin film, By performing the nitrogen doping step, a GaOxNy layer having a nitrogen concentration of 1×10 21 cm −3 or more and 1×10 23 cm −3 or less is formed at the interface.

2. The oxide thin film is SiO ２ Thin film or Al ２ O ３ The method for manufacturing a nitride semiconductor device according to claim 1 , wherein the nitride semiconductor device is a thin film.

3. 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the oxide thin film has a thickness of 0.5 nm or more and 3 nm or less.

4. The insulating film is made of SiO ２ film, SiON film, Al ２ O ３ 4. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the nitride semiconductor device comprises at least one of a nitride film, an AlON film, an AlSiO film, and a HfO film.

5. The method for manufacturing a nitride semiconductor device according to claim 1 , further comprising the step of, after forming the insulating film, subjecting the entire substrate including the insulating film to a heat treatment.

6. forming a gate insulating film of a MOSFET on the gallium nitride layer, The method for manufacturing a nitride semiconductor device according to claim 1 , comprising the steps of forming the oxide thin film, doping the nitride semiconductor layer with nitrogen, and forming the insulating film.

7. A method for manufacturing a nitride semiconductor device according to claim 1, wherein the step of forming the oxide thin film and the step of doping the nitrogen are repeated.

8. a gallium nitride layer; an insulating film provided on the gallium nitride layer; a nitride layer present between the gallium nitride layer and the insulating film, The nitride layer is a GaOxNy layer in contact with the gallium nitride layer; an oxynitride thin film in contact with the insulating film, A nitride semiconductor device, wherein the nitrogen concentration in the GaOxNy layer is 1×10 21 cm −3 or more and 1×10 23 cm −3 or less.

9. 9. The nitride semiconductor device according to claim 8, wherein said oxynitride thin film is a SiON thin film or an AlON thin film.

10. 10. The nitride semiconductor device according to claim 8, wherein said oxynitride thin film contains nitrogen at a higher concentration than said insulating film.

11. a MOSFET provided on the gallium nitride layer, 11. The nitride semiconductor device according to claim 8, wherein a gate insulating film of said MOSFET includes said insulating film and said oxynitride thin film.

12. A process for forming an oxide thin film on a surface of a gallium nitride layer by a plasma CVD method, a thermal CVD method, or a thermal sputtering method; a step of irradiating the oxide thin film and the interface between the oxide thin film and the gallium nitride layer with plasma in an atmosphere containing nitrogen to dope the oxide thin film and the interface with nitrogen; forming an insulating film on the nitrogen-doped oxide thin film in contact with the oxide thin film, After forming the insulating film, the method further includes a step of subjecting the entire substrate including the insulating film to a heat treatment; The method for manufacturing a nitride semiconductor device, wherein the heat treatment is performed at a temperature of 800° C. or higher.

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