Indication device

Abstract

To provide a display device which can improve display characteristics.SOLUTION: A display device comprises: a pixel array which is provided between first and second substrates opposed to each other and has a plurality of pixels; a plurality of scan lines GL which is connected to the pixel array and extends in a first direction; an integrated circuit 13 which is provided on the first substrate and drives the pixel array; and a plurality of lead-out wires 20 which is provided on the first substrate and connect the plurality of scan lines with the integrated circuit 13. The plurality of lead-out wires 20 respectively includes: a plurality of lower layer wires 20A included in a first level wire layer; a plurality of upper layer wires 20B included in a second level wire layer arranged via an insulation layer on an upper side of the first level wire layer; and a plurality of contacts 24 which connects the plurality of lower layer wires 20A with the plurality of upper layer wires 20B. The plurality of lower layer wires 20A and the plurality of upper layer wires 20B are alternately arranged in a direction in which the lead-out wires 20 are adjacent to each other.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a display device. [Background technology]

[0002] A liquid crystal display device includes an array substrate on which TFTs (Thin Film Transistors) are provided, a counter substrate on which color filters are provided, and a liquid crystal layer sandwiched between the array substrate and the counter substrate. The liquid crystal display device includes a display area where an image is displayed, and a pixel array is provided in the display area. A plurality of scanning lines and a plurality of signal lines are arranged in the pixel array. The plurality of scanning lines and a plurality of signal lines are provided on the array substrate.

[0003] The scanning lines are connected to an integrated circuit such as an LSI (Large-Scale Integrated Circuit) by means of a plurality of lead-out wirings provided in a peripheral region around the display region, and the signal lines are connected to the integrated circuit by means of a plurality of lead-out wirings.

[0004] By devising a wiring method for the scan lines, it is possible to narrow the left and right frame of an LCD display. One method for narrowing the left and right frame is two-layer alternating wiring, in which two layers of scan lines are arranged alternately.

[0005] When using two-layer alternating wiring, wiring patterns on different layers are used, so film formation processes must be performed more than once. This results in differences in the finish (wiring width, etc.) between odd-numbered and even-numbered scan lines. The difference in the finish between odd-numbered and even-numbered scan lines results in a difference in the time constant of the wiring. This difference in time constant causes problems such as streaky unevenness to appear on the screen. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-147448 [Patent Document 2] Japanese Patent Application Publication No. 5-53127 Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention provides a display device capable of improving display characteristics. [Means for solving the problem]

[0008] According to a first aspect of the present invention, there is provided a display device comprising: a pixel array provided between opposing first and second substrates, the pixel array having a plurality of pixels; a plurality of scanning lines connected to the pixel array and extending in a first direction; an integrated circuit provided on the first substrate for driving the pixel array; and a plurality of pull-out wirings provided on the first substrate for connecting the plurality of scanning lines and the integrated circuit, wherein the plurality of pull-out wirings each include a plurality of lower-layer wirings included in a first-level wiring layer, a plurality of upper-layer wirings included in a second-level wiring layer arranged above the first-level wiring layer via an insulating layer, and a plurality of contacts connecting the plurality of lower-layer wirings and the plurality of upper-layer wirings, and the plurality of lower-layer wirings and the plurality of upper-layer wirings are alternately arranged in the direction in which the plurality of pull-out wirings are adjacent to each other.

[0009] According to a second aspect of the present invention, there is provided a display device according to the first aspect, wherein each of the plurality of pull-out wirings includes a first portion extending from an end of the scanning line in a second direction perpendicular to the first direction, and a second portion extending from an end of the first portion toward the integrated circuit, and each of the plurality of contacts is arranged in the second portion.

[0010] According to a third aspect of the present invention, there is provided the display device according to the second aspect, wherein the plurality of contacts are arranged so as to be shifted in order in the first direction.

[0011] According to a fourth aspect of the present invention, there is provided the display device according to the second aspect, wherein the plurality of contacts are arranged such that the more outer the contacts included in the lead-out wiring arranged, the farther they are from the integrated circuit.

[0012] According to a fifth aspect of the present invention, there is provided the display device according to the first or second aspect, wherein the plurality of contacts are respectively arranged in the center of the plurality of lead-out wirings.

[0013] According to a sixth aspect of the present invention, there is provided the display device according to any one of the first to fifth aspects, wherein the lower layer wiring and the upper layer wiring are made of the same conductive material.

[0014] According to a seventh aspect of the present invention, there is provided the display device according to any one of the first to fifth aspects, wherein the lower layer wiring and the upper layer wiring are made of different conductive materials.

[0015] According to an eighth aspect of the present invention, there is provided the display device according to any one of the first to seventh aspects, wherein the pixel array includes a liquid crystal layer. [Effects of the Invention]

[0016] According to the present invention, it is possible to provide a display device capable of improving display characteristics. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 1 is a schematic plan view of a liquid crystal display device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a side view of the liquid crystal display device shown in FIG. [Figure 3] FIG. 3 is a cross-sectional view mainly showing the contact connected to the scan line. [Figure 4] FIG. 4 is a plan view of the lead wiring. [Figure 5] FIG. 5 is a cross-sectional view of the lead wiring taken along the line AA′ shown in FIG. [Figure 6]FIG. 6 is a cross-sectional view of the lead wiring taken along line BB′ shown in FIG. [Figure 7] FIG. 7 is a plan view of the lead wiring according to the first comparative example. [Figure 8] FIG. 8 is a plan view of the lead wiring according to the second comparative example. [Figure 9] FIG. 9 is a diagram illustrating the resistance of the lead wiring according to the comparative example. [Figure 10] FIG. 10 is a diagram illustrating the resistance of the lead wiring according to this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments will be described with reference to the drawings. However, the drawings are schematic or conceptual, and the dimensions and proportions of each drawing are not necessarily the same as those of the actual drawing. Furthermore, even when the same parts are shown in different drawings, the dimensional relationships and proportions may be different. In particular, the following embodiments are illustrative of devices and methods for embodying the technical concept of the present invention, and the shape, structure, arrangement, etc. of the components do not specify the technical concept of the present invention. In the following description, elements having the same function and configuration are designated by the same reference numerals, and redundant description will be omitted.

[0019] [1] Configuration of liquid crystal display device 1 Fig. 1 is a schematic plan view of a liquid crystal display device 1 according to an embodiment of the present invention. The X direction in Fig. 1 is a direction along one side of the liquid crystal display device 1, and the Y direction is a direction perpendicular to the X direction. Fig. 2 is a side view of the liquid crystal display device 1 shown in Fig. 1. Fig. 2 is a side view of the liquid crystal display device 1 of Fig. 1 as viewed from the right side.

[0020] The liquid crystal display device 1 has a display area 2 and a peripheral area 3 surrounding the display area 2.

[0021] An image is displayed in the display area 2. The display area 2 is provided with a pixel array made up of a plurality of pixels PX arranged in a matrix.

[0022] The peripheral region 3 is an area where wiring and circuits for driving the pixel array are provided. A black light-shielding layer is provided in the peripheral region 3, and the peripheral region 3 is visually recognized as a black area by a viewer. The peripheral region 3 is also called a frame.

[0023] The liquid crystal display device 1 includes an array substrate 10, a counter substrate 11, liquid crystal elements 12, and an integrated circuit (IC) 13. The integrated circuit 13 may be an LSI (Large-Scale Integrated Circuit) or the like.

[0024] The array substrate 10 and the counter substrate 11 are made of insulating and transparent substrates, such as glass substrates, and are bonded to each other with a sealant.

[0025] Between the array substrate 10 and the counter substrate 11, liquid crystal elements 12 that constitute a pixel array are provided. The liquid crystal elements 12 include switching elements, pixel electrodes, a liquid crystal layer, color filters, a common electrode, etc. The array substrate 10 is provided with switching elements and pixel electrodes. The counter substrate 11 is provided with color filters and a common electrode. A detailed description of the multiple layers that constitute the pixel array is omitted here.

[0026] The liquid crystal mode is not particularly limited, and it is possible to use VA (Vertical Alignment) mode, TN (Twisted Nematic) mode, homogeneous mode, STN (Super Twisted Nematic) mode, FFS (Fringe-Field Switching) mode, etc. Although not shown in the figure, two polarizing plates or the like are appropriately provided to sandwich the array substrate 10 and the counter substrate 11.

[0027] The integrated circuit 13 is provided at an end of the array substrate 10 in the Y direction. The array substrate 10 is configured to have a larger area in the Y direction than the counter substrate 11. The integrated circuit 13 is disposed on a portion of the array substrate 10 that protrudes from the counter substrate 11 in a plan view. The integrated circuit 13 includes a plurality of circuits for driving the pixel array. Specifically, the integrated circuit 13 includes a gate driver (scanning line driving circuit), a source driver (signal line driving circuit), a common electrode driver (common electrode driving circuit), a voltage generating circuit, a control circuit, and the like.

[0028] In the display area 2, a plurality of scanning lines GL each extending in the X direction and aligned in the Y direction, and a plurality of signal lines SL each extending in the Y direction and aligned in the X direction are arranged. For simplification, FIG. 1 illustrates six scanning lines GL1 to GL6 and three signal lines SL1 to SL3. In reality, more scanning lines GL and signal lines SL than illustrated are arranged. The scanning lines GL1 to GL6 are provided on the array substrate 10 and are formed in wiring layers at the same level. The signal lines SL1 to SL3 are provided on the array substrate 10 and are formed in wiring layers at the same level.

[0029] Pixels PX are arranged in the intersections of the scanning lines GL and the signal lines SL. Each pixel PX includes a switching element 14 and a pixel electrode 15. The switching element 14 is, for example, a thin film transistor (TFT), and an n-channel TFT is used. The pixel electrode 15 is configured to sandwich a liquid crystal layer together with a common electrode.

[0030] The plurality of scanning lines GL are electrically connected to the integrated circuit 13 via a plurality of lead-out wirings 20. In the example of FIG. 1, the scanning lines GL1 to GL6 are electrically connected to the integrated circuit 13 via lead-out wirings 20-1 to 20-6, respectively. The lead-out wirings 20-1 to 20-6 are provided on the array substrate 10. In this specification, when there is no need to particularly distinguish between reference symbols with sub-numbers, the sub-numbers will be omitted to provide a common explanation for the reference symbols.

[0031] The odd-numbered lead-out wirings 20-1, 20-3, and 20-5 and the even-numbered lead-out wirings 20-2, 20-4, and 20-6 are configured in different level wiring layers. The odd-numbered lead-out wirings 20-1, 20-3, and 20-5 are configured in lower layer wiring. The even-numbered lead-out wirings 20-2, 20-4, and 20-6 are configured in upper layer wiring. The lower layer wirings are included in the first level wiring layer. The upper layer wirings are included in the second level wiring layer. The second level wiring layer is disposed above the first level wiring layer via an insulating layer. More specifically, each lead-out wiring 20 is configured so that the lower layer wiring and the upper layer wiring are interchanged midway. A more specific configuration of the lead-out wirings 20 will be described later.

[0032] For example, scan lines GL2, GL4, and GL6 are included in the first-level wiring layer. Odd-numbered scan lines GL1, GL3, and GL5 are connected to lead-out lines 20-1, 20-3, and 20-5 at the same level as these scan lines. Even-numbered scan lines GL2, GL4, and GL6 are pulled up to the second-level wiring layer by contacts 21-1, 21-2, and 21-3, respectively, and connected to lead-out lines 20-2, 20-4, and 20-6.

[0033] Fig. 3 is a cross-sectional view mainly showing the contact 21-1 connected to the scan line GL2. Fig. 3 is a cross-sectional view taken in the X direction of the region of the contact 21-1 in Fig. 1. The configurations of the contacts 21-2 and 21-3 are the same as those in Fig. 3.

[0034] A scanning line GL2 extending in the X direction is provided on the array substrate 10. A lead-out wiring 20-1 extending in the Y direction is also provided on the array substrate 10. An insulating layer 22 is provided on the scanning line GL2. A lead-out wiring 20-2 extending in the Y direction is provided on the insulating layer 22. A contact 21-1 connecting the lead-out wiring 20-2 and the scanning line GL2 is provided in the insulating layer 22.

[0035] The contact 21-1 is made of the same material as the lead-out wiring 20-2. The contact 21-1 is formed by forming a through-hole in the insulating layer 22 to expose the scanning line GL2, and filling this through-hole with the same material as the lead-out wiring 20-2.

[0036] An insulating layer 23 is provided on the lead-out wiring 20-2. The insulating layers 22 and 23 are made of a transparent insulating material, such as silicon nitride (SiN).

[0037] As shown in FIG. 1, the plurality of signal lines SL are electrically connected to the integrated circuit 13 via a plurality of lead-out wirings.

[0038] The gate electrode GL, signal line SL, and lead-out wiring 20 are made of, for example, any one of aluminum (Al), molybdenum (Mo), chromium (Cr), and tungsten (W), or an alloy containing one or more of these.

[0039] [2] Configuration of lead wiring 20 Next, a specific configuration of the lead-out wiring 20 will be described.

[0040] Fig. 4 is a plan view of the lead-out wiring 20. Fig. 4 is a plan view corresponding to the partial region P shown in Fig. 1. Fig. 5 is a cross-sectional view of the lead-out wiring 20 taken along line AA' shown in Fig. 4. Fig. 6 is a cross-sectional view of the lead-out wiring 20 taken along line BB' shown in Fig. 4.

[0041] 4 shows only four lead-out wirings 20-1 to 20-4 and also shows partial regions of the lead-out wirings 20-1 to 20-4. In reality, a plurality of lead-out wirings are arranged in order inside the lead-out wiring 20-4.

[0042] Each of the lead-out wirings 20-1 to 20-4 includes a lower layer wiring 20A and an upper layer wiring 20B. The lead-out wirings 20-1 to 20-4 are configured such that the lower layer wirings 20A and the upper layer wirings 20B are alternately arranged in the direction in which they are adjacent to each other. The lower layer wirings 20A and the upper layer wirings 20B are made of, for example, the same conductive material.

[0043] The lead-out wiring 20-1 includes a lower layer wiring 20A-1 and an upper layer wiring 20B-1. The lower layer wiring 20A-1 is provided on the array substrate 10. The lower layer wiring 20A-1 has an L-shape and includes a wiring portion extending in the Y direction and a wiring portion extending in the X direction. One end of the lower layer wiring 20A-1 is connected to the scanning line GL1. An insulating layer 22 is provided on the lower layer wiring 20A-1.

[0044] An upper layer wiring 20B-1 extending in the X direction is provided on the insulating layer 22. One end of the upper layer wiring 20B-1 is connected to the other end of the lower layer wiring 20A-1 via a contact 24-1. The contact 24-1 is formed by forming a through hole in the insulating layer 22 to expose the lower layer wiring 20A-1, and filling this through hole with the same material as the upper layer wiring 20B-1. The end of the upper layer wiring 20B-1 that contacts the contact 24-1 is formed so that its lengths in the X direction and Y direction are longer than its wiring width. An insulating layer 23 is provided on the upper layer wiring 20B-1.

[0045] Similarly, the lead-out wiring 20-2 includes a lower layer wiring 20A-2, an upper layer wiring 20B-2, and a contact 24-2. The lead-out wiring 20-3 includes a lower layer wiring 20A-3, an upper layer wiring 20B-3, and a contact 24-3. The lead-out wiring 20-4 includes a lower layer wiring 20A-4, an upper layer wiring 20B-4, and a contact 24-4.

[0046] In the direction in which the lead-out wirings 20-1 to 20-4 are adjacent to each other, the lower layer wiring 20A-1, the upper layer wiring 20B-2, the lower layer wiring 20A-3, and the upper layer wiring 20B-4 are arranged side by side. In addition, in the direction in which the lead-out wirings 20-1 to 20-4 are adjacent to each other, the upper layer wiring 20B-1, the lower layer wiring 20A-2, the upper layer wiring 20B-3, and the lower layer wiring 20A-4 are arranged side by side.

[0047] The contacts 24 are not arranged in the wiring portion of the lead-out wiring 20 extending in the Y direction (the wiring portion directly connected to the scanning line GL), but are arranged in the wiring portion extending in the X direction (the wiring portion directly connected to the integrated circuit 13). This makes it possible to narrow the width of the peripheral region 3 on the left side of the display region 2, as shown in FIG. 1. This in turn makes it possible to narrow the frame of the liquid crystal display device 1.

[0048] The contacts 24-1 to 24-4 are arranged in this order, shifted in the X direction, so as not to overlap in the Y direction.

[0049] The contacts 24 included in the outermost lead-out wiring 20 are arranged so as to be farther away from the integrated circuit 13. "Outside" refers to the positional relationship when viewed from the display region 2. In the example of FIG. 4, the contacts 24-1 to 24-4 are arranged so as to be closer to the integrated circuit 13 in this order. In the example of FIG. 4, the contact 24-1 is arranged farthest from the integrated circuit 13, and the contact 24-4 is arranged closest to the integrated circuit 13.

[0050] 1, the outermost the lead-out wiring 20 is, the longer the wiring portion extending in the Y direction. As described above, by arranging the contacts 24 included in the outermost lead-out wiring 20 so that they are farther away from the integrated circuit 13, the difference in length between the lower layer wiring 20A and the upper layer wiring 20B that make up the lead-out wiring 20 becomes smaller. This makes it possible to reduce the difference in resistance among the multiple lead-out wirings 20 even if the wiring widths of the lower layer wiring 20A and the upper layer wiring 20B are different.

[0051] In this embodiment, the contacts 24 are arranged so as to minimize the difference in length between the lower layer wiring 20A and the upper layer wiring 20B that make up the lead-out wiring 20. Ideally, the contacts 24 are arranged so that the lengths of the lower layer wiring 20A and the upper layer wiring 20B are the same. In other words, each of the multiple contacts 24 is arranged in the center of the multiple lead-out wirings 20.

[0052] FIG. 7 is a plan view of lead-out wiring according to a first comparative example. In the first comparative example, a plurality of lead-out wirings are configured such that lower-layer wirings and upper-layer wirings are alternately arranged. Lead-out wiring 1 (wire 1 in the figure) is configured from lower-layer wiring, and lead-out wiring 2 (wire 2 in the figure) is configured from upper-layer wiring. In the first comparative example, each lead-out wiring is configured from a wiring layer at the same level throughout. When the wiring widths of wire 1 and wire 2 are approximately the same, their time constants are also approximately the same.

[0053] FIG. 8 is a plan view of a lead-out wiring according to a second comparative example. The second comparative example is an example in which the wiring widths of the lower-layer wiring and the upper-layer wiring are different. Lead-out wiring 1 (wire 1 in the figure) is made up of lower-layer wiring and has a relatively wide wiring width (thickened line). Lead-out wiring 2 (wire 2 in the figure) is made up of upper-layer wiring and has a relatively narrow wiring width (thinned line). In this case, the resistance of wiring 2 becomes high and the time constant also becomes high.

[0054] Fig. 9 is a diagram illustrating the resistance of the lead-out wiring according to the comparative example. The two graphs on the left of Fig. 9 represent the resistance when the wiring widths of wire 1 and wire 2 are the same. The two graphs on the left of Fig. 9 correspond to the lead-out wiring in Fig. 7. When wire 1 and wire 2 are made thicker or thinner, the resistance may vary within the range indicated by the arrows.

[0055] The two graphs on the right of Figure 9 show the worst case scenario, where wire 1 is thinned and wire 2 is thickened. The two graphs on the right of Figure 9 correspond to the lead-out wires in Figure 8. In the worst case scenario, the difference in resistance between the lower-layer wires and the upper-layer wires is large, degrading the display characteristics of the LCD device. Specifically, streaky unevenness appears on the screen.

[0056] 10 is a diagram illustrating the resistance of the lead-out wiring according to this embodiment. Lead-out wiring 1 (wire 1 in the figure) and lead-out wiring 2 (wire 2 in the figure) are arranged adjacent to each other. Each of wires 1 and 2 is configured so that the lower layer wiring and the upper layer wiring are interchanged midway.

[0057] The two graphs on the left of Figure 10 show the resistance when the wiring widths of wire 1 and wire 2 are the same. When wire 1 and wire 2 are made thicker or thinner, the resistance may vary within the range indicated by the arrows.

[0058] The two graphs on the right of Figure 10 show the worst case scenario, where the lower layer wiring is thicker and the upper layer wiring is thinner. In this embodiment, even if the wiring widths of the lower layer wiring and the upper layer wiring are different, the resistances of wiring 1 and wiring 2 can be made approximately the same.

[0059] As a modification, when the contact 24 is disposed at the center of the lead-out wiring 20, the lower layer wiring 20A and the upper layer wiring 20B that constitute the lead-out wiring 20 may be configured to be made of different conductive materials.

[0060] [3] Effects of the embodiment In this embodiment, each of the lead-out wirings 20 is configured such that the lower layer wiring and the upper layer wiring are interchanged midway. In addition, the plurality of lead-out wirings 20 are arranged such that the lower layer wirings 20A and the upper layer wirings 20B are alternately arranged in the direction in which the plurality of lead-out wirings 20 are adjacent to each other (the direction perpendicular to the wiring).

[0061] Therefore, according to this embodiment, even if the wiring widths of the lower layer wiring 20A and the upper layer wiring 20B differ due to the manufacturing process, the difference in resistance among the plurality of lead-out wirings 20 can be reduced. Also, the difference in time constant among the plurality of lead-out wirings 20 can be reduced. This makes it possible to realize a liquid crystal display device 1 capable of improving display characteristics. Also, the occurrence of streaky unevenness on the screen can be suppressed.

[0062] Furthermore, the distance between the lower layer wiring and the upper layer wiring can be narrowed, which allows the liquid crystal display device 1 to have a narrower frame.

[0063] Furthermore, contacts 24 that connect the lower layer wiring 20A and the upper layer wiring 20B are arranged in the area below (on the integrated circuit 13 side of) the display area 2. This allows the left and right picture frame areas of the liquid crystal display device 1 to be narrowed.

[0064] In the above embodiment, a liquid crystal display device has been described as an example, but the present invention is not limited to this. The present embodiment can be applied to a display device having a plurality of scanning lines arranged in a pixel array. The present embodiment can also be applied to an organic electroluminescence (EL) display device, an electrophoretic display device, or the like.

[0065] The present invention is not limited to the above-described embodiments, and various modifications can be made in the implementation stage without departing from the spirit of the invention. Furthermore, the embodiments may be implemented in appropriate combinations, in which case the combined effects can be obtained. Furthermore, the above-described embodiments include various inventions, and various inventions can be extracted by combining selected elements from the disclosed elements. For example, if the problem can be solved and the desired effect can be obtained even if some elements are deleted from all elements shown in the embodiments, the configuration from which these elements are deleted can be extracted as an invention. [Explanation of symbols]

[0066] 1...liquid crystal display device, 2...display area, 3...peripheral area, 10...array substrate, 11...opposing substrate, 12...liquid crystal element, 13...integrated circuit, 14...switching element, 15...pixel electrode, 20...drawing wiring, 20A...lower layer wiring, 20B...upper layer wiring, 21...contact, 22...insulating layer, 23...insulating layer, 24...contact, GL...scanning line, SL...signal line.

Claims

1. a pixel array provided between opposing first and second substrates and having a plurality of pixels; a plurality of scan lines connected to the pixel array and extending in a first direction; an integrated circuit provided on the first substrate, arranged adjacent to the pixel array in a second direction perpendicular to the first direction, and configured to drive the pixel array; a plurality of lead-out wirings provided on the first substrate and connecting the plurality of scanning lines and the integrated circuit; Equipped with each of the plurality of lead-out wirings includes a lower layer wiring included in a first level wiring layer, an upper layer wiring included in a second level wiring layer disposed above the first level wiring layer via an insulating layer, and a contact connecting the lower layer wiring and the upper layer wiring; the plurality of lower layer wirings and the plurality of upper layer wirings are alternately arranged in a direction in which the plurality of lead-out wirings are adjacent to each other, each of the plurality of lead-out wirings includes a first portion extending from an end of the scanning line in the second direction, and a second portion extending in the first direction and extending from an end of the first portion toward the integrated circuit; The contact is disposed on the second portion. Display device.

2. The plurality of contacts are arranged so as not to overlap in the second direction. The display device according to claim 1 .

3. The plurality of contacts are arranged so that the more contacts included in the lead-out wiring arranged outside the pixel array, the farther they are from the integrated circuit. The display device according to claim 1 or 2.

4. The contact is disposed at the center of the entire length of the lead-out wiring. The display device according to claim 1 .

5. The contact is disposed at the center of the width of the lead-out wiring in a plan view. The display device according to claim 1 .

6. The lower layer wiring and the upper layer wiring are made of the same conductive material. The display device according to any one of claims 1 to 5.

7. The lower layer wiring and the upper layer wiring are made of different conductive materials. The display device according to any one of claims 1 to 5.

8. The pixel array includes a liquid crystal layer. The display device according to any one of claims 1 to 7.

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