Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device that has a resistive element and a capacitive element, and is reducible in area.SOLUTION: A semiconductor device comprises: a base 1 of a first conductivity type; a first diffusion layer 2 of a second conductivity type provided on the base 1; conductive layers 6a to 6f embedded in trenches 4a to 4f provided on the first diffusion layer 2 across an insulation film 5 to constitute a capacitive element with the first diffusion layer 2 and insulation film 5; and a second diffusion layer 3 of the first conductivity type provided on the first diffusion layer 2 more shallowly than the trenches 4a to 4f to constitute a resistive element, wherein at least parts of the trenches 4a to 4f and at least a part of the second diffusion layer 3 being provided alternately.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] A known conventional RC filter is one that combines an n-type diffused resistor and a planar MOS capacitor. One terminal of the n-type diffused resistor is connected to one terminal of the MOS capacitor. The other terminal of the MOS capacitor is applied with ground (GND) potential. The other terminal of the n-type diffused resistor is the input, and the connection point between the n-type diffused resistor and the MOS capacitor is the output. The n-type diffused resistor is serpentine to provide high resistance.

[0003] Patent Document 1 discloses a semiconductor integrated circuit in which an LC filter is formed by forming an inductor element above a capacitor formed on a semiconductor substrate. Patent Document 2 discloses a semiconductor device in which a resistor made of second polycrystalline silicon doped with impurities and having a desired resistance value is embedded in a vertical groove in a substrate, via a capacitive insulating film, a first polycrystalline silicon film heavily doped with impurities, and a silicon oxide film. Patent Document 3 discloses a low-pass filter including large-capacity and small-capacity capacitors connected in parallel, the large-capacity capacitor connected in series with a resistor. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-288104 [Patent Document 2] Patent No. 3161412 specification [Patent Document 3] Patent No. 4704329 specification Summary of the Invention [Problem to be solved by the invention]

[0005] However, in a semiconductor device having resistors, inductors, and capacitors of various conventional filters, the resistors, inductors, and capacitors are arranged in separate regions, resulting in a large surface area.

[0006] In view of the above problems, an object of the present invention is to provide a semiconductor device having a resistor element and a capacitor element, which can reduce the area, and a method for manufacturing the same. [Means for solving the problem]

[0007] One aspect of the present invention is a semiconductor device comprising: (a) a substrate of a first conductivity type; (b) a first diffusion layer of a second conductivity type provided on the substrate; (c) a conductive layer embedded in a trench provided on the first diffusion layer via an insulating film and constituting a capacitance element together with the first diffusion layer and the insulating film; and (d) a second diffusion layer of the first conductivity type provided on the first diffusion layer shallower than the trench and constituting a resistance element, wherein at least a portion of the trench and at least a portion of the second diffusion layer are alternately arranged.

[0008] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising the steps of: (a) forming a first diffusion layer of a second conductivity type on top of a substrate of a first conductivity type; (b) forming a second diffusion layer of the first conductivity type on top of the first diffusion layer, the second diffusion layer constituting a resistive element; (c) forming a trench on top of the first diffusion layer that is deeper than the second diffusion layer; and (d) burying a conductive layer in the trench via an insulating film, the conductive layer constituting a capacitive element together with the first diffusion layer and the insulating film, wherein at least a portion of the trench and at least a portion of the second diffusion layer are formed alternately. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a semiconductor device having a resistor element and a capacitor element, and a method for manufacturing the same, which can reduce the area. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along line AA′ in FIG. 2. [Figure 4] FIG. 3 is another plan view of the semiconductor device according to the first embodiment. [Figure 5] FIG. 10 is a plan view of a semiconductor device according to a comparative example. [Figure 6] FIG. 6 is a cross-sectional view taken along line AA′ in FIG. 5. [Figure 7] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 8 is a cross-sectional view continuing from FIG. 7 for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 9] FIG. 9 is a cross-sectional view continuing from FIG. 8 for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view continuing from FIG. 9 for illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 11 is a cross-sectional view continuing from FIG. 10 for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 12] 11 is a cross-sectional view continuing from FIG. 10 for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 13] FIG. 10 is a plan view of a semiconductor device according to a second embodiment. [Figure 14] FIG. 10 is a plan view of a semiconductor device according to a third embodiment. [Figure 15] FIG. 10 is a plan view of a semiconductor device according to a fourth embodiment. [Figure 16] FIG. 10 is a plan view of a semiconductor device according to a fifth embodiment. [Figure 17] FIG. 10 is a plan view of a semiconductor device according to a sixth embodiment. [Figure 18] FIG. 13 is a plan view of a semiconductor device according to a seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, first to seventh embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the first to seventh embodiments shown below are examples of devices and methods for embodying the technical concept of the present invention, and the technical concept of the present invention does not limit the materials, shapes, structures, arrangements, etc. of component parts to those described below.

[0012] Furthermore, in this specification, the case where the semi-first conductivity type is n-type and the second conductivity type is p-type will be described as an example. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. Furthermore, the "+" or "-" attached to the "p" or "n" indicating the conductivity type of a semiconductor region indicates a semiconductor region with a relatively higher or lower impurity concentration, respectively, compared to a semiconductor region without the "+" or "-" attached. However, semiconductor regions with the same "p" and "p" attached do not necessarily have the same impurity concentration. Furthermore, in the following description, components or regions that are limited to "p-type" or "n-type" refer to components or regions made of semiconductor material, even if there is no explicit limitation.

[0013] Furthermore, the definitions of directions such as up and down in this specification are merely for the convenience of explanation and do not limit the technical concept of the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are inverted and read as such.

[0014] (First embodiment) As shown in Fig. 1, the semiconductor device according to the first embodiment includes an RC filter consisting of a resistor R and a capacitor C. An input signal IN is input to one end of the resistor R. One end of the capacitor C is connected to the other end of the resistor R. A ground (GND) potential is applied to the other end of the capacitor C. An output signal OUT is output from the connection point between the other end of the resistor R and the one end of the capacitor C. The RC filter shown in Fig. 1 may be, for example, a component of a high-side power IC.

[0015] Fig. 2 shows a planar layout of the RC filter shown in Fig. 1. Fig. 3 shows a cross-sectional view taken along line AA' in Fig. 2. As shown in Figs. 2 and 3, the semiconductor device according to the first embodiment includes an n-type substrate 1. The substrate 1 may be, for example, an n-type + The substrate 1 may be an epitaxially grown layer formed on a semiconductor substrate of the same type. The substrate 1 is made of, for example, silicon (Si), but may also be made of a semiconductor (wide bandgap semiconductor) with a wider bandgap than Si, such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), or aluminum nitride (AlN).

[0016] 2 and 3, a p-type diffusion layer (first diffusion layer) 2 is provided on the upper part of a base 1. The first diffusion layer 2 has a substantially rectangular planar pattern. An n-type diffusion layer (second diffusion layer) 3 is provided on the upper part of the first diffusion layer 2. The second diffusion layer 3 forms a resistive element (diffused resistor) and corresponds to the resistor R shown in FIG.

[0017] The second diffusion layer 3 has a meandering planar pattern. The second diffusion layer 3 has a plurality of stripe portions 3a-3e and a plurality of connection portions 3f-3i. The stripe portions 3a-3e extend parallel to each other and are arranged side by side in a direction perpendicular to the extending direction.

[0018] The multiple connecting portions 3f-3i connect adjacent stripes 3a-3e. Connecting portion 3f connects the ends of stripes 3a and 3b. Connecting portion 3g connects the ends of stripes 3b and 3c on the opposite side of connecting portion 3f. Connecting portion 3h connects the ends of stripes 3c and 3d on the same side of connecting portion 3f but opposite connecting portion 3g. Connecting portion 3i connects stripes 3d and 3e on the opposite side of connecting portions 3f and 3h but on the same side of connecting portion 3g.

[0019] 2 and 3 show five stripes 3a to 3e as an example, the number of stripes in the second diffusion layer 3 is not particularly limited and may be 1 to 4, or 6 or more. The number of stripes in the second diffusion layer 3 and the number of connecting portions connecting the stripes can be appropriately selected depending on the resistance value required for the resistor element formed by the second diffusion layer 3.

[0020] The stripes 3a-3e and the connecting portions 3f-3i may have the same width or different widths, for example. The stripes 3a-3e may have the same width or different widths, and the connecting portions 3f-3i may have the same width or different widths.

[0021] 2 and 3, trenches 4a to 4f are provided in the upper part of the first diffusion layer 2. The trenches 4a to 4f are provided shallower than the first diffusion layer 2. The bottoms of the trenches 4a to 4f are located shallower than the bottom surface of the first diffusion layer 2. The trenches 4a to 4f are provided deeper than the second diffusion layer 3. The bottoms of the trenches 4a to 4f are located deeper than the bottom surface of the second diffusion layer 3.

[0022] The trenches 4a to 4d have a stripe-like planar pattern extending parallel to each other. The trenches 4a to 4d are arranged side by side in a direction perpendicular to the direction in which they extend. The trenches 4a to 4d are arranged alternately with the stripe portions 3a to 3e of the second diffusion layer 3.

[0023] The trench 4a is provided between the stripe portions 3a and 3b of the second diffusion layer 3. The trench 4b is provided between the stripe portions 3b and 3c of the second diffusion layer 3. The trench 4c is provided between the stripe portions 3c and 3d of the second diffusion layer 3. The trench 4d is provided between the stripe portions 3d and 3e of the second diffusion layer 3.

[0024] One side of stripe portion 3a, located at one end of the arrangement of stripe portions 3a to 3e of second diffusion layer 3, contacts trench 4a, and the width of stripe portion 3a is determined by trench 4a. Both side surfaces of stripe portion 3b contact trenches 4a and 4b, and the width of stripe portion 3b is determined by trenches 4a and 4b. Both side surfaces of stripe portion 3c contact trenches 4b and 4c, and the width of stripe portion 3c is determined by trenches 4b and 4c. Both side surfaces of stripe portion 3d contact trenches 4c and 4d, and the width of stripe portion 3d is determined by trenches 4c and 4d. One side surface of stripe portion 3e, located at the other end of the arrangement of stripe portions 3a to 3e of second diffusion layer 3, contacts trench 4d, and the width of stripe portion 3e is determined by trench 4d.

[0025] One side of connection portion 3f of second diffusion layer 3 contacts trench 4a, and the width of connection portion 3f is determined by trench 4a. One side of connection portion 3g of second diffusion layer 3 contacts trench 4b, and the width of connection portion 3g is determined by trench 4b. One side of connection portion 3h of second diffusion layer 3 contacts trench 4c, and the width of connection portion 3h is determined by trench 4c. One side of connection portion 3i of second diffusion layer 3 contacts trench 4d, and the width of connection portion 3i is determined by trench 4d.

[0026] Trench 4e has a planar pattern extending in a direction perpendicular to the extension direction of trenches 4a to 4d, and is connected to one end of trenches 4a and 4c in the longitudinal direction. Trench 4f is provided on the opposite side of trench 4e, with trenches 4a to 4d in between. Trench 4f has a striped planar pattern extending in a direction perpendicular to the extension direction of trenches 4a to 4d, and is connected to one end of trenches 4b and 4d in the longitudinal direction.

[0027] 2 and 3, conductive layers 6a to 6f are buried in the trenches 4a to 4f via an insulating film 5. The first diffusion layer 2, the insulating film 5, and the conductive layers 6a to 6f form a trench-type capacitive element (2, 5, 6a to 6f), which corresponds to the capacitance C shown in FIG.

[0028] The conductive layers 6a to 6d have a striped planar pattern extending parallel to each other. The conductive layer 6a is provided between the stripe portions 3a and 3b of the second diffusion layer 3 with the insulating film 5 interposed therebetween. The conductive layer 6b is provided between the stripe portions 3b and 3c of the second diffusion layer 3 with the insulating film 5 interposed therebetween. The conductive layer 6c is provided between the stripe portions 3c and 3d of the second diffusion layer 3 with the insulating film 5 interposed therebetween. The conductive layer 6d is provided between the stripe portions 3d and 3e of the second diffusion layer 3 with the insulating film 5 interposed therebetween.

[0029] The conductive layer 6e has a planar pattern extending in a direction perpendicular to the extension direction of the conductive layers 6a to 6d, and is connected to one end of the conductive layers 6a and 6c in the longitudinal direction. The conductive layer 6f is provided on the opposite side of the conductive layers 6a to 6d from the conductive layer 6e, with the conductive layers 6a to 6d in between. The conductive layer 6f has a planar pattern extending in a direction perpendicular to the extension direction of the conductive layers 6a to 6d, and is connected to one end of the conductive layers 6b and 6d in the longitudinal direction.

[0030] The insulating film 5 may be, for example, a silicon oxide film (SiO2 film), but other than SiO2 film, silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si3N4) film, or aluminum oxide (Al2O3) film may also be used. Alternatively, magnesium oxide (MgO) film, yttrium oxide (YO3) film, hafnium oxide (HfO2) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, or bismuth oxide (Bi2O3) film may also be used. Furthermore, composite films formed by selecting and stacking several of these single-layer films may also be used.

[0031] The conductive layers 6a to 6f may be made of, for example, polysilicon (doped polysilicon) doped with a high concentration of n-type or p-type impurities, or may be made of, other than doped polysilicon (DOPOS), such as tungsten (W), molybdenum (Mo), titanium (Ti), or other high-melting-point metals, or silicides of high-melting-point metals and polysilicon. Furthermore, the conductive layers 6a to 6f may be made of polycide, which is a composite film of polysilicon and silicide of a high-melting-point metal.

[0032] As shown in FIG. 3, an insulating film 7 is provided on the upper surface of the substrate 1. The insulating film 7 is made of, for example, a field oxide film such as a local insulating film (LOCOS film). The insulating film 7 has an opening 7a that defines an active region along the periphery of the first diffusion layer 2. In FIG. 2, the insulating film 7 is not shown, and the opening 7a in the insulating film 7 is schematically indicated by a dashed line. Note that interlayer insulating films are also provided on the upper surfaces of the first diffusion layer 2, the second diffusion layer 3, the insulating film 5, and the conductive layers 6a to 6f, but are not shown in FIGS. 2 and 3.

[0033] Fig. 4 is a planar layout in which wirings 11 to 13 are added to the planar layout shown in Fig. 2. An end of the stripe portion 3e, which is one end of the second diffusion layer 3, is connected to the wiring 11 through a via 21. An input signal IN is input to the wiring 11.

[0034] The wiring 12 is connected to the end of the stripe portion 3a, which is the other end of the second diffusion layer 3, via a via 22. Furthermore, a conductive layer 6e is connected to the wiring 12 via a via 23. Furthermore, a conductive layer 6f is connected to the wiring 12 via a via 24. The wiring 12 serves as a connection point between the resistance element formed by the second diffusion layer 3 and the capacitance elements (2, 5, 6a to 6f). The capacitance elements (2, 5, 6a to 6f) are configured by a parallel connection of a capacitance section (2, 5, 6a, 6c, 6e) including the conductive layers 6a, 6c, 6e and a capacitance section (2, 5, 6b, 6d, 6f) including the conductive layers 6b, 6d, 6f. An output signal OUT is output from the wiring 12.

[0035] The first diffusion layer 2 is connected to the wiring 13 through a via 25. A GND potential is applied to the wiring 13.

[0036] <Comparative Example> Next, a semiconductor device according to a comparative example will be described. The circuit configuration of the semiconductor device according to the comparative example is the same as that of the RC filter shown in Fig. 1. As shown in Figs. 5 and 6, the semiconductor device according to the comparative example includes a p-type diffusion layer 102 provided on an n-type substrate 101. An n-type diffusion layer 103 that constitutes a resistor element is provided above the p-type diffusion layer 102. The n-type diffusion layer 103 has a serpentine planar pattern.

[0037] A conductive layer 109 made of polysilicon is provided on the upper surface of the p-type diffusion layer 102 via an insulating film 108. The p-type diffusion layer 102, the insulating film 108, and the conductive layer 109 form a MOS-type capacitance element (102, 108, 109).

[0038] 6, an insulating film 107 is provided on the upper surface of the p-type diffusion layer 102. The insulating film 107 has an opening 107a surrounding the periphery of the n-type diffusion layer 103 and an opening 107b surrounding the periphery of the capacitive elements (102, 108, 109). In FIG. 5, the insulating film 107 is not shown, and the openings 107a and 107b are schematically indicated by dashed lines.

[0039] As shown in FIG. 5, a wiring 111 is connected to one end of the n-type diffusion layer 103 through a via 121. An input signal IN is input to the wiring 111. A wiring 112 is connected to the other end of the n-type diffusion layer 103 through a via 122. The wiring 112 is connected to the conductive layer 109 through a via 123. The wiring 112 serves as a connection point between the resistive element formed by the n-type diffusion layer 103 and the capacitive elements (102, 108, 109), and outputs an output signal OUT. A wiring 113 is connected to the p-type diffusion layer 102 through a via 124. A GND potential is applied to the wiring 113.

[0040] In the semiconductor device according to the comparative example, as shown in Figures 5 and 6, the resistive element formed by the n-type diffusion layer 103 and the capacitive elements (102, 108, 109) are formed in separate regions, resulting in a large area. In contrast, in the semiconductor device according to the first embodiment, as shown in Figures 2 to 4, trenches 4a to 4d and stripe portions 3a to 3e of the second diffusion layer 3 are alternately provided, and the resistive element formed by the second diffusion layer 3 and the trench-type capacitive elements (2, 5, 6a to 6f) are arranged closely to each other. This makes it possible to reduce the area of ​​the RC filter, thereby realizing an RC filter with good area efficiency.

[0041] 5 and 6, n-type impurities are ion-implanted using a mask having openings in a serpentine pattern to form the n-type diffusion layer 103. However, because the implanted n-type impurities diffuse laterally due to heat treatment after the ion implantation, it is necessary to ensure in advance the spacing between the stripes of the serpentine pattern of the second diffusion layer 3. In contrast, in the semiconductor device according to the first embodiment, as shown in FIGS. 2 to 4, the widths of the stripes 3a to 3e of the second diffusion layer 3 are defined (defined) by the spacing between the trenches 4a to 4d, thereby narrowing the spacing between the stripes 3a to 3e of the second diffusion layer 3 and reducing the area of ​​the resistor element formed by the second diffusion layer 3.

[0042] <Method of manufacturing a semiconductor device> Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to Figures 7 to 12. The right side of Figures 7 to 12 shows the manufacturing process of the RC filter of the semiconductor device according to the first embodiment, and the left side of Figures 7 to 12 shows the manufacturing process of a trench-gate metal oxide semiconductor field effect transistor (MOSFET), which is a power semiconductor element formed on the same semiconductor chip as the RC filter.

[0043] First, as shown in Figure 7, + An n-type semiconductor substrate 10 is prepared, and an n-type base 1 is epitaxially grown on the upper surface of the semiconductor substrate 10.

[0044] Next, photolithography and ion implantation steps are repeatedly performed to implant p-type and n-type impurities into the substrate 1. Next, the implanted p-type and n-type impurities are activated by heat treatment. As a result, as shown on the right side of FIG. 8, a p-type first diffusion layer 2 is formed on the substrate 1, and an n-type second diffusion layer 3 is formed on the first diffusion layer 2. Furthermore, as shown on the left side of FIG. 8, a p-type diffusion layer 31 and a p-type base region 32 for a trench gate MOSFET are formed.

[0045] Next, a photoresist film is applied to the upper surface of the substrate 1, and the photoresist film is patterned by photolithography. Using the patterned photoresist film as a mask, trenches 4a-4d are formed by dry etching, as shown on the right side of FIG. 9. At this time, trenches 4e and 4f shown in FIG. 2 are also formed simultaneously. As a result, portions of the second diffusion layer 3 are selectively removed by the trenches 4a-4d, and the widths of the stripe portions 3a-3e and the connection portions 3f-3i are defined (defined). Furthermore, as shown on the left side of FIG. 9, trenches 34a and 34b are formed for burying the gate electrode structure of a trench-gate MOSFET.

[0046] Next, as shown in FIG. 10, an insulating film 7 made of a LOCOS film is selectively (locally) formed by a local oxidation of silicon (LOCOS) method or the like.

[0047] Next, an insulating film is formed on the entire surface, including the trenches 4a-4f and the trenches 34a, 34b, by thermal oxidation or the like. Next, a polysilicon layer doped with a high concentration of impurities is deposited by CVD or the like so as to fill the trenches 4a-4f and the trenches 34a, 34b via the insulating film. Then, photolithography and dry etching are used to selectively remove portions of the insulating film and polysilicon layer. As a result, as shown on the right side of FIG. 11, conductive layers 6a-6d are filled in the trenches 4a-4d via the insulating film 5. At the same time, conductive layers 6e, 6f are also filled in the trenches 4e, 4f shown in FIG. 2 via the insulating film 5. Furthermore, as shown on the left side of FIG. 11, gate electrodes 36a, 36b are filled in the trenches 34a, 34b via the gate insulating film 35, forming gate electrode structures (35, 36a, 36b).

[0048] Next, photolithography and ion implantation steps are repeated to implant p-type impurities and n-type impurities into the substrate 1. Next, the implanted p-type impurities and n-type impurities are activated by heat treatment. As a result, as shown on the left side of FIG. 12, the n-type impurities of the trench gate MOSFET are formed above the base region 32. + The source regions 37a, 37b and p + The contact region 38 is formed. + A trench gate MOSFET is formed using a semiconductor substrate 10 as a drain region.

[0049] 3, and wiring such as gate wiring and source electrodes for trench gate MOSFETs are formed on the upper surface of the base 1. Furthermore, drain electrodes and the like for trench gate MOSFETs are formed on the lower surface of the base 1, thereby completing the semiconductor device according to the first embodiment.

[0050] According to the manufacturing method of the semiconductor device of the first embodiment, the trenches 4a to 4f for forming the trench-type capacitance elements (2, 5, 6a to 6f) can be formed in the same process as the trenches 34a, 34b for the trench-gate MOSFET, thereby suppressing an increase in the number of steps.

[0051] (Second embodiment) 13, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 3 in that connection portions 3f-3h of the second diffusion layer 3 contact trenches 4e, 4f. Connection portions 3f, 3h of the second diffusion layer 3 contact trench 4f. Connection portion 3g of the second diffusion layer 3 contacts trench 4e. Other configurations of the semiconductor device according to the second embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore redundant explanations will be omitted.

[0052] In the semiconductor device according to the second embodiment, the area of ​​the RC filter can be reduced by arranging the resistive element formed by the second diffusion layer 3 and the trench-type capacitive elements (2, 5, 6a to 6f) closely together. Furthermore, by having the connecting portions 3f to 3h of the second diffusion layer 3 contact the trenches 4e and 4f, the area can be further reduced compared to when the connecting portions 3f to 3h of the second diffusion layer 3 are spaced apart from the trenches 4e and 4f.

[0053] (Third embodiment) 14, the semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 3 in that the second diffusion layer 3 has only a plurality of stripe portions 3a to 3e and does not have a connecting portion connecting adjacent stripe portions 3a to 3e. The plurality of stripe portions 3a to 3e are separated by trenches 4a to 4d provided between the stripe portions 3a to 3e.

[0054] The semiconductor device according to the third embodiment further includes relay wirings 14 to 17 in addition to the wirings 11 to 13. Relay wiring 14 is connected to one end of stripe portion 3a through via 41 and to one end of stripe portion 3b through via 42. Relay wiring 15 is connected to the other end of stripe portion 3b through via 43 and to one end of stripe portion 3c through via 44.

[0055] The relay wiring 16 is connected to the other end of the stripe portion 3c through a via 45 and to one end of the stripe portion 3d through a via 46. The relay wiring 17 is connected to the other end of the stripe portion 3d through a via 47 and to one end of the stripe portion 3e through a via 48. The plurality of stripe portions 3a to 3e of the second diffusion layer 3 are connected in series by the relay wirings 14 to 17 to form a resistor element. The other configuration of the semiconductor device according to the third embodiment is similar to that of the semiconductor device according to the first embodiment, so a duplicated description will be omitted.

[0056] According to the semiconductor device of the third embodiment, the area of ​​the RC filter can be reduced by arranging the resistive element formed by the second diffusion layer 3 and the trench-type capacitive elements (2, 5, 6a to 6f) in close proximity to each other. Furthermore, when the plurality of stripe portions 3a to 3e are separated and connected by relay wirings 14 to 17, any of the plurality of stripe portions 3a to 3e can be selectively connected by changing the configuration of the relay wirings 14 to 17. This makes it easy to adjust the resistance value of the resistive element formed by the second diffusion layer 3.

[0057] (Fourth embodiment) As shown in Fig. 15, the semiconductor device according to the fourth embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 3 in that some of the trenches 4a to 4f, namely, trenches 4c and 4d, are separated to form dummy trenches. Trench 4c is separated from trench 4e. Trench 4d is separated from trench 4f. The trenches to be separated from the trenches 4a to 4f are not limited to trenches 4c and 4d, and can be selected as appropriate. The other configurations of the semiconductor device according to the fourth embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0058] According to the semiconductor device of the fourth embodiment, the area of ​​the RC filter can be reduced by arranging the resistive element formed by the second diffusion layer 3 and the trench-type capacitive elements (2, 5, 6a to 6f) closely together. Furthermore, even when it is desired to suppress the capacitance value due to the characteristics of the RC filter, the capacitance value of the trench-type capacitive elements (2, 5, 6a, 6b, 6e, 6f) can be adjusted by dividing a part of the trenches 4a to 4f.

[0059] (Fifth embodiment) 16, the semiconductor device according to the fifth embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 3 in that the stripe portions 3a to 3e of the second diffusion layer 3 are spaced apart from the trenches 4a to 4d. The first diffusion layer 2 is provided between the stripe portions 3a to 3e of the second diffusion layer 3 and the trenches 4a to 4d.

[0060] The widths of the stripe portions 3a to 3e are not defined by the trenches 4a to 4d. Therefore, when manufacturing the semiconductor device according to the fifth embodiment, n-type impurity ions are implanted using a mask having a serpentine-shaped opening to form the serpentine shape of the second diffusion layer 3. The other configurations of the semiconductor device according to the fifth embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0061] In the semiconductor device according to the fifth embodiment, the area of ​​the RC filter can be reduced by arranging the resistive element formed by the second diffusion layer 3 and the trench-type capacitive elements (2, 5, 6a to 6f) close to each other. Furthermore, the parasitic capacitance can be reduced by separating the stripe portions 3a to 3e of the second diffusion layer 3 from the trenches 4a to 4d.

[0062] (Sixth embodiment) As shown in FIG. 17, the semiconductor device according to the sixth embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 3 in that the configuration of the wirings 11 to 13, 51 is changed, and the resistive element formed by the second diffusion layer 3 and the capacitive elements (2, 5, 6a to 6f) are provided as separate elements.

[0063] The wiring 11 is connected to the stripe portion 3e, which is one end of the second diffusion layer 3, via a via 21. The wiring 12 is connected to the stripe portion 3a, which is the other end of the second diffusion layer 3, via a via 22. The wiring 13 is connected to the first diffusion layer 2 via a via 25. The wiring 51 is connected to the conductive layer 6c via a via 23 and to the conductive layer 6d via a via 24. That is, the resistive element formed by the second diffusion layer 3 and the capacitive elements (2, 5, 6a to 6f) are provided as individual elements without constituting an RC filter. The other configuration of the semiconductor device according to the sixth embodiment is the same as that of the semiconductor device according to the first embodiment, so a duplicated description will be omitted.

[0064] According to the semiconductor device of the sixth embodiment, even if the resistive element formed by the second diffusion layer 3 and the capacitive elements (2, 5, 6a to 6f) are provided as separate elements, the area can be reduced by arranging the resistive element formed by the second diffusion layer 3 and the trench-type capacitive elements (2, 5, 6a to 6f) in close proximity to each other.

[0065] That is, as long as the configuration includes a resistive element formed by the second diffusion layer 3 and trench-type capacitive elements (2, 5, 6a to 6f), it may be configured other than an RC filter. For example, the resistive element formed by the second diffusion layer 3 and the capacitive elements (2, 5, 6a to 6f) may not be connected and may be used as elements of completely different circuits. As a specific example, the resistive element formed by the second diffusion layer 3 may be used in a dividing circuit, and the capacitive elements (2, 5, 6a to 6f) may be combined with other elements to configure a delay circuit (timer) that utilizes the charging and discharging of the capacitive elements (2, 5, 6a to 6f).

[0066] Seventh embodiment 18, the semiconductor device according to the seventh embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 3 in that the trench 4 and the second diffusion layer 3 have a spiral planar pattern. One end of the second diffusion layer 3 is connected to the wiring 11 through a via 21. The other end of the second diffusion layer 3 is connected to the wiring 12 through a via 22. A conductive layer 6 is provided in the trench 4 with an insulating film 5 interposed therebetween. The conductive layer 6 is connected to the wiring 12 through a via 23. The first diffusion layer 2 is connected to the wiring 13 through a via 25. The other configuration of the semiconductor device according to the seventh embodiment is similar to that of the semiconductor device according to the first embodiment, and therefore a repeated description will be omitted.

[0067] According to the semiconductor device of the seventh embodiment, even when the trench 4 and the second diffusion layer 3 have a spiral planar pattern, the area of ​​the RC filter can be reduced by arranging the resistive element formed by the second diffusion layer 3 and the trench-type capacitive elements (2, 5, 6a to 6f) in close proximity to each other.

[0068] (Other embodiments) As described above, the present invention has been described with reference to the first to seventh embodiments, but the descriptions and drawings that form part of this disclosure should not be construed as limiting the present invention. Various alternative embodiments, examples, and application techniques will become apparent to those skilled in the art from this disclosure.

[0069] For example, the semiconductor devices according to the first to seventh embodiments are applicable to any configuration having a resistive element and a capacitive element, and are also applicable to power integrated circuits (power ICs) and general ICs other than power ICs.

[0070] In the first semiconductor device manufacturing method, a trench gate type MOSFET is formed simultaneously with the RC filter. + The drain region formed in the semiconductor substrate 10 is p + Alternatively, an insulated gate bipolar transistor may be formed with a collector region of the same type.

[0071] Furthermore, in the semiconductor devices according to the first to seventh embodiments, the planar pattern of the second diffusion layer 3 has been illustrated as being serpentine or spiral, but this is not limiting. That is, in order to arrange the resistive element formed by the second diffusion layer 3 and the trench-type capacitive element in close proximity to each other, it is sufficient that at least a portion of the trenches constituting the trench-type capacitive element and at least a portion of the second diffusion layer are alternately arranged. For example, two trenches may sandwich one stripe portion of the second diffusion layer, or one trench may be sandwiched between two stripe portions of the second diffusion layer.

[0072] Furthermore, the configurations disclosed in the first to seventh embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description. [Explanation of symbols]

[0073] 1...Base 2...p-type diffusion layer 3...n-type diffusion layer 3a~3e...Striped section 3f~3i...Connection 4, 4a to 4f...Trench 5...Insulating film 6, 6a to 6f...Conductive layer 7...Insulating film 7a...Opening 10...Semiconductor substrate 11~13,51...Wiring 14~17...Relay wiring 21~25...Beer 31...p-type diffusion layer 32...p-type base region 34a, 34b...Trench 35...Gate insulating film 36a, 36b...gate electrodes 37a, 37b...Source region 38...Contact area 41~48...Beer 101...Base 102...p-type diffusion layer 103...n-type diffusion layer 107...insulating film 107a, 107b...opening 108...insulating film 109...Conductive layer 111~113...Wiring 121~124...Beer C…Capacity R…Resistance

Claims

1. a substrate of a first conductivity type; a first diffusion layer of a second conductivity type provided on the upper portion of the substrate; a conductive layer embedded in a trench provided above the first diffusion layer via an insulating film, the conductive layer constituting a capacitance element together with the first diffusion layer and the insulating film; a second diffusion layer of the first conductivity type that is shallower than the trench and above the first diffusion layer, and that constitutes a resistor element; Equipped with At least a portion of the trench and at least a portion of the second diffusion layer are alternately provided.

2. 2. The semiconductor device according to claim 1, wherein at least a part of the side surface of the second diffusion layer contacts the trench.

3. 3. The semiconductor device according to claim 2, wherein the width of at least a part of the second diffusion layer is defined by the interval between adjacent trenches.

4. The semiconductor device according to claim 1 , wherein at least a part of the side surface of the second diffusion layer is spaced apart from the trench.

5. the second diffusion layer has a plurality of stripe portions extending parallel to each other, The plurality of stripes are alternately provided with the trenches.

3. The semiconductor device according to claim 1, wherein the first insulating film is a semiconductor material.

6. 6. The semiconductor device according to claim 5, wherein the second diffusion layer has a meandering planar pattern.

7. 6. The semiconductor device according to claim 5, wherein the plurality of stripe portions are separated from one another by the trenches and electrically connected to one another by relay wiring.

8. 3. The semiconductor device according to claim 1, wherein the second diffusion layer has a spiral planar pattern.

9. 3. The semiconductor device according to claim 1, wherein the resistive element and the capacitive element form an RC filter.

10. 3. The semiconductor device according to claim 1, further comprising a trench gate type semiconductor element provided on the substrate.

11. 6. The semiconductor device according to claim 5, wherein a part of the trench constitutes a dummy trench.

12. forming a first diffusion layer of a second conductivity type on a substrate of a first conductivity type; forming a second diffusion layer of a first conductivity type constituting a resistor element on the first diffusion layer; forming a trench deeper than the second diffusion layer above the first diffusion layer; a step of burying a conductive layer that constitutes a capacitance element together with the first diffusion layer and the insulating film in the trench via an insulating film; Including, a second diffusion layer formed on the second insulating layer and a second insulating layer formed on the second insulating layer;

13. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the step of forming the trench defines a width of the second diffusion layer as the resistor element by removing a part of the second diffusion layer by the trench.

14. 14. The method for manufacturing a semiconductor device according to claim 12, wherein the step of forming the trench is carried out simultaneously with a step of forming a trench for burying a gate electrode structure of a trench-gate type semiconductor element formed on the base.

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