Semiconductor device manufacturing method

Abstract

To highly accurately form an impurity implantation region at the time of ion implantation to an SiC substrate.SOLUTION: A manufacturing method of a semiconductor device includes a first step of implanting a first conductivity type impurity to an SiC substrate and a second step of implanting a second conductivity type impurity to the SiC substrate. In a thickness direction of the SiC substrate, there is included a decrease region where a concentration of the first conductivity type impurity continuously decreases as concentration distribution of the first conductivity type impurity implanted in the first step separates from a position of a first peak value. In the thickness direction of the SiC substrate, concentration distribution of the second conductivity type impurity implanted in the second step has a second peak value. A position of the second peak value overlaps a specific region which is the inside of the decrease region and has the concentration of the first conductivity type impurity equal to or higher than 10% of the first peak value. The position of the first peak value becomes a first conductivity type region. At least a portion of the specific region becomes a second conductivity type region.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device.

[0002] Patent Document 1 discloses a technique for ion-implanting impurities into a SiC substrate (that is, a semiconductor substrate made of silicon carbide). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-015978 Summary of the Invention [Problem to be solved by the invention]

[0004] When ions are implanted into a SiC substrate, the implanted impurities diffuse over a wide area. This makes it difficult to form an impurity-implanted region with high precision. Since thermal diffusion of impurities is difficult to occur during activation annealing in a SiC substrate, forming an impurity-implanted region with high precision during ion implantation leads to improved accuracy in forming p-type or n-type regions. This specification proposes a technology for forming an impurity-implanted region with high precision during ion implantation into a SiC substrate. [Means for solving the problem]

[0005] The present specification discloses a method for manufacturing a semiconductor device, which includes a first step of implanting a first-conductivity-type impurity into a SiC substrate and a second step of implanting a second-conductivity-type impurity into the SiC substrate, and the first and second steps are performed to satisfy the following conditions: a concentration distribution of the first-conductivity-type impurity implanted in the first step in a thickness direction of the SiC substrate has a first peak value that is a maximum value and a decrease region in which the first-conductivity-type impurity concentration continuously decreases with increasing distance from the first peak value; a concentration distribution of the second-conductivity-type impurity implanted in the second step in the thickness direction of the SiC substrate has a second peak value that is a maximum value; the position of the second peak value overlaps with a region in the decrease region that has a first-conductivity-type impurity concentration that is 10% or more of the first peak value; the position of the first peak value corresponds to a first-conductivity-type region; and at least a portion of the specific region corresponds to a second-conductivity-type region.

[0006] One of the first conductivity type region and the second conductivity type region is p-type, and the other is n-type. That is, when the first conductivity type region is p-type, the second conductivity type region is n-type, and when the first conductivity type region is n-type, the second conductivity type region is p-type.

[0007] The first peak value, the second peak value, and the decreasing region are identified based on a distribution graph from which noise occurring during measurement of the impurity concentration has been removed.

[0008] In addition, either the first step or the second step may be carried out first.

[0009] In this manufacturing method, the concentration distribution of the first-conductivity-type impurity implanted in the first step has a first peak value, which is the maximum value, and a decrease region in which the first-conductivity-type impurity concentration continuously decreases with increasing distance from the first peak value. The decrease region is a region into which impurities are implanted due to variations in implantation depth during ion implantation. Furthermore, in this manufacturing method, the position of the second peak value in the concentration distribution of the second-conductivity-type impurity implanted in the second step overlaps with a specific region within the decrease region that has a first-conductivity-type impurity concentration that is 10% or more of the first peak value. At least a portion of the specific region becomes a second-conductivity-type region. Therefore, the first-conductivity-type region can be formed limited to the vicinity of the position of the first peak value. In this way, this manufacturing method enables the first-conductivity-type region to be formed with high precision. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is an explanatory diagram of the first step of the first embodiment. [Figure 2] FIG. 2(a) is a diagram showing the cross section of the concentration distribution of the p-type impurity implanted in the first step of Example 1, and FIG. 2(b) is a graph showing the p-type impurity concentration distribution at the position of line AA. [Figure 3] FIG. 2 is an explanatory diagram of the first process of the second step of Example 1. [Figure 4] FIG. 4(a) is a diagram showing the effective p-type impurity concentration distribution in a cross section after the second step of Example 1 is carried out, and FIG. 4(b) is a graph showing the impurity concentration distribution at the position of line AA. [Figure 5] FIG. 2 is an explanatory diagram of the second process of the second step in Example 1. [Figure 6] 1 is a cross-sectional view of a MOSFET manufactured by the manufacturing method of Example 1. FIG. [Figure 7] FIG. 10 is an explanatory diagram of the first step of Example 2. [Figure 8] FIG. 8(a) is a diagram showing the cross section of the concentration distribution of the p-type impurity implanted in the first step of Example 2, and FIG. 8(b) is a graph showing the concentration distribution of the p-type impurity at the position of line AA. [Figure 9] FIG. 10 is an explanatory diagram of the second step of the second embodiment. [Figure 10] FIG. 10(a) is a diagram showing the effective p-type impurity concentration distribution in a cross section after the second step of Example 2 is carried out, and FIG. 10(b) is a graph showing the impurity concentration distribution at the position of line AA. [Figure 11] 1 is a cross-sectional view of a MOSFET manufactured by the manufacturing method of Example 1. FIG. [Figure 12] 12 is an explanatory diagram of the manufacturing process of the MOSFET of FIG. 11. [Figure 13] 12 is an explanatory diagram of the manufacturing process of the MOSFET of FIG. 11. DETAILED DESCRIPTION OF THE INVENTION

[0011] In the exemplary manufacturing method disclosed herein, the position of the second peak value may overlap with the specific region that is shallower than the position of the first peak value.

[0012] In the exemplary manufacturing method disclosed herein, the position of the second peak value may overlap with the specific region that is located deeper than the position of the first peak value.

[0013] The above "shallow" means that the implantation distance of the impurity in the first step is short, and the above "deep" means that the implantation distance of the impurity in the first step is long.

[0014] The exemplary manufacturing method disclosed herein may further include a step of forming a mask having an opening on a surface of the SiC substrate, in which the first step may implant a first conductivity type impurity into the SiC substrate through the mask, and the second step may implant a second conductivity type impurity into the SiC substrate through the mask.

[0015] When implanting through a mask, the first conductivity type impurity tends to diffuse laterally (i.e., in a direction parallel to the surface of the semiconductor substrate) in the first step. By using the same mask as in the first step in the second step, the second conductivity type impurity can be diffused laterally in the second step. This allows the formation area of ​​the first conductivity type region to be limited laterally as well.

[0016] In one example of the manufacturing method disclosed herein, the opening may have a width of 3.5 μm or less.

[0017] In one example of the manufacturing method disclosed herein, a semiconductor device manufactured by the manufacturing method may have an active region and a p-type guard ring extending to surround the active region, and in this case, the first conductivity type region formed at the position of the first peak value may be the guard ring.

[0018] In one example of a manufacturing method disclosed herein, a semiconductor device manufactured by the manufacturing method may have a superjunction structure in which a plurality of p-type layers and a plurality of n-type layers are laterally alternately arranged in a drift region, and the first conductivity type region formed at the position of the first peak value may be the p-type layer of the superjunction structure. [Example]

[0019] The method for manufacturing the semiconductor device of Example 1 includes a mask formation step, a first step of implanting p-type impurities into the SiC substrate, and a second step of implanting n-type impurities into the SiC substrate.

[0020] In the mask formation step, as shown in FIG. 1, a mask 70 is formed on the upper surface 12a of the SiC substrate 12. The mask 70 has an opening 72. The SiC substrate 12 is made of n-type SiC. The n-type impurity concentration of the SiC substrate 12 is, for example, 1×10 15 cm -3 That's about it.

[0021] After the mask formation step, the first step is performed. In the first step, as shown in FIG. 1, p-type impurities are ion-implanted into the SiC substrate 12 through the mask 70. Therefore, the p-type impurities are implanted into the SiC substrate 12 from the upper surface 12a within the opening 72. Here, the p-type impurities are implanted along the thickness direction of the SiC substrate 12. Also, here, the p-type impurities are implanted multiple times while changing the acceleration energy. As a result, the p-type impurities are implanted at approximately the same concentration at each of the depths D1, D2, and D3.

[0022] FIG. 2 shows the concentration distribution of p-type impurities after the first process. FIG. 2(a) shows the same cross section as FIG. 1, with the concentration of p-type impurities indicated by the density of the hatching. FIG. 2(b) shows the concentration distribution of p-type impurities at the position of line AA in FIG. 2(a). Note that graphs G1 to G7 in FIG. 2(b) show the results of performing the first process by changing the width W of the opening 72. Graph G8 in FIG. 2(b) also shows the results of performing the first process without the mask 70 for reference.

[0023] As described above, in the first step, p-type impurities are implanted to a plurality of depths D1, D2, and D3. Therefore, within the depth range including the depths D1, D2, and D3, the p-type impurity concentration is a high value (for example, 8×10 17 cm -3) is distributed almost uniformly. Hereinafter, the region where the p-type impurity concentration is distributed almost uniformly at a high value is referred to as the primary region 50. A peak value Pmax of the p-type impurity is formed within the primary region 50. Above and below the primary region 50, there are decrease regions 52, 54, where the p-type impurity concentration continuously decreases with increasing distance from the primary region 50. Note that FIG. 2(b) shows the decrease region 52 of graph G7 as an example. The decrease regions 52, 54 are regions formed due to variations in the implantation depth of the p-type impurity in the first step. The decrease region 52 is formed on the upper side of the primary region 50 (i.e., on the shallower side in the implantation direction of the p-type impurity). In the decrease region 52, the p-type impurity concentration continuously decreases toward the upper side. The decrease region 54 is formed on the lower side of the primary region 50 (i.e., on the deeper side in the implantation direction of the p-type impurity). In the decrease region 54, the p-type impurity concentration continuously decreases toward the lower side.

[0024] Furthermore, an increase region 56 exists above the decrease region 52. The increase region 56 has a higher p-type impurity concentration than the upper end of the decrease region 52. The increase region 56 is a region into which p-type impurities scattered and reflected by the mask 70 are implanted. Therefore, as shown in graph G8 in FIG. 2(b), if the mask 70 does not exist, the increase region 56 will not be formed. Furthermore, as shown in graphs G1 to G7 in FIG. 2(b), the smaller the width W of the opening 72, the higher the p-type impurity concentration in the increase region 56 tends to be. This is thought to be because the smaller the width W of the opening 72, the more p-type impurities are scattered and reflected by the mask 70.

[0025] 2(a), a peripheral region 58 in which p-type impurities are distributed at a low concentration is formed at a position adjacent to the main region 50 in the lateral direction (i.e., the direction perpendicular to the ion implantation direction). The peripheral region 58 is a region into which p-type impurities scattered and reflected by the mask 70 are implanted.

[0026] As described above, in the first step, the p-type impurity is implanted not only into the main region 50, which is the target of implantation of the p-type impurity, but also into the surrounding decrease region 52, decrease region 54, increase region 56, and peripheral region 58.

[0027] The second step is performed after the first step. In the second step, n-type impurities are ion-implanted into the SiC substrate 12 through the mask 70. Therefore, the n-type impurities are implanted into the SiC substrate 12 from the upper surface 12a within the opening 72. Here, the n-type impurities are implanted along the thickness direction of the SiC substrate 12. The implantation depth and implantation concentration of the n-type impurities in the second step are set corresponding to the p-type impurity concentration distribution formed in the first step. Below, the second step will be described using as an example a case where p-type impurities are implanted in the first step as shown in graph G7 of FIG. 2(b). The second step includes a first process in which n-type impurities are implanted into the upper side of the main region 50 and a second process in which n-type impurities are implanted into the lower side of the main region 50.

[0028] In the first process, as shown in FIG. 3, n-type impurities are implanted multiple times above the main region 50 while changing the acceleration energy. As a result, the n-type impurities are implanted to multiple depths in the region above the main region 50. FIG. 4(b) shows a graph G10 of the concentration distribution of n-type impurities implanted into the SiC substrate 12 in the first process, superimposed on graph G7. Region 52a in FIG. 4(b) is a region in the decrease region 52 that has a p-type impurity concentration higher than 10% of the peak value Pmax. In the first process, n-type impurities are implanted at least once to a depth within region 52a. In the example shown in FIG. 4(b), n-type impurities are implanted into the decrease region 52 at depths D11, D12, and D13, including depths D12 and D13, within region 52a. Here, among depths D11 to D13, the closer the depth is to the main region 50, the higher the concentration of n-type impurities implanted. That is, the n-type impurity is implanted at the highest concentration at depth D13 closest to the main region 50, and at the lowest concentration at depth D11 farthest from the main region 50. Therefore, in the decrease region 52, a peak value Nmax1 of the n-type impurity is formed at depth D13 in region 52a. Here, the n-type impurity is also implanted at multiple depths in the increase region 56. Here, the n-type impurity is implanted so that the n-type impurity concentration is higher than the p-type impurity concentration in the range above depth D13.

[0029] In the second process, as shown in FIG. 5, n-type impurities are implanted multiple times below the main region 50 while changing the acceleration energy. As a result, n-type impurities are implanted to multiple depths in the region below the main region 50. FIG. 4(b) shows a graph G11 of the concentration distribution of n-type impurities implanted into the SiC substrate 12 in the second process, superimposed on graph G7. Region 54a in FIG. 4(b) is a region in the decrease region 54 that has a p-type impurity concentration higher than 10% of the peak value Pmax. In the second process, n-type impurities are implanted at least once to a depth within region 54a. In the example shown in FIG. 4(b), n-type impurities are implanted into the decrease region 54 at depths D21 and D22, including depth D21, within region 54a. Here, at depths D21 and D22, the closer the depth is to the main region 50, the higher the concentration of n-type impurities is implanted. That is, n-type impurities are implanted at a higher concentration at depth D21 than at depth D22. Therefore, in the reduced region 54, a peak value Nmax2 of the n-type impurity is formed at a depth D21. Here, the n-type impurity is implanted so that the n-type impurity concentration is higher than the p-type impurity concentration in the range below the depth D21. Furthermore, when the n-type impurity is implanted in the second process, the n-type impurity is scattered and reflected by the mask 70. The n-type impurity scattered and reflected by the mask 70 is implanted into the peripheral region 58.

[0030] As described above, in the second step, n-type impurities are implanted into the decrease region 52, the decrease region 54, the increase region 56, and the peripheral region 58. Graph G13 in FIG. 4(b) shows the effective p-type impurity concentration obtained by subtracting the n-type impurity concentration from the p-type impurity concentration. That is, graph G13 shows the distribution of values ​​obtained by subtracting the values ​​of graphs G10 and G11 from the values ​​of graph G7. As shown in FIG. 4(b), implanting n-type impurities into the decrease region 52, the decrease region 54, and the increase region 56 reduces the effective p-type impurity concentrations in these regions. FIG. 4(a) shows the distribution of the effective p-type impurity concentration in the same cross section as FIG. 5. As shown in FIG. 4(a), implanting n-type impurities into the peripheral region 58 reduces the effective p-type impurity concentration in the peripheral region 58. In the decrease region 52, decrease region 54, increase region 56, and peripheral region 58, the n-type impurity concentration is higher than the p-type impurity concentration, except in the vicinity of the main region 50. Therefore, the effective p-type impurity concentration is a positive value in the main region 50 and its vicinity, and the effective p-type impurity concentration is a negative value in other regions.

[0031] Next, the SiC substrate 12 is annealed. This activates the p-type impurities and n-type impurities implanted into the SiC substrate 12. Regions with a positive effective p-type impurity concentration become p-type regions 20, and regions with a negative effective p-type impurity concentration (i.e., regions where the n-type impurity concentration is higher than the p-type impurity concentration) become n-type regions 22. That is, the p-type regions 20 are formed in the hatched regions in FIG. 4(a), and the unhatched regions in FIG. 4(a) remain as n-type regions 22. As described above, the positive effective p-type impurity concentration is in the main region 50 and its vicinity, and therefore a p-type region is formed in the main region 50 and its vicinity. At least a portion of the regions 52a and 54a adjacent to the main region 50 becomes an n-type region, thereby narrowing the area in which the p-type region is formed. Thus, according to this manufacturing method, the p-type region 20 can be formed in a region narrower than the region implanted with the p-type impurities in the first step.

[0032] FIG. 6 shows a MOSFET (metal-oxide-semiconductor field effect transistor) as a specific example of a semiconductor device manufactured by the manufacturing method of Example 1. The SiC substrate 12 has an element region 60 and a peripheral region 61. A MOSFET structure is formed in the element region 60, including an n-type source region 62, a p-type body region 63, a trench gate electrode 64, a bottom p-type region 65, an n-type drift region 66, and an n-type drain region 67. The trench gate electrode 64 is a gate electrode disposed in a trench and is insulated from the SiC substrate 12 by a gate insulating film. The bottom p-type region 65 contacts the bottom surface of the trench. The peripheral region 61 is provided around the element region 60. A drift region 66 is distributed in the peripheral region 61. A plurality of p-type guard rings 68 are provided in the peripheral region 61. Each guard ring 68 is provided within the drift region 66. When the SiC substrate 12 is viewed from above, each guard ring 68 has a rectangular ring shape that surrounds the periphery of the device region 60. Each guard ring 68 is disposed at the same depth as the bottom p-type region 65. Each guard ring 68 is formed after the device region 60 is formed. In the step of forming each guard ring 68, a mask 70 is formed on the upper surface 12a of the SiC substrate 12, and the first step (i.e., implantation of p-type impurities) and the second step (i.e., implantation of n-type impurities) can be performed through the mask 70. This method allows the formation of small guard rings 68, thereby enabling the miniaturization of the MOSFET.

[0033] In the above-described first embodiment, n-type impurities are implanted into both the upper and lower sides of the main region 50 in the second step. However, n-type impurities may be implanted into only one of the upper and lower sides of the main region 50 in the second step. When n-type impurities are implanted into the upper side of the main region 50 through the mask 70, the decrease region 52 and the increase region 56 can be made n-type. When n-type impurities are implanted into the lower side of the main region 50 through the mask 70, the decrease region 54 and the peripheral region 58 can be made n-type.

[0034] In the first embodiment described above, the impurity implantation in the first and second steps was performed through a mask 70. However, the impurity implantation in the first and second steps may also be performed without a mask. Even with this configuration, a small p-type region can be formed by implanting n-type impurities into the decrease region of graph G8 in FIG. 2(b). However, when p-type impurities are implanted through a mask, the problem of p-type impurities being implanted into the increase region 56 and the peripheral region 58 becomes more pronounced. In particular, as shown in FIG. 2(b), when the width of the mask opening is 3.5 μm or less, the problem of p-type impurities being implanted into the increase region 56 and the peripheral region 58 becomes more pronounced. Therefore, when the width of the mask opening is 3.5 μm or less, the technique disclosed herein can be used to more effectively suppress the expansion of the p-type region. [Example]

[0035] In Example 2, the mask forming step is carried out in the same manner as in Example 1. Thereafter, the first and second steps are carried out.

[0036] In the first step of Example 2, as shown in FIG. 7, p-type impurities are ion-implanted into the SiC substrate 12 through a mask 70. Here, the p-type impurities are implanted multiple times while changing the acceleration energy. Unlike Example 1, the p-type impurities are implanted at equal intervals in a depth range from the upper surface 12a of the SiC substrate 12 to a depth D100. Here, the p-type impurities are implanted at approximately the same concentration at each depth.

[0037] FIG. 8 shows the concentration distribution of p-type impurities after the first step is performed. More specifically, FIG. 8(a) shows the same cross section as FIG. 7, and the concentration of p-type impurities is represented by the density of the hatching. FIG. 8(b) shows the concentration distribution of p-type impurities at the position of line AA in FIG. 8(a) by graph G100. Within the depth range from the upper surface 12a to a depth D100, the p-type impurity concentration is high (for example, 8×10 17 cm -3) is distributed almost uniformly. Hereinafter, the region where the p-type impurity concentration is distributed almost uniformly will be referred to as the main region 150. A peak value Pmax of the p-type impurity is formed within the main region 150. Below the main region 150, there is a decrease region 154 where the p-type impurity concentration continuously decreases with increasing distance from the main region 150. The decrease region 154 is a region formed due to variations in the implantation depth of the p-type impurity in the first step.

[0038] 8(a), a peripheral region 158 in which p-type impurities are distributed at a low concentration is formed at a position adjacent to the main region 150 in the lateral direction (i.e., the direction perpendicular to the ion implantation direction). The peripheral region 158 is a region into which p-type impurities scattered and reflected by the mask 70 are implanted.

[0039] The second process is performed after the first process. In the second process, n-type impurities are ion-implanted into the SiC substrate 12 through a mask 70. The implantation depth and implantation concentration of the n-type impurities in the second process are set corresponding to the p-type impurity concentration distribution formed in the first process. In the second process, as shown in FIG. 9, n-type impurities are implanted multiple times below the main region 150 while changing the acceleration energy. As a result, n-type impurities are implanted to multiple depths in the region below the main region 150. FIG. 10(b) shows a graph G101 of the concentration distribution of n-type impurities implanted into the SiC substrate 12 in the second process, superimposed on graph G100. Furthermore, region 154a in FIG. 10(b) is a region in the decreasing region 154 that has a p-type impurity concentration higher than 10% of the peak value Pmax. In the second process, n-type impurities are implanted at least once to a depth within region 154a. In the example shown in FIG. 10(b), n-type impurities are implanted into the reduced region 154 at depths D121 and D122, including the depth D121, in the region 154a. Here, at depths D121 and D122, the n-type impurities are implanted at a higher concentration the closer they are to the main region 150. That is, the n-type impurities are implanted at a higher concentration at depth D121 than at depth D122. Therefore, in the reduced region 154, a peak value Nmax of the n-type impurities is formed at depth D121. Here, the n-type impurities are implanted so that the n-type impurity concentration is higher than the p-type impurity concentration in the range below depth D121. Furthermore, when the n-type impurities are implanted in the second step, the n-type impurities are scattered and reflected by the mask 70. The n-type impurities scattered and reflected by the mask 70 are implanted into the peripheral region 158.

[0040] As described above, in the second step, n-type impurities are implanted into the reduced region 154 and the peripheral region 158. Graph G102 in FIG. 10(b) shows the effective p-type impurity concentration, which is the p-type impurity concentration minus the n-type impurity concentration. As shown in FIG. 10(b), implanting n-type impurities into the reduced region 154 reduces the effective p-type impurity concentration in the reduced region 154. FIG. 10(a) shows the distribution of the effective p-type impurity concentration in the same cross section as FIG. 9. As shown in FIG. 10(a), implanting n-type impurities into the peripheral region 158 reduces the effective p-type impurity concentration in the peripheral region 158. In the reduced region 154 and the peripheral region 158, the n-type impurity concentration is higher than the p-type impurity concentration, except in the vicinity of the main region 150. Therefore, the effective p-type impurity concentration is positive in the main region 150 and its vicinity, and negative in other regions.

[0041] Next, the SiC substrate 12 is annealed. This activates the p-type impurities and n-type impurities implanted into the SiC substrate 12. Regions with a positive effective p-type impurity concentration become p-type regions 120, and regions with a negative effective p-type impurity concentration (i.e., regions where the n-type impurity concentration is higher than the p-type impurity concentration) become n-type regions 122. That is, the p-type regions 120 are formed in the hatched regions in FIG. 10(a), and the non-hatched regions in FIG. 10(a) remain as n-type regions 122. As described above, the positive effective p-type impurity concentration is in the main region 150 and its vicinity, and therefore a p-type region is formed in the main region 150 and its vicinity. In particular, since at least a portion of the region 154a adjacent to the main region 150 becomes an n-type region, the area in which the p-type region is formed can be narrower. As such, this manufacturing method allows the p-type region 120 to be formed in a region narrower than the region implanted with p-type impurities in the first step.

[0042] FIG. 11 shows a MOSFET as a specific example of a semiconductor device manufactured by the manufacturing method of Example 2. A MOSFET structure having an n-type source region 62, a p-type body region 63, a trench gate electrode 64, a drift region 66, and an n-type drain region 67 is formed in a SiC substrate 12. The drift region 66 has a superjunction structure in which multiple p-type regions 66a and multiple n-type regions 66b are alternately arranged in the horizontal direction. Each of the p-type region 66a and the n-type region 66b has an elongated shape extending in the thickness direction of the SiC substrate 12. In this MOSFET manufacturing method, first, as shown in FIG. 12, the drift region 66 is formed on the drain region 67 by epitaxial growth. At this stage, the entire drift region 66 is composed of a low-concentration n-type region. Next, as shown in FIG. 13, a mask 70 is formed on the upper surface of the drift region 66, and multiple p-type regions 66a are formed by implanting impurities through the mask 70. At this time, by applying the technique of Example 2, the formation range of the p-type regions 66a can be accurately controlled. The n-type regions remaining between the p-type regions 66a become n-type regions 66b. Then, an epitaxial layer is formed on the drift region 66, and the source region 31, the body region 32, the trench gate electrode 36, etc. are formed in the formed epitaxial layer, thereby completing the MOSFET shown in FIG.

[0043] In the second embodiment described above, the first and second impurity implantations were performed through a mask 70. However, the first and second impurity implantations may also be performed without a mask. Even with this configuration, a small p-type region can be formed by implanting n-type impurities into the reduced region 154. However, implanting p-type impurities through a mask can result in the problem of p-type impurities being implanted into the peripheral region 158. This problem is particularly pronounced when the width of the mask opening is 3.5 μm or less. Therefore, by using the technology disclosed herein when the width of the mask opening is 3.5 μm or less, a greater effect can be achieved in suppressing the expansion of the p-type region.

[0044] In the above-described Examples 1 and 2, p-type impurities were ion-implanted in the first step, and n-type impurities were ion-implanted in the second step. However, n-type impurities may be ion-implanted in the first step, and p-type impurities may be ion-implanted in the second step.

[0045] In addition, in the above-described Examples 1 and 2, the second step was carried out after the first step, but the first step may be carried out after the second step.

[0046] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0047] 12: SiC substrate, 50: main region, 52, 54: reduction region, 70: mask, 72: opening

Claims

1. A method for manufacturing a semiconductor device, comprising: A first step of implanting a first conductivity type impurity into a SiC substrate (12); a second step of implanting a second conductivity type impurity into the SiC substrate; and The first step and the second step satisfy the following conditions: In the thickness direction of the SiC substrate, the concentration distribution (G7) of the first conductivity type impurity implanted in the first step has a first peak value (Pmax) that is a maximum value and a decreasing region (52, 54) in which the first conductivity type impurity concentration continuously decreases with increasing distance from the position of the first peak value. In the thickness direction of the SiC substrate, the concentration distribution (G10, G11) of the second conductivity type impurity implanted in the second step has second peak values ​​(Nmax1, Nmax2) that are maximum values. The position of the second peak value overlaps with a specific region (52a, 54a) in the decrease region that has a first conductivity type impurity concentration that is 10% or more of the first peak value. The position of the first peak value is in the first conductivity type region. At least a part of the specific region is a second conductivity type region. It is implemented to satisfy the condition that The position of the second peak value overlaps with the specific region (54a) that exists deeper than the position of the first peak value. Manufacturing method.

2. A method for manufacturing a semiconductor device, comprising: A first step of implanting a first conductivity type impurity into a SiC substrate (12); a second step of implanting a second conductivity type impurity into the SiC substrate; and The first step and the second step satisfy the following conditions: In the thickness direction of the SiC substrate, the concentration distribution (G7) of the first conductivity type impurity implanted in the first step has a first peak value (Pmax) that is a maximum value and a decreasing region (52, 54) in which the first conductivity type impurity concentration continuously decreases with increasing distance from the position of the first peak value. In the thickness direction of the SiC substrate, the concentration distribution (G10, G11) of the second conductivity type impurity implanted in the second step has second peak values ​​(Nmax1, Nmax2) that are maximum values. The position of the second peak value overlaps with a specific region (52a, 54a) in the decrease region that has a first conductivity type impurity concentration that is 10% or more of the first peak value. The position of the first peak value is in the first conductivity type region. At least a part of the specific region is a second conductivity type region. It is implemented to satisfy the condition that The semiconductor device manufactured by the manufacturing method has an element region (60) and a p-type guard ring (68) extending to surround the periphery of the element region, the first conductivity type region formed at the position of the first peak value is the guard ring; Manufacturing method.

3. A method for manufacturing a semiconductor device, comprising: A first step of implanting a first conductivity type impurity into a SiC substrate (12); a second step of implanting a second conductivity type impurity into the SiC substrate; and The first step and the second step satisfy the following conditions: In the thickness direction of the SiC substrate, the concentration distribution (G7) of the first conductivity type impurity implanted in the first step has a first peak value (Pmax) that is a maximum value and a decreasing region (52, 54) in which the first conductivity type impurity concentration continuously decreases with increasing distance from the position of the first peak value. In the thickness direction of the SiC substrate, the concentration distribution (G10, G11) of the second conductivity type impurity implanted in the second step has second peak values ​​(Nmax1, Nmax2) that are maximum values. The position of the second peak value overlaps with a specific region (52a, 54a) in the decrease region that has a first conductivity type impurity concentration that is 10% or more of the first peak value. The position of the first peak value is in the first conductivity type region. At least a part of the specific region is a second conductivity type region. It is implemented to satisfy the condition that The semiconductor device manufactured by the manufacturing method has a superjunction structure in which a plurality of p-type layers (66 a) and a plurality of n-type layers (66 b) are alternately arranged in a lateral direction in a drift region (66), the first conductivity type region formed at the position of the first peak value is the p-type layer of the super junction structure; Manufacturing method.

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