Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device in which the voltage withstanding between a drain region and a source region and the substrate breakdown voltage are high and the manufacturing cost will not increase, and a manufacturing method for the semiconductor device.SOLUTION: In a semiconductor device, on a surface of an N-type epitaxial layer 2 where an N-type embedded layer 3 (first embedded layer) and a P-type embedded layer 4 (second embedded layer) are formed, a body region 5 including a source region 6 and a drift region 7 including a drain region 8 are disposed, and a gate electrode 9 is formed over a channel region between the source region 6 and the drain region 8 through a gate oxide film. A part of the gate electrode 9 is formed on a field oxide film 10. An end part of the P-type embedded layer 4 on the source region 6 side is disposed on the source region 6 side relative to an end part of the field oxide film 10 on the source region 6 side and is formed so as to overlap with the drain region 8 and not to overlap with the source region 6.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a MOS type semiconductor device and a manufacturing method thereof. [Background technology]

[0002] A so-called RESURF (Reduced Surface Field) structure is known for increasing the breakdown voltage and decreasing the on-resistance of MOS semiconductor devices, such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). For example, Patent Document 1 discloses an LDMOSFET (Lateral Double Diffused Metal Oxide Semiconductor Field Effect Transistor) with a high drain-source breakdown voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-88334 Summary of the Invention [Problem to be solved by the invention]

[0004] FIG. 9 is an explanatory diagram illustrating a semiconductor device 200 having a conventional RESURF structure. As shown in FIG. 9, this type of conventional semiconductor device 200 includes an N-type epitaxial layer 22 formed on a P-type semiconductor substrate 21, and an N-type buried layer 23 and a P-type buried layer 24 formed between the semiconductor substrate 21 and the epitaxial layer 22. A P-type body region 25 is formed on the surface of the epitaxial layer 22 so as to contact the P-type buried layer 24, and an N-type source region 26 is formed on the surface of the body region 25. A portion of the N-type epitaxial layer surrounded by the body region 25 and the P-type buried layer 24 functions as a drift region 27. An N-type drain region 28 is formed on the surface of the drift region 27. A gate electrode 29 is formed on the body region 25 and the drift region 27 between the source region 26 and the drain region 28, with a gate insulating film interposed therebetween. Reference numeral 30 denotes a field oxide film, and reference numeral 31 denotes an isolation region composed of a lower isolation region 31a and an upper isolation region 31b. In the semiconductor device 200 having such a structure, when a high voltage is applied between the source region 26 and the drain region 28, a depletion layer spreads from the body region 25 and the P-type buried layer 24, completely depleting the drift region 27. As a result, the electric field distribution between the drain region 28 and the source region 26 is made uniform, preventing local electric field concentration, and the semiconductor device 200 can be made to withstand a high voltage.

[0005] When manufacturing a semiconductor device 200 having such a RESURF structure, as disclosed in Patent Document 1, it is necessary to perform ion implantation and epitaxial growth to form the N-type buried layer 23, and then perform ion implantation and epitaxial growth to form the P-type buried layer 24, which poses a problem of increased manufacturing costs.

[0006] Furthermore, when the P-type buried layer 24 and the lower isolation region 31a are formed simultaneously, the impurity concentrations of the P-type buried layer 24 and the lower isolation region 31a are formed to be approximately equal. For example, if the P-type buried layer 24 and the lower isolation region 31a are formed to have an impurity concentration suitable for forming the lower isolation region 31a, the resulting structure includes the P-type buried layer 24 with a high impurity concentration, which reduces the junction breakdown voltage between the drain region 28 and the P-type buried layer 24 and between the source region 26 and the P-type buried layer 24. This poses a problem in that a substrate breakdown voltage of approximately 60 V (substrate breakdown voltage between the drain region 28 and the semiconductor substrate 21, and substrate breakdown voltage between the source region 26 and the semiconductor substrate 21) cannot be obtained. To improve the substrate breakdown voltage, the impurity concentration of the P-type buried layer 24 needs to be reduced. However, if the impurity concentration of the lower isolation region 31a formed simultaneously is low, element isolation becomes impossible. To solve these problems, it is necessary to perform the ion implantation for forming the P-type buried layer 24 and the ion implantation for forming the lower isolation region 31a separately, which poses a problem of increased manufacturing costs.

[0007] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor device that has a high breakdown voltage between the drain and source regions and a high substrate breakdown voltage, and that does not increase manufacturing costs, and a method for manufacturing the same. [Means for solving the problem]

[0008] The semiconductor device of the present invention One aspect ofa first conductivity type semiconductor substrate; a semiconductor layer of a second conductivity type opposite to the first conductivity type and disposed on the semiconductor substrate; an isolation region of the first conductivity type extending from the surface of the semiconductor layer to the semiconductor substrate; a first buried layer of the second conductivity type disposed between the semiconductor substrate and the semiconductor layer; a second buried layer of the first conductivity type disposed in the semiconductor layer on the first buried layer and in contact with the first buried layer; a body region of the first conductivity type disposed on the surface of the semiconductor layer and spaced apart from the second buried layer; a source region of the second conductivity type and a body contact region of the first conductivity type disposed on the surface of the body region; a drift region on the surface of the semiconductor layer; a drain region of the second conductivity type disposed on the surface of the drift region; an insulating region disposed on the surface of the drift region between the source region and the drain region; Another aspect of the semiconductor device of the present invention includes a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type opposite to the first conductivity type and disposed on the semiconductor substrate, an isolation region of the first conductivity type extending from the surface of the semiconductor layer to the semiconductor substrate, a first buried layer of the second conductivity type disposed between the semiconductor substrate and the semiconductor layer, a second buried layer of the first conductivity type disposed in the semiconductor layer on the first buried layer and in contact with the first buried layer, a body region of the first conductivity type disposed on the surface of the semiconductor layer and spaced apart from the second buried layer, a source region of the second conductivity type and a body contact region of the first conductivity type disposed on the surface of the body region, a drift region on the surface of the semiconductor layer, and a source region of the second conductivity type and a body contact region of the first conductivity type disposed on the surface of the drift region. the source region and the drain region, an insulating region disposed on the surface of the drift region between the source region and the drain region, and a gate insulating film and a gate electrode disposed on the insulating region; the second buried layer is disposed so that its end on the source region side is closer to the source region than the end of the insulating region on the source region side and overlaps with the drain region but does not overlap with the source region; and the second buried layer is configured so that when a voltage is applied between the source region and the drain region, a first depletion layer formed at a junction between the second buried layer and the semiconductor layer and a second depletion layer formed by a junction between the body region and the semiconductor layer are connected to each other.

[0009] A method for manufacturing a semiconductor device of the present invention includes the steps of: introducing a second conductivity type impurity into a first buried layer formation planned region of a first conductivity type semiconductor substrate to form a second conductivity type impurity implanted region; simultaneously introducing a first conductivity type impurity having a faster thermal diffusion rate than the second conductivity type impurity into a second buried layer formation planned region and an isolation region formation planned region of the first conductivity type semiconductor substrate to form a first conductivity type impurity implanted region; forming a second conductivity type semiconductor layer on the semiconductor substrate, and forming a first buried layer between the semiconductor layer and the semiconductor substrate, into which the impurity has diffused from the second conductivity type impurity implanted region, and a second buried layer and a lower isolation region, into which the impurity has diffused from the first conductivity type impurity implanted region; the second buried layer is configured so that its end on the source region side is located closer to the source region than the end of the insulating region on the source region side, and so as to overlap with the drain region but not to overlap with the source region. [Effects of the Invention]

[0010] According to the semiconductor device of the present invention, since the second buried layer functioning as a RESURF structure is not disposed directly below the source region, it is possible to provide a semiconductor device having a desired breakdown voltage between the drain region and the source region and a substrate breakdown voltage without reducing the breakdown voltage between the source region and the substrate. Furthermore, according to the manufacturing method of the semiconductor device of the present invention, it is possible to simultaneously form the second buried layer functioning as a RESURF structure and the lower isolation region functioning as an isolation region, and it is possible to form a second buried layer with a low impurity concentration without increasing manufacturing costs, and it is possible to manufacture a semiconductor device having a desired breakdown voltage between the drain region and the source region and a substrate breakdown voltage. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is an explanatory diagram of an embodiment of a semiconductor device of the present invention; [Figure 2] 1A to 1C are explanatory diagrams illustrating an embodiment of a method for manufacturing a semiconductor device according to the present invention. [Figure 3] 1A to 1C are explanatory diagrams illustrating an embodiment of a method for manufacturing a semiconductor device according to the present invention. [Figure 4] 1A to 1C are explanatory diagrams illustrating an embodiment of a method for manufacturing a semiconductor device according to the present invention. [Figure 5] 1A to 1C are explanatory diagrams illustrating an embodiment of a method for manufacturing a semiconductor device according to the present invention. [Figure 6] 10 is a graph showing the drain-source breakdown voltage when the width of the P-type impurity implanted region is changed by the manufacturing method of the semiconductor device of the present invention. [Figure 7] 10 is a graph showing the drain-semiconductor substrate breakdown voltage when the width of the P-type impurity implanted region is changed by the manufacturing method of the semiconductor device of the present invention. [Figure 8] 10 is a graph showing the breakdown voltage between the source and the semiconductor substrate when the width of the P-type impurity implanted region is changed by the manufacturing method of the semiconductor device of the present invention. [Figure 9] FIG. 1 is an explanatory diagram of a conventional semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0012] Next, embodiments of the semiconductor device of the present invention and implementations of the manufacturing method thereof will be described with reference to the drawings, but the present invention is not limited to these embodiments and implementations, and the members, materials, etc. described below can be variously modified within the scope of the spirit of the present invention. Furthermore, in the drawings, the same reference numerals indicate equivalent or identical items, and the size and positional relationship between each component are for convenience and do not reflect the actual situation.

[0013] (Embodiment) FIG. 1 is an explanatory diagram illustrating an embodiment of a semiconductor device of the present invention and is a cross-sectional schematic diagram of an LDMOSFET. As shown in FIG. 1, in a semiconductor device 100 of this embodiment, a low-concentration N-type epitaxial layer 2 corresponding to a semiconductor layer is formed on a P-type semiconductor substrate 1. Between the semiconductor substrate 1 and the epitaxial layer 2, an N-type buried layer 3 corresponding to a first buried layer and a P-type buried layer 4 corresponding to a second buried layer are formed. The P-type buried layer 4 is formed in contact with the N-type buried layer 3. A P-type body region 5 is formed on the surface of the epitaxial layer 2, and a high-concentration N-type source region 6 is formed on the surface of the body region 5. An N-type drift region 7 is formed on the surface of the epitaxial layer 2, spaced apart from the body region 5, and a high-concentration N-type drain region 8 is formed on the surface of the drift region 7. A gate electrode 9 made of polysilicon is formed on the body region 5, epitaxial layer 2, and drift region 7, which form a channel region between the source region 6 and the drain region 8, via a gate insulating film. Reference numeral 10 denotes a field oxide film corresponding to an insulating region formed on the surface of drift region 7 between source region 6 and drain region 8, and a portion of gate electrode 9 is laminated on this field oxide film 10. Reference numeral 11 denotes an isolation region that surrounds a portion of epitaxial layer 2 and defines the region where the semiconductor device is to be formed, and is composed of a lower isolation region 11a and an upper isolation region 11b of a P-type region. Reference numeral 12 denotes a highly doped P-type body contact region.

[0014] In the semiconductor device 100 of this embodiment, the P-type buried layer 4 corresponds to a part of a RESURF structure, and the end of the P-type buried layer 4 on the source region 6 (body region 5) side is located closer to the source region 6 than the end of the field oxide film 10 on the source region 6 side. The P-type buried layer 4 is also formed in a position that overlaps with the drain region 8 but does not overlap with the source region 6. When the P-type buried layer 4 is positioned in this manner, even when the P-type buried layer 4 is in a floating state, it comes into contact with the surrounding N-type region (epitaxial layer 2 and drift region 7) to form a PN junction, and a depletion layer corresponding to the first depletion layer is formed at this junction. The body region 5 also comes into contact with the surrounding N-type region (epitaxial layer 2) to form a PN junction, and a depletion layer corresponding to the second depletion layer is formed at this junction.

[0015] When the source region 6, body region 5, and semiconductor substrate 1 are set to 0 V and the voltage applied to the drain region 8 is increased, the second depletion layer expands. Meanwhile, the first depletion layer also expands due to the influence of the surrounding electric field.

[0016] When the voltage applied to the drain region 8 reaches a predetermined voltage, the first depletion layer and the second depletion layer become interconnected. This depletion reduces the electric field strength on the surface of the body region 5, making it possible to achieve a high breakdown voltage between the drain region 8 and the source region 6. In this way, the P-type buried layer 4 according to this embodiment functions as a RESURF structure.

[0017] The substrate breakdown voltage will now be described. First, the substrate breakdown voltage between the drain region 8 and the semiconductor substrate 1 will be described. The impurity concentration of the P-type buried layer 4 can be lower than that of the P-type buried layer in a typical semiconductor device of this type. This impurity concentration is approximately the same as the impurity concentration at the end of the lower isolation region 11a formed at the same depth. The P-type impurities constituting the P-type buried layer 4 diffuse into the N-type buried layer 3 and the P-type buried layer 4 with a concentration profile approximately equal to that of the P-type impurities constituting the lower isolation region 11a. However, since the N-type impurities constituting the N-type buried layer 3 are more abundant in the relatively high-impurity-concentration region, the N-type buried layer 3 exhibits N-type conductivity, while the region exhibiting P-type conductivity has a low impurity concentration. This is because, as will be described later, the P-type buried layer 4 is formed simultaneously with the lower isolation region 11a and the N-type buried layer 3. As a result, it is possible to suppress a decrease in the substrate breakdown voltage between the drain region 8 and the semiconductor substrate 1 and maintain a high substrate breakdown voltage while providing a RESURF structure.

[0018] Next, the substrate breakdown voltage between the source region 6 and the semiconductor substrate 1 will be described. In the semiconductor device of this embodiment, since there is no P-type buried layer 4 directly below the source region 6, the substrate breakdown voltage between the source region 6 and the semiconductor substrate 1 can be increased. Furthermore, in the semiconductor device 100 of this embodiment, the source region 6 and the semiconductor substrate 1 can be electrically isolated. Therefore, when the semiconductor substrate 1 is set to 0 V and the body region 5 and the source region 6 are set to a potential higher than that of the semiconductor substrate 1, and the voltage applied to the drain region 8 is increased, the second depletion layer expands. Meanwhile, the first depletion layer also expands due to the influence of the surrounding electric field. Therefore, even when the semiconductor device 100 of this embodiment is used as a high-side element, the P-type buried layer 4 functions as a RESURF structure, enabling a high breakdown voltage between the drain region 8 and the source region 6.

[0019] Naturally, the breakdown voltage between the drain region 8 and the source region 6 of the semiconductor device 100, the breakdown voltage between the drain region 8 and the semiconductor substrate 1, and the breakdown voltage between the source region 6 and the semiconductor substrate 1 will change depending on the impurity concentration of the P-type buried layer 4, the impurity concentration of the epitaxial layer 2, the dimension between the P-type buried layer 4 and the body region 5, the dimension between the P-type buried layer 4 and the drift region 7, etc., so the impurity concentration and dimensions must be set appropriately.

[0020] 1, the drift region 7 is configured as an N-type region formed on the surface of the epitaxial layer 2 to reduce the on-resistance of the semiconductor device 100, but the present invention is not limited to this. For example, the drift region 7 shown in FIG. 1 may not be formed, and a portion of the N-type epitaxial layer 2 may be used as the drift region. In this case, a portion of the epitaxial layer 2 closer to the source region 6 than the drain region 8 becomes the drift region. Alternatively, for example, the epitaxial layer 2 shown in FIG. 1 may be an N-type well region. In this case, the body region 5, drift region 7, etc. are formed in the N-type well, and a portion of the N-type well closer to the source region 6 than the drain region 8 becomes the drift region.

[0021] (Method of manufacturing a semiconductor device) Next, an embodiment of the method for manufacturing a semiconductor device according to the present invention will be described.

[0022] 2 to 5 are explanatory diagrams of one embodiment of the method for manufacturing a semiconductor device of the present invention, and are explanatory diagrams of the method for manufacturing the semiconductor device 100 described in the above embodiment. First, a P-type semiconductor substrate 1 is prepared, and antimony (Sb) or arsenic (As) as an N-type impurity is ion-implanted into an N-type buried layer formation region corresponding to a first buried layer formation region, thereby forming an N-type impurity implanted region 13 corresponding to a second conductivity type impurity implanted region. The ion implantation conditions are, for example, a dose of 1×10 15 ~3×10 15 / cm 2 The implantation energy is about 40 keV. In addition, boron (B), which is a P-type impurity, is implanted into the P-type buried layer formation region corresponding to the second buried layer formation region to form a P-type impurity implanted region 14 corresponding to the first conductivity type impurity implanted region. The P-type impurity implanted region 14 is formed in a region overlapping with a region where a drain region (described later) is formed. As an example of ion implantation conditions, a dose of 2×10 14 ~4×10 14 / cm 2 2, the P-type impurity implanted region 14 is formed so as to overlap a part of the N-type impurity implanted region 13. If the width W indicated by the arrow in FIG. 2 is the width of the P-type impurity implanted region 14, then the width W is set to, for example, about 2 μm.

[0023] At the same time, boron, a P-type impurity, is ion-implanted into the isolation region formation region to form a P-type impurity implanted region 15 corresponding to the first conductivity type impurity implanted region. The impurities implanted here are selected from impurities whose thermal diffusion rate is faster than that of N-type impurities. The ion implantation conditions are set so that the dose of the N-type impurity is greater than the dose of the P-type impurity.

[0024] After a heat treatment for defect recovery by ion implantation, a low-concentration N-type epitaxial layer 2 corresponding to a semiconductor layer is grown on the semiconductor substrate 1. When forming a semiconductor device with a breakdown voltage between the drain and source regions of approximately 50 to 100 V, the epitaxial layer 2 is grown to have a resistivity of 1 to 3 Ωcm and a thickness of approximately 5 to 8 μm. As an example, when forming a semiconductor device with a breakdown voltage between the drain and source regions of approximately 70 V, the epitaxial layer 2 is grown to have a resistivity of 1.6 Ωcm and a thickness of approximately 5.5 μm. During this epitaxial growth process, the impurity ions implanted into the N-type impurity implanted region 13 and the P-type impurity implanted regions 14 and 15 diffuse into the semiconductor substrate 1 and the epitaxial layer 2, forming an N-type buried layer 3 corresponding to the first buried layer, a P-type buried layer 4 corresponding to the second buried layer, and a lower isolation region 11a. Since the implanted P-type impurities have a faster thermal diffusion rate than N-type impurities, a P-type buried layer 4 is formed outside the N-type buried layer 3 so as to be in contact with the N-type buried layer, as shown in Figure 3. The P-type impurities implanted to form the P-type buried layer 4 also diffuse into the N-type buried layer 3, but since the dose of the N-type impurities is greater than the dose of the P-type impurities, the N-type buried layer 3 is formed in the region where both impurities are diffused.

[0025] The P-type buried layer 4 and the lower isolation region 11a are formed under the same ion implantation and heat treatment conditions, but the region that becomes the P-type buried layer 4 corresponds to the end of the diffusion region and has a low impurity concentration.

[0026] N-type impurities, such as arsenic, are ion-implanted from the surface of epitaxial layer 2 into the region where the drift region is to be formed. P-type impurities are ion-implanted into the region where the body region is to be formed and the region where the upper isolation region is to be formed. A mask film such as a nitride film is then formed to open the region where the field oxide film is to be formed, and field oxide film 10, which corresponds to the insulating region, is formed. The implanted impurity ions are diffused by the heat treatment to form field oxide film 10, forming body region 5, drift region 7, and upper isolation region 11b (FIG. 4). The ion implantation to form body region 5 does not necessarily have to be performed simultaneously with the ion implantation to form upper isolation region 11b.

[0027] The body region 5 and drift region 7, the N-type buried layer 3, and the P-type buried layer 4 are arranged so that the P-type buried layer 4 and drift region 7 overlap, but the P-type buried layer 4 and body region 7 do not overlap. The N-type buried layer 3 is also arranged so that the body region 5 and drift region 7 overlap. Furthermore, the end of the P-type buried layer 4 on the body region 5 side (the source region side to be formed in a later process) is located closer to the body region 5 than the end of the field oxide film 10 on the body region 5 side. It is preferable that the end of the P-type buried layer 4 on the body region 5 side and the end of the body region 5 on the drift region 7 side do not overlap. As will be described later, the P-type buried layer 4 is arranged so that it overlaps the drain region 8 but does not overlap the source region 6.

[0028] Thereafter, an N-type impurity, such as arsenic, is ion-implanted into the region where the source region is to be formed from the surface of the body region 5. At the same time, an N-type impurity is ion-implanted into the region where the drain region is to be formed from the surface of the drift region 7. Furthermore, a P-type impurity is ion-implanted into the region where the body contact region is to be formed from the surface of the body region 5.

[0029] The entire surface is thermally oxidized to form a gate oxide film. This thermal oxidation process forms the source region 6, drain region 8, and body contact region 12. As shown in Figure 5, the source region 6 overlaps only the N-type buried layer 3 and does not overlap the P-type buried layer 4. The drain region 8 overlaps the P-type buried layer 4.

[0030] A gate electrode 9 made of polysilicon is formed via a gate insulating film on the body region 5, which serves as a channel region between the source region 6 and the drain region 8, the epitaxial layer 2, and the drift region 7. A portion of the gate electrode 9 is stacked on a field oxide film 10 (FIG. 5).

[0031] Thereafter, in accordance with a normal semiconductor device manufacturing method, electrodes, a surface protection film, wiring, etc. connected to the source region 6 and the drain region 8 are formed to complete the semiconductor device 100. Note that the electrodes, etc. connected to the source region 6 are not shown in the semiconductor device 100 shown in FIGS.

[0032] As described in the above embodiment of the present invention, the semiconductor device 100 formed by the semiconductor device manufacturing method of this embodiment is provided with a resurf structure, which enables a high breakdown voltage between the drain region 8 and the source region 6, and further enables a reduction in the substrate breakdown voltage between the source region 6 and the semiconductor substrate 1, and between the drain region 8 and the semiconductor substrate 1.

[0033] In the method for manufacturing a semiconductor device according to this embodiment, the implantation width of the P-type impurity implanted region 14 described in FIG. 2 can be appropriately set to form a semiconductor device 100 having the desired breakdown voltage between the drain region 8 and the source region 6 and the desired substrate breakdown voltage. Here, the "implantation width" is the width W indicated by the arrow in FIG. 2. By changing this implantation width, the arrangement and impurity concentration of the P-type buried layer 4 to be formed can be changed.

[0034] The breakdown voltage between the drain region 8 and the source region 6 will now be described. FIG. 6 shows the breakdown voltage (drain-source breakdown voltage) between the drain region 8 and the source region 6 of a semiconductor device formed by aligning the center of the P-type impurity implanted region 14 with the center of the region where the drain region is to be formed and changing the width of the P-type impurity implanted region 14. When the width of the P-type impurity implanted region 14 is 0 μm, a structure without the P-type buried layer 4 is obtained. As shown in FIG. 6, the drain-source breakdown voltage increases as the width of the P-type impurity implanted region 14 increases, and decreases when the width exceeds 2 μm.

[0035] Increasing the width of the P-type impurity-implanted region 14 increases the width of the formed P-type buried layer 4, bringing it closer to the body region 5. As a result, the depletion layer corresponding to the first depletion layer formed by the PN junction between the P-type buried layer 4 and the epitaxial layer 2 and the depletion layer corresponding to the second depletion layer extending from the body region 5 are connected, thereby reducing the electric field strength on the surface of the body region 5. In the example shown in Figure 6, when the width of the P-type impurity-implanted region 14 is 2 µm, the breakdown voltage exceeds 70 V, which shows an improvement in characteristics compared to when there is no P-type buried layer 14 (when the width of the P-type impurity-implanted region is 0 µm).

[0036] Furthermore, when the width of the P-type impurity implanted region 14 exceeds 2 μm, the drain-source breakdown voltage tends to decrease. This is thought to be because, by increasing the width of the P-type impurity implanted region 14, the P-type buried layer 4 formed is brought closer to the source region 6, or because the impurity concentration of the P-type buried layer 4 increases.

[0037] In such a case, the breakdown voltage between the drain region 8 and the source region 6 can be further improved by making design changes such as increasing the separation between the drain region 8 and the source region 6 or lowering the impurity concentration in the drift region 7.

[0038] The substrate breakdown voltage between the drain region 8 and the semiconductor substrate 1 will now be described. FIG. 7 shows the substrate breakdown voltage (drain-semiconductor substrate breakdown voltage) between the drain region 8 and the semiconductor substrate 1 of a semiconductor device formed by aligning the center of the P-type impurity implanted region 14 with the center of the region where the drain region is to be formed and changing the width of the P-type impurity implanted region 14. When the width of the P-type impurity implanted region 14 is 0 μm, a structure without the P-type buried layer 4 is obtained. As shown in FIG. 7, the drain-semiconductor substrate breakdown voltage decreases as the width of the P-type impurity implanted region 14 increases.

[0039] When the width of the P-type impurity-implanted region 14 is increased, the impurity concentration of the formed P-type buried layer 4 increases. This is thought to reduce the breakdown voltage of the PN junction between the P-type buried layer 4 and the drain region 8, thereby reducing the drain-semiconductor substrate breakdown voltage. However, in the semiconductor device 100 formed by the manufacturing method of this embodiment, the impurity concentration of the P-type buried layer 4 is low. As a result, the drain-semiconductor substrate breakdown voltage is increased to a substrate breakdown voltage (approximately 75 V when the P-type impurity-implanted region is 2 μm wide) that exceeds the drain-source breakdown voltage (72 V when the P-type impurity-implanted region is 2 μm wide) described in FIG. 6, and a semiconductor device 100 that can be used without any problems is obtained.

[0040] If a design change is made, such as changing the separation width between the drain region 8 and the source region 6, in order to improve the breakdown voltage of the drain region 8 and the source region 6, the substrate breakdown voltage between the drain region 8 and the semiconductor substrate 1 will also change, so it is sufficient to make an appropriate design change to achieve the desired substrate breakdown voltage between the drain region 8 and the semiconductor substrate 1.

[0041] The substrate breakdown voltage between the source region 6 and the semiconductor substrate 1 will now be described. FIG. 8 shows the substrate breakdown voltage (source-semiconductor substrate breakdown voltage) between the source region 6 and the semiconductor substrate 1 of a semiconductor device formed by aligning the center of the P-type impurity implanted region 14 with the center of the region where the drain region is to be formed and changing the width of the P-type impurity implanted region 14. A width of the P-type impurity implanted region 14 of 0 μm results in a structure without the P-type buried layer 4. As shown in FIG. 8, the source-semiconductor substrate breakdown voltage decreases as the width of the P-type impurity implanted region 14 increases.

[0042] When the width of the P-type impurity-implanted region 14 is increased, the formed P-type buried layer 4 approaches the source region 6, or the impurity concentration of the P-type buried layer 4 increases, which is thought to lower the breakdown voltage of the PN junction between the P-type buried layer 4 and the source region 6 and reduce the source-semiconductor substrate breakdown voltage. However, in the semiconductor device 100 formed by the manufacturing method of this embodiment, the impurity concentration of the P-type buried layer 4 is low. Therefore, the source-semiconductor substrate breakdown voltage is equivalent to the substrate breakdown voltage (approximately 71 V when the P-type impurity-implanted region is 2 μm wide) as the drain-source breakdown voltage (72 V when the P-type impurity-implanted region is 2 μm wide) described in FIG. 6, and the semiconductor device 100 can be used without any problems.

[0043] If a design change is made, such as changing the distance between the drain region 8 and the source region 6, in order to improve the breakdown voltage of the drain region 8 and the source region 6, the substrate breakdown voltage between the source region 6 and the semiconductor substrate 1 will also change. Therefore, appropriate design changes can be made to achieve the desired substrate breakdown voltage between the source region 6 and the semiconductor substrate 1.

[0044] As described above, the semiconductor device manufacturing method of this embodiment forms the N-type buried layer 3 and the P-type buried layer 4 by diffusing impurities from the N-type impurity-implanted region 13 and the P-type impurity-implanted region 14, which are implanted with impurities having a faster diffusion rate than the N-type impurities. This eliminates the need for additional processes to form the body region 5, source region 6, drain region 8, and other regions at desired locations, resulting in a manufacturing method that does not increase manufacturing costs. Furthermore, by appropriately setting the width of the P-type impurity-implanted region 14 shown in FIG. 2 , the arrangement and impurity concentration of the P-type buried layer 4 to be formed can be changed, thereby enabling appropriate setting of the breakdown voltage between the drain region 8 and the source region 6, the substrate breakdown voltage between the drain region 8 and the semiconductor substrate 1, and the substrate breakdown voltage between the source region 6 and the semiconductor substrate 1, resulting in a simple manufacturing method. In particular, the manufacturing cost required to change the width of the P-type impurity-implanted region 14 is limited to the cost required to change the ion implantation mask, and therefore does not significantly increase manufacturing costs.

[0045] Although the embodiments of the semiconductor device manufacturing method of the present invention have been described above, the present invention is not limited to these embodiments. For example, when manufacturing a semiconductor device in which the drift region 7 of semiconductor device 100 is formed of an N-type epitaxial layer, the epitaxial layer may be formed to a desired thickness with a desired impurity concentration. Furthermore, when manufacturing a semiconductor device in which an N-well is formed in the region in which the body region 5 and drift region 7 are formed, the desired N-well may be formed in the epitaxial layer.

[0046] (summary) (1) One embodiment of the semiconductor device of the present invention includes a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type opposite to the first conductivity type and disposed on the semiconductor substrate, an isolation region of the first conductivity type extending from a surface of the semiconductor layer to the semiconductor substrate, a first buried layer of the second conductivity type disposed between the semiconductor substrate and the semiconductor layer, a second buried layer of the first conductivity type disposed in the semiconductor layer on the first buried layer and in contact with the first buried layer, a body region of the first conductivity type disposed on the surface of the semiconductor layer and spaced apart from the second buried layer, and a solenoid of the second conductivity type disposed on the surface of the body region. the second buried layer may be configured to have an end portion on the source region side closer to the source region than an end portion of the insulating region on the source region side, and to overlap with the drain region but not overlap with the source region.

[0047] (2) The second buried layer may be configured such that, when a voltage is applied between the source region and the drain region, a first depletion layer formed at the junction between the second buried layer and the semiconductor layer is connected to a second depletion layer formed by the junction between the body region and the semiconductor layer.

[0048] According to the semiconductor device of the present invention, as the voltage applied to the source region 6 and the drain region 8 is increased, the depletion layer (first depletion layer) formed by the PN junction between the P-type buried layer 4 (second buried layer) and the surrounding epitaxial layer 2 (semiconductor layer) and the depletion layer (second depletion layer) formed by the PN junction between the body region 5 and the surrounding epitaxial layer 2 (semiconductor layer) are interconnected, thereby mitigating the electric field strength on the surface of the body region 5 and enabling a high breakdown voltage between the drain region 8 and the source region 6. Furthermore, the impurity concentration of the second buried layer (P-type buried layer 4) disposed directly below the drain region 8 is low, thereby increasing the substrate breakdown voltage between the drain region 8 and the semiconductor substrate 1. Furthermore, by adopting a structure in which the P-type buried layer 4 (second buried layer) is not disposed directly below the body region 5, the substrate breakdown voltage between the source region 6 and the semiconductor substrate 1 is also increased.

[0049] (3) In one embodiment of the method for manufacturing a semiconductor device of the present invention, the method includes the steps of: introducing a second conductivity type impurity into a first buried layer formation planned region of a first conductivity type semiconductor substrate to form a second conductivity type impurity implanted region; simultaneously introducing a first conductivity type impurity having a faster thermal diffusion rate than the second conductivity type impurity into a second buried layer formation planned region and an isolation region formation planned region of the first conductivity type semiconductor substrate to form a first conductivity type impurity implanted region; forming a second conductivity type semiconductor layer on the semiconductor substrate, and forming a first buried layer between the semiconductor layer and the semiconductor substrate, into which the impurity has diffused from the second conductivity type impurity implanted region, and a second buried layer and a lower isolation region, into which the impurity has diffused from the first conductivity type impurity implanted region; the second buried layer is formed so that its end on the source region side is located closer to the source region than the end on the source region side of the insulating region, and so as to overlap with the drain region but not to overlap with the source region.

[0050] (4) In the step of forming the first-conductivity-type impurity-implanted region, the first-conductivity-type impurity-implanted region may be configured so that at least a portion of the first-conductivity-type impurity-implanted region overlaps with a region where a drain region is to be formed, and the position of the end portion on the side of the region where a source region is to be formed is set to a width of the first-conductivity-type impurity-implanted region required to obtain a desired arrangement and impurity concentration of the second buried layer.

[0051] According to the method for manufacturing a semiconductor device of the present invention, an N-type buried layer 3 (first buried layer) and a P-type buried layer 4 (second buried layer) are formed from an N-type impurity-implanted region 13 and a P-type impurity-implanted region 14 implanted with an impurity having a faster diffusion rate than the N-type impurity, and no additional steps are required to form the body region 5, source region 6, drain region 8, etc. in desired positions, resulting in a manufacturing method that does not increase manufacturing costs. Furthermore, by appropriately setting the width of the P-type impurity-implanted region 14, the location of the P-type buried layer 4 to be formed and its impurity concentration can be changed. As a result, when a desired voltage is applied to the source region 6 and the drain region 8, the depletion layer (first depletion layer) formed by the PN junction between the P-type buried layer 4 (second buried layer) and the surrounding epitaxial layer 2 (semiconductor layer) and the depletion layer (second depletion layer) formed by the PN junction between the body region 5 and the surrounding epitaxial layer 2 (semiconductor layer) can be formed to be interconnected, and the breakdown voltage between the drain region 8 and the source region 6, the substrate breakdown voltage between the drain region 8 and the semiconductor substrate 1, and the substrate breakdown voltage between the source region 6 and the semiconductor substrate 1 can be appropriately set, resulting in a simple manufacturing method. [Explanation of symbols]

[0052] 100, 200 Semiconductor device 1, 21 Semiconductor substrate 2, 22 Epitaxial layer 3, 23 N-type buried layer 4, 24 P-type buried layer 5, 25 body region 6, 26 Source region 7, 27 Drift region 8, 28 Drain region 9, 29 Gate electrode 10, 30 Field oxide 11, 31 Separation area 11a, 31a Lower isolation area 11b, 31b Upper separation area 12 Body Contact Area 13 N-type impurity implanted region 14, 15 P-type impurity implanted region

Claims

1. a semiconductor substrate of a first conductivity type; a second conductivity type semiconductor layer, which is opposite in conductivity to the first conductivity type and is disposed on the semiconductor substrate; an isolation region of a first conductivity type extending from the surface of the semiconductor layer to the semiconductor substrate; a first buried layer of a second conductivity type disposed between the semiconductor substrate and the semiconductor layer; a second buried layer of the first conductivity type disposed in the semiconductor layer on the first buried layer and in contact with the first buried layer; a first conductivity type body region disposed on the surface of the semiconductor layer and spaced apart from the second buried layer; a source region of a second conductivity type and a body contact region of a first conductivity type disposed on a surface of the body region; a drift region on the surface of the semiconductor layer; a drain region of a second conductivity type disposed on a surface of the drift region; an insulating region disposed on the drift region surface between the source region and the drain region; a gate insulating film and a gate electrode disposed on the insulating region; Equipped with the second buried layer is arranged so that an end portion on the source region side is closer to the source region than an end portion on the source region side of the insulating region, and overlaps with the drain region but does not overlap with the source region; The first buried layer is doped with impurities of a first conductivity type from a region where the second buried layer is formed, and the first buried layer exhibits a second conductivity type due to the presence of the second conductive type impurities in a larger amount than the first conductive type impurities. Semiconductor device.

2. A semiconductor substrate of a first conductivity type; a second conductivity type semiconductor layer, which is opposite in conductivity to the first conductivity type and is disposed on the semiconductor substrate; an isolation region of a first conductivity type extending from the surface of the semiconductor layer to the semiconductor substrate; a first buried layer of a second conductivity type disposed between the semiconductor substrate and the semiconductor layer; a second buried layer of the first conductivity type disposed in the semiconductor layer on the first buried layer and in contact with the first buried layer; a first conductivity type body region disposed on the surface of the semiconductor layer and spaced apart from the second buried layer; a source region of a second conductivity type and a body contact region of a first conductivity type disposed on a surface of the body region; a drift region on the surface of the semiconductor layer; a drain region of a second conductivity type disposed on a surface of the drift region; an insulating region disposed on the drift region surface between the source region and the drain region; a gate insulating film and a gate electrode disposed on the insulating region; Equipped with the second buried layer is arranged so that an end portion on the source region side is closer to the source region than an end portion on the source region side of the insulating region, and overlaps with the drain region but does not overlap with the source region; the second buried layer is provided so that, when a voltage is applied between the source region and the drain region, a first depletion layer formed at a junction between the second buried layer and the semiconductor layer is connected to a second depletion layer formed by a junction between the body region and the semiconductor layer. Semiconductor device.

3. a step of introducing a second conductivity type impurity into a first buried layer formation region of a first conductivity type semiconductor substrate to form a second conductivity type impurity implanted region; forming a first conductivity type impurity implanted region by simultaneously introducing a first conductivity type impurity having a faster thermal diffusion rate than the second conductivity type impurity into a second buried layer formation region and an isolation region formation region of the first conductivity type semiconductor substrate; forming a semiconductor layer of a second conductivity type on the semiconductor substrate, and forming a first buried layer between the semiconductor layer and the semiconductor substrate, in which impurities are diffused from the second conductivity type impurity-implanted region, and a second buried layer and a lower isolation region, in which impurities are diffused from the first conductivity type impurity-implanted region; forming a source region of a second conductivity type and a body contact region of the first conductivity type on a surface of a body region of the first conductivity type formed on a surface of the semiconductor layer; forming a drain region of a second conductivity type on a surface of a drift region on the surface of the semiconductor layer; forming an insulating region on the surface of the drift region in a region where a gate electrode is to be formed; forming a gate electrode extending over the insulating region through a gate insulating film on a channel region between the source region and the drain region; The second buried layer is formed so that an end portion on the source region side is located closer to the source region than an end portion on the source region side of the insulating region, and overlaps with the drain region but does not overlap with the source region. A method for manufacturing a semiconductor device.

4. In the step of forming the first conductivity type impurity implanted region, the first conductivity type impurity implanted region is at least partially overlapped with a region where a drain region is to be formed, and the position of the end portion on the side of the region where a source region is to be formed is set to a width of the first conductivity type impurity implanted region required to obtain a desired arrangement and impurity concentration of the second buried layer. The method for manufacturing a semiconductor device according to claim 3.

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