Semiconductor Devices

Abstract

To provide a semiconductor device that restores degraded data.SOLUTION: A semiconductor device includes a first circuit, a storage unit, and a calculation unit, in which the first circuit has a current source and a first switch, the storage unit has a first transistor and a first capacitor, and the calculation unit has a second transistor. A first terminal of the first transistor is electrically connected to a control terminal of the first switch, a first terminal of the first switch is electrically connected to an output terminal of the current source, and a second terminal of the first switch is electrically connected to a first terminal of the second transistor. Upon restoring data held in the storage unit, the first transistor is turned into an ON state to provide the data held in the storage unit to the control terminal of the first switch via the first transistor. The first switch turns into either of an ON state and an OFF state depending on the data and applies the current to the calculation unit from the current source via the second transistor to replenish electric charges to a holding unit of the calculation unit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof. [Background technology]

[0003] Currently, active development is underway on integrated circuits that mimic the workings of the human brain. These integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brain-morphic," or "brain-inspired." These integrated circuits have a non-von Neumann architecture, and are expected to be able to perform parallel processing with significantly less power consumption than von Neumann architectures, which consume more power as processing speed increases.

[0004] An information processing model that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose a computing device that configures an artificial neural network using SRAM (Static Random Access Memory). [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] M. Kang et al., “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No.2, p.642-655. [Non-patent document 2] J. Zhang et al., “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No.4, p.915-924. Summary of the Invention [Problem to be solved by the invention]

[0006] In an artificial neural network, a calculation is performed in which the connection strength (sometimes called a weighting coefficient) of a synapse connecting two neurons is multiplied by the signal transmitted between the two neurons. In particular, in a hierarchical artificial neural network, the connection strength of each synapse between multiple first neurons in the first layer and one of the second neurons in the second layer is multiplied and added by each signal input from the multiple first neurons in the first layer to one of the second neurons in the second layer. In other words, a multiply-and-sum operation is required between the connection strength and the signal. The number of connection strengths and the number of parameters representing the signal used in the multiply-and-sum operation depend on the scale of the artificial neural network. Furthermore, the second neuron performs an activation function operation using the result of the multiply-and-sum operation between the synaptic connection strength and the signal output by the first neuron, and outputs the result of the operation as a signal to the third neuron in the third layer. In other words, the greater the number of layers and neurons in an artificial neural network, the greater the number of circuits corresponding to "neurons" and "synapses," and the greater the amount of calculation required. This may result in increased power consumption and heat generation by the circuit.

[0007] Furthermore, increasing the number of circuits constituting a chip increases power consumption and the amount of heat generated when the device is running. In particular, the higher the amount of heat generated, the greater the impact on the characteristics of the circuit elements contained in the chip. Therefore, it is preferable for the circuits constituting the chip to have circuit elements that are less susceptible to temperature effects. Furthermore, variations in the characteristics of the transistors, current sources, and other components contained in the chip will also lead to variations in the results of calculations.

[0008] Furthermore, when performing the above-described sum-of-products operation, the circuit that performs the multiplication (referred to herein as a multiplication cell) must continuously store a weighting factor as a multiplier (or sometimes a multiplicand). Therefore, the multiplication cell is provided with a storage element, such as a capacitor, that stores the weighting factor. However, over time, the data stored in the storage element may deteriorate, causing the value of the weighting factor to change. Data deterioration occurs when the charge stored in the storage element decreases. Examples of the cause of the charge decrease include leakage current from the storage element. Examples of leakage current include leakage current that flows in an off-state in a switching element such as a transistor, and leakage current that flows through a dielectric between a pair of electrodes in a capacitor. In the case of leakage current that flows in an off-state in a switching element such as a transistor, the effect of the leakage current can be reduced by increasing the capacitance of the capacitor. On the other hand, in the case of leakage current that flows through a dielectric between a pair of electrodes in a capacitor, increasing the capacitance of the capacitor does not change the amount of leakage current per unit area of ​​the pair of electrodes, making it difficult to reduce the overall effect of the leakage current.

[0009] Therefore, in order to prevent the degradation of data stored in an arithmetic circuit including a multiplier cell, measures other than increasing the capacitance value of the capacitive element are necessary. One example of such measures is to periodically rewrite the weighting coefficient to the memory element of the multiplier cell. Alternatively, it is also preferable to provide a dummy cell or the like in the arithmetic circuit including the multiplier cell, monitor the data stored in the dummy cell, and rewrite the weighting coefficient to the multiplier cell when the data deteriorates. Note that, in this specification, "data rewriting" refers to the operation of rewriting the same data as the data originally stored in the cell to the cell. Furthermore, "data rewriting" also refers to the operation of replenishing the same amount of charge as originally stored in a cell in order to restore data to a cell whose absolute value of the charge it held has decreased.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device or the like that performs a product-sum operation and / or a function operation. Another object of one embodiment of the present invention is to provide a semiconductor device that rewrites data stored in a multiplication cell. Another object of one embodiment of the present invention is to provide a semiconductor device that stores digital values, performs digital-to-analog conversion on the digital values, and performs an operation using analog values. Another object of one embodiment of the present invention is to provide a semiconductor device or the like that performs convolution processing such as a convolutional neural network (CNN). Another object of one embodiment of the present invention is to provide a semiconductor device or the like for artificial intelligence (AI). Another object of one embodiment of the present invention is to provide a semiconductor device or the like for a deep neural network (DNN). Another object of one embodiment of the present invention is to provide a semiconductor device or the like that consumes low power. Another object of one embodiment of the present invention is to provide a semiconductor device or the like that is less susceptible to environmental temperature. Another object of one embodiment of the present invention is to provide a semiconductor device or the like that is less susceptible to variations in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device or the like that is less susceptible to variations in characteristics of a current source.Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like.

[0011] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0012] (1) One embodiment of the present invention is a semiconductor device including a first circuit, a second circuit, and a third circuit. The first circuit includes a current source and a first switch. The second circuit includes a first transistor, a third transistor, a fourth transistor, and a first capacitor. The third circuit includes a second transistor. A first terminal of the first transistor is electrically connected to a control terminal of the first switch. A second terminal of the first transistor is electrically connected to a first terminal of the fourth transistor. The second terminal of the fourth transistor is electrically connected to a first terminal of the first capacitor. A gate of the fourth transistor is electrically connected to the second terminal of the first capacitor and the first terminal of the third transistor. The first terminal of the first switch is electrically connected to an output terminal of the current source. The second terminal of the first switch is electrically connected to the first terminal of the second transistor.

[0013] (2) Alternatively, one aspect of the present invention may have a configuration in (1) above, which includes a fourth circuit including a latch circuit. The first terminal of the first transistor and the control terminal of the first switch are electrically connected by electrically connecting the first terminal of the fourth circuit to the first terminal of the first transistor and electrically connecting the second terminal of the fourth circuit to the control terminal of the first switch.

[0014] (3) Another embodiment of the present invention is a semiconductor device including a first circuit, a second circuit, a third circuit, and a sense amplifier. The first circuit includes a current source and a first switch. The second circuit includes a first transistor and a first capacitor. The third circuit includes a second transistor. A first terminal of the first transistor is electrically connected to a control terminal of the first switch via the sense amplifier. A second terminal of the first transistor is electrically connected to a first terminal of the first capacitor. The first terminal of the first switch is electrically connected to an output terminal of the current source. The second terminal of the first switch is electrically connected to a first terminal of the second transistor.

[0015] (4) Alternatively, in one embodiment of the present invention, in any one of the above (1) to (3), a gate of the first transistor may be electrically connected to a gate of the second transistor.

[0016] (5) Another embodiment of the present invention is a semiconductor device including a first circuit, a second circuit, and a third circuit. The first circuit includes a current source and a first switch. The second circuit includes a first transistor, a third transistor, and a first capacitor. The third circuit includes a second transistor. A first terminal of the first transistor is electrically connected to a control terminal of the first switch. A first terminal of the third transistor is electrically connected to a first terminal of the first capacitor and a gate of the first transistor. A first terminal of the first switch is electrically connected to an output terminal of the current source. A second terminal of the first switch is electrically connected to a first terminal of the second transistor.

[0017] (6) Alternatively, one embodiment of the present invention may have a fourth circuit including a latch circuit. The first terminal of the first transistor and the control terminal of the first switch are electrically connected to each other by electrically connecting the first terminal of the fourth circuit to the first terminal of the first transistor and electrically connecting the second terminal of the fourth circuit to the control terminal of the first switch.

[0018] (7) Alternatively, in one aspect of the present invention, in the above configuration (5) or (6), a second terminal of the first capacitor may be electrically connected to a gate of the second transistor.

[0019] (8) Alternatively, in one embodiment of the present invention, in any one of the above (1) to (7), a transistor included in the second circuit may have a metal oxide in a channel formation region.

[0020] (9) Another embodiment of the present invention is a semiconductor device including a first circuit and a fifth circuit. The first circuit includes a first current source, a second current source, a first switch, a fifth transistor, and a sixth transistor. The fifth circuit includes a seventh transistor, an eighth transistor, a second capacitor, a second switch, a third switch, and a current comparison circuit. It is preferable that an output terminal of the first current source is electrically connected to a first terminal of the first switch, and an output terminal of the second current source is electrically connected to a gate of the fifth transistor, a gate of the sixth transistor, and a first terminal of the sixth transistor. It is also preferable that a first terminal of the seventh transistor is electrically connected to a first terminal of the eighth transistor, a first terminal of the second switch, and a first terminal of the third switch, and a gate of the seventh transistor is electrically connected to a second terminal of the eighth transistor and a first terminal of the second capacitor. It is also preferable that the second terminal of the first switch is electrically connected to the second terminal of the second switch, the first terminal of the current comparison circuit is electrically connected to the second terminal of the third switch, and the second terminal of the current comparison circuit is electrically connected to the first terminal of the fifth transistor.

[0021] (10) Alternatively, one embodiment of the present invention is a semiconductor device different from the semiconductor device described in (9) above, including a first circuit and a fifth circuit. The first circuit includes a first current source, a third current source, a first switch, and a fourth switch, and the fifth circuit includes a seventh transistor, an eighth transistor, a second capacitor, a second switch, a third switch, a fifth switch, and a current comparison circuit. Preferably, the output terminal of the first current source is electrically connected to a first terminal of the first switch, and the input terminal of the third current source is electrically connected to a first terminal of the fourth switch. Preferably, the first terminal of the seventh transistor is electrically connected to a first terminal of the eighth transistor, a first terminal of the second switch, and a first terminal of the third switch, and the gate of the seventh transistor is electrically connected to a second terminal of the eighth transistor and a first terminal of the second capacitor. Preferably, the second terminal of the first switch is electrically connected to a second terminal of the second switch, and the second terminal of the fourth switch is electrically connected to a first terminal of the fifth switch. Preferably, the first terminal of the current comparison circuit is electrically connected to the second terminal of the third switch, and the second terminal of the current comparison circuit is electrically connected to the second terminal of the fifth switch.

[0022] (11) Alternatively, in one embodiment of the present invention, in the above-described (9) or (10), the seventh transistor may have silicon in a channel formation region, and the eighth transistor may have metal oxide in a channel formation region.

[0023] (12) Alternatively, in one aspect of the present invention, in the above (10), the fifth circuit may include a ninth transistor, a tenth transistor, a third capacitor, and a sixth switch. Preferably, a first terminal of the ninth transistor is electrically connected to a first terminal of the tenth transistor, a first terminal of the second switch, and a first terminal of the sixth switch, and a gate of the ninth transistor is electrically connected to a second terminal of the tenth transistor and a first terminal of the third capacitor. Preferably, a second terminal of the sixth switch is electrically connected to a first terminal of the fifth switch and a second terminal of the fourth switch. Preferably, a gate of the eighth transistor and a gate of the tenth transistor are not directly connected.

[0024] (13) Alternatively, in one embodiment of the present invention, in the above (12), the seventh transistor and the ninth transistor may each have silicon in a channel formation region, and the eighth transistor and the tenth transistor may each have metal oxide in a channel formation region.

[0025] (14) Another embodiment of the present invention is an electronic device including the semiconductor device described in any one of (1) to (13) above and a housing.

[0026] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, an electronic component in which a chip is housed in a package, etc. are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices or may include semiconductor devices.

[0027] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0028] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0029] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0030] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0031] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0032] Note that even when independent components are shown electrically connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, in this specification, the term "electrically connected" also includes such cases where one conductive film has the functions of multiple components.

[0033] Furthermore, in this specification and the like, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, a wiring having a resistance value higher than 0Ω, etc. Therefore, in this specification and the like, a "resistance element" is intended to include a wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, etc. Therefore, the term "resistance element" can sometimes be replaced with terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be replaced with a resistance value of 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0034] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, a gate capacitance of a transistor, etc. Therefore, in this specification, a "capacitive element" is intended to include a circuit element including a pair of electrodes and a dielectric between the electrodes. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with terms such as "capacitance." Conversely, the term "capacitance" can sometimes be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," "pair of regions," etc. The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0035] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0036] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Furthermore, when operating in the saturation region, the multi-gate structure can provide a voltage-current characteristic with a flat slope, whereby the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing a voltage-current characteristic with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0037] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors electrically connected in series. For example, when a circuit diagram shows one capacitor, this includes two or more capacitors electrically connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors electrically connected in series, with the gates of the transistors electrically connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors electrically connected in series or parallel, with the gates of the transistors electrically connected to each other.

[0038] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0039] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0040] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0041] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current flow and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive or negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0042] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0043] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0044] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0045] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0046] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Furthermore, terms such as "electrode" and "wiring" include cases where multiple "electrodes," "wirings," etc. are integrally formed. Furthermore, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0047] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0048] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0049] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals for passing a current in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific type as long as it can control a current.

[0050] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0051] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0052] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0053] According to one embodiment of the present invention, a semiconductor device or the like that performs a product-sum operation and / or a function operation can be provided. According to one embodiment of the present invention, a semiconductor device that rewrites data stored in a multiplication cell can be provided. According to one embodiment of the present invention, a semiconductor device that stores digital values, performs digital-to-analog conversion on the digital values, and performs an operation using the analog values ​​can be provided. According to one embodiment of the present invention, a semiconductor device or the like that performs convolution processing such as CNN can be provided. According to one embodiment of the present invention, a semiconductor device or the like for AI can be provided. According to one embodiment of the present invention, a semiconductor device or the like for DNN can be provided. According to one embodiment of the present invention, a semiconductor device or the like with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device or the like that is less susceptible to variations in characteristics of transistors can be provided. According to one embodiment of the present invention, a semiconductor device or the like that is less susceptible to variations in characteristics of current sources can be provided. According to one embodiment of the present invention, a novel semiconductor device or the like can be provided.

[0054] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0055] [Figure 1] 1A and 1B are block diagrams showing an example of the configuration of a semiconductor device, and FIG. 1C is a perspective view showing the example of the configuration of a semiconductor device. [Figure 2]2A to 2C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 3] FIG. 3 is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 4] FIG. 4 is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 5] FIG. 5 is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 6] FIG. 6 is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 7] 7A to 7E are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 8] FIG. 8 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 9] FIG. 9 is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 10] FIG. 10A is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device, and FIGS. 10B to 10E are circuit diagrams showing an example of the configuration of a memory cell included in the semiconductor device. [Figure 11] FIG. 11 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 12] FIG. 12 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 13] FIG. 13 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 14] FIG. 14A is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device, and FIG. 14B is a circuit diagram showing an example of the configuration of a part of the circuit included in the circuit. [Figure 15] FIG. 15 is a block diagram showing a configuration example of a semiconductor device. [Figure 16] FIG. 16 is a block diagram showing a configuration example of a semiconductor device. [Figure 17]FIG. 17A is a block diagram showing an example of the configuration of a semiconductor device, and FIG. 17B is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 18] 18A to 18D are circuit diagrams showing configuration examples of semiconductor devices. [Figure 19] FIG. 19 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 20] FIG. 20A is a circuit diagram showing an example of the configuration of a semiconductor device, and FIG. 20B is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 21] FIG. 21A is a circuit diagram showing an example of the configuration of a semiconductor device, and FIG. 21B is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 22] 22A and 22B are circuit diagrams showing configuration examples of semiconductor devices. [Figure 23] FIG. 23 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 24] 24A and 24B are diagrams illustrating a hierarchical neural network. [Figure 25] FIG. 25 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 26] FIG. 26 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 27] 27A to 27C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 28] FIG. 28 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 29] 29A to 29F are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 30] FIG. 30 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 31] FIG. 31 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 32] FIG. 32 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 33] 33A to 33E are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 34] 34A to 34C are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 35] FIG. 35 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 36] 36A to 36C are cross-sectional views showing examples of the structure of a transistor. [Figure 37] FIG. 37 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 38] 38A and 38B are cross-sectional views showing examples of the structure of a transistor. [Figure 39] FIG. 39 is a schematic cross-sectional view showing a configuration example of a transistor. [Figure 40] FIG. 40A is a diagram illustrating the classification of IGZO crystal structures, FIG. 40B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 40C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. [Figure 41] FIG. 41A is a perspective view showing an example of a semiconductor wafer, FIG. 41B is a perspective view showing an example of a chip, and FIGS. 41C and 41D are perspective views showing an example of an electronic component. [Figure 42] FIG. 42 is a schematic diagram illustrating an example of an electronic device. [Figure 43] 43A to 43C are schematic diagrams showing an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0056] In an artificial neural network (hereafter referred to as a neural network), the strength of synaptic connections can be changed by providing existing information to the neural network. This process of providing existing information to a neural network and determining connection strengths is sometimes called "learning."

[0057] Furthermore, by providing some information to a neural network that has undergone "learning" (with connection strengths determined), new information can be output based on the connection strengths. In this way, the process of outputting new information based on the provided information and connection strengths in a neural network is sometimes called "inference" or "cognition."

[0058] Neural network models include, for example, Hopfield and hierarchical types. In particular, neural networks with multi-layer structures are sometimes called "deep neural networks" (DNNs), and machine learning using deep neural networks is sometimes called "deep learning."

[0059] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0060] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0061] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0062] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0063] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0064] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0065] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0066] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m,n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m,n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0067] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0068] (Embodiment 1) In this embodiment, a structure of a semiconductor device according to one embodiment of the present invention will be described.

[0069] <Configuration Example 1 of Semiconductor Device> 1A is a block diagram showing a configuration example of a semiconductor device SDV1 according to one embodiment of the present invention. The semiconductor device SDV1 includes, as an example, a memory device MINT, a circuit ILD, and a calculation unit CLP. FIG. 1A also shows a memory device MEXT to illustrate the configuration of electrical connections with the semiconductor device SDV1.

[0070] As an example, the memory device MEXT is provided outside the semiconductor device SDV1. In this embodiment, the memory device MEXT holds data for calculations to be performed by the calculation unit CLP. The memory device MEXT also transmits the data to the memory device MINT as a digital voltage signal or the like. The memory device MEXT may also transmit the data not only to the memory device MINT but also to a circuit ILD (described later). In other words, the semiconductor device SDV1 may be configured to be able to switch between the memory device MINT and the circuit ILD as the destination of the memory device MEXT.

[0071] Furthermore, when the semiconductor device SDV1 is configured so that the destination of a signal output from the memory device MEXT can be switched between the memory device MINT and the circuit ILD, when data is transmitted from the memory device MEXT to the memory device MINT, the number of bits of the data may be reduced to reduce the memory capacity of the memory device MINT. When data is transmitted from the memory device MEXT to the circuit ILD, the number of bits of the data may be increased. Alternatively, when data is transmitted from the memory device MEXT to the memory device MINT, the high-bit value of the data may be transmitted to reduce the memory capacity of the memory device MINT, and if a low-bit value is required, the low-bit value may be input from the memory device MEXT to the circuit ILD. In other words, data may be input to the circuit ILD simultaneously from the memory device MINT and the memory device MEXT.

[0072] The storage device MEXT may be, for example, a storage such as an HDD (hard disk drive) or an SSD (solid state drive).

[0073] The semiconductor device SDV1 can be fabricated by forming circuit elements and the like on a single substrate BSE, for example.

[0074] Various substrates can be used as the substrate BSE. Examples of various substrates include semiconductor substrates (e.g., single-crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates with stainless steel foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, and base films. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include the following: plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Other examples include synthetic resins such as acrylic. Other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. In particular, by manufacturing transistors using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, it is possible to manufacture transistors with small size, high current capability, and little variation in characteristics, size, or shape. By configuring a circuit using such transistors, it is possible to reduce the power consumption of the circuit or to achieve high integration of the circuit.

[0075] Alternatively, a flexible substrate may be used as the substrate BSE, and the transistors may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistor. The release layer can be used to separate a semiconductor device, after a part or all of the semiconductor device is completed thereon, from the substrate and transfer it to another substrate. In this case, the transistor can also be transferred to a substrate with poor heat resistance, a flexible substrate, or the like. Note that the release layer may be, for example, a laminated structure of inorganic films such as a tungsten film and a silicon oxide film, or a structure in which an organic resin film such as polyimide is formed on a substrate.

[0076] That is, a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed on yet another substrate (e.g., a BSE substrate). Examples of substrates onto which transistors may be transferred include the above-mentioned substrates on which transistors can be formed, as well as paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester), or recycled fibers (acetate, cupra, rayon, recycled polyester)), leather substrates, and rubber substrates. The use of these substrates allows for the formation of transistors with good characteristics, transistors with low power consumption, the manufacture of durable devices, the provision of heat resistance, and the reduction of weight and thickness.

[0077] It is possible to form all of the circuits required to achieve a given function on the same substrate (e.g., a glass substrate, a plastic substrate, a single-crystal substrate, or an SOI substrate), thereby reducing the number of components and thereby reducing costs, and improving reliability by reducing the number of connections to circuit components.

[0078] It is possible that not all of the circuits necessary to realize a predetermined function are formed on the same substrate. That is, a portion of the circuits necessary to realize a predetermined function may be formed on one substrate, and another portion of the circuits necessary to realize the predetermined function may be formed on another substrate. For example, a portion of the circuits necessary to realize a predetermined function may be formed on a glass substrate, and another portion of the circuits necessary to realize the predetermined function may be formed on a single-crystal substrate (or an SOI substrate). Then, the single-crystal substrate (also called an IC chip) on which the other portion of the circuits necessary to realize the predetermined function is formed may be connected to the glass substrate by COG (Chip-On-Glass) and the IC chip may be disposed on the glass substrate. Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Automated Bonding), COF (Chip-On-Film), SMT (Surface Mount Technology), a printed circuit board, or the like. In this way, forming a portion of the circuit on the same substrate as the pixel unit may reduce the number of components, thereby reducing costs, or reduce the number of connections with circuit components, thereby improving reliability. In particular, circuits with high drive voltages or high drive frequencies often consume a lot of power. Therefore, these circuits are formed on a substrate (such as a single-crystal substrate) separate from the pixel section to form an IC chip. Using this IC chip can prevent an increase in power consumption.

[0079] For example, by using a semiconductor substrate containing silicon as the substrate BSE, the transistors included in the calculation unit CLP and the transistors included in the circuit ILD can be formed as Si transistors on the substrate BSE. Furthermore, by using OS transistors as the transistors included in the memory device MINT, the memory device MINT can be provided above the calculation unit CLP and / or the circuit ILD. That is, as an example, the semiconductor device SDV1 can be configured as shown in FIG. 1C , in which the calculation unit CLP and the circuit ILD are provided above the substrate BSE, and the memory device MINT is provided above the calculation unit CLP and the circuit ILD.

[0080] The memory device MINT provided in the semiconductor device SDV1 has a function of, for example, acquiring information read by a memory device MEXT provided outside the semiconductor device SDV1 and storing the information. The memory device MINT also has a function of reading information stored in the memory device MINT and transmitting the information to the circuit ILD. The information sent from the memory device MEXT to the memory device MINT is treated as data for performing calculations by a calculation unit CLP, which will be described later.

[0081] In this specification, the memory device MINT is described as storing digital values. By configuring the memory device MINT as a memory device that stores digital values, even if the absolute value of the charge amount stored in the memory element decreases, the range of potentials from which data can be read is wide, allowing data to be read unchanged from when it was written. Furthermore, in the case of a memory device that stores digital values, refreshing data stored in the memory element is easy, allowing the potential (charge) stored in the memory element to be maintained for a long time. Therefore, it is preferable that the memory device MINT have a function to periodically refresh the data stored therein. Furthermore, a refresh operation may be performed after transmitting data to the calculation unit CLP (circuit ILD) described below. In this specification, data refresh refers to the operation of reading a voltage corresponding to the data in the memory element, boosting or lowering the voltage to an appropriate level using an amplifier circuit such as a sense amplifier, and writing the voltage back to the memory element. When properly rewriting data in a memory cell of the memory device MINT, data may be read from the memory device MEXT and written to the memory cell. Furthermore, the memory device MINT of the semiconductor device of the present invention may be configured to store not only digital values ​​but also multi-values, analog values, etc. Furthermore, for example, if the memory cells of the memory device MINT are configured to be able to hold multiple values ​​(multiple bits), by making the number of bits of the memory cells smaller than the number of bits held in the multiplication cells of the calculation unit CLP, multiple memory cells of the memory device MINT can be made to correspond to one multiplication cell of the calculation unit CLP. For example, if each memory cell of the memory device MINT can hold a 4-bit value and each multiplication cell of the calculation unit CLP can hold an 8-bit value, an 8-bit value can be written to the multiplication cell of the calculation unit CLP by writing two 4-bit values ​​to the memory cells of the memory device MINT.

[0082] The transistor included in the memory device MINT is preferably, for example, an OS transistor. In particular, the metal oxide included in the channel formation region of the OS transistor is preferably, for example, an In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.). Alternatively, the transistor may be a transistor having silicon in the channel formation region (hereinafter referred to as a Si transistor). Examples of silicon that can be used include single-crystal silicon, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, and polycrystalline silicon. In addition, examples of transistors that can be used other than OS transistors and Si transistors include transistors that contain Ge or the like in the channel formation region, transistors that contain compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, and SiGe in the channel formation region, transistors that contain carbon nanotubes in the channel formation region, and transistors that contain organic semiconductors in the channel formation region.

[0083] As an example, the circuit ILD functions as a current source circuit for supplying a current to the calculation unit CLP. Specifically, the circuit ILD supplies a current corresponding to information read from the memory device MINT to a circuit included in the calculation unit CLP. Note that the circuit ILD may function not as a current source circuit for supplying a current to the calculation unit CLP, but as a voltage source circuit (voltage generation circuit) for inputting a voltage corresponding to information read from the memory device MINT to the calculation unit CLP, for example.

[0084] The calculation unit CLP has a plurality of circuits functioning as multiplication cells. For example, the multiplication cells have the function of storing data used in calculations as analog values. The circuits are arranged in a matrix in the calculation unit CLP. The circuits store information (e.g., current, voltage, etc.) sent from the circuit ILD, and then input a voltage corresponding to a multiplier to the calculation unit CLP, thereby calculating the product of a value corresponding to the information and the multiplier. When the product calculated by the circuits is output as a current, the currents output from the multiple circuits are added together, and the sum of the currents corresponds to the sum of the products of the information (e.g., current, voltage, etc.) stored in the multiple circuits and the multiple multipliers. The calculation unit CLP also includes a drive circuit for operating the multiplication cells. The circuit configuration of the calculation unit CLP and the principle of product-sum calculation in the calculation unit CLP will be described in detail in the second embodiment.

[0085] Incidentally, when the memory device MINT has the function of storing digital values ​​and the multiplication cells of the calculation unit CLP have the function of storing analog values, digital-to-analog conversion is required when transmitting data used in calculations from the memory device MINT to the calculation unit. In this case, it is preferable that the circuit ILD has the function of not only a current source circuit but also a digital-to-analog conversion circuit. Furthermore, the larger the analog data written to the calculation unit CLP, the larger the memory capacity required for the memory device MINT. Specifically, for example, if one multiplication cell in the calculation unit CLP stores data corresponding to an 8-bit numerical value, the memory device MINT requires eight binary memory cells. In this case, since the circuit area of ​​the memory device MINT needs to be increased, it is preferable that the semiconductor device SDV1 be configured such that the memory device MINT is provided above the calculation unit CLP (including a circuit for driving the calculation unit CLP) and the circuit ILD, as shown in FIG. 1C above. Furthermore, the area per memory cell can be reduced by using a trench type capacitor for the memory cell of the memory device MINT.

[0086] Furthermore, if the multiplication cells of the calculation unit CLP have the function of storing analog values, leakage current from the multiplication cells may deteriorate the analog data stored in the multiplication cells. For this reason, it is preferable that the semiconductor device SDV1 periodically converts digital data stored in the memory device MINT (the same value as the data stored in the multiplication cells) into analog data using the circuit ILD, transmits the analog data to the calculation unit CLP, and rewrites it into the memory elements of the multiplication cells of the calculation unit CLP (by inputting current, voltage, etc., or replenishing charge). In this case, the memory device MINT functions as a circuit for storing digital data equivalent to the analog data to compensate for the analog data stored in the memory elements of the multiplication cells of the calculation unit CLP. With this configuration, the memory device MINT may also be referred to as a main memory for the calculation unit CLP. In this case, the memory elements provided in the multiplication cells of the calculation unit CLP can be considered as temporary memories. Furthermore, for example, if the memory cells MCL of the memory device MINT are circuits capable of holding digital data (2 bits) and the multiplication cells of the arithmetic unit CLP are circuits capable of holding analog data equivalent to 8 bits, the memory cells MCL of the memory device MINT can hold data longer than the multiplication cells of the arithmetic unit CLP (because the data value is less likely to change due to a decrease in the absolute value of the charge amount caused by leakage current), and therefore it is preferable to treat the memory device MINT as a main memory. Furthermore, since operations that handle analog data are more computationally efficient than operations that handle digital data, it is preferable that the semiconductor device SDV1 be configured to convert digital data read out from the memory device MINT into analog data and perform operations that handle the analog data in the arithmetic unit CLP.

[0087] Furthermore, the semiconductor device SDV1 may have a plurality of arithmetic units CLP. For example, as shown in FIG. 1B, instead of the arithmetic unit CLP of FIG. 1A, the semiconductor device SDV1 may have arithmetic units CLPa and CLPb. By providing a plurality of arithmetic units in this way, the semiconductor device SDV1 can, for example, write data transmitted from the memory device MINT to one of the arithmetic units CLPa or CLPb, and during that time, perform an operation in the other of the arithmetic units CLPa or CLPb.

[0088] 1B, one of the calculation units CLPa and CLPb may be a circuit that performs analog calculations, and the other of the calculation units CLPa and CLPb may be a circuit that performs digital calculations.Furthermore, both the calculation units CLPa and CLPb may be circuits that perform digital calculations.

[0089] <<Circuit ILD>> Here, a specific example of the circuit configuration of the circuit ILD will be described. Here, a VI conversion circuit (sometimes called a digital-to-analog conversion circuit) that outputs an analog current based on a digital value read from the memory device MINT will be described as the circuit ILD. The circuit ILD shown in FIG. 2A is an example of a current source circuit that can be applied to the circuit ILD of FIG. 1A. The circuit ILD of FIG. 2A has a circuit WCS1, which has constant current sources CC[1] to CC[K] (K is an integer equal to or greater than 1) and switches SW[1] to SW[K].

[0090] An input terminal of the constant current source CC[u] (u is an integer between 1 and K) is electrically connected to the wiring VDL, an output terminal of the constant current source CC[u] is electrically connected to a first terminal of the switch SW[u], a second terminal of the switch SW[u] is electrically connected to the wiring IL, and a control terminal of the switch SW[u] is electrically connected to the wiring DIL[u].

[0091] The wirings DIL[1] to DIL[K] shown in Fig. 2A are electrically connected to the memory device MINT included in the semiconductor device SDV1 of Fig. 1 A. That is, the wirings DIL[1] to DIL[K] function as wirings for transmitting information read from the memory device MINT.

[0092] The wiring VDL functions as a wiring that applies a constant voltage, for example, which is preferably a high-level potential.

[0093] The wiring IL functions as a wiring for electrically connecting to the calculation unit CLP. In other words, the wiring IL functions as a wiring for passing a current generated by the circuit ILD according to the information held in the memory device MINT to the calculation unit CLP. The wiring IL functions, for example, as a write data line extending to the calculation unit CLP. Therefore, when the calculation unit CLP has multiple columns of multiplication cells, it is preferable that the circuit ILD has multiple circuits WCS1. Furthermore, depending on the configuration of the calculation unit CLP, two write data lines may be provided for multiple multiplication cells arranged in one column. Therefore, in FIG. 2A, one of the wirings is illustrated as the wiring IL, and the other wiring is illustrated in parentheses as the wiring ILB.

[0094] The circuit WCS1 of FIG. 2A is, for example, a K-bit (2 K The circuit WCS1 has the function of outputting information of the value of the 1st bit (K is an integer of 1 or more) as a current. Specifically, for example, information corresponding to the value of the 1st bit is input to the wiring DIL[1], information corresponding to the value of the uth bit is input to the wiring DIL[u], and information corresponding to the value of the Kth bit is input to the wiring DIL[K], and the circuit WCS1 can determine the amount of current to be passed through the wiring IL. At this time, the constant current passed by the constant current source CC[1] is defined as I ut When this is done, the constant current flowing from the constant current source CC[u] is 2 u-1 ×I ut The constant current flowing from the constant current source CC[K] is 2 K-1 ×I ut It is preferable to set the following.

[0095] A decoder DEC for converting binary numbers to decimal numbers may be provided between the memory device MINT and the circuit ILD. The circuit configuration of the circuit ILD in this case is shown in FIG. 2B. In FIG. 2B, the circuit WCS2 included in the circuit ILD includes constant current sources CC[1] to CC[2]. K -1] and switches SW[1] to SW[2 K -1].

[0096] The decoder DEC is electrically connected to the wirings DIL[1] to DIL[K], and is also electrically connected to the wirings DEL[1] to DEL[2]. K -1]. Also, the constant current source CC[t] (t is 1 or more, 2 K An input terminal of constant current source CC[t] is electrically connected to a wiring VDL, an output terminal of constant current source CC[t] is electrically connected to a first terminal of switch SW[t], a second terminal of switch SW[t] is electrically connected to wiring IL, and a control terminal of switch SW[t] is electrically connected to wiring DEL[t].

[0097] The decoder DEC converts the K-bit (binary) information sent to the wiring DIL[1] to the wiring DIL[K] into decimal information and outputs it to the wiring DEL[1] to the wiring DEL[2]. K -1].

[0098] The circuit WCS2 of FIG. 2B is, for example, a K-bit (2 K However, since the circuit WCS2 receives information converted into decimal by the decoder DEC, the constant current sources CC[1] to CC[2] are used to output the information of the constant current sources CC[1] to CC[2]. K -1] flows a constant current of I ut It is preferable to set the following.

[0099] The constant current source CC included in the circuit WCS1 of Fig. 2A and the circuit WCS2 of Fig. 2B may be configured to include, for example, a transistor. Furthermore, the switch SW included in the circuit WCS1 of Fig. 2A and the circuit WCS2 of Fig. 2B may be, for example, an electrical switch such as an analog switch or a transistor. Furthermore, the switch SW may be, for example, a mechanical switch.

[0100] In this specification and the like, the switch SW is assumed to be in an off state when a high-level potential is applied to the control terminal, and to be in an on state when a low-level potential is applied to the control terminal.

[0101] A specific example of the above is shown in Fig. 2C. The circuit ILD in Fig. 2C has a circuit configuration in which, in the circuit ILD in Fig. 2A, for example, the constant current source CC[1] has a transistor CTr[1], the constant current source CC[u] has a transistor CTr[u], for example, the constant current source CC[K] has a transistor CTr[K], the switch SW[1] has a transistor STr[1], the switch SW[u] has a transistor STr[u], and the switch SW[K] has a transistor STr[K].

[0102] 2C, it is preferable to use Si transistors as the transistors CTr[1] to CTr[K] and the transistors STr[1] to STr[K]. As transistors other than Si transistors, for example, transistors including Ge or the like in a channel formation region, transistors including a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe in a channel formation region, transistors including carbon nanotubes in a channel formation region, and transistors including an organic semiconductor in a channel formation region can be used.

[0103] 2C, the transistors CTr[1] to CTr[K] and the transistors STr[1] to STr[K] are p-channel transistors, for example. Depending on the circumstances, the transistors CTr[1] to CTr[K] and the transistors STr[1] to STr[K] may be n-channel transistors. When the transistors CTr[1] to CTr[K] and the transistors STr[1] to STr[K] are n-channel transistors, the transistors CTr[1] to CTr[K] and the transistors STr[1] to STr[K] may be OS transistors.

[0104] For example, the first terminal of the transistor CTr[1] is electrically connected to the wiring VDL, the second terminal of the transistor CTr[1] is electrically connected to the first terminal of the transistor STr[1], and the second terminal of the transistor STr[1] is electrically connected to the wiring IL. The gate of the transistor CTr[1] is electrically connected to the wiring BIAL, and the gate of the transistor STr[1] is electrically connected to the wiring DIL[1]. For example, the first terminal of the transistor CTr[u] is electrically connected to the wiring VDL, the second terminal of the transistor CTr[u] is electrically connected to the first terminal of the transistor STr[u], and the second terminal of the transistor STr[u] is electrically connected to the wiring IL. The gate of the transistor CTr[u] is electrically connected to the wiring BIAL, and the gate of the transistor STr[u] is electrically connected to the wiring DIL[u]. For example, a first terminal of the transistor CTr[K] is electrically connected to the wiring VDL, a second terminal of the transistor CTr[K] is electrically connected to the first terminal of the transistor STr[K], and a second terminal of the transistor STr[K] is electrically connected to the wiring IL. A gate of the transistor CTr[K] is electrically connected to the wiring BIAL, and a gate of the transistor STr[K] is electrically connected to the wiring DIL[K].

[0105] For example, the wiring BIAL functions as a wiring that applies a constant voltage. Since the wiring BIAL is electrically connected to the gates of the transistors CTr[1] to CTr[K], the constant voltage functions as a bias voltage for causing current to flow through each of the transistors CTr[1] to CTr[K]. The bias voltage is preferably, for example, a low-level potential or a ground potential.

[0106] In the case of the circuit ILD of FIG. 2C, when the ratio of the channel width (hereinafter referred to as W length) to the channel length (hereinafter referred to as L length) of the transistor CTr[1] is W / L, the ratio of the W length to the L length of the transistor CTr[u] is 2 u-1 ×W / L or a value close to it, and the ratio of the W length to the L length of the transistor CTr[K] is preferably 2 K-1 × W / L or a value close to that. As a result, the ratio of the currents flowing through the transistors CTr[1], CTr[u], and CTr[K] is approximately 1:2. u-1 :2 K-1 In addition, 2 u-1 × W / L, for example, 2 u-1 × W / L. K-1 × W / L, for example, 2 K-1 × W / L.

[0107] Or, in the circuit ILD of FIG. 2C, the transistor CTr[u] is 2 u-1 Alternatively, the transistor CTr[K] may be replaced with a configuration in which two transistors having the same structure are electrically connected in parallel, and the gates of the respective transistors are electrically connected to the wiring DIL[u]. K-1Alternatively, the transistors CTr[1], CTr[u], and CTr[K] may be electrically connected in parallel, with the gates of the transistors electrically connected to the wiring DIL[K]. This allows the ratio of the currents flowing through the transistors CTr[1], CTr[u], and CTr[K] to be approximately 1:2. u-1 :2 K-1 This becomes:

[0108] Unless otherwise specified, the transistor CTr is considered to ultimately operate in the saturation region when it is on. That is, the gate voltage, source voltage, and drain voltage of the transistor CTr are considered to include a case where they are appropriately biased to voltages within the range where they operate in the saturation region. However, one aspect of the present invention is not limited to this. The transistor CTr may operate in the linear region in order to reduce the amplitude of the supplied voltage. Furthermore, the transistor CTr may operate in the subthreshold region in order to reduce the amount of current flowing through the transistor CTr. Alternatively, the transistor CTr may be operated near the boundary between the saturation region and the subthreshold region. In this specification and the like, the vicinity of the boundary between the saturation region and the subthreshold region refers to, for example, when the threshold voltage of the transistor is set to V th When the gate-source voltage is V th -1.0V or more, V th -0.5V or more, or V th -0.1V or more, and V th +0.1V or less, V th +0.5V or less, or V th This includes cases where the voltage is +1.0 V or less. Note that the above-mentioned lower limit and upper limit values ​​can be combined with each other. Alternatively, for example, the transistor CTr may operate in a mixture of a linear region, a saturation region, and a subthreshold region, or may operate in a mixture of a linear region and a saturation region, or may operate in a mixture of a saturation region and a subthreshold region, or may operate in a linear region and a subthreshold region.

[0109] Furthermore, in this specification and the like, unless otherwise specified, the transistor STr is considered to ultimately operate in the linear region when it is on. That is, the transistor STr is considered to include a case where the gate voltage, source voltage, and drain voltage are appropriately biased to voltages within the range in which it operates in the linear region. However, one embodiment of the present invention is not limited thereto. For example, the transistor STr may operate in the saturation region or the subthreshold region when it is on. Alternatively, the transistor STr may operate near the boundary between the saturation region and the subthreshold region. Alternatively, the transistor STr may operate in both the linear region and the saturation region, or may operate in both the saturation region and the subthreshold region, or may operate in the linear region, the saturation region, and the subthreshold region.

[0110] Note that the circuit ILD may be, for example, a digital-to-analog conversion circuit using an operational amplifier, instead of the configurations shown in Figures 2A to 2C. Note that, when power consumption is to be reduced, it is preferable to use the VI conversion circuit having the configurations shown in Figures 2A to 2C.

[0111] <<Configuration example 1 of memory device MINT and circuit ILD>> Next, the memory device MINT and the electrical connection configuration between the memory device MINT, the circuit ILD, and the arithmetic unit CLP will be described.

[0112] FIG. 3 is a circuit configuration example showing the memory device MINT, a part of the circuit ILD in FIG. 2A described above, and a part of the calculation unit CLP.

[0113] 3 is, by way of example, a part of the arithmetic circuit 110 described in embodiment 2. Therefore, for details of the arithmetic unit CLP shown in FIG. 3, the description of embodiment 2 should be referred to.

[0114] 3 has a configuration in which two write data lines are provided in a plurality of multiplication cells arranged in one column. One of the write data lines, a wiring IL, is electrically connected to a circuit WCS1 included in a circuit ILD. Although the electrical connection between the other write data line, a wiring ILB, and the circuit ILD is not shown, it is assumed that the wiring ILB is electrically connected to a circuit WCS1 different from the wiring IL.

[0115] The memory device MINT has a configuration including a memory circuit called NOSRAM (Nonvolatile Oxide Semiconductor Random Access Memory) (registered trademark). Specifically, in Fig. 3, the memory device MINT includes memory cells MCL[1] to MCL[m] (m is an integer of 1 or more), a switch RSW, a circuit WWD, and a circuit RWD, and each of the memory cells MCL[1] to MCL[m] includes a transistor F1 to a transistor F3 and a capacitance CI.

[0116] As described above, each of the transistors F1 to F3 can be an OS transistor. Alternatively, each of the transistors F1 to F3 can be a Si transistor. Examples of transistors other than OS transistors and Si transistors include transistors whose channel formation regions include Ge, transistors whose channel formation regions include compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, and SiGe, transistors whose channel formation regions include carbon nanotubes, and transistors whose channel formation regions include organic semiconductors.

[0117] In addition, by using an OS transistor as the transistor included in the memory device MINT and an OS transistor as the transistor included in the calculation unit CLP, the OS transistors may be fabricated simultaneously in the same process. By fabricating the OS transistors included in the memory device MINT and the calculation unit CLP simultaneously, the fabrication time of the semiconductor device SDV1 can be shortened.

[0118] Unless otherwise specified, the transistor F1 is considered to ultimately operate in the saturation region when it is on. That is, the transistor F1 is considered to ultimately operate in the saturation region when it is on. That is, the transistor F1 includes a case where the gate voltage, source voltage, and drain voltage are appropriately biased to voltages within the range in which the transistor F1 operates in the saturation region. However, one embodiment of the present invention is not limited thereto. The transistor F1 may operate in the linear region to reduce the amplitude of the supplied voltage. Furthermore, the transistor F1 may operate in the subthreshold region to reduce the amount of current flowing through the transistor F1. Alternatively, the transistor F1 may operate near the boundary between the saturation region and the subthreshold region. Alternatively, for example, the transistor F1 may operate in a combination of the linear region, the saturation region, and the subthreshold region, or may operate in a combination of the linear region and the saturation region, or may operate in a combination of the saturation region and the subthreshold region, or may operate in a combination of the linear region and the subthreshold region.

[0119] Furthermore, in this specification and the like, unless otherwise specified, the transistors F2 and F3 are considered to ultimately operate in a linear region when they are on. That is, the gate voltage, source voltage, and drain voltage of each of the above-described transistors are considered to include a case where they are appropriately biased to voltages within a range in which they operate in a linear region. However, one embodiment of the present invention is not limited thereto. For example, the transistors F2 and F3 may operate in a saturation region or a subthreshold region when they are on. Alternatively, the transistors F2 and F3 may operate near the boundary between the saturation region and the subthreshold region. Alternatively, the transistors F2 and F3 may operate in a linear region and a saturation region in a mixed manner, or may operate in a saturation region and a subthreshold region in a mixed manner, or may operate in a linear region, a saturation region, and a subthreshold region in a mixed manner, or may operate in a linear region and a subthreshold region in a mixed manner.

[0120] The switch RSW may be, for example, an electrical switch such as an analog switch or a transistor, or the switch SW may be, for example, a mechanical switch.

[0121] In this specification and the like, the switch RSW is assumed to be in an on state when a high-level potential is applied to the control terminal, and in an off state when a low-level potential is applied to the control terminal.

[0122] As an example, the memory device MINT can be configured such that memory cells MCL are arranged in a matrix. For example, the memory device MINT can be configured such that memory cells MCL[1] to MCL[m] form one column, and multiple columns are arranged in the memory device MINT. Note that in the memory device MINT of FIG. 3, memory cells MCL[1] to MCL[m] are arranged in K columns, and only the memory cells MCL[1] to MCL[m] in the u-th column are shown here.

[0123] The memory cells MCL[1] to MCL[m] in the u-th column of the memory device MINT are electrically connected to the wiring DIL[u]. That is, the memory cells MCL[1] to MCL[m] in the u-th column are electrically connected to the switch SW[u] of the circuit WCS1 included in the circuit ILD.

[0124] In the memory cell MCL[1], the first terminal of the transistor F1 is electrically connected to the wiring VEA, the second terminal of the transistor F1 is electrically connected to the first terminal of the transistor F3, and the gate of the transistor F1 is electrically connected to the first terminal of the transistor F2 and the first terminal of the capacitor CI. The second terminal of the transistor F2 is electrically connected to the wiring WBL[u], and the gate of the transistor F2 is electrically connected to the wiring WWL[1]. The second terminal of the transistor F3 is electrically connected to the wiring RBL[u], and the gate of the transistor F3 is electrically connected to the wiring RWL[1]. The second terminal of the capacitor CI is electrically connected to the wiring VEA.

[0125] In the memory cell MCL[m], the first terminal of the transistor F1 is electrically connected to the wiring VEA, the second terminal of the transistor F1 is electrically connected to the first terminal of the transistor F3, and the gate of the transistor F1 is electrically connected to the first terminal of the transistor F2 and the first terminal of the capacitor CI. The second terminal of the transistor F2 is electrically connected to the wiring WBL[u], and the gate of the transistor F2 is electrically connected to the wiring WWL[m]. The second terminal of the transistor F3 is electrically connected to the wiring RBL[u], and the gate of the transistor F3 is electrically connected to the wiring RWL[m]. The second terminal of the capacitor CI is electrically connected to the wiring VEA.

[0126] The wirings WWL[1] to WWL[m] are electrically connected to the circuit WWD, and the wirings RWL[1] to RWL[m] are electrically connected to the circuit RWD.

[0127] The wiring RBL[u] is electrically connected to a first terminal of the switch RSW and the wiring DIL[u]. The second terminal of the switch RSW is electrically connected to the wiring VDL2. The control terminal of the switch RSW is electrically connected to the wiring SL11.

[0128] The wirings WWL[1] to WWL[m] function as write word lines for the memory cells MCL[1] to MCL[m], respectively. The circuit WWD is a driver circuit that selects a memory cell to be written and has a function of transmitting a selection signal for writing to any one of the wirings WWL[1] to WWL[m].

[0129] The wirings RWL[1] to RWL[m] function as read word lines for the memory cells MCL[1] to MCL[m], respectively. The circuit RWD is a driver circuit that selects a memory cell from which data is to be read and has a function of transmitting a read selection signal to any one of the wirings RWL[1] to RWL[m].

[0130] The wiring WBL[u] functions as a write data line (sometimes called a write bit line) in the memory cells MCL[1] to MCL[m]. Note that the wiring WBL[u] is electrically connected to the memory device MEXT in FIG. 1 because the memory device MINT holds information sent from the memory device MEXT. In other words, the wiring WBL[u] functions as a wiring for transmitting information read from the memory device MEXT to the memory device MINT.

[0131] The wiring RBL[u] functions as a read data line (sometimes referred to as a read bit line) in the memory cells MCL[1] to MCL[m].

[0132] The wiring VDL2 functions as a wiring for precharging the wiring RBL[u] with a predetermined potential before reading data stored in any one of the memory cells MCL[1] to MCL[m] of the memory device MINT. Therefore, the wiring VDL2 is preferably a wiring for applying a constant voltage. Furthermore, the constant voltage (the voltage precharged to the wiring RBL[u]) can be, for example, a high-level potential.

[0133] For example, the wiring VEA functions as a wiring that applies a source potential to the first terminal of the transistor F1. Therefore, the wiring VEA is preferably a wiring that applies a constant voltage. Furthermore, the constant voltage (voltage precharged to the wiring RBL[u]) can be, for example, a low-level potential.

[0134] Furthermore, the wiring VEA functions as a wiring that applies a constant voltage, thereby fixing the potential of the second terminal of the capacitor CI. This allows the first terminal of the capacitor CI to be in a floating state, thereby maintaining the voltage between the first and second terminals of the capacitor CI, for example, the gate-source voltage of the transistor F1. Note that the second terminal of the capacitor CI may be electrically connected to another wiring that applies a constant voltage, instead of the wiring VEA.

[0135] The wiring SL11 functions as a wiring for transmitting a control signal (digital value) that switches the switch RSW between an on state and an off state.

[0136] [Writing to the MINT memory device] When writing data read from the memory cell MEXT to the memory cell MCL[1], first, a low-level potential is input to each of the wirings RWL[1] to RWL[m] to turn off the transistor F3 of each of the memory cells MCL[1] to MCL[m]. Next, a high-level potential is input to the wiring WWL[1], and a low-level potential is input to the wirings WWL[2] to WWL[m]. This turns on the transistor F2 of the memory cell MCL[1], and turns off the transistor F2 of each of the memory cells MCL[2] to MCL[m]. Here, a potential V corresponding to the data read from the memory cell MEXT is input to the wiring WBL[u]. DATA By inputting, the potential of the first terminal of the capacitance CI of the memory cell MCL[1] becomes V DATA After that, a low level potential is input to the wiring WWL[1] to turn off the transistor F2 of the memory cell MCL[1], and V is input to the memory cell MCL[1] as the information read from the memory device MEXT. DATA can be held.

[0137] [Reading from the memory device MINT] Memory cell MCL[1] to V DATA When reading out and inputting to the circuit ILD, first, a high-level potential is applied to the wiring SL11 to turn on the switch RSW. As a result, the potential of the wiring RBL[u] becomes the high-level potential applied by the wiring VDL2. Here, the high-level potential applied by the wiring VDL2 is V PR In addition, the potential of the wiring RBL[u] is V PR After the potential of the wiring RBL[u] reaches a high level potential, a low level potential is applied to the wiring SL11 to turn off the switch RSW, thereby completing the precharging of the wiring RBL[u].PR Therefore, in the circuit ILD, the switch SW[u] is in the OFF state, and the current generated by the current source CC[u] does not flow through the wire IL.

[0138] Next, a high-level potential is input to the wiring RWL[1], and a low-level potential is input to the wirings RWL[2] to RWL[m]. As a result, the transistor F2 of the memory cell MCL[1] is turned on, and the transistors F2 of the memory cells MCL[2] to MCL[m] are turned off. At this time, in the memory cell MCL[1], conduction is established between the second terminal of the transistor F1 and the wiring RBL[u], so that the second terminal of the transistor F1 is supplied with a potential V PR At this time, the gate-source voltage of transistor F1 is V DATA -V S And V DATA -V S is the threshold voltage V of transistor F1. th When the potential of the second terminal of the transistor F1 is higher than V, a current flows between the source and drain of the transistor F1. As a result of the current flowing between the source and drain of the transistor F1, the potential of the precharged wiring RBL[u] decreases, and when the potential of the second terminal of the transistor F1 decreases to a predetermined potential, the transistor F1 is turned off. DATA -V S is the threshold voltage V of transistor F1. th When the potential of the precharged wiring RBL[u] is lower than , the transistor F1 is turned off, and no current flows between the source and drain of the transistor F1, so the potential of the precharged wiring RBL[u] does not change.

[0139] As described above, whether the potential of the precharged line RBL[u] fluctuates or not depends on the voltage held at the first terminal of the capacitor CI. Therefore, by inputting a high-level potential to the line RWL[1] to turn on the transistor F3 and then measuring the potential of the line RBL[u], the voltage held at the first terminal of the capacitor CI can be read.

[0140] In addition, since the wiring RBL[u] is electrically connected to the wiring DIL[u], a change in the potential of the wiring RBL[u] also changes the potential of the wiring DIL[u]. Therefore, a potential corresponding to the information read from the memory cell MCL[1] is applied to the control terminal of the switch SW[u] of the circuit WCS1, thereby determining the on / off state of the switch SW[u]. Specifically, V DATA -V S is the threshold voltage V of transistor F1. th When the potential of the wiring DIL[u] is higher than V PR Since the voltage is lower than V, the switch SW[u] is turned on. DATA -V S is the threshold voltage V of transistor F1. th When the potential of the wiring DIL[u] is lower than V PR Since the signal level remains unchanged, the switch SW[u] remains in the off state.

[0141] 3, the information stored in each of the memory cells MCL[1] to MCL[m] in the u-th column of the memory cell MINT can be associated with the on / off state of the switch SW[u] in the circuit WCS1. In addition, the circuit configuration of FIG. 3 eliminates the need for a read circuit for reading data from the memory device, thereby enabling reductions in circuit area and power consumption.

[0142] 3 is applied to the semiconductor device SDV1, it is possible to read data from the memory device MINT and write the data to the multiplication cells of the calculation unit CLP. In addition, by performing this operation at regular intervals, it is possible to periodically rewrite data (absolute value of the reduced amount of charge) degraded by leakage current in the multiplication cells of the calculation unit CLP to the original data (absolute value of the original amount of charge). In other words, by applying the configuration shown in FIG. 3 to the semiconductor device SDV1, it is possible to easily perform a rewrite operation on the data held in the memory elements of the multiplication cells of the calculation unit CLP.

[0143] <<Configuration example 2 of memory device MINT and circuit ILD>> Furthermore, the configuration of the memory device MINT and the circuit ILD according to one embodiment of the present invention is not limited to the circuit configuration shown in Fig. 3. The configuration of the memory device MINT and the circuit ILD may be modified in terms of the included circuit elements, connection configuration, and the like, depending on the case or situation.

[0144] For example, the configuration of the memory device MINT and the circuit ILD shown in Fig. 3 may be changed to the circuit configuration shown in Fig. 4. Fig. 4 shows a configuration in which a circuit BF is provided between the electrical paths of the wiring RBL[u] and the wiring DIL[u] in Fig. 3.

[0145] The circuit BF can include, for example, an amplifier circuit such as a buffer circuit, an inverter circuit, or a latch circuit. Specifically, the circuit BF can have a function of referring to the potential of the wiring RBL[u] and outputting the amplified potential to the wiring DIL[u].

[0146] As shown in FIG. 4, by providing the circuit BF, it is possible to stabilize the potential input to the control terminal of the switch SW[u].

[0147] By applying the configuration shown in FIG. 4 to the semiconductor device SDV1, it is possible to easily perform the rewrite operation on the data held in the storage element of the multiplication cell of the arithmetic unit CLP.

[0148] <<Configuration example 3 of memory device MINT and circuit ILD>> 5 is a circuit configuration example showing the memory device MINT, a part of the circuit ILD described above, and the arithmetic unit CLP in the case where the decoder DEC is electrically connected to the circuit ILD as shown in FIG. 2B. As shown in FIG. 5, the memory device MINT is electrically connected to the decoder DEC via wirings DIL[1] to DIL[K], and the circuit ILD is electrically connected to the decoder DEC via wirings DEL[1] to DEL[L].

[0149] For details of the calculation unit CLP, please refer to the explanation of the calculation unit CLP shown in FIG.

[0150] 5, as an example, similar to FIG. 3, the memory device MINT in FIG. 5 has a configuration including a memory circuit called NOSRAM (registered trademark). Note that the memory device MINT in FIG. 5 has a configuration in which memory cells similar to memory cells MCL[1] to MCL[m] shown in FIG. 3 are arranged in a matrix of m rows and K columns. In addition, in FIG. 5, the memory cells arranged in the matrix are referred to as memory cells MCL[1,1] to MCL[m,K]. The memory device MINT in FIG. 5 also has switches RSW[1] to RSW[K], a circuit WWD, and a circuit RWD, which correspond to the switch RSW shown in FIG. 3.

[0151] For the circuit WWD and the circuit RWD, please refer to the description of the circuit WWD and the circuit RWD shown in FIG.

[0152] The memory cells MCL[1,1] to MCL[m,1] located in the first column are electrically connected to the wirings WBL[1] and RBL[1]. The memory cells MCL[1,K] to MCL[m,K] located in the K-th column are electrically connected to the wirings WBL[K] and RBL[K]. The memory cells MCL[1,1] to MCL[1,K] located in the first row are electrically connected to the wirings WWL[1] and RWL[1]. The memory cells MCL[m,1] to MCL[m,K] located in the m-th row are electrically connected to the wirings WWL[m] and RWL[m].

[0153] The wiring RBL[1] is electrically connected to a first terminal of the switch RSW[1] and a wiring DIL[1]. The second terminal of the switch RSW[1] is electrically connected to a wiring VDL2. The wiring RBL[K] is electrically connected to a first terminal of the switch RSW[m] and a wiring DIL[K]. The second terminal of the switch RSW[K] is electrically connected to a wiring VDL2. The control terminals of the switches RSW[1] to RSW[K] are electrically connected to a wiring SL11.

[0154] In the memory device MINT of Figure 5, by performing a data read operation in the same manner as the memory device MINT shown in Figure 3, information read from multiple memory cells MCL in any one of the first to mth rows can be input to the decoder DEC.

[0155] For example, when memory cells MCL[1,1] to MCL[1,K] located in the first row are selected in a read operation of the memory device MINT in FIG. 5, the information read from memory cells MCL[1,1] to MCL[1,K] is input to the decoder DEC via wiring DIL[1] to wiring DIL[K]. At this time, K-bit data is transmitted to the decoder DEC from wiring DIL[1] to wiring DIL[K]. The decoder DEC converts the binary data transmitted from wiring DIL[1] to wiring DIL[K] into decimal data and outputs the converted data from wiring DEL[1] to wiring DEL[2]. K As a result, the switches SW[1] to SW[2] of the circuit WCS2 included in the circuit ILD are K Decimal data from the decoder DEC is input to the control terminals of the switches SW[1] to SW[2]. K That is, the number of switches that are turned on among the switches SW[1] to SW[2] is determined by the information written in the memory cells MCL located in one row of the memory device MINT. KThe number of switches that are turned on among [1-1] is determined, and a current according to the number of switches that are turned on flows from the circuit WCS2 to the wire IL.

[0156] 5 as the semiconductor device SDV1, it is possible to read data from the memory device MINT and write the data to the multiplication cells of the arithmetic unit CLP, as in the case of FIG. 3. Furthermore, by performing this operation at regular intervals, it is possible to periodically rewrite data degraded by leakage current (absolute value of the reduced amount of charge) to the original data (absolute value of the original amount of charge) in the multiplication cells of the arithmetic unit CLP. In other words, even by applying the configuration shown in FIG. 5 as the semiconductor device SDV1, it is possible to easily perform the operation of rewriting data held in the memory elements of the multiplication cells of the arithmetic unit CLP.

[0157] 3 to 5 include three transistors and one capacitor, but one embodiment of the present invention is not limited to this. In one embodiment of the present invention, for example, the memory cell MCL included in the memory device MINT may include two transistors and one capacitor. An example of such a configuration is shown in FIG. 6. The memory cell MCL of the memory device MINT shown in FIG. 6 differs from the memory cell MCL of the memory device MINT shown in FIGS. 3 to 5 in that it does not include a transistor F3 and that the second terminal of the capacitor CI is electrically connected to the wiring RWL.

[0158] In the memory cells MCL[1] to MCL[m] shown in Fig. 6, the second terminal of the transistor F1 is electrically connected to the wiring RBL[u]. The second terminal of the capacitor CI of the memory cell MCL[1] in Fig. 6 is electrically connected to the wiring RWL[1], and the second terminal of the capacitor CI of the memory cell MCL[m] in Fig. 6 is electrically connected to the wiring RWL[m].

[0159] When writing data read from the memory device MEXT to the first terminals of the capacitors CI of the memory cells MCL[1] to MCL[m], a high-level potential is preferably input to the wirings RWL[1] to RWL[m]. Furthermore, while data is being stored in the first terminals of the capacitors CI of the memory cells MCL[1] to MCL[m], a low-level potential is preferably input to the wirings RWL[1] to RWL[m]. In particular, in this case, it is preferable that a low-level potential be applied to the wirings RWL[1] to RWL[m] to turn off the transistor F1. Furthermore, when reading data written to the first terminals of the capacitors CI from any one of the memory cells MCL[1] to MCL[m], a high-level potential is preferably input to the wirings RWL[1] to RWL[m]. In particular, in this case, it is preferable that a high-level potential be input to the wirings RWL[1] to RWL[m] to turn on the transistor F1.

[0160] 3 to 6, for example, one embodiment of the present invention may have a configuration in which the wiring WBL[u] and the wiring RBL[u] are combined into a single common wiring. FIG. 7 shows a configuration in which the wiring WBL[u] and the wiring RBL[u] are combined into a single common wiring RBL[u] in the memory device MINT of FIG. 3. The wiring RBL[u] of the memory device MINT of FIG. 7 functions not only as a read data line but also as a write data line. Therefore, the memory device MINT includes, in addition to the switch RSW, switches WSW and RSW2 for switching between a write operation and a read operation.

[0161] In the memory device MINT of Figure 7, the switch WSW is provided in the electrical path between the wiring WBL[u] and the wiring RBL[u], and the switch RSW2 is provided in the electrical path between the wiring RBL[u] and the wiring DIL[u].

[0162] Furthermore, as the switch WSW and the switch RSW2, for example, a switch applicable to the switch RSW described above can be used.

[0163] When writing information read from the memory device MEXT to the first terminal of the capacitance CI of each of the memory cells MCL[1] to MCL[m] of the memory device MINT in Figure 7, the switch WSW is turned on, and the switches RSW and RSW2 are turned off. For subsequent operations of the memory cells MCL[1] to MCL[m], please refer to the description of the write operation of the memory device MINT in Figure 3. Furthermore, when reading information written to the first terminal of the capacitance CI from any one of the memory cells MCL[1] to MCL[m] of the memory device MINT in Figure 7, the switch WSW is first turned off. For subsequent operations of the memory cells MCL[1] to MCL[m], please refer to the description of the read operation of the memory device MINT in Figure 3.

[0164] <<Configuration example 4 of memory device MINT and circuit ILD>> 3 to 7 have a circuit configuration including NOSRAM (registered trademark), the memory device MINT according to the semiconductor device of one embodiment of the present invention is not limited to this. The memory device MINT may have a circuit configuration including, for example, a dynamic random access memory (DRAM).

[0165] 8 is a circuit configuration example showing a memory device MINT and a part of the circuit ILD described above. The memory device MINT has memory cells MCL[1] to MCL[m], a circuit SA, and a circuit WRD. Each of the memory cells MCL[1] to MCL[m] included in the memory device MINT has a DRAM configuration including a transistor F4 and a capacitance CI2.

[0166] The transistor F4 can be, for example, a transistor that can be applied to the transistor F2 shown in Figures 3 to 7. Therefore, for the configuration of the transistor F4, the description of the transistor F2 in this specification and the like should be referred to.

[0167] In particular, when an OS transistor is used as the transistor F4, the memory device MINT in FIG. 8 may be called a Dynamic Oxide Semiconductor Random Access Memory (DOSRAM) (registered trademark).

[0168] As an example, the memory device MINT can be configured such that memory cells MCL are arranged in a matrix. For example, the memory device MINT can be configured such that multiple columns of memory cells MCL[1] to MCL[m] are arranged in one column. Note that in the memory device MINT of FIG. 8, the memory cells MCL[1] to MCL[m] are arranged in K columns, and only the memory cells MCL[1] to MCL[m] in the u-th column are shown here.

[0169] The memory cells MCL[1] to MCL[m] in the u-th column of the memory device MINT are electrically connected to a wiring RBL[u]. The circuit SA is electrically connected to a wiring WBL[u], a wiring RBL[u], and a wiring DIL[u].

[0170] In each of the memory cells MCL[1] to MCL[m], a first terminal of the transistor F4 is electrically connected to a first terminal of the capacitor CI2, a second terminal of the capacitor CI2 is electrically connected to the wiring VEA, and a second terminal of the transistor F4 is electrically connected to the wiring RBL[u].

[0171] In the memory cell MCL[1], the gate of the transistor F4 is electrically connected to the wiring WRL[1]. In the memory cell MCL[m], the gate of the transistor F4 is electrically connected to the wiring WRL[m].

[0172] The wirings WRL[1] to WRL[m] are electrically connected to the circuit WRD.

[0173] The wirings WRL[1] to WRL[m] each function as a word line for writing and reading data to and from the memory cells MCL[1] to MCL[m]. The circuit WRD is a driver circuit that selects a memory cell to be written to or read from, and transmits a write or read selection signal to any one of the wirings WRL[1] to WRL[m].

[0174] The wiring RBL[u] functions as a data line for performing write and read operations in the memory cells MCL[1] to MCL[m].

[0175] The wiring VEA functions as a wiring that applies a constant voltage, similar to the wiring VEA shown in Figures 3 to 7. The constant voltage can be, for example, a low-level potential, a ground potential, or the like.

[0176] The circuit SA has a function of amplifying information (such as voltage and current) read from the memory device MEXT and transmitted to the wiring WBL[u], and supplying the amplified information to the wiring RBL[u]. The circuit SA also has a function of amplifying information read from any one of the memory cells MCL[1] to MCL[m] and transmitted to the wiring RBL[u], and transmitting the amplified information to the wiring DIL[u]. Therefore, the circuit SA included in the memory device MINT in FIG. 8 can have a configuration including a circuit for switching between a write operation and a read operation, an amplifier circuit (e.g., a sense amplifier), and the like. For this reason, the circuit SA may also be referred to as a read circuit. The circuit SA may also have a function of writing back data to any one of the memory cells MCL[1] to MCL[m] in which data has been corrupted during a read operation.

[0177] 8, in a configuration in which a memory circuit of DRAM (or DOSRAM (registered trademark)) is provided in the memory device MINT, the read signal (voltage) from the memory cell MCL to the wiring RBL[u] during read can be increased by increasing the capacitance value of the capacitor C1 provided in the memory cell MCL. As a means for increasing the capacitance value of the capacitor C1, for example, a trench type capacitor may be applied to the capacitor C1.

[0178] Note that one embodiment of the present invention is not limited to the circuit configuration shown in Figure 8. One embodiment of the present invention may be modified from the circuit configuration shown in Figure 8 depending on the case or situation. For example, the memory device MINT shown in Figure 8 can be combined with the configuration of the memory device MINT including the NOSRAM (registered trademark) memory circuit shown in Figures 3 to 7.

[0179] For example, one embodiment of the present invention may have a configuration in which a decoder DEC is added to the circuit configuration of FIG. 8, as in FIG. 5. As a specific example, FIG. 9 shows a configuration in which the memory device MINT is electrically connected to the decoder DEC through wirings DIL[1] to DIL[K], and the circuit ILD is electrically connected to the decoder DEC through wirings DEL[1] to DEL[L].

[0180] The memory device MINT in Fig. 9 has a configuration in which memory cells similar to the memory cells MCL[1] to MCL[m] shown in Fig. 8 are arranged in a matrix of m rows and K columns. In Fig. 9, the memory cells arranged in the matrix are referred to as memory cells MCL[1,1] to MCL[m,K]. The memory device MINT in Fig. 9 also has circuits SA[1] to SA[K] corresponding to the circuit SA shown in Fig. 8.

[0181] The memory cells MCL[1,1] to MCL[m,1] located in the first column are electrically connected to a wiring RBL[1]. The memory cells MCL[1,K] to MCL[m,K] located in the K-th column are electrically connected to a wiring RBL[K]. The memory cells MCL[1,1] to MCL[1,K] located in the first row are electrically connected to a wiring WRL[1]. The memory cells MCL[m,1] to MCL[m,K] located in the m-th row are electrically connected to a wiring WRL[m].

[0182] The circuit SA[1] is electrically connected to the wiring WBL[1], the wiring RBL[1], and the wiring DIL[1]. The circuit SA[K] is electrically connected to the wiring WBL[K], the wiring RBL[K], and the wiring DIL[K].

[0183] For the electrical connection between the decoder DEC and the circuit ILD, please refer to the explanation of FIG. 2B.

[0184] In the memory device MINT of Figure 9, by performing a data read operation in the same manner as the memory device MINT shown in Figure 8, information read from multiple memory cells MCL in any one of the first to mth rows can be input to the decoder DEC.

[0185] 9 as the semiconductor device SDV1, it is possible to read data from the memory device MINT and write the data to the multiplication cells of the arithmetic unit CLP, as in the case of FIG. 3. Furthermore, by performing this operation at regular intervals, it is possible to periodically rewrite data degraded by leakage current (absolute value of the reduced amount of charge) to the original data (absolute value of the original amount of charge) in the multiplication cells of the arithmetic unit CLP. In other words, even by applying the configuration shown in FIG. 9 as the semiconductor device SDV1, it is possible to easily perform the operation of rewriting data held in the memory elements of the multiplication cells of the arithmetic unit CLP.

[0186] <<Configuration example 5 of memory device MINT and circuit ILD>> 3 to 7 have a circuit configuration including NOSRAM (registered trademark), and the memory devices MINT shown in FIGS. 8 and 9 have a circuit configuration including DRAM (or DOSRAM (registered trademark)). However, the memory device MINT according to the semiconductor device of one embodiment of the present invention is not limited thereto. The memory device MINT may have a circuit configuration including, for example, a load circuit LC.

[0187] 10A is a circuit configuration example showing a memory device MINT and a part of the circuit ILD described above, in which the memory device MINT includes memory cells MCL[1] to MCL[m], a circuit IVC, a switch WSW, a switch RSW2, and a circuit WRD. Each of the memory cells MCL[1] to MCL[m] included in the memory device MINT includes a transistor F4 and a load circuit LC.

[0188] The transistor F4 can be, for example, a transistor that can be applied to the transistor F2 shown in Figures 3 to 7. Therefore, for the configuration of the transistor F4, the description of the transistor F2 in this specification and the like should be referred to.

[0189] For the switches WSW and RSW2, the description of the switches WSW and RSW2 shown in FIG. 7 should be taken into consideration.

[0190] For the circuit WRD, please refer to the description of the circuit WRD shown in FIG.

[0191] As an example, the load circuit LC is a circuit that can change the resistance between the first terminal and the second terminal of the load circuit LC. By changing the resistance between the first terminal and the second terminal of the load circuit LC, the amount of current flowing between the first terminal and the second terminal of the load circuit LC can be changed.

[0192] 10A, the configuration of each of the memory cells MCL[1] to MCL[m] included in the memory device MINT is the same as that of the memory cells MCL shown in FIGS. 8 and 9, except that the capacitance CI2 is replaced with a load circuit. Specifically, a first terminal of the load circuit LC is electrically connected to a first terminal of the transistor F4, and a second terminal of the load circuit LC is electrically connected to the wiring VEA.

[0193] As an example, the memory device MINT can be configured such that memory cells MCL are arranged in a matrix. For example, the memory device MINT can be configured such that multiple columns of memory cells MCL[1] to MCL[m] are arranged in one column. Note that in the memory device MINT of FIG. 10A, the memory cells MCL[1] to MCL[m] are arranged in K columns, and only the memory cells MCL[1] to MCL[m] in the u-th column are shown here.

[0194] 10A, the switch WSW is provided in the electrical path between the wiring WBL[u] and the wiring RBL[u], and the switch RSW2 is provided in the electrical path between the wiring RBL[u] and the input terminal of the circuit IVC. The output terminal of the circuit IVC is electrically connected to the wiring DIL[u].

[0195] The memory cells MCL[1] to MCL[m] in the u-th column of the memory device MINT are electrically connected to the wiring RBL[u]. The circuit IVC is electrically connected to the wiring RBL[u] through the switch RSW2. The circuit IVC is also electrically connected to the wiring DIL[u].

[0196] The wiring VEA functions as a wiring that applies a constant voltage, similar to the wiring VEA shown in Figures 3 to 7. The magnitude of the constant voltage may be determined appropriately depending on, for example, the configuration of the load circuit LC.

[0197] The circuit IVC has a function of converting a current corresponding to data read from any one of the memory cells MCL[1] to MCL[m], which flows through the wiring RBL[u], into a voltage and supplying the voltage to the wiring DIL[u]. The circuit IVC may also have a function of applying a predetermined voltage to the wiring RBL[u] in order to read data from any one of the memory cells MCL[1] to MCL[m]. As described above, the circuit IVC included in the memory device MINT in FIG. 10A functions as a read circuit.

[0198] When writing information read from the memory device MEXT to the memory cells MCL[1] to MCL[m] included in the memory device MINT of FIG. 10A, the transistor F4 and switch WSW of the memory cell MCL to be written are turned on, and the switch RSW is turned off. Then, the information read from the memory device MEXT is input to the load circuit LC of the memory cell MCL to be written via the wiring WBL[u], switch WSW, and wiring RBL[u]. When reading information written to the load circuit LC from any one of the memory cells MCL[1] to MCL[m] of the memory device MINT of FIG. 10A, first, the switch WSW is turned off, and the switch RSW2 is turned on. Next, if necessary, a desired potential is applied to the wiring RBL[u] by the circuit IVC. Then, by turning on the transistor F4 of the memory cell MCL to be read, a current corresponding to the information flows from the load circuit LC to the circuit IVC (although depending on the information stored in the load circuit LC, no current may flow). Then, the circuit IVC can output a voltage according to the amount of the current to the wiring DIL[u], and turn on or off the switch SW[u] included in the circuit WCS1 of the circuit ILD.

[0199] As the load circuit LC, for example, a resistance change element VR included in a ReRAM (Resistive Random Access Memory) or the like can be used, as shown in Fig. 10B. Alternatively, as the load circuit LC, for example, a load circuit LC including a MTJ (Magnetic Tunnel Junction) element MR included in a MRAM (Magnetoresistive Random Access Memory) or the like can be used, as shown in Fig. 10C. Alternatively, as the load circuit LC, for example, a resistance element including a phase change material used in a phase change memory (PCM) or the like (for convenience, referred to as a phase change memory PCM in this specification and the like) can be used, as shown in Fig. 10D.

[0200] As the load circuit LC, for example, as shown in Fig. 10E, a ferroelectric capacitor FEC sandwiched between a pair of electrodes, which is used in a FeRAM (Ferroelectric Random Access Memory), etc., can be used. In Fig. 10E, a first terminal of the ferroelectric capacitor FEC is electrically connected to a first terminal of the transistor F4, and a second terminal of the ferroelectric capacitor FEC is electrically connected to the wiring VEA.

[0201] In this case, the wiring VEA does not function as a wiring for supplying a constant voltage, but functions as a plate line for polarizing the ferroelectric film of the ferroelectric capacitor or for reversing the polarization of the ferroelectric film.

[0202] For example, writing information from the memory device MEXT to the ferroelectric capacitor FEC is performed by turning on the transistor F4, applying a voltage corresponding to the information to the wiring RBL, and applying a predetermined voltage to the wiring VEA, thereby polarizing the ferroelectric film included in the ferroelectric capacitor FEC. Reading the written information from the ferroelectric capacitor FEC is performed by turning on the transistor F4 and then applying a pulse voltage to the wiring VEA. The magnitude of the pulse voltage applied to the wiring VEA may be the same as the voltage applied to the wiring VEA during writing. The ferroelectric capacitor FEC determines whether the stored information is "0" or "1" depending on whether polarization reversal occurs due to the pulse voltage from the wiring VEA. When polarization reversal occurs in the ferroelectric film of the ferroelectric capacitor FEC, a current flows through the wiring RBL via the transistor F4. The amount of current flowing through the wiring RBL can be obtained using a circuit IVC configured, for example, as an integrator circuit (or a current-charge (IQ) conversion circuit) or a current-voltage conversion circuit. The amount of current determines the on or off state of the switch SW[u] included in the circuit WCS1 of the circuit ILD. As a result, the amount of current flowing through the wiring IL is determined by the on or off state of each of the switches SW[1] to SW[K] included in the circuit WCS1.

[0203] 10 has a configuration in which the memory cell MCL includes a load circuit LC, one embodiment of the present invention is not limited to this. In one embodiment of the present invention, for example, the memory cell MCL included in the memory device MINT may include a static random access memory (SRAM).

[0204] In this case, the memory device MINT has a configuration as shown in FIG. 11, for example. The memory device MINT in FIG. 11 can have a configuration in which memory cells MCL are arranged in a matrix, for example. For example, the memory device MINT can have a configuration in which memory cells MCL[1] to MCL[m] form one column, and multiple columns are arranged in the memory device MINT in FIG. 11. The memory cells MCL[1] to MCL[m] are arranged in K columns in the memory device MINT in FIG. 11, and only the memory cells MCL[1] to MCL[m] in the u-th column are shown here.

[0205] 11, each of the memory cells MCL[1] to MCL[m] includes a transistor F4, an inverter circuit INV1, and an inverter circuit INV2. The first terminal of the transistor F4 is electrically connected to the output terminal of the inverter circuit INV1 and the input terminal of the inverter circuit INV2, and the input terminal of the inverter circuit INV1 is electrically connected to the output terminal of the inverter circuit INV2. That is, in each of the memory cells MCL[1] to MCL[m], the inverter circuit INV1 and the inverter circuit INV2 form an inverter loop circuit.

[0206] The gate of the transistor F4 in the memory cell MCL[1] is electrically connected to the wiring WRL[1], the gate of the transistor F4 in the memory cell MCL[m] is electrically connected to the wiring WRL[m], and the second terminals of the transistors F4 in the memory cells MCL[1] to MCL[m] are electrically connected to the wiring RBL[u].

[0207] 11. For the circuit WRD and the wirings WRL[1] to WRL[m] included in the memory device MINT in FIG. 11, the description of the memory device MINT in FIG. 10 can be referred to.

[0208] 11 includes a switch WSW, a switch RSW, and a switch RSW2. Note that the functions and connection configurations of the switches WSW, RSW, RSW2, wiring WBL[u], wiring VDL2, wiring RBL[u], and wiring DIL[u] shown in FIG. 11 should be referred to the description of the memory device MINT in FIG. 7.

[0209] When writing information read from the memory cell MEXT to the memory cells MCL[1] to MCL[m] included in the memory device MINT of FIG. 11, the transistor F4 and switch WSW of the memory cell MCL to be written are turned on, and the switches RSW and RSW2 are turned off. Then, the information read from the memory cell MEXT is input to the inverter loop circuit of the memory cell MCL to be written via the wiring WBL[u], switch WSW, and wiring RBL[u]. When reading information written to the inverter loop circuit from any one of the memory cells MCL[1] to MCL[m] of the memory device MINT of FIG. 11, first, the switches WSW and RSW2 are turned off, the switch RSW is turned on, and the wiring RBL[u] is initialized by applying the potential of the wiring VDL2 (e.g., a high-level potential). Then, the transistor F4 of any one of the memory cells MCL[1] to MCL[m] to be read is turned on, and the switch RSW2 is turned on. As a result, read data can be input from the memory cell MCL to be read to the circuit ILD via the wiring RBL[u], the switch RSW2, and the wiring DIL. The potential of the wiring DIL is determined according to the data, which determines the on or off state of the switch SW[u] included in the circuit WCS1 of the circuit ILD. As a result, the amount of current flowing through the wiring IL is determined by the on or off state of each of the switches SW[1] to SW[K] included in the circuit WCS1.

[0210] In addition to the above, examples of storage devices that can be applied to the storage device MINT include flash memory.

[0211] 10, 11, etc., can be applied to the semiconductor device SDV1, so that data can be read from the memory device MINT and written to the multiplication cells of the arithmetic unit CLP, as in the case of FIG. 3. Furthermore, by performing this operation at regular intervals, data degraded by leakage current (absolute value of the reduced amount of charge) can be periodically rewritten to the original data (absolute value of the original amount of charge) in the multiplication cells of the arithmetic unit CLP. In other words, by applying the configurations illustrated in FIGS. 10, 11, etc. to the semiconductor device SDV1, the operation of rewriting data held in the memory elements of the multiplication cells of the arithmetic unit CLP can be easily performed.

[0212] <<Configuration example 6 of memory device MINT and circuit ILD>> Here, we will explain the electrical connection configuration of the memory device MINT, circuit ILD, and calculation unit CLP that is applicable to the semiconductor device SDV1, which is different from the electrical connection configuration of the memory device MINT, circuit ILD, and calculation unit CLP shown in Figures 3 to 10.

[0213] Fig. 12 shows a modified example of the electrical connection configuration between the memory device MINT, the circuit ILD, and the operation unit CLP in Fig. 3. The connection configuration shown in Fig. 12 differs from the connection configuration in Fig. 3 in that the memory device MINT does not have a circuit RWD. In addition, the wirings RWL[1] to RWL[m] electrically connected to the memory cells MCL[1] to MCL[m] of the memory device MINT, respectively, are electrically connected to the wirings WL[1] to WL[m] of the operation unit CLP, respectively.

[0214] Specifically, the wirings WL[1] to WL[m] function as write data lines for writing information to the multiplication cells (referred to as circuits MP[1] to MP[m] in FIG. 12) in the calculation unit CLP. The wirings WL[1] to WL[m] will be described in Embodiment 2. Each of the wirings WL[1] to WL[m] is electrically connected to a circuit WLD. The circuit WLD functions as a driver circuit for transmitting a selection signal for selecting a multiplication cell (circuit MP) in the calculation unit CLP to write information.

[0215] 12, the wirings RWL[1] to RWL[m] that function as read word lines of the memory device MINT and the wirings WL[1] to WL[m] that function as write data lines of the operation unit CLP are shared by each other. By transmitting a selection signal to any one of the wirings RWL[1] (wiring WL[1]) to RWL[m] (wiring WL[m]) by the circuit WLD of the operation unit CLP, information can be read from a predetermined memory cell MCL in the memory device MINT.

[0216] In addition, since the read word line (wire RWL) of the memory device MINT and the write data line (wire WL) of the calculation unit CLP are combined into a single wire, when information is read from a predetermined memory cell MCL in the memory device MINT, a selection signal is also input to the multiplication cell (circuit MP) of the calculation unit CLP located in the same row as the memory cell MCL. In other words, when information is read from a predetermined memory cell MCL in the memory device MINT, the write transistor included in the multiplication cell (circuit MP) is also turned on.

[0217] For example, when data is read from K memory cells MCL[1] located in the first row of the memory device MINT, a selection signal is sent from the circuit WLD to the wiring RWL[1] (wiring WL[1]). At this time, potentials corresponding to the data stored in each of the K memory cells MCL[1] located in the first row are read, and the respective potentials are input to the circuit WCS1 of the circuit ILD. In the circuit WCS1, the on / off states of the switches SW[1] to SW[K] are determined according to the respective potentials. That is, the amount of current flowing from the circuit WCS1 to the wiring IL is determined by the combination of the on / off states of the switches SW[1] to SW[K]. Furthermore, in the calculation unit CLP, since a selection signal is sent to the wiring WL[1] (wiring RWL[1]), the write transistor included in the multiplication cell (circuit MP) located in the first row is turned on. Therefore, the current of the corresponding amount output from the circuit ILD flows to the multiplication cell (circuit MP) located in the first row via the wiring IL. This allows the information held in the memory cell MCL of the memory device MINT to be written to the multiplication cell (circuit MP) of the arithmetic unit CLP.

[0218] Furthermore, by applying the configuration of FIG. 12 to the semiconductor device SDV1, the memory device MINT can be configured not to include the circuit RWD, which is a drive circuit during reading, and therefore the area of ​​the memory device MINT can be reduced.

[0219] Furthermore, the connection configuration between the memory device MINT, the circuit ILD, and the calculation unit CLP according to one embodiment of the present invention is not limited to the circuit configuration shown in Fig. 12. The connection configuration between the memory device MINT, the circuit ILD, and the calculation unit CLP may be changed depending on the case or situation, in terms of the included circuit elements, the connection configuration, and the like.

[0220] For example, the connection configuration between the memory device MINT, the circuit ILD, and the arithmetic unit CLP may be such that the circuit BF described with reference to FIG. 4 is provided between the memory device MINT and the circuit ILD in FIG. 12, as shown in FIG.

[0221] In the connection configuration of the memory device MINT, the circuit ILD, and the arithmetic unit CLP in FIG. 13, a circuit BF is provided between the electrical paths of the wiring RBL[u] and the wiring DIL[u]. Further, as the circuit BF, for example, similar to the description of FIG. 4, it can be configured to include an amplification circuit such as a buffer circuit, an inverter circuit, a latch circuit, etc.

[0222] In particular, by configuring the circuit BF to have a latch circuit that temporarily holds the potential of the wiring RBL[u], it may be possible to increase the speed of writing information to the multiplication cell (circuit MP) of the arithmetic unit CLP. In this case, for example, as in the connection configuration of the memory device MINT, the circuit ILD, and the arithmetic unit CLP in FIG. 14A, a wiring WL[0] is provided in the arithmetic unit CLP, and the wiring WL[0] and the wiring RWL[1] are electrically connected, and the wiring WL[1] and the wiring RWL[2] are electrically connected. That is, the wiring RWL[i] (where i is 1 or more and m or less here) of the memory device MINT and the wiring WL[i - 1] of the arithmetic unit CLP may be electrically connected. Note that a multiplication cell (circuit MP) does not have to be provided on the wiring WL[0] in the arithmetic unit CLP.

[0223] Further, as an example, the circuit BF can be configured as shown in FIG. 14B. The circuit BF includes a latch circuit LAT1, a latch circuit LAT2, and an inverter circuit INV. The input terminal of the latch circuit LAT1 is electrically connected to the wiring RBL[u], the output terminal of the latch circuit LAT1 is electrically connected to the input terminal of the latch circuit LAT2, and the output terminal of the latch circuit LAT2 is electrically connected to the wiring DIL[u]. Also, the enable signal input terminal (which may be called a clock signal input terminal in some cases) of the latch circuit LAT1 is electrically connected to the wiring CLK, the input terminal of the inverter circuit INV is electrically connected to the wiring CLK, and the output terminal of the inverter circuit INV is electrically connected to the enable signal input terminal of the latch circuit LAT2.

[0224] An example of operation in the connection configuration of the memory device MINT, the circuit ILD, and the arithmetic unit CLP in FIG. 14A will be described. First, a selection signal is sent from the circuit WLD to the wiring WL[0] to read information stored in the memory cell MCL[1] located in the first row of the memory device MINT. The read information is input as a potential to the input terminal of the circuit BF via the wiring RBL[u]. At this time, in the circuit BF, a first potential (e.g., one of a high-level potential or a low-level potential) is input to the wiring CLK, causing the latch circuit LAT1 to hold the potential input from the wiring RBL[u] and output it to the output terminal of the latch circuit LAT1. Furthermore, a second potential (e.g., the other of a high-level potential or a low-level potential) is input to the wiring CLK, causing the latch circuit LAT2 to hold the potential from the output terminal of the latch circuit LAT1 and output it to the output terminal of the latch circuit LAT2. Furthermore, when a second potential (e.g., the other of a high-level potential or a low-level potential) is input to the wiring CLK, a selection signal is sent from the circuit WLD to the wiring WL[1] to read out information stored in the memory cell MCL[1] located in the first row of the memory device MINT. As a result, the read-out information is input as a potential to the input terminal of the circuit BF via the wiring RBL[u]. Meanwhile, in the calculation unit CLP, since the selection signal is sent to the wiring WL[1], the write transistor of the multiplication cell (circuit MP) in the first row is turned on. At this time, the output terminal of the latch circuit LAT2 of the circuit BF outputs a potential corresponding to the information read out from the memory cell MCL[1] of the memory device MINT, and the circuit ILD passes a current corresponding to the potential to the wiring IL. Then, the current flows from the wiring IL to the multiplication cell (circuit MP), and the information is written to the multiplication cell (circuit MP).

[0225] In the semiconductor device SDV1, by applying the connection configuration of the memory device MINT, the circuit ILD, and the arithmetic unit CLP of Figure 14A, the speed at which information held in the memory device MINT is written to the multiplication cell of the arithmetic unit CLP can be increased in the operation of rewriting data held in the memory element of the multiplication cell of the arithmetic unit CLP.

[0226] In the above example of operation, the circuit BF has been described as having a configuration in which the latch circuits LAT1 and LAT2 are connected in series, but the circuit BF may also have a configuration in which two latch circuits are connected in parallel instead of in series (not shown). For example, one latch circuit may be configured to acquire information (voltage) sent from the memory device MINT, and the other latch circuit may be configured to transmit information (voltage) acquired in advance to the circuit ILD.

[0227] The configuration of the semiconductor device SDV1 may be selected from the configurations of FIGS. 3 to 9, 10A, 11 to 13, 14A, etc., and may be a combination of these configurations.

[0228] <Configuration Example 2 of Semiconductor Device> Next, a semiconductor device that is different from the semiconductor device SDV1 in FIG. 1 and that is capable of supplementing data held in an arithmetic circuit will be described.

[0229] 15 is a block diagram showing a configuration example of a semiconductor device SDV2 according to one embodiment of the present invention. The semiconductor device SDV2 includes, for example, a circuit ILD, a calculation unit CLP, and a circuit LMNT. Also, in order to show the configuration of electrical connections with the semiconductor device SDV2, a memory device MEXT is also shown in FIG.

[0230] The semiconductor device SDV2 can be fabricated by forming circuit elements and the like on a single substrate BSE, for example, in the same way as the semiconductor device SDV1.

[0231] For example, by using a semiconductor substrate containing silicon as the substrate BSE, the transistors included in the calculation unit CLP, the transistors included in the circuit ILD, and the transistors included in the circuit LMNT can each be formed as Si transistors on the substrate BSE.

[0232] For example, the circuit ILD provided in the semiconductor device SDV2 acquires information read by a memory device MEXT provided outside the semiconductor device SDV2, and supplies a current, voltage, etc. according to the information to a calculation unit CLP (described later). The information is treated as data for calculation by the calculation unit CLP.

[0233] The semiconductor device SDV2 does not have a memory device MINT, and therefore, unlike the semiconductor device SDV1, the semiconductor device SDV2 is configured to directly input information read by the memory device MEXT to the circuit ILD. Therefore, when the circuit ILD functions as a current source circuit, the circuit ILD directly supplies a current corresponding to the information read from the memory device MEXT to the circuit included in the calculation unit CLP. Note that the circuit ILD may not be provided as a current source circuit for supplying a current to the calculation unit CLP, but may be provided as, for example, a voltage source circuit (voltage generation circuit) for inputting a voltage corresponding to the information read from the memory device MEXT to the calculation unit CLP.

[0234] When the circuit ILD functions as a current source circuit, the specific configuration of the circuit ILD is to be referred to the description of the circuit ILD in FIGS. 2A to 2C.

[0235] The arithmetic unit CLP has a plurality of circuits that function as multiplication cells. Regarding the arithmetic unit CLP, please refer to the description of the arithmetic unit CLP included in the semiconductor device SDV1 in FIG. 1A. The circuit configuration of the arithmetic unit CLP and the principle of the product-sum operation in the arithmetic unit CLP will be described in detail in the second embodiment.

[0236] The circuit LMNT has a function of monitoring information (e.g., current, voltage, etc.) stored in the multiplication cell included in the calculation unit CLP (or the memory element included in the circuit LMNT). Specifically, for example, when the information (e.g., current, voltage, etc.) stored in the multiplication cell fluctuates due to charge leakage or the like, the circuit LMNT transmits a command signal to the memory element MEXT, etc. Upon receiving the command signal, the memory element MEXT reads the information from the memory element MEXT, transmits the information to the circuit ILD, and rewrites the information from the circuit ILD to the multiplication cell (replenishes charge in the memory element). At this time, the memory element included in the circuit LMNT is also similarly rewritten to the original information. This makes it possible to prevent deterioration of the data stored in the multiplication cell of the calculation unit CLP.

[0237] <<Configuration example 1 of circuit LMNT and circuit ILD>> Next, a configuration example of the circuit LMNT included in the semiconductor device SDV2 of FIG. 15 will be described.

[0238] The circuit LMNT shown in FIG. 16 includes a circuit LMC[i] (where i is an integer greater than or equal to 1 and less than or equal to the number of wirings IL). The circuit LMC[i] also includes a memory cell DC and a switch DSW1. The memory cell DC also includes a transistor M1d, a transistor M2d, and a capacitance C1d. In addition to the circuit LMNT, FIG. 16 also illustrates a semiconductor device SDV2 including a circuit ILD and an arithmetic unit CLP, as well as a memory device MEXT and a circuit EXMNT.

[0239] In the circuit LMNT, a plurality of circuits LMC[i] may be provided. Specifically, the circuit LMNT may be configured such that the same number of circuits LMC[i] as the number of wirings IL electrically connected to the circuit ILD are arranged in one row. For example, if the number of wirings IL is 2m, the circuit LMNT may be configured such that circuits LMC[1] to LMC[2m] are arranged in one row.

[0240] As the switch DSW1, for example, a switch applicable to the above-mentioned switch RSW can be used.

[0241] The memory device MEXT is electrically connected to the circuit ILD. The circuit ILD is electrically connected to the wiring IL. The circuit EXMNT is electrically connected to the memory device MEXT.

[0242] The line IL is electrically connected to a first terminal of the switch DSW1, and a second terminal of the switch DSW1 is electrically connected to the line DLd, which is electrically connected to the circuit EXMNT and the memory cell DC.

[0243] In the memory cell DC, a first terminal of the transistor M1d is electrically connected to a wiring VEd, a second terminal of the transistor M1d is electrically connected to a wiring DLd, and a gate of the transistor M1d is electrically connected to a first terminal of a capacitor C1d and a first terminal of a transistor M2d. A second terminal of the transistor M2d is electrically connected to a wiring DLd, and a gate of the transistor M2d is electrically connected to a wiring WLd. The second terminal of the capacitor C1d is electrically connected to a wiring VEd. In FIG. 16, the electrical connection point between the gate of the transistor M1d, the first terminal of the capacitor C1d, and the first terminal of the transistor M2d is referred to as a node n1d.

[0244] For example, the line DLd functions as a line for transmitting data to be written to the first terminal of the capacitance C1d of the memory cell DC. Also, for example, the line DLd functions as a line for passing a current according to the potential of the first terminal of the capacitance C1d of the memory cell DC.

[0245] For example, the wiring WLd functions as a write word line in the memory cell DC.

[0246] For example, the wiring VEd functions as a wiring that applies a constant voltage, which may be, for example, a low-level potential or a ground potential.

[0247] The transistor M1d preferably has a structure similar to that of the transistor M1 described in embodiment 2, which is included in the multiplication cell (circuit MC) of the calculation unit CLP. The transistor M2d preferably has a structure similar to that of the transistor M2 described in embodiment 2, which is included in the multiplication cell (circuit MC) of the calculation unit CLP. For example, if the transistor M1 is a Si transistor and the transistor M2 is an OS transistor, the transistor M1d is preferably a Si transistor, and the transistor M2d is preferably an OS transistor. The capacitor C1d preferably has a structure similar to that of the capacitor C1 described in embodiment 2, which is included in the multiplication cell (circuit MC) of the calculation unit CLP.

[0248] The transistor M1d may be a transistor that can be used as the transistor F1, and the transistor M2d may be a transistor that can be used as the transistor F2.

[0249] The circuit EXMNT is provided, for example, outside the semiconductor device SDV2. The circuit EXMNT has a function of monitoring the potential (or charge amount) held at the first terminal of the capacitor C1d of the memory cell DC included in the circuit LMC[i]. Specifically, for example, the circuit EXMNT acquires the amount of current input from the wiring DLd and compares the amount of current with a desired amount of current. When the amount of current becomes equal to or less than the desired amount of current, the circuit EXMNT determines that the voltage held in the memory cell DC and the multiplication cell included in the calculation unit CLP has decreased (or the absolute value of the charge amount has decreased), and transmits a command signal to the external memory device MEXT, circuit ILD, etc. to rewrite the same data as the data originally held in the memory cell DC and the multiplication cell included in the calculation unit CLP.

[0250] Next, an example of the operation of the circuit LMNT in FIG. 16 will be described.

[0251] First, in the circuit LMC[i], the switch DSW1 is turned on and the transistor M2d is turned on. With the transistor M2d turned on, conduction occurs between the node n1d and the second terminal of the transistor M1d, and the potentials of the node n1d and the second terminal of the transistor M1d become approximately equal.

[0252] At this time, for example, when the circuit ILD is a current source circuit, an initialization current having a current amount I0 is passed from the circuit ILD to the wiring DLd via the wiring IL. The initialization current can be, for example, a current output from the circuit WCS1 or the circuit WCS2 included in the circuit ILD shown in FIGS. 2A to 2C. In this case, for example, the initialization current amount I0 is set to I, which is the minimum value of the current amount that the circuit WCS1 or the circuit WCS2 can generate. ut or the maximum value (2 K -1)×I ut It may also be possible to use the following.

[0253] Since the transistor M2d is turned on, the first terminal of the capacitor C1d is charged with the electric charge flowing from the wiring DLd. Finally, a current of the amount I0 flows between the first terminal and the second terminal of the transistor M1d (between the wiring DLd and the wiring VEd), and the potential of the node n1d reaches a level corresponding to the amount of current I0. At this time, the potential of the node n1d is set to V nd Let's say.

[0254] Also, for example, when the circuit ILD is a voltage source circuit, a voltage is written from the circuit ILD to the first terminal of the capacitor C1d via the wiring IL and the transistor M2d. In this case, the voltage written from the circuit ILD to the first terminal of the capacitor C1d is V nd At this time, a current of a current amount I0 flows between the first terminal and the second terminal of the transistor M1d (between the wiring DLd and the wiring VEd). Here, it is assumed that the wiring VED is at a low level potential or a ground potential, and a positive current flows from the wiring DLd to the wiring VEd.

[0255] Whether the circuit ILD is a current source circuit or a voltage source circuit, the potential of the first terminal of the capacitance C1d is V nd When this occurs, the transistor M2d is turned off, and the first terminal of the capacitor C1d of the memory cell DC is supplied with a potential V nd At this time, the first terminal of the capacitor C1d of the memory cell DC has a potential V nd By holding this, the transistor M1d functions as a current source that supplies a current of I0. After the transistor M2d is turned off, the switch DSW1 may be turned off.

[0256] When starting to monitor the current flowing between the first terminal and the second terminal of the transistor M1d, the switch DSW1 is turned off. This causes a current of a magnitude I0 to flow from the memory cell DC to the circuit EXMNT via the wiring DLd. Specifically, a positive current flows from the circuit EXMNT to the memory cell DC via the wiring DLd.

[0257] Here, the potential V held at the first terminal of the capacitor C1d is nd decreases due to charge leakage or the like, the amount of current flowing between the first terminal and the second terminal of the transistor M1d decreases from I0. When the amount of current flowing from the memory cell DC through the wiring DLd to the circuit EXMNT becomes equal to or less than a desired amount of current, the circuit EXMNT determines that the data held in the memory cell DC has deteriorated, and transmits a command signal (e.g., a pulse signal) to the memory device MEXT to read data to be rewritten in the multiplication cell of the calculation unit CLP and transmit the data to the circuit ILD.

[0258] The desired current amount here is a current amount smaller than the current amount I0 flowing from the circuit ILD to the wiring DLd via the wiring IL. The current amount smaller than the current amount I0 here can be, for example, 0.95, 0.90, or 0.80 times the current amount I0.

[0259] When the command signal is input to the memory device MEXT, the memory device MEXT reads out the information stored in the memory device MEXT and transmits it to the semiconductor device SDV2. Then, the semiconductor device SDV2 writes the information to the multiplication cells included in the calculation unit CLP using the circuit ILD, and also writes the original voltage (or current) to the memory cells DC. This allows data to be rewritten (charge replenished) to the degraded data stored in the multiplication cells of the calculation unit CLP and the memory cells DC.

[0260] 16 is applied to the semiconductor device SDV2, it is possible to easily detect the deterioration of data held in the memory element of the multiplication cell of the operation unit CLP (decrease in the absolute value of the charge amount due to leakage current).In addition, by detecting this, it is possible to rewrite data (replenish charge) to the multiplication cell of the operation unit CLP and the memory cell DC.

[0261] <<Configuration example 2 of circuit LMNT and circuit ILD>> Next, a configuration example of the circuit LMNT that is different from the configuration of the circuit LMNT in FIG. 16 and that can be applied to the semiconductor device SDV2 in FIG. 15 will be described.

[0262] The circuit LMNT shown in FIG. 17A includes a circuit LMC[i] (where i is an integer greater than or equal to 1 and less than or equal to the number of wirings IL). The circuit LMC[i] also includes a memory cell DC, a circuit DTC, a switch DSW1, and a switch DSW2. The memory cell DC also includes a transistor M1d, a transistor M2d, and a capacitance C1d. In addition to the circuit LMNT, FIG. 17A also illustrates a semiconductor device SDV2 including a circuit ILD and an arithmetic unit CLP, and a memory device MEXT.

[0263] Also, the memory cell DC shown in Fig. 17A has the same configuration as the memory cell DC shown in Fig. 16. Therefore, for the transistor M1d, the transistor M2d, and the capacitance C1d included in the memory cell DC in Fig. 17A, and the wiring VEd, the wiring WLd, and the wiring DLd shown in Fig. 17A, please refer to the description of the circuit LMNT in Fig. 16.

[0264] The circuit LMNT in Fig. 17A can have a plurality of circuits LMC[i], similar to the circuit LMNT in Fig. 16. Specifically, for example, the circuit LMNT can be configured such that the same number of circuits LMC[i] as the number of wirings IL electrically connected to the circuit ILD are arranged in one row.

[0265] As the switches DSW1 and DSW2, similar to the switch DSW1 in FIG. 16, for example, switches applicable to the above-mentioned switch RSW can be used.

[0266] The memory device MEXT is electrically connected to the circuit ILD, which is electrically connected to the wiring IL.

[0267] The wiring IL is electrically connected to a first terminal of a switch DSW1, and a second terminal of the switch DSW1 is electrically connected to a wiring DLd. The wiring DLd is also electrically connected to a first terminal of a switch DSW2, and a second terminal of the switch DSW2 is electrically connected to a first input terminal of a circuit DTC, and a second input terminal of the circuit DTC is electrically connected to a wiring IRFE, and an output terminal of the circuit DTC is electrically connected to a memory device MEXT. The wiring IRFE is also electrically connected to a circuit ILD, for example.

[0268] The circuit DTC monitors the current input to its first input terminal. Specifically, the circuit DTC compares the amount of current input to its first input terminal with the amount of current input to its second input terminal (hereinafter referred to as the "reference current"). When the current input to the first input terminal of the circuit DTC falls below the reference current, the circuit DTC outputs a command signal (e.g., a pulse voltage) to the memory device MEXT from its output terminal. In other words, the circuit DTC may include a current comparator. When the circuit DTC includes a current comparator, the circuit DTC may have the configuration of the circuit ACTF[j] described in the second embodiment. Therefore, the circuit DTC can be used in common with the circuit ACTF[j] described in the second embodiment.

[0269] 17A, a positive current flows from the first terminal of the circuit DTC to the memory cell DC via the switch DSW2 and the line DLd. Therefore, it is preferable that the current input to the second terminal of the circuit DTC is a positive current that flows from the second terminal of the circuit DTC to the line IRFE.

[0270] Therefore, the wiring IRFE functions as a wiring that provides a constant current as a reference current, for example. Furthermore, as will be described in detail later, the amount of current I0 flowing between the first terminal and the second terminal of the transistor M1d is input to the first input terminal of the circuit DTC. The constant current used as the reference current may be, for example, a current amount smaller than the current amount I0. Specifically, the current amount smaller than the current amount I0 may be, for example, 0.95, 0.90, or 0.80 times the current amount I0.

[0271] The reference current may also be generated by the circuit ILD. For example, in FIG. 17A, the circuit ILD is electrically connected to the wiring IRFE, so that the circuit ILD can supply the reference current generated by the circuit ILD to the wiring IRFE.

[0272] Furthermore, the memory device MEXT receives a command signal from the circuit DTC to read data to be rewritten (data originally written in the multiplication cell) from the memory device MEXT. The read data is input to the calculation unit CLP via the circuit ILD.

[0273] An example of the configuration of the circuit ILD in this case is shown in Fig. 17B. The circuit ILD shown in Fig. 17B includes, as an example, a circuit WCS1 and a circuit WCSA.

[0274] The circuit WCS1 in Figure 17B is a part of the circuit WCS1 in Figure 2A, and shows only the circuit elements related to writing to the memory cell DC. Specifically, the circuit WCS1 in Figure 17B shows only the current source CC[u] and the switch SW[u]. At this time, the switches SW[1] to SW[K] other than the switch SW[u] are assumed to be in the off state, and the currents generated by the current sources CC[1] to CC[K] other than the current source CC[u] do not flow through the wiring IL.

[0275] 17B includes a current source CCA, a transistor F6A, and a transistor F6B. An input terminal of the current source CCA is electrically connected to a wiring VDL, an output terminal of the current source CCA is electrically connected to a first terminal of the transistor F6B, a gate of the transistor F6B, and a gate of the transistor F6A, and a second terminal of the transistor F6B is electrically connected to a wiring VSE. A first terminal of the transistor F6A is electrically connected to a wiring IRFE, and a second terminal of the transistor F6A is electrically connected to the wiring VSE.

[0276] The wiring VSE functions as a wiring that applies a constant voltage, for example, a low-level potential or a ground potential.

[0277] The transistors F6A and F6B are preferably Si transistors, for example. In addition to Si transistors, OS transistors, transistors including Ge or the like in a channel formation region, transistors including a compound semiconductor in a channel formation region, transistors including carbon nanotubes in a channel formation region, transistors including an organic semiconductor in a channel formation region, and the like can be used.

[0278] It is also assumed that the amounts of current generated by the current source CC[u] and the current source CCA are equal to each other.

[0279] The transistors F6A and F6B of the circuit WCSA are configured as a current mirror circuit. Therefore, if the sizes (e.g., channel length, channel width, structure, etc.) of the transistors F6A and F6B are equal, ideally, the amount of current flowing between the first and second terminals of the transistor F6B will be equal to the amount of current flowing between the first and second terminals of the transistor F6A. In other words, the amount of current generated by the current source CCA will be equal to the amount of current flowing between the first and second terminals of the transistor F6A.

[0280] In addition, since the circuit LMNT in Figure 17A is configured so that a positive current flows from the second terminal of the circuit DTC to the wiring IRFE, the circuit WCSA of the circuit ILD shown in Figure 17B is configured so that a positive current flows from the wiring IRFE to the first terminal of the transistor F6A.

[0281] Here, by making the ratio W / L of the W length to the L length of transistor F6A smaller than the ratio W / L of the W length to the L length of transistor F6B, the amount of current flowing between the first terminal and the second terminal of transistor F6A can be made smaller than the amount of current flowing between the first terminal and the second terminal of transistor F6B (i.e., the amount of current generated by current source CCA).

[0282] 17B, ​​the amount of current flowing through the wiring IRFE can be made smaller than the amount of current flowing through the wiring IL, as described above. Note that the ratio W / L of the width to the length of the transistor F6A and the ratio W / L of the width to the length of the transistor F6B may be made the same, and the amount of current generated by the current source CC[u] may be increased to create a difference between the amount of current I0 and the reference current.

[0283] Next, an example of the operation of the circuit LMNT in FIG. 17A will be described.

[0284] First, in the circuit LMC[i], the switch DSW1 is turned on, the switch DSW2 is turned off, and the transistor M2d is turned on. Next, similar to the circuit LMNT in FIG. 16, a voltage V nd is written, the transistor M2d is turned off, and the voltage of the node n1d is maintained.

[0285] At this time, an initialization current with a current amount I0 flows between the first terminal and the second terminal of the transistor M1d (between the wiring DLd and the wiring VEd). After that, the switch DSW1 is turned off to stop the current flowing between the first terminal and the second terminal of the transistor M1d.

[0286] When starting to monitor the current flowing between the first and second terminals of transistor M1d, switch DSW1 is turned off and switch DSW2 is turned on, causing a current of magnitude I0 to flow between the first and second terminals of transistor M1d from the first input terminal of circuit DTC to line VEd via switch DSW2 and line DLd.

[0287] Here, the potential V held at the first terminal of the capacitor C1d is ndWhen the amount of current flowing from the first input terminal of the circuit DTC to the wiring VEd decreases due to charge leakage or the like, the amount of current flowing between the first terminal and the second terminal of the transistor M1d decreases from I0. When the amount of current flowing from the first input terminal of the circuit DTC to the wiring VEd becomes equal to or less than the amount of the reference current flowing from the wiring IRFE, or when it becomes less than the amount of the reference current, the circuit DTC determines that the data held in the memory cell DC has deteriorated, and transmits a command signal from the output terminal of the circuit DTC to the memory device MEXT to read data to be rewritten from the memory device MEXT (data originally written in the multiplication cell). As a result, the data read from the memory device MEXT is input to the calculation unit CLP via the circuit ILD, and the deteriorated data is overwritten with that data. At this time, the potential held in the memory cell DC is also restored to the data before deterioration (potential V nd ) is preferable.

[0288] 17A is applied to the semiconductor device SDV2, it is possible to easily detect the deterioration of data held in the memory element of the multiplication cell of the operation unit CLP (decrease in the absolute value of the charge amount due to leakage current). Furthermore, by detecting this, it is possible to rewrite data (replenish charge) to the multiplication cell of the operation unit CLP and the memory cell DC.

[0289] <<Configuration example 3 of circuit LMNT and circuit ILD>> Here, a configuration example of the circuit LMNT that is different from the circuit LMNT in FIGS. 16 and 17A and that can be applied to the semiconductor device SDV2 will be described.

[0290] 16, the circuit LMNT shown in FIG. 18A includes a circuit LMC[i] (where i is an integer greater than or equal to 1 and less than or equal to the number of wirings IL). However, the circuit LMC[i] in FIG. 18A differs from the circuit LMC[i] in FIG. 16 in that it includes a memory cell DC, a circuit CMPD, and a switch DSW1. Note that FIG. 18A also illustrates a circuit ILD.

[0291] Also, the memory cell DC shown in Fig. 18A has the same configuration as the memory cell DC shown in Fig. 16. Therefore, for the transistor M1d, the transistor M2d, and the capacitance C1d included in the memory cell DC in Fig. 18A, and the wiring VEd, the wiring WLd, and the wiring DLd shown in Fig. 18A, please refer to the description of the circuit LMNT in Fig. 16.

[0292] The circuit LMNT in Fig. 18A can have a plurality of circuits LMC[i], similar to the circuit LMNT in Fig. 16. Specifically, for example, the circuit LMNT can be configured such that the same number of circuits LMC[i] as the number of wirings IL electrically connected to the circuit ILD are arranged in one row.

[0293] As the switch DSW1, similar to the switch DSW1 in FIG. 16, for example, a switch applicable to the above-mentioned switch RSW can be used.

[0294] The wiring IL is electrically connected to a first terminal of a switch DSW1, and a second terminal of the switch DSW1 is electrically connected to a wiring DLd. Also, a first input terminal of the circuit CMPD is electrically connected to the gate of the transistor M1d, the second terminal of the transistor M2d, and the first terminal of the capacitor C1. A second input terminal of the circuit CMPD is electrically connected to a wiring VRFE. An output terminal of the circuit CMPD is electrically connected to a wiring RSUL. Also, the wiring VRFE is electrically connected to the circuit ILD. Although not shown, the wiring RSUL is electrically connected to the memory device MEXT.

[0295] The wiring VRFE functions as a wiring that applies a constant voltage, for example. The constant voltage is a voltage V written to the node n1d by a circuit ILD (current source circuit or voltage source circuit). nd Specifically, the voltage V nd For example, a voltage lower than V nd It can be set to 0.95 times, 0.90 times, 0.80 times, etc. Hereinafter, the constant voltage given by the wiring VRFE is referred to as the reference potential.

[0296] The reference potential may be generated by the circuit ILD. For example, in FIG. 18A, the circuit ILD is electrically connected to the wiring IRFE, and therefore the circuit ILD can supply the reference current generated by the circuit ILD to the wiring IRFE.

[0297] An example of the configuration of the circuit ILD in this case is shown in Fig. 19. The circuit ILD shown in Fig. 19 includes, as an example, a circuit WCS1 and a circuit WCSA.

[0298] The circuit WCS1 shown in Fig. 19 is a part of the circuit WCS1 in Fig. 2A, and shows only circuit elements related to writing to the memory cell DC. Specifically, the circuit WCS1 in Fig. 19 shows only the current source CC[u] and the switch SW[u]. At this time, the switches SW[1] to SW[K] other than the switch SW[u] are set to the off state, and the current generated by the current sources CC[1] to CC[K] other than the current source CC[u] does not flow through the wiring IL.

[0299] 19 also includes a current source CCB and a transistor F7. An input terminal of the current source CCB is electrically connected to a first terminal of the transistor F7, a gate of the transistor F7, and a wiring VRFE, and a second terminal of the transistor F7 is electrically connected to a wiring VSE.

[0300] The transistor F7 may be, for example, the transistor F6A or F6B shown in FIG. 17B, or a transistor applicable to the transistor M1d shown in FIG. 17A.

[0301] It is also assumed that the amounts of current generated by the current source CC[u] and the current source CCB are equal to each other.

[0302] The transistor F7 of the circuit WCSB is configured as a diode. Furthermore, when focusing on the memory cell DC in FIG. 18A, the connection between the transistor F7 and the current source CCB is roughly the same as the connection between the transistor M1d and the current source CC[u] when the transistor M2d is in the on state. In this case, if the transistors F7 and M1d have the same size (e.g., channel length, channel width, structure, etc.), ideally, the potential at the first terminal (gate) of the transistor F7 and the potential at the node n1d will be equal.

[0303] Here, by making the ratio W / L of the width to the length of the transistor F7 larger than the ratio W / L of the width to the length of the transistor M1d, the potential of the first terminal (gate) of the transistor F7 is set to the potential V nd By making the ratio W / L of the width to the length of the transistor F7A and the ratio W / L of the width to the length of the transistor M1d the same and increasing the amount of current generated by the current source CC[u], the voltage V held at the node n1d can be reduced. nd A difference may be made between the potential and the reference potential.

[0304] By configuring the circuit ILD as shown in FIG. 19, as described above, the potential given to the wiring VRFE is nd can be made smaller than

[0305] The circuit CMPD has a function of comparing a voltage input to a first input terminal of the circuit CMPD with a voltage input to a second input terminal of the circuit CMPD and outputting the comparison result to an output terminal of the circuit CMPD. Therefore, the circuit CMPD can be configured to include, for example, a voltage comparator.

[0306] Next, an example of the operation of the circuit LMNT in FIG. 18A will be described.

[0307] First, in the circuit LMC[i], the switch DSW1 is turned on and the transistor M2d is turned on. Next, similarly to the circuit LMNT of FIG. 16, a voltage V nd is written, the transistor M2d is turned off, and the voltage of the node n1d is maintained.

[0308] At this time, the first input terminal of the circuit CMPD receives the voltage V nd Also, the second input terminal of the circuit CMPD is V nd A reference potential lower than the reference potential is input.

[0309] Next, for example, as time passes, the voltage V nd When the potential of node n1d becomes lower than the reference potential due to leakage or the like, the signal (voltage) output from the output terminal of circuit CMPD changes. For example, if circuit CMPD outputs a low-level potential from its output terminal when the potential of node n1d is higher than the reference potential and outputs a high-level potential from its output terminal when the potential of node n1d is lower than the reference potential, when the voltage of node n1d becomes lower than the reference potential, the potential output from the output terminal of circuit CMPD changes from a low-level potential to a high-level potential. In other words, circuit CMPD determines that the data held in memory cell DC has deteriorated and changes the signal (voltage) output from the output terminal of circuit CMPD. Therefore, this signal (voltage) can be used as a trigger signal for a rewrite operation for the data held in the multiplication cell of calculation unit CLP and the potential held in memory cell DC.

[0310] When a change in the signal (voltage) from the circuit CMPD is input to the memory device MEXT, the memory device MEXT reads out the data held in the memory device MEXT (the data originally written in the multiplication cell) and transmits it to the semiconductor device SDV2. As a result, the data read out from the memory device MEXT is input to the calculation unit CLP via the circuit ILD, and the degraded data is overwritten with the data. At this time, the potential held in the memory cell DC is also restored to the data before degradation (potential V nd ) is preferable.

[0311] 18A illustrates the configuration of the circuit LMNT that monitors the potential of the node n1d of the memory cell DC and detects the potential when the potential becomes lower than the reference potential, but the circuit included in the semiconductor device of one embodiment of the present invention is not limited to this. For example, the circuit included in the semiconductor device of one embodiment of the present invention may be one in which the configuration of the circuit LMNT in FIG. 18A is modified depending on the case or situation.

[0312] For example, since the circuit LMNT in Fig. 18A monitors the potential of the node n1d, the memory cell DC may not have the transistor M1d. Specifically, the circuit LMNT may be configured such that the memory cell DC does not have the transistor M1d, as shown in Fig. 18B.

[0313] 18C, a circuit BF2 functioning as a buffer circuit may be provided instead of the circuit CMPD. Specifically, the circuit LMNT in FIG. 18C is configured such that the input terminal of the circuit BF2 is electrically connected to a first terminal of a capacitor C1d, a gate of a transistor M1d, and a first terminal of a transistor M2d, and the output terminal of the circuit BF2 is electrically connected to a wiring RSUL. The circuit BF2 may be configured to include, for example, a source follower circuit or a voltage follower circuit using an operational amplifier.

[0314] 18D, the circuit LMNT may have a configuration including a circuit CMPD and a circuit BF2. Specifically, the circuit LMNT in Fig. 18D has a configuration in which a first terminal of a capacitor C1d, a gate of a transistor M1d, and a first terminal of a transistor M2d are electrically connected to an input terminal of a circuit BF2, a first input terminal of the circuit CMPD is electrically connected to an output terminal of the circuit BF2, a second input terminal of the circuit CMPD is electrically connected to a wiring VRFE, and an output terminal of the circuit CMPD is electrically connected to a wiring RSUL.

[0315] <<Configuration example 4 of circuit LMNT and circuit ILD>> Next, a description will be given of a configuration example of the circuit LMNT that is different from those in FIGS. 16, 17A, and 18A to 18D and that can be applied to the semiconductor device SDV2.

[0316] 16, the circuit LMNT shown in FIG. 20A includes a circuit LMC[i] (where i is an integer greater than or equal to 1 and less than or equal to the number of wirings IL). However, the circuit LMC[i] in FIG. 20A differs from the circuit LMC[i] in FIG. 16 in that it includes a memory cell DC, a circuit DTC, a switch DSW2, a switch DSW3, and a switch DSW4. Note that FIG. 20 also illustrates a circuit ILD.

[0317] 20A has the same configuration as the memory cell DC shown in Fig. 16. Therefore, for the transistor M1d, the transistor M2d, and the capacitance C1d included in the memory cell DC in Fig. 16, and the wiring VEd, the wiring WLd, and the wiring DLd shown in Fig. 20A, the description of the circuit LMNT in Fig. 16 should be referred to.

[0318] The circuit LMNT in Fig. 20A can have a plurality of circuits LMC[i], similar to the circuit LMNT in Fig. 16. Specifically, for example, the circuit LMNT can be configured such that the same number of circuits LMC[i] as the number of wirings IL electrically connected to the circuit ILD are arranged in one row.

[0319] As the switches DSW2 to DSW4, similar to the switch DSW1 in FIG. 16, for example, switches applicable to the switch RSW described above can be used.

[0320] The wiring IL is electrically connected to a first terminal of a switch DSW4, and a second terminal of the switch DSW4 is electrically connected to a wiring DLd. The first terminal of the switch DSW2 is electrically connected to the wiring DLd, and a first input terminal of the circuit DTC is electrically connected to a second terminal of the switch DSW2. The first terminal of the switch DSW3 is electrically connected to the wiring IL, and a second input terminal of the circuit DTC is electrically connected to a second input terminal of the switch DSW3. The output terminal of the circuit DTC is electrically connected to a wiring RSUL. Although not shown, the wiring RSUL is electrically connected to the memory device MEXT.

[0321] For the circuit DTC, please refer to the description of the circuit DTC included in the circuit LMNT shown in FIG.

[0322] Next, a configuration example of the circuit ILD when the circuit LMNT in FIG. 20A is applied will be described.

[0323] FIG. 20B shows a configuration example of a circuit ILD when the circuit LMNT of FIG. 20A is applied, and includes a circuit WCS1 and a circuit WCSD.

[0324] The circuit WCS1 shown in Figure 20B is a part of the circuit WCS1 in Figure 2A, and shows only the circuit elements related to writing to the memory cell DC. Specifically, the circuit WCS1 in Figure 20B shows only the current source CC[u] and the switch SW[u]. At this time, the switches SW[1] to SW[K] other than the switch SW[u] are set to the off state, and the current generated by the current sources CC[1] to CC[K] other than the current source CC[u] does not flow through the wiring IL.

[0325] 20B includes a current source CCD and a switch SWN. A first terminal of the switch SWN is electrically connected to a second terminal of the switch SW[u] and a line IL, the second terminal of the switch SWN is electrically connected to an input terminal of the current source CCD, and an output terminal of the current source CCD is electrically connected to a line VSE.

[0326] The switch SWN can be any switch that can be used for the switch RSW described above. If a transistor is used as an electrical switch for the switch SWN, it is preferable that the transistor be an n-channel transistor.

[0327] Moreover, the current source CCD preferably has, as an example, an n-channel transistor whose gate is supplied with a bias voltage and whose source is supplied with a low-level potential or a ground potential (a potential provided by the wiring VSE).

[0328] Furthermore, the amount of current generated by the current source CCD is assumed to be smaller than the amount of current generated by the current source CC[u]. Specifically, for example, when the amount of current generated by the current source CC[u] is I0, the amount of current generated by the current source CCD can be 0.95, 0.90, 0.80 times the amount of current I0. Hereinafter, the current generated by the current source CCD will be referred to as the reference current.

[0329] Next, an example of the operation of the circuit LMNT in FIG. 20A will be described.

[0330] First, in the circuit LMC[i], the switch DSW4 is turned on, the switches DSW2 and DSW3 are turned off, and the transistor M2d is turned on. At this time, in FIG. 20B, the switch SW[u] is turned on, and the switch SWN is turned off. This causes a current of a magnitude I0 to flow from the circuit ILD to the memory cell DC via the wiring IL. Next, similar to the circuit LMNT in FIG. 16, a voltage V is applied to the first terminal of the capacitor C1d of the memory cell DC. nd is written, the transistor M2d is turned off, and the voltage of the node n1d is maintained.

[0331] At this time, an initialization current with a current amount I0 flows between the first terminal and the second terminal of the transistor M1d (between the wiring DLd and the wiring VEd). After that, the switch DSW1 is turned off to stop the current flowing between the first terminal and the second terminal of the transistor M1d.

[0332] When starting to monitor the current flowing between the first and second terminals of transistor M1d, switch DSW4 is turned off and switch DSW2 is turned on, causing a current of magnitude I0 to flow between the first and second terminals of transistor M1d from the first input terminal of circuit DTC to line VEd via switch DSW2 and line DLd.

[0333] At the same time that switch DSW2 is turned on, switch DSW3 is turned on. Also, in FIG. 20B, switch SW[u] is turned off and switch SWN is turned on. This causes a reference current to flow from the second input terminal of circuit DTC to line VSE via switch DSW3, line IL, and switch SWN.

[0334] Here, the potential V held at the first terminal of the capacitor C1d is nd decreases due to charge leakage or the like, the amount of current flowing between the first terminal and the second terminal of the transistor M1d decreases from I0. When the amount of current flowing from the first input terminal of the circuit DTC to the wiring VEd becomes equal to or less than the amount of the reference current flowing from the wiring IL, the circuit DTC determines that the data held in the memory cell DC has deteriorated, and transmits a command signal (for example, a pulse signal) to the memory device MEXT to read data to be rewritten in the multiplication cell of the calculation unit CLP and transmit the data to the circuit ILD.

[0335] 16, the memory device MEXT receives the command signal, reads out the information stored in the memory device MEXT, and transmits it to the semiconductor device SDV2. Then, the semiconductor device SDV2 writes the information to the multiplication cell included in the calculation unit CLP by the circuit ILD, and also writes the original voltage (or current) to the memory cell DC. This allows data to be rewritten (charge replenished) to the degraded data stored in the multiplication cell of the calculation unit CLP and the memory cell DC.

[0336] 20A is applied to the semiconductor device SDV2, it is possible to easily detect the deterioration of data held in the memory element of the multiplication cell of the operation unit CLP (decrease in the absolute value of the charge amount due to leakage current). Furthermore, by detecting this, it is possible to rewrite data (replenish charge) to the multiplication cell of the operation unit CLP and the memory cell DC.

[0337] <<Configuration example 5 of circuit LMNT and circuit ILD>> Next, a description will be given of an example of the configuration of the circuit LMNT that can be applied to the semiconductor device SDV2 of FIG. 15, which differs from the configurations of the circuit LMNT shown in the circuit 15, FIGS. 17A, 18A to 18D, and 20A.

[0338] The circuit LMNT shown in Figure 21A includes a circuit LMC[i] (where i is an integer greater than or equal to 1 and less than or equal to the number of wirings IL) and a circuit LMCr[i]. The circuit LMC[i] also includes a memory cell DC, a memory cell DCr, a circuit DTC, a switch DSW1, a switch DSW2, a switch DSW3, a switch DSW4, and a switch DSW4r. Figure 21A also shows a circuit ILD.

[0339] The memory cell DC has a transistor M1d, a transistor M2d, and a capacitor C1d. The memory cell DCr can have the same configuration as the memory cell DC or a different configuration from the memory cell DC. In FIG. 21A, the memory cell DCr has the same configuration as the memory cell DC. Therefore, the memory cell DCr is designated by the symbol "r" to distinguish it from the memory cell DC. The symbols of the circuit elements included in the circuit MCr, which will be described later, are also designated by the symbol "r." For example, the transistor M1dr, the transistor M2dr, and the capacitor C1dr included in the memory cell DCr shown in FIG. 21A correspond to the transistor M1d, the transistor M2d, and the capacitor C1d included in the memory cell DC, respectively. For example, the wiring VEdr and the wiring DLdr electrically connected to the memory cell DCr shown in FIG. 21A correspond to the wiring VEd and the wiring DLd electrically connected to the memory cell DC.

[0340] 21A has the same configuration as the memory cell DC shown in Fig. 16. Therefore, for the transistor M1d, the transistor M2d, and the capacitance C1d included in the memory cell DC in Fig. 21A, and the wiring VEd, the wiring WLd, and the wiring DLd shown in Fig. 21A, the description of the circuit LMNT in Fig. 16 should be referred to.

[0341] The circuit LMNT in Fig. 21A can have a plurality of circuits LMC[i], similar to the circuit LMNT in Fig. 16. Specifically, for example, the circuit LMNT can be configured such that the same number of circuits LMC[i] as the number of wirings IL electrically connected to the circuit ILD are arranged in one row.

[0342] As the switches DSW2, DSW3, and DSW4, similar to the switch DSW1 in FIG. 16, for example, switches applicable to the above-mentioned switch RSW can be used.

[0343] The circuit ILD is electrically connected to the wiring IL and the wiring ILB.

[0344] The wiring IL is electrically connected to a first terminal of a switch DSW4, and the second terminal of the switch DSW4 is electrically connected to a wiring DLd. The wiring DLd is electrically connected to a first terminal of a switch DSW2, and the second terminal of the switch DSW2 is electrically connected to a first input terminal of a circuit DTC, and the output terminal of the circuit DTC is electrically connected to a wiring RSUL. The wiring ILB is electrically connected to a first terminal of a switch DSW3 and a first terminal of a switch DSW4r, and the second terminal of the switch DSW4r is electrically connected to the wiring DLdr. The second input terminal of the circuit DTC is electrically connected to the second terminal of the switch DSW3. The output terminal of the circuit DTC is electrically connected to a wiring RSUL. Although not shown, the wiring RSUL is electrically connected to a memory device MEXT.

[0345] For the circuit DTC, please refer to the description of the circuit DTC shown in FIG. 17A.

[0346] Next, a configuration example of the circuit ILD when the circuit LMNT in FIG. 21A is applied will be described.

[0347] FIG. 21B shows a configuration example of a circuit ILD when the circuit LMNT of FIG. 21A is applied, and includes a circuit WCS1, a circuit WCS1r, a circuit WCSD, and a circuit WCSDr.

[0348] The circuit WCS1 and the circuit WCSD shown in Fig. 21B have the same configuration as the circuit WCS1 and the circuit WCSD shown in Fig. 20B, respectively. Therefore, for the circuit WCS1 and the circuit WCSD in Fig. 21B, please refer to the description of the circuit WCS1 and the circuit WCSD in Fig. 20B.

[0349] 21B are similar in configuration to the circuits WCS1 and WCSD in FIG. 21B. Therefore, the reference symbols "r" are added to the circuits WCS1r and WCSDr to distinguish them from the circuits WCS1 and WCSD. For example, the current source CCr[u] and switch SWr[u] included in the circuit WCS1r in FIG. 21B correspond to the current source CC[u] and switch SW[u] included in the circuit WCS1. For example, the current source CCDr[u] and switch SWNr[u] included in the circuit WCSDr in FIG. 21B correspond to the current source CCD[u] and switch SWN[u] included in the circuit WCSD.

[0350] The wiring IL is electrically connected to the second terminal of the switch SW[u] and the first terminal of the switch SWN. The wiring ILB is electrically connected to the second terminal of the switch SWr[u] and the first terminal of the switch SWNr.

[0351] Next, an example of the operation of the circuit LMNT in FIG. 21A will be described.

[0352] First, in the circuit LMC[i], the switch DSW4 is turned on, the switches DSW2 and DSW3 are turned off, and the transistor M2d is turned on. At this time, in FIG. 21B, the switch SW[u] is turned on, and the switch SWN is turned off. This causes a current of a magnitude I0 to flow from the circuit ILD to the memory cell DC via the wiring IL. Next, similar to the circuit LMNT in FIG. 16, a voltage V is applied to the first terminal of the capacitor C1d of the memory cell DC. nd is written, the transistor M2d is turned off, and the voltage of the node n1d is maintained.

[0353] At this time, an initialization current with a current amount I0 flows between the first terminal and the second terminal of the transistor M1d (between the wiring DLd and the wiring VEd). After that, the switch DSW1 is turned off to stop the current flowing between the first terminal and the second terminal of the transistor M1d.

[0354] When starting to monitor the current flowing between the first and second terminals of transistor M1d, switch DSW4 is turned off and switch DSW2 is turned on, causing a current of magnitude I0 to flow from the first input terminal of circuit DTC to line VEd via switch DSW2, line DLd, and transistor M1d.

[0355] At the same time that switch DSW2 is turned on, switch DSW3 is turned on and switch DSW4r is turned off. Also, in FIG. 21B, switch SWr[u] is turned off and switch SWNr is turned on. This causes a reference current to flow from the second input terminal of circuit DTC to line VSE via switch DSW3, line ILB, and switch SWNr.

[0356] Here, the potential V held at the first terminal of the capacitor C1d is nd decreases due to charge leakage or the like, the amount of current flowing between the first terminal and the second terminal of the transistor M1d decreases from I0. When the amount of current flowing from the first input terminal of the circuit DTC to the wiring VEd becomes equal to or less than the amount of the reference current flowing from the wiring IL, the circuit DTC determines that the data held in the memory cell DC has deteriorated, and transmits a command signal (for example, a pulse signal) to the memory device MEXT to read data to be rewritten in the multiplication cell of the calculation unit CLP and transmit the data to the circuit ILD.

[0357] 16, the memory device MEXT receives the command signal, reads out the information stored in the memory device MEXT, and transmits it to the semiconductor device SDV2. Then, the semiconductor device SDV2 writes the information to the multiplication cell included in the calculation unit CLP by the circuit ILD, and also writes the original voltage (or current) to the memory cell DC. This allows data to be rewritten (charge replenished) to the degraded data stored in the multiplication cell of the calculation unit CLP and the memory cell DC.

[0358] 21A is applied to the semiconductor device SDV2, it is possible to easily detect the deterioration of data held in the memory element of the multiplication cell of the operation unit CLP (decrease in the absolute value of the charge amount due to leakage current). Furthermore, by detecting this, it is possible to rewrite data (replenish charge) to the multiplication cell of the operation unit CLP and the memory cell DC.

[0359] <<Configuration example 6 of circuit LMNT and circuit ILD>> Next, as a modification of the circuit LMNT shown in FIG. 21A, a configuration example of the circuit LMNT that can be applied to the semiconductor device SDV2 of FIG. 15 will be described.

[0360] The circuit LMNT shown in Figure 22A is a modified example of the circuit LMNT shown in Figure 21A, and is configured such that the gate of transistor M2d included in memory cell DC is electrically connected to wiring WLd, and the gate of transistor M2dr included in memory cell DCr is electrically connected to wiring WLdr. In other words, the circuit LMNT of Figure 22A is configured such that the gate of transistor M2d and the gate of transistor M2dr are not directly connected. Therefore, for the parts of the circuit LMNT shown in Figure 22A that are common to the circuit LMNT of Figure 21A, please refer to the description of the circuit LMNT of Figure 21A.

[0361] Furthermore, as the circuit ILD in the circuit LMNT of Fig. 22A, for example, the circuit ILD shown in Fig. 21B can be applied. Hereinafter, the description will be given assuming that the circuit ILD of Fig. 21B is applied to the circuit ILD of Fig. 22A.

[0362] Next, an example of the operation of the circuit LMNT in FIG. 22A will be described.

[0363] First, in the circuit LMC[i], the switch DSW4 is turned on and the switch DSW2 is turned off. Next, a high-level potential is applied to the wiring WLd to turn on the transistor M2d. At this time, in FIG. 21B, the switch SW[u] is turned on and the switch SWN is turned off. This causes a current of a current amount I0 to flow from the circuit ILD to the memory cell DC via the wiring IL. Next, similar to the circuit LMNT in FIG. 16, a voltage V is applied to the first terminal of the capacitor C1d of the memory cell DC. nd , and a low-level potential is applied to the wiring WLd to turn off the transistor M2d, thereby holding the voltage of the node n1d.

[0364] At this time, an initialization current with a current amount I0 flows between the first terminal and the second terminal of the transistor M1d (between the wiring DLd and the wiring VEd). After that, the switch DSW1 is turned off to stop the current flowing between the first terminal and the second terminal of the transistor M1d.

[0365] When starting to monitor the current flowing between the first and second terminals of the transistor M1d, the switch DSW4r is turned on and the switch DSW3 is turned off. Next, a high-level potential is applied to the wiring WLdr to turn on the transistor M2dr. At this time, in FIG. 21B, the switch SWr[u] is turned off and the switch SWNr is turned on. This causes a reference current to flow from the circuit ILD to the transistor M1dr of the memory cell DCr via the wiring ILB. Also, the potential of the node n1dr at this time is set to V REF Then, a low-level potential is applied to the wiring WLdr to turn off the transistor M2dr, and the voltage VREF is maintained.

[0366] After that, switch DSW4 is turned off and switch DSW2 is turned on. As a result, a current of magnitude I0 flows from the first input terminal of circuit DTC to line VEd via switch DSW2, line DLd, and transistor M1d. Also, a reference current flows from the second input terminal of circuit DTC to line VEdr via switch DSW3, switch DSW4r, line DLdr, and transistor M1dr.

[0367] Here, the potential V held at the first terminal of the capacitor C1d is nd decreases due to charge leakage or the like, the amount of current flowing between the first terminal and the second terminal of the transistor M1d decreases from I0. When the amount of current flowing from the first input terminal of the circuit DTC to the wiring VEd becomes equal to or less than the amount of the reference current flowing from the second input terminal of the circuit DTC to the wiring VEdr, or when it becomes less than the amount of the reference current, the circuit DTC determines that the data held in the memory cell DC has deteriorated, and transmits a command signal (for example, a pulse signal) to the memory device MEXT to read data to be rewritten in the multiplication cell of the calculation unit CLP and transmit the data to the circuit ILD.

[0368] 16, the memory device MEXT receives the command signal, reads out the information stored in the memory device MEXT, and transmits it to the semiconductor device SDV2. Then, the semiconductor device SDV2 writes the information to the multiplication cell included in the calculation unit CLP by the circuit ILD, and also writes the original voltage (or current) to the memory cell DC. This allows data to be rewritten (charge replenished) to the degraded data stored in the multiplication cell of the calculation unit CLP and the memory cell DC.

[0369] 22A is applied to the semiconductor device SDV2, it is possible to easily detect the deterioration of data held in the memory element of the multiplication cell of the operation unit CLP (decrease in the absolute value of the charge amount due to leakage current). Furthermore, by detecting this, it is possible to rewrite data (replenish charge) to the multiplication cell of the operation unit CLP and the memory cell DC.

[0370] In the above example of operation, the memory cell DCr is supplied with a voltage V REF In order to retain the data, the deterioration of the data in the memory cell DCr (voltage V REF In this case, the memory cell DCr is applied with a potential V REF By starting to monitor the current flowing between the first terminal and the second terminal of the transistor M1d immediately after holding the data, it is possible to reduce the influence of deterioration of the data.

[0371] Furthermore, the configuration of the circuit LMNT according to one embodiment of the present invention is not limited to the circuit configuration shown in Fig. 22A. The configuration of the circuit LMNT may change the included circuit elements, connection configuration, etc. depending on the case or situation.

[0372] For example, the circuit LMNT may be configured such that the memory cells DC and DCr are arranged in a single column instead of a single row, as shown in Fig. 22B. Also, in Fig. 22B, the wiring VEd is electrically connected to the memory cell DCr instead of the wiring VEdr. Therefore, the wiring VEd and wiring VEdr shown in Fig. 22A can be combined into a single wiring by changing the configuration to that of Fig. 22B.

[0373] The memory cells DC described above may be included in, for example, the arithmetic unit CLP, not in the circuit LMNT. In this case, it is preferable that the memory cells DC are fabricated together with the multiplication cells (such as the circuits MC and MCr described in the second embodiment). Alternatively, the multiplication cells of the arithmetic unit CLP (such as the circuits MC and MCr described in the second embodiment) may be used as the memory cells DC.

[0374] The configuration of the semiconductor device SDV2 may be selected from the configurations of the above-mentioned Figures 16, 17A, 18A to 18D, 20A, 21A, 22A, and 22B, and may be a combination of these configurations.

[0375] 1A to 1C and the semiconductor device illustrated in FIG. 15 have been described in this embodiment, but the semiconductor device of one embodiment of the present invention is not limited thereto. For example, one embodiment of the present invention may have a structure in which the semiconductor device SDV1 includes the circuit LMNT included in the semiconductor device SDV2 as the semiconductor device SDV3, as illustrated in FIG. 23. That is, the structural example of the semiconductor device SDV1 described in this embodiment can be appropriately combined with the structural example of the semiconductor device SDV2.

[0376] Incidentally, when information (e.g., current, voltage, etc.) held in a circuit included in the calculation unit CLP changes due to leakage, etc., it is preferable to periodically perform a refresh operation or a rewrite operation on the circuit. Specifically, for example, when information (e.g., current, voltage, etc.) held in a circuit included in the calculation unit CLP changes, the information read out from the memory device MINT is again transmitted to the circuit ILD, and the circuit ILD supplies a current (or sometimes a voltage) according to the information to the circuit.

[0377] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0378] (Embodiment 2) In this embodiment, an example of the calculation unit CLP described in the above embodiment will be described.

[0379] <Hierarchical neural network> Before describing the arithmetic circuit, a hierarchical neural network will be described. A hierarchical neural network, for example, has one input layer, one or more intermediate layers (hidden layers), and one output layer, for a total of three or more layers. The hierarchical neural network 100 shown in FIG. 24A shows an example, and the neural network 100 has a first layer through an Rth layer (where R can be an integer equal to or greater than four). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to intermediate layers. Note that FIG. 24A illustrates the (k-1)th layer and the kth layer (where k is an integer equal to or greater than three and equal to or less than R-1) as intermediate layers, and does not illustrate the other intermediate layers.

[0380] Each layer of the neural network 100 has one or more neurons. In FIG. 24A, the first layer is made up of neurons N1 (1) Neuron N p (1) (where p is an integer equal to or greater than 1), and the (k-1)th layer has neurons N1 (k-1) Neuron N m (k-1) (where m is an integer greater than or equal to 1), and the kth layer has neurons N1 (k) Neuron N n (k) (where n is an integer greater than or equal to 1), and the Rth layer has neurons N1 (R) Neuron N q (R) (where q is an integer equal to or greater than 1).

[0381] In addition, in Figure 24A, neuron N1 (1) , neuron N p (1) , neuron N1 (k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , neuron N1 (R) , neuron N q (R)In addition, the (k-1)th layer neuron N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j (k) (where j is an integer between 1 and n) are also shown, and other neurons are omitted from the illustration.

[0382] Next, we will explain the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals input and output at each neuron. j (k) Focus on.

[0383] Figure 24B shows the k-th layer neuron N j (k) and neuron N j (k) and the signal input to neuron N j (k) 10 shows the signal output from the

[0384] Specifically, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) The output signal z1 (k-1) ~z m (k-1) But neuron N j (k) The output is directed to neuron N j (k) is z1 (k-1) ~z m (k-1) Depending on z j (k) Generate z j (k) is output as an output signal to each neuron in the (k+1)th layer (not shown).

[0385] The degree of signal transmission for a signal input from a neuron in the previous layer to a neuron in the next layer is determined by the connection strength (hereinafter referred to as a weighting coefficient) of the synapse connecting those neurons. In the neural network 100, the signal output from a neuron in the previous layer is multiplied by the corresponding weighting coefficient before being input to a neuron in the next layer. If i is an integer between 1 and m, then the (k-1)th layer neuron N i (k-1) and the k-th layer neuron N j (k) The weight coefficient of the synapse between i (k-1) j (k) Then, the k-th layer neuron N j (k) The signal input to can be expressed by equation (2.1).

[0386]

number

[0387] That is, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) From each of these, the k-th layer neuron N j (k) When a signal is transmitted to the (k-1) ~z m (k-1) The weighting coefficients w1 corresponding to each signal are (k-1) j (k) Or even w m (k-1) j (k) Then, the k-th layer neuron N j (k) has w1 (k-1) j (k) z1 (k-1) Or even w m (k-1) j (k) z m (k-1)is input. At this time, the k-th layer neuron N j (k) The sum of the signals input to j (k) is expressed as equation (2.2).

[0388]

number

[0389] Also, the weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) and the neuron signal z1 (k-1) ~z m (k-1) The result of the sum of products of and can be given a bias. When the bias is b, equation (2.2) can be rewritten as the following equation.

[0390]

number

[0391] Neuron N j (k) u j (k) Depending on j (k) where neuron N j (k) Output signal z from j (k) is defined as follows:

[0392]

number

[0393] The function f(u j (k)) is an activation function in a hierarchical neural network, and can be a step function, a ramp function (ReLU function), a sigmoid function, a tanh function, a softmax function, or the like. The activation function may be the same for all neurons or may be different. In addition, the activation function of neurons may be the same for each layer or may be different.

[0394] The signals, weight coefficients w, or biases b output by neurons in each layer may be analog or digital values. Digital values ​​may be, for example, binary or ternary. Values ​​with even larger bit counts may also be used. For example, in the case of analog values, activation functions such as linear ramp functions and sigmoid functions may be used. In the case of binary digital values, step functions that output either -1 or 1, or either 0 or 1 may be used. Furthermore, signals output by neurons in each layer may be ternary or more. For example, activation functions that output three values ​​may be ternary or more, such as step functions that output either -1, 0, or 1, or step functions that output either 0, 1, or 2. Furthermore, activation functions that output five values ​​may be step functions that output either -2, -1, 0, 1, or 2. By using digital values ​​for at least one of the signals output by neurons in each layer, the weighting coefficient w, or the bias b, it is possible to reduce the circuit size, reduce power consumption, or increase the calculation speed, etc. Furthermore, by using analog values ​​for at least one of the signals output by neurons in each layer, the weighting coefficient w, or the bias b, it is possible to improve the accuracy of calculations.

[0395] When an input signal is input to the first layer (input layer), neural network 100 generates an output signal in each layer, from the first layer (input layer) to the last layer (output layer), based on the signal input from the previous layer, using equations (2.1), (2.2) (or (2.3)), and (2.4), and outputs the output signal to the next layer. The signal output from the last layer (output layer) corresponds to the result of calculation by neural network 100.

[0396] <Configuration example 1 of an arithmetic circuit> Here, we will explain an example of an arithmetic circuit that can perform the calculations of formula (2.2) (or formula (2.3)) and formula (2.4) in the above-mentioned neural network 100. In this arithmetic circuit, as an example, the weight coefficients of the synapse circuits of the neural network 100 are set to binary (a combination of "-1" and "+1", or a combination of "0" and "+1"), ternary (a combination of "-1", "0", and "1"), or multiple values ​​of four or more (in the case of quinary values, a combination of "-2", "-1", "0", "1", and "2"), and the activation function of the neuron is set to a function that outputs binary (a combination of "-1" and "+1", or a combination of "0", "+1"), ternary (a combination of "-1", "0", and "1"), or multiple values ​​of four or more (in the case of quaternary values, a combination of "0", "1", "2", and "3"). In this specification, either the weight coefficient or the value of a signal input from a neuron in a previous layer to a neuron in a next layer (sometimes referred to as a calculated value) may be referred to as first data, and the other may be referred to as second data. Note that the weight coefficients and calculated values ​​of the synapse circuits of neural network 100 are not limited to digital values, and at least one of them may be an analog value.

[0397] The arithmetic circuit 110 shown in FIG. 25 is, as an example, a semiconductor device having a circuit ILD and an arithmetic unit CLP. The arithmetic unit CLP has an array unit ALP, a circuit WLD, a circuit XLD, and a circuit AFP. Note that FIG. 25 does not show the circuit LMNT electrically connected to the wiring IL and the wiring ILB, and the wiring electrically connecting the wiring IL and the wiring ILB to the circuit LMNT. The arithmetic circuit 110 is a semiconductor device having a k-th layer neuron N1 in FIGS. 24A and 24B. (k) Neuron N n (k) The signal z1 input to (k-1) ~z m (k-1) and neuron N1 (k) Neuron N n (k) The signal z1 output from each (k) ~z n (k) This is a circuit that generates

[0398] Note that the entire arithmetic circuit 110, or a part thereof, may be used for purposes other than neural networks (including CNNs and RNNs (recurrent neural networks) that perform convolutional processing) and AI. For example, when performing multiply-and-accumulate processing, matrix calculation processing, etc. in graphics calculations or scientific calculations, the entire arithmetic circuit 110, or a part thereof, may be used to perform the processing. In other words, the entire arithmetic circuit 110, or a part thereof, may be used not only for AI calculations but also for general calculations.

[0399] For example, the circuit ILD is electrically connected to wirings IL[1] to IL[n] and ILB[1] to ILB[n]. For example, the circuit WLD is electrically connected to wirings WLS[1] to WLS[m]. For example, the circuit XLD is electrically connected to wirings XLS[1] to XLS[m]. For example, the circuit AFP is electrically connected to wirings OL[1] to OL[n] and OLB[1] to OLB[n].

[0400] <<Array section ALP>> The array unit ALP has, for example, m×n circuits MP. The circuits MP are arranged in a matrix of m rows and n columns within the array unit ALP. In FIG. 25, the circuit MP located in the i-th row and j-th column (where i is an integer between 1 and m, and j is an integer between 1 and n) is represented as circuit MP[i,j]. However, in FIG. 25, only circuit MP[1,1], circuit MP[m,1], circuit MP[i,j], circuit MP[1,n], and circuit MP[m,n] are illustrated.

[0401] As an example, the circuit MP[i,j] is electrically connected to wiring IL[j], wiring ILB[j], wiring WLS[i], wiring XLS[i], wiring OL[j], and wiring OLB[j].

[0402] The circuit MP[i,j] is, for example, a neuron N i (k-1) and neuron N j (k) Specifically, the circuit MP[i,j] holds information (such as potential, resistance, and current) corresponding to the first data (weighting coefficient) input from the wiring IL[j] and the wiring ILB[j]. The circuit MP[i,j] also holds information corresponding to the first data (weighting coefficient) input from the wiring IL[j] and the wiring ILB[j]. i (k-1) The signal z output from i (k-1) (It may be called the other of the first data or the second data. Here, it is called the second data) and the first data. As a specific example, the circuit MP[i,j] receives the second data z from the wiring XLS[i]. i (k-1)When the first data and the second data are input, information corresponding to the product of the first data and the second data (e.g., a current, a voltage, etc.) or information related to the product of the first data and the second data (e.g., a current, a voltage, etc.) is output to the wiring OL[j] and the wiring OLB[j]. Note that although FIG. 25 illustrates an example in which the wiring IL[j] and the wiring ILB[j] are provided, one embodiment of the present invention is not limited to this. In one embodiment of the present invention, the arithmetic circuit 110 in FIG. 25 may have a configuration in which only one of the wiring IL[j] and the wiring ILB[j] is provided.

[0403] A specific example of the configuration of the circuit MP will be described later.

[0404] <<Circuit ILD>> For example, the circuit ILD transmits the first data w1 to the circuits MP[1,1] to MP[m,n] via the wirings IL[1] to IL[n] and the wirings ILB[1] to ILB[n]. (k-1) 1 (k) Or even w m (k-1) n (k) As a specific example, the circuit ILD has a function of inputting information (for example, potential, resistance value, current value, etc.) corresponding to the first data w i (k-1) j (k) The information (for example, potential, resistance value, or current value) corresponding to the first data w1 is supplied via the wiring IL[j] and the wiring ILB[j]. Specifically, the memory device MINT or the memory device MEXT described in the first embodiment is supplied with the first data w1 (k-1) 1 (k) Or even w m (k-1) n (k) is held, and the first data is transmitted from the memory device MINT or the memory device MEXT to the circuit ILD, so that the circuit ILD receives one data w i (k-1) j (k)Information corresponding to the circuit ILD (for example, a potential, a resistance value, or a current value) is supplied via the wiring IL[j] and the wiring ILB[j]. Note that the specific circuit configuration of the circuit ILD is described in the first embodiment and the like.

[0405] <<Circuit XLD>> For example, the circuit XLD transmits second data z1 to the circuits MP[1,1] to MP[m,n] via the wirings XLS[1] to XLS[m]. (k-1) ~z m (k-1) Specifically, the circuit XLD supplies the second data z i (k-1) 25 , information (for example, a potential, a current value, or the like) corresponding to the second data z is supplied via the wiring XLS[i]. Note that although the example in which the wiring XLS[i] is provided is shown, one embodiment of the present invention is not limited to this. For example, in one embodiment of the present invention, in the arithmetic circuit 110 in FIG. 25 , the wiring XLS[i] is provided as a plurality of wirings, and the second data z i (k-1) The information (for example, potential, current value, etc.) corresponding to the voltage may be supplied via a plurality of wirings.

[0406] <<Circuit WLD>> For example, the circuit WLD has a function of selecting a circuit MP to which information (e.g., a potential, a resistance value, a current value, etc.) corresponding to the first data input from the circuit ILD is to be written. For example, when writing information (e.g., a potential, a resistance value, a current value, etc.) to the circuits MP[i,1] to MP[i,n] located in the i-th row of the array portion ALP, the circuit WLD may supply a signal to the wiring WLS[i] for turning on or off the write switching elements included in the circuits MP[i,1] to MP[i,n] and supply a potential to the wiring WLS for turning off the write switching elements included in the circuits MP other than the i-th row. Note that although an example in which the wiring WLS[i] is provided is shown, one embodiment of the present invention is not limited thereto. In addition to the wiring WLS[i], for example, a wiring for transmitting an inverted signal of a signal input to the wiring WLS[i] may be provided separately.

[0407] 25 illustrates a configuration example in which a wiring WLS[i] is provided in the arithmetic circuit 110; however, one embodiment of the present invention is not limited to this. For example, the wiring WLS[i] may be replaced with a plurality of wirings. Furthermore, for example, the wiring XLS[i] may be replaced with a plurality of wirings, and some of the wiring XLS[i] may also be used as selection signal lines for writing data to the circuits MP[i,1] to MP[i,n]. Specifically, as in the arithmetic circuit 130 illustrated in FIG. 26, the wiring XLS[i] of the arithmetic circuit 110 may be replaced with wiring WX1L[i] and wiring X2L[i], and the wiring WX1L[i] may be electrically connected to the circuits WLD and XLD. When a signal for turning on or off the write switching elements included in the circuits MP[i,1] to MP[i,n] is supplied to the wiring WX1L[i] from the circuit WLD, the circuit XLD preferably has a function of bringing the circuit XLD and the wiring WX1L into a non-conduction state. (k-1) ~z m (k-1) When the signal is supplied from the circuit WLD to the circuits MP[i,1] to MP[i,n], the circuit WLD preferably has a function of bringing the circuit WLD and the wiring WX1L into a non-conductive state.

[0408] <<Circuit AFP>> The circuit AFP includes, for example, circuits ACTF[1] to ACTF[n]. For example, the circuit ACTF[j] is electrically connected to a wiring OL[j] and a wiring OLB[j]. For example, the circuit ACTF[j] generates a signal according to information (e.g., potential, current value, etc.) input from the wiring OL[j] and the wiring OLB[j]. For example, the circuit ACTF[j] compares information (e.g., potential, current value, etc.) input from the wiring OL[j] and the wiring OLB[j] and generates a signal according to the comparison result. That is, for example, the circuits ACTF[1] to ACTF[n] function as circuits that perform the activation function calculation of the neural network described above. However, one embodiment of the present invention is not limited thereto. For example, the circuits ACTF[1] to ACTF[n] may have a function of converting an analog signal into a digital signal. Alternatively, for example, the circuits ACTF[1] to ACTF[n] may have a function of amplifying and outputting an analog signal, that is, a function of converting output impedance. Alternatively, for example, the circuits ACTF[1] to ACTF[n] may have a function of converting current or charge into voltage. Alternatively, for example, the circuits ACTF[1] to ACTF[n] may have a function of initializing the potentials of the wirings OL[j] and OLB[j].

[0409] 25 illustrates an example in which the circuit ACTF is provided in the arithmetic circuit 110; however, one embodiment of the present invention is not limited to this. For example, the circuit ACTF does not necessarily have to be provided in the circuit AFP.

[0410] An example of the configuration of the circuit ACTF will be described later.

[0411] <<Circuit MP>> FIG. 27A shows an example of the configuration of a circuit MP[i,j] that can be applied to the arithmetic circuit 110. As an example, the circuit MP[i,j] includes a circuit MC and a circuit MCr. The circuit MC and the circuit MCr are circuits that calculate the product of the weight coefficient and the input signal (operation value) of the neuron in the circuit MP. The circuit MC can have the same configuration as the circuit MCr, or a different configuration from the circuit MCr. Therefore, the circuit MCr is marked with "r" to distinguish it from the circuit MC. Furthermore, the circuit elements included in the circuit MCr, which will be described later, are also marked with "r."

[0412] For example, the circuit MC includes a circuit HC, and the circuit MCr includes a circuit HCr. The circuit HC and the circuit HCr each have a function of retaining information (e.g., potential, resistance value, current value, etc.). Note that the first data w set in the circuit MP[i,j] i (k-1) j (k) is determined according to information (such as potential, resistance value, current value, etc.) held in each of the circuits HC and HCr. i (k-1) j (k) The wirings IL[j] and ILB[j] are electrically connected to the wirings IL[j] and ILB[j] that supply information (for example, potential, resistance value, current value, etc.) according to the above.

[0413] In FIG. 27A, the circuit MP[i,j] is electrically connected to the wiring VE[j] and the wiring VEn[j]. The circuits MC and MCr are electrically connected to the wiring OL[j] and the wiring OLB[j], respectively. The wiring VE[j] and the wiring VEn[j] function as wirings that supply a constant voltage. The wiring VE[j] also functions as a wiring that drains current from the wiring OL via the circuit MC. The wiring VEn[j] also functions as a wiring that drains current from the wiring OLB via the circuit MCr. In other words, the wiring VE[j] and the wiring VEn[j] each function as wirings that apply a constant voltage. Note that the constant voltage may be, for example, a ground potential or a low-level potential.

[0414] The wiring WL[i] shown in FIG. 27A corresponds to the wiring WLS[i] in FIG. 25. The wiring WL[i] is electrically connected to each of the circuit HC and the circuit HCr. The first data w i (k-1) j (k) When writing information (for example, a potential, a resistance value, a current value, etc.) according to the first data w, a predetermined potential is supplied to the wiring WL[i], thereby bringing the wiring IL[j] and the circuit HC into a conductive state and bringing the wiring ILB[j] and the circuit HCr into a conductive state. i (k-1) j (k) By supplying a potential or the like according to the data w, the potential or the like can be input to each of the circuits HC and HCr. After that, a predetermined potential is supplied to the wiring WL[i] to bring the wiring IL[j] and the circuit HC into a non-conductive state and the wiring ILB[j] and the circuit HCr into a non-conductive state. Then, the first data w is supplied to each of the circuits HC and HCr. i (k-1) j (k) Each current according to the above is maintained.

[0415] For example, the first data w i(k-1) j (k) Consider the case where the first data w takes one of the three values ​​"-1", "0", or "1". i (k-1) j (k) When the first data w is "1", for example, a predetermined potential is held in the circuit HC so that a current corresponding to "1" flows from the wiring OL[j] or the wiring OLB[j] to the wiring VE[j] via the circuit MC, and a potential V0 is held in the circuit HCr so that a current does not flow from the wiring OL[j] and the wiring OLB[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) When the first data w is "-1", for example, the potential V0 is held in the circuit HC so that no current flows from the wiring OL[j] and the wiring OLB[j] to the wiring VE[j] via the circuit MC, and a predetermined potential is held in the circuit HCr so that a current corresponding to "-1" flows from the wiring OL[j] or the wiring OLB[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) is "0", for example, a potential V0 is held in the circuit HC so that no current flows from the wiring OL[j] to the wiring VE[j] through the circuit MC, and a potential V0 is held in the circuit HCr so that no current flows from the wiring OLB[j] to the wiring VEl[j] through the circuit MC. Note that the potential V0 can be set to be equal to the potential applied by the wiring VE and / or the wiring VEl. Furthermore, the circuit ILD preferably has a function of supplying the potential V0 to the wirings IL and ILB.

[0416] Therefore, for example, the circuit ILD may be applied by changing the configuration of FIG. 2A to the configuration shown in FIG. 28. The circuit ILD of FIG. 28 is configured such that the circuit ILD of FIG. 2A is provided with a circuit LGC and the circuit WCS1 has a switch SW[0]. A first terminal of the switch SW[0] is electrically connected to the wiring IL (wiring ILB), and a second terminal of the switch SW[0] is electrically connected to the wiring VEG. Wirings DIL[1] to DIL[K] are electrically connected to the input terminals of the circuit LGC, respectively, and the output terminal of the circuit LGC is electrically connected to the control terminal of the switch SW[0] via the wiring DAL. The wiring VEG functions as a wiring that applies a potential (e.g., a low-level potential, a ground potential, etc.) equal to the potential applied by the wiring VE and / or the wiring VEl.

[0417] Note that it is preferable to use, as the switch SW[0], a transistor that can be applied to the switches SW[1] to SW[K], for example.

[0418] The circuit LGC has a function of transmitting a signal to turn on the switch SW[0] from the output terminal of the circuit LGC when, for example, each of the wirings DIL[1] to DIL[K] transmits a signal to turn off the switches SW[1] to SW[K]. In other words, the circuit LGC has a function of transmitting a signal to turn off the switch SW[0] from the output terminal of the circuit LGC when each of the wirings DIL[1] to DIL[K] transmits a signal to turn on any one of the switches SW[1] to SW[K]. Therefore, the circuit LGC can be, for example, a logic circuit having a NAND gate when the switches SW[0] to SW[K] are p-channel transistors, or a logic circuit having a NOR gate when the switches SW[0] to SW[K] are n-channel transistors.

[0419] Also, the first data i (k-1) j (k)Let us consider a case where the first data w is not a multi-value such as "-1", "0", or "1", but an analog value, specifically a "negative analog value", "0", or a "positive analog value". i (k-1) j (k) is a "positive analog value," for example, a predetermined potential is held in the circuit HC so that an analog current corresponding to the "positive analog value" flows from the wiring OL[j] to the wiring VE[j] via the circuit MC, and a potential V0 is held in the circuit HCr so that no current flows from the wiring OLB[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) is a "negative analog value," for example, a potential V0 is held in the circuit HC so that no current flows from the wiring OL[j] to the wiring VE[j] via the circuit MC, and a predetermined potential is held in the circuit HCr so that an analog current corresponding to the "negative analog value" flows from the wiring OLB[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) is "0", for example, the potential V0 is held in the circuit HC so that no current flows from the wiring OL[j] to the wiring VE[j] through the circuit MC, and the potential V0 is held in the circuit HCr so that no current flows from the wiring OLB[j] to the wiring VEr[j] through the circuit MC. Note that the potential V0 is preferably supplied from the circuit ILD through the wiring IL and the wiring ILB, as in the previous example.

[0420] As another example, the circuit MC has a function of outputting a current or the like corresponding to information (e.g., potential, resistance, or current) held in the circuit HC to one of the wiring OL[j] and the wiring OLB[j], and the circuit MCr has a function of outputting a current or the like corresponding to information (e.g., potential, resistance, or current) held in the circuit HCr to the other of the wiring OL[j] and the wiring OLB[j]. For example, when a first potential is held in the circuit HC, the circuit MC flows a current having a first current value from the wiring OL[j] or the wiring OLB[j] to the wiring VE, and when a second potential is held in the circuit HC, the circuit MC flows a current having a second current value from the wiring OL[j] or the wiring OLB[j] to the wiring VE. Similarly, when the circuit HCr holds a first potential, the circuit MCr flows a current having a first current value from the wiring OL[j] or the wiring OLB[j] to the wiring VEr, and when the circuit HCr holds a second potential, the circuit MCr flows a current having a second current value from the wiring OL[j] or the wiring OLB[j] to the wiring VE. The magnitudes of the first current value and the second current value are respectively determined by the first data w i (k-1) j (k) The first current value is determined by the value of . As an example, the first current value may be greater than or less than the second current value. Furthermore, as another example, one of the first current value and the second current value may be zero current, i.e., the current value may be 0. Alternatively, the current having the first current value and the current having the second current value may flow in different directions.

[0421] In particular, for example, the first data w i (k-1) j (k) When the first data w takes one of the three values ​​"-1", "0", and "1", it is preferable to configure the circuits MC and MCr so that either the first current value or the second current value becomes zero. i (k-1) j (k)takes an analog value, for example, a "negative analog value," "0," or a "positive analog value," the first current value or the second current value can also take an analog value, for example.

[0422] Incidentally, when the current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VE through the circuit MC is made equal to the current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VEr through the circuit MCr, the potential held in the circuit MC may not be equal to the potential held in the circuit MCr because the characteristics of the transistors may vary due to factors such as the manufacturing process of the transistors. The arithmetic circuit described in this embodiment can make the amount of current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VE through the circuit MC approximately equal to the amount of current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VEr through the circuit MCr, even if the characteristics of the transistors vary.

[0423] In this specification, the current or voltage corresponding to the information (e.g., potential, resistance value, or current value) stored in the circuit HC and the circuit HCr may be a positive current or voltage, a negative current or voltage, a zero current or zero voltage, or a mixture of positive, negative, and zero. In other words, for example, the above description "has the function of outputting a current or voltage corresponding to information (e.g., potential, resistance, or current value) held in the circuit HC to one of the wiring OL[j] and the wiring OLB[j], and the circuit MCr has the function of outputting a current or voltage corresponding to information (e.g., potential, resistance, or current value) held in the circuit HCr to the other of the wiring OL[j] and the wiring OLB[j]" can be rephrased as "has the function of discharging a current, voltage, or the like corresponding to information (e.g., potential, resistance, or current value) held in the circuit HC from one of the wiring OL[j] and the wiring OLB[j], and the circuit MCr has the function of discharging a current, voltage, or the like corresponding to information (e.g., potential, resistance, or current value) held in the circuit HCr from the other of the wiring OL[j] and the wiring OLB[j]."

[0424] The wiring X1L[i] and the wiring X2L[i] shown in FIG. 27A correspond to the wiring XLS[i] in FIG. 25. Note that the second data z i (k-1) is determined by, for example, the potential or current of each of the wirings X1L[i] and X2L[i]. Therefore, the second data z i (k-1) Each potential corresponding to the above is input.

[0425] The circuit MC is electrically connected to the wiring OL[j] and the wiring OLB[j], and the circuit MCr is electrically connected to the wiring OL[j] and the wiring OLB[j]. For example, the circuit MC and the circuit MCr transmit the first data w to the wiring OL[j] and the wiring OLB[j] in response to a potential or a current input to the wiring X1L[i] and the wiring X2L[i]. i (k-1) j (k) and the second data z i (k-1) and outputs a current or potential according to the product of these. As a specific example, the destination of the current output from the circuit MC and the circuit MCr is determined by the potentials of the wiring X1L[i] and the wiring X2L[i]. For example, the circuit MC and the circuit MCr are configured so that the current output from the circuit MC flows to either the wiring OL[j] or the wiring OLB[j], and the current output from the circuit MCr flows to the other wiring OL[j] or the wiring OLB[j]. In other words, the currents output from the circuit MC and the circuit MCr do not flow through the same wiring, but through different wirings. Note that, as an example, there may be cases where no current flows from the circuit MC or the circuit MCr to either the wiring OL[j] or the wiring OLB[j].

[0426] For example, the second data z i (k-1) Consider the case where the second data z takes one of three values: "-1", "0", or "1".i (k-1) is "1", the circuit MP brings the circuit MC and the wiring OL[j] into a conductive state, and brings the circuit MCr and the wiring OLB[j] into a conductive state. For example, i (k-1) is "-1", the circuit MP brings the circuit MC and the wiring OLB[j] into a conductive state, and brings the circuit MCr and the wiring OL[j] into a conductive state. For example, i (k-1) When is "0", in order to prevent the currents output by the circuits MC and MCr from flowing to either the wiring OL[j] or the wiring OLB[j], the circuit MP brings the circuit MC and the wiring OL[j] and the circuit MC and the wiring OLB[j] into a non-conductive state, and brings the circuit MCr and the wiring OL[j] and the circuit MC and the wiring OLB[j] into a non-conductive state.

[0427] An example of the above operations is shown below. i (k-1) j (k) When the first data w is "1", a current may flow from the wiring OL[j] or wiring OLB[j] to the wiring VE[j] via the circuit MC, and a current does not flow from the wiring OL[j] or wiring OLB[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) When the second data z is "-1", current may not flow from the wiring OL[j] or wiring OLB[j] to the wiring VE[j] via the circuit MC, and current may flow from the wiring OL[j] or wiring OLB[j] to the wiring VEr[j] via the circuit MCr. i (k-1) When the second data z is "1", the circuit MC and the wiring OL[j], and the circuit MCr and the wiring OLB[j] are in a conductive state. i (k-1) When the first data w is "-1", the circuit MC and the wiring OLB[j], and the circuit MCr and the wiring OL[j] are in a conductive state. i (k-1)j (k) and the second data z i (k-1) When the product of the first data w is a positive value, a current flows from the wiring OL[j] to the wiring VE[j] via the circuit MCr, or a current flows from the wiring OL[j] to the wiring VEn[j] via the circuit MCr. i (k-1) j (k) and the second data z i (k-1) When the product of the first data w is a negative value, either a current flows from the wiring OL[j] to the wiring VEr[j] via the circuit MCr, or a current flows from the wiring OLB[j] to the wiring VE[j] via the circuit MC. i (k-1) j (k) and the second data z i (k-1) When the product is zero, no current flows from the wiring OL[j] or wiring OLB[j] to the wiring VE[j], and no current flows from the wiring OL[j] or wiring OLB[j] to the wiring VEr[j].

[0428] To take the above example as a specific example, the first data w i (k-1) j (k) is "1", and the second data z i (k-1) When the first data w is "1", for example, a current I1[i, j] having a first current value flows from the circuit MC to the wiring OL[j], and a current I2[i, j] having a second current value flows from the circuit MCr to the wiring OLB[j]. In this case, the magnitude of the second current value is, for example, zero. i (k-1) j (k) is "-1", and the second data z i (k-1) When the first data w is "1", for example, a current I1[i, j] having a second current value flows from the circuit MC to the wiring OL[j], and a current I2[i, j] having a first current value flows from the circuit MCr to the wiring OLB[j]. In this case, the magnitude of the second current value is, for example, zero.i (k-1) j (k) is "0", and the second data z i (k-1) When is "1", a current I1[i, j] having a second current value flows from the circuit MC to the wiring OL[j], and a current I2[i, j] having a second current value flows from the circuit MCr to the wiring OLB[j]. In this case, the magnitude of the second current value is, for example, zero.

[0429] Also, the first data i (k-1) j (k) is "1", and the second data z i (k-1) When the first data w is "-1", a current I1[i, j] having a first current value flows from the circuit MC to the wiring OLB[j], and a current I2[i, j] having a second current value flows from the circuit MCr to the wiring OL[j]. In this case, the magnitude of the second current value is, for example, zero. i (k-1) j (k) is "-1", and the second data z i (k-1) When the first data w is "-1", a current I1[i, j] having a second current value flows from the circuit MC to the wiring OLB[j], and a current I2[i, j] having a first current value flows from the circuit MCr to the wiring OL[j]. In this case, the magnitude of the second current value is, for example, zero. i (k-1) j (k) is "0", and the second data z i (k-1) is "-1", a current I1[i, j] having a second current value flows from the circuit MC to the wiring OLB[j], and a current I2[i, j] having a second current value flows from the circuit MCr to the wiring OL[j]. In this case, the magnitude of the second current value is, for example, zero.

[0430] Also, the second data z i (k-1)When the first data w is "0", for example, the circuit MC and the wiring OL[j] and the circuit MC and the wiring OLB[j] are in a non-conductive state. Similarly, the circuit MCr and the wiring OL[j] and the circuit MCr and the wiring OLB[j] are in a non-conductive state. Therefore, the first data w i (k-1) j (k) Whatever the value of is, no current is output from the circuit MC and the circuit MCr to the wiring OL[j] and the wiring OLB[j].

[0431] In this way, as an example, the first data w i (k-1) j (k) and the second data z i (k-1) When the product of the first data w and the second data w is a positive value, a current flows from either the circuit MC or the circuit MCr to the wiring OL[j]. i (k-1) j (k) When is a positive value, current flows from the circuit MC to the wiring OL[j], and the first data w i (k-1) j (k) When the first data w is a negative value, a current flows from the circuit MCr to the wiring OL[j]. i (k-1) j (k) and the second data z i (k-1) When the product of w and w is a negative value, a current flows from either the circuit MC or the circuit MCr to the wiring OLB[j]. i (k-1) j (k) When is a positive value, current flows from the circuit MC to the wiring OLB[j], and the first data w i (k-1) j (k)If is a negative value, a current flows from the circuit MCr to the wiring OLB[j]. Therefore, the sum of the currents output from the multiple circuits MC or circuits MCr connected to the wiring OL[j] flows through the wiring OL[j]. In other words, a current that is the sum of positive values ​​flows through the wiring OL[j]. On the other hand, the sum of the currents output from the multiple circuits MC or circuits MCr connected to the wiring OLB[j] flows through the wiring OLB[j]. In other words, a current that is the sum of negative values ​​flows through the wiring OLB[j]. As a result of the above operation, a product-sum operation can be performed by using the total current value flowing through the wiring OL[j], i.e., the sum of positive values, and the total current value flowing through the wiring OLB[j], i.e., the sum of negative values. For example, if the total current value flowing through the wiring OL[j] is greater than the total current value flowing through the wiring OLB[j], the product-sum operation result can be determined to be a positive value. If the total current value flowing through the wiring OL[j] is smaller than the total current value flowing through the wiring OLB[j], it can be determined that the result of the product-sum operation will be a negative value. If the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same value, it can be determined that the result of the product-sum operation will be a zero value.

[0432] In addition, the second data z i (k-1) The same operation can be performed when the first data w is any one of two values ​​of "-1", "0", and "1", for example, when the first data w is either "-1" or "1", or when the first data w is either "0" or "1". i (k-1) j (k) The same operation can be performed when the value is one of two values ​​"-1", "0", or "1", for example, when the value is two values ​​"-1" or "1", or when the value is two values ​​"0" or "1".

[0433] In addition, the first data i (k-1) j (k)may take on a multi-bit (multi-value) digital value. i (k-1) j (k) The first data w can take five values: "-2", "-1", "0", "1", and "2". i (k-1) j (k) When "+2" is set, the magnitude of the current flowing from the circuit MC is the first data w i (k-1) j (k) The voltages of the circuits HC and HCr of the circuit MP are maintained so that the current flow is double that when the first data w is "+1" and the current flowing from the circuit MCr is zero. i (k-1) j (k) When "-2" is set, the magnitude of the current flowing from the circuit MCr is set to the first data w i (k-1) j (k) is "-1", and the voltages of the circuits HC and HCr of the circuit MP are maintained so that the amount of current flowing from the circuit MC is zero.

[0434] Also, the first data i (k-1) j (k) may take an analog value. As a specific example, a "negative analog value" may be used instead of "-1", and a "positive analog value" may be used instead of "1". In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr may also be, for example, the first data w i (k-1) j (k) It becomes an analog value according to the absolute value of the value.

[0435] Also, the second data z i (k-1) When treating as four or more values ​​or analog values, for example, an integrating circuit that converts the charge flowing as a current into a voltage is provided, and the second data zi (k-1) , and a voltage is input to the wiring X1L[i] and the wiring X2L[i] during the input time. i (k-1) When is a positive value, the second data z i (k-1) A high-level potential may be applied to the wiring X1L[i] and a low-level potential may be applied to the wiring X2L[i] for a period of time corresponding to the second data z i (k-1) When is a negative value, the second data z i (k-1) A low-level potential is applied to the wiring X1L[i] and a high-level potential is applied to the wiring X2L[i] for a period of time corresponding to the first data w i (k-1) j (k) The integration circuit converts the amount of charge flowing through the line OL[j] or the line OLB[j] into a voltage, thereby obtaining the first data w i (k-1) j (k) and the second data z i (k-1) In other words, by applying the above configuration, it is possible to obtain a voltage according to the product of the first data w i (k-1) j (k) is a multi-value or analog value, and the second data z i (k-1) It is possible to perform a multiplication operation using multi-valued or analog values.

[0436] Furthermore, the circuit MC may have two or more circuits HC and HCr. By having two or more circuits HC (circuits HCr) in the circuit MC (circuit MCr), two or more first data can be stored in the circuit MP. Furthermore, by providing a driving circuit or the like that selects one of the two or more circuits HC (circuits HCr) in the calculation unit CLP, the first data to be calculated in the calculation unit CLP can be selected. Therefore, by configuring such a circuit MP, the circuit MP can multiply one selected from the two or more first data and input second data by switching between the two or more circuits HC (circuits HCr) included in the circuit MC (circuit MCr). Furthermore, by applying such a circuit MP to the entire array unit ALP, when performing a product-sum operation on multiple first data and multiple second data, each of the multiple first data can be switched to another multiple first data.

[0437] Next, a specific example of the circuit configuration of Fig. 27A will be described. The circuit configuration shown in Fig. 27B is an example of the circuit configuration of the circuit MP of Fig. 27A, and the circuit MC included in the circuit MP of Fig. 27B has, as an example, transistors M1 to M5, which are n-channel transistors, and a capacitor C1. Note that, for example, a circuit HC is formed by a transistor M2 and a capacitor C1.

[0438] 27B, the circuit MCr has a circuit configuration similar to that of the circuit MC. Therefore, the circuit elements of the circuit MCr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MC. Therefore, for the transistors M1r to M5r, the capacitance C1r, and the node n1r, please refer to the explanations of the transistors M1 to M5, the capacitance C1, and the node n1 below.

[0439] Furthermore, in this specification and the like, unless otherwise specified, the transistor M1 is considered to ultimately operate in the saturation region when it is on. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are considered to include a case where they are appropriately biased to voltages within the range in which they operate in the saturation region. However, one aspect of the present invention is not limited to this. The transistor M1 may operate in the linear region to reduce the amplitude of the supplied voltage. Furthermore, the transistor M1 may operate in the subthreshold region to reduce the amount of current flowing through the transistor M1. Alternatively, the transistor M1 may operate near the boundary between the saturation region and the subthreshold region. Note that when the first data (weighting coefficient) is an analog value, the transistor M1 may operate in a combination of the linear region, the saturation region, and the subthreshold region, depending on the magnitude of the first data (weighting coefficient). Alternatively, the transistor M1 may operate in a combination of a linear region and a saturation region, a combination of a saturation region and a subthreshold region, or a combination of a linear region and a subthreshold region.

[0440] Furthermore, in this specification and the like, unless otherwise specified, the transistors M2 to M5 are considered to ultimately operate in a linear region when they are on. That is, the gate voltage, source voltage, and drain voltage of each of the above-described transistors are considered to include a case where they are appropriately biased to voltages within a range where they operate in a linear region. However, one embodiment of the present invention is not limited to this. For example, the transistors M2 to M5 may operate in a saturation region or a subthreshold region when they are on. Alternatively, they may operate near the boundary between the saturation region and the subthreshold region. Alternatively, the transistors M2 to M5 may operate in a combination of a linear region and a saturation region, a combination of a saturation region and a subthreshold region, a combination of a linear region and a subthreshold region, or a combination of a linear region, a saturation region, and a subthreshold region.

[0441] Furthermore, it is preferable that the sizes, for example, the channel length and the channel width, of the transistors M3 and M4 shown in FIG. 27B are equal to each other. Such a circuit configuration may enable an efficient layout. It may also be possible to make the currents flowing through the transistors M3 and M4 uniform. Similarly, it is preferable that the sizes of the transistors M1 and M1r shown in FIG. 27B are equal to each other. Similarly, it is preferable that the sizes of the transistors M2 and M2r shown in FIG. 27B are equal to each other. Similarly, it is preferable that the sizes of the transistors M5 and M5r shown in FIG. 27B are equal to each other. Similarly, it is preferable that the sizes of the transistors M3 and M3r, and the sizes of the transistors M4 and M4r shown in FIG. 27B are equal to each other.

[0442] 27B, each of the transistors M1 to M5 is illustrated as an n-channel transistor, but each of the transistors M1 to M5 may be replaced with a p-channel transistor. In this case, each of the transistors may be a p-channel transistor having an SOI (Silicon On Insulator) structure. The constant voltage applied to the wirings VE and VEr is preferably a high-level potential. Incidentally, in order to reduce the amplitude of the voltage applied to the gate of the transistor M2 (for example, an OS transistor), the transistor M1 (for example, a Si transistor) is preferably an n-channel transistor.

[0443] 27B, each of the transistors M2 to M5 may be replaced with an analog switch, a mechanical switch, etc. The analog switch may have a CMOS configuration using, for example, an n-channel transistor and a p-channel transistor.

[0444] Transistors M1 to M5 shown in FIG. 27B are, for example, n-channel transistors with a multi-gate structure having gates above and below the channel, and each of transistors M1 to M5 has a first gate and a second gate. For convenience, the present specification and the like distinguishes between the first gate (sometimes referred to as a front gate) and the second gate (sometimes referred to as a back gate), but the first gate and the second gate can be interchanged. Therefore, the term "gate" can be interchanged with the term "back gate" in this specification and the like. Similarly, the term "back gate" can be interchanged with the term "gate." Specifically, a connection configuration in which "the gate is electrically connected to a first wiring, and the back gate is electrically connected to a second wiring" can be replaced with a connection configuration in which "the back gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring."

[0445] Furthermore, the semiconductor device of one embodiment of the present invention does not depend on the connection configuration of the back gate of the transistor. Although the back gates of the transistors M1 to M5 in FIG. 27B are illustrated, the connection configuration of the back gates is not illustrated. However, the electrical connection destination of the back gate can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected to increase the on-state current of the transistor. That is, for example, the gate and the back gate of the transistor M2 may be electrically connected. Furthermore, in a transistor having a back gate, for example, a wiring electrically connected to an external circuit or the like may be provided to apply a fixed or variable potential to the back gate of the transistor by the external circuit or the like in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor. Note that this also applies to transistors described elsewhere in the specification or illustrated in other drawings, not just FIG. 27B.

[0446] Furthermore, the semiconductor device of one embodiment of the present invention does not depend on the structure of the transistors included in the semiconductor device. For example, each of the transistors M1 to M5 illustrated in FIG. 27B may have a structure without a back gate, that is, a single-gate transistor. Furthermore, some of the transistors may have a back gate, and other transistors may have a structure without a back gate.

[0447] Furthermore, in this specification and the like, transistors with various structures can be used as transistors. Therefore, the type of transistor to be used is not limited. Examples of transistors include transistors having single crystal silicon, and transistors having non-single crystal semiconductor films typified by amorphous silicon, polycrystalline silicon, and microcrystalline (also referred to as microcrystal, nanocrystal, or semi-amorphous) silicon. Alternatively, thin film transistors (TFTs) formed by thinning such semiconductors can be used. The use of TFTs offers various advantages. For example, TFTs can be manufactured at lower temperatures than single crystal silicon, thereby reducing manufacturing costs and increasing the size of the manufacturing equipment. The use of larger manufacturing equipment allows for manufacturing on a large substrate. Therefore, a large number of display devices can be manufactured simultaneously, resulting in low manufacturing costs. Alternatively, the low manufacturing temperature allows for the use of a substrate with poor heat resistance. Therefore, transistors can be manufactured on a light-transmitting substrate. Alternatively, light transmission through a display element can be controlled using a transistor on a light-transmitting substrate. Alternatively, the thin film thickness of the transistor allows light to pass through a portion of the film forming the transistor. Therefore, the aperture ratio can be improved.

[0448] Examples of transistors that can be used include transistors containing compound semiconductors (e.g., SiGe, GaAs, etc.) or oxide semiconductors (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, In-Sn-O (ITO), Sn-O, Ti-O, Al-Zn-Sn-O (AZTO), In-Sn-Zn-O, etc.). Alternatively, thin-film transistors formed by thinning these compound semiconductors or these oxide semiconductors can be used. This allows the manufacturing temperature to be lowered, making it possible to manufacture transistors at room temperature, for example. As a result, transistors can be formed directly on substrates with low heat resistance, such as plastic substrates or film substrates. These compound semiconductors or oxide semiconductors can be used not only for the channel portion of transistors but also for other applications. For example, these compound semiconductors or oxide semiconductors can be used as wiring, resistors, pixel electrodes, or light-transmitting electrodes. These can be deposited or formed simultaneously with transistors, thereby reducing costs.

[0449] As an example of a transistor, a transistor formed by an inkjet method or a printing method can be used. These methods allow manufacturing at room temperature, in a low vacuum, or on a large substrate. Therefore, manufacturing can be performed without using a mask (reticle), and the layout of the transistor can be easily changed. Furthermore, manufacturing can be performed without using a resist, which reduces material costs and the number of steps. Furthermore, since a film can be applied only to a necessary portion, materials are not wasted and costs can be reduced compared to a manufacturing method in which a film is formed on the entire surface and then etched.

[0450] As an example of a transistor, a transistor having an organic semiconductor, a carbon nanotube, or the like can be used. This allows a transistor to be formed on a flexible substrate. A device using a transistor having an organic semiconductor, a carbon nanotube, or the like can be made resistant to impacts.

[0451] It should be noted that various other structures of transistors can be used. For example, MOS transistors, junction transistors, bipolar transistors, etc. can be used as transistors. By using MOS transistors as transistors, the size of the transistors can be reduced. Therefore, a large number of transistors can be mounted. By using bipolar transistors as transistors, a large current can be passed. Therefore, the circuit can operate at high speed. It should be noted that MOS transistors and bipolar transistors can be mixed and formed on a single substrate. This can achieve low power consumption, miniaturization, high-speed operation, etc.

[0452] As an example of a transistor, a transistor with a structure in which gate electrodes are arranged above and below the active layer can be applied. By adopting a structure in which gate electrodes are arranged above and below the active layer, a circuit configuration is created in which multiple transistors are connected in parallel. This increases the channel formation region, making it possible to increase the current value. Alternatively, by adopting a structure in which gate electrodes are arranged above and below the active layer, it becomes easier to create a depletion layer, making it possible to improve the S value.

[0453] Examples of the transistor include a transistor having a structure in which a gate electrode is disposed above an active layer, a structure in which a gate electrode is disposed below an active layer, a staggered structure, an inverted staggered structure, a structure in which a channel region is divided into multiple regions, a structure in which active layers are connected in parallel, or a structure in which active layers are connected in series. Alternatively, the transistor may have various configurations, such as a planar type, a FIN type (fin type), a TRI-GATE type, a top gate type, a bottom gate type, and a double gate type (gates are disposed above and below the channel).

[0454] As an example of a transistor, a transistor having a structure in which a source electrode and a drain electrode overlap with an active layer (or a part thereof) can be used. By using a structure in which the source electrode and the drain electrode overlap with the active layer (or a part thereof), it is possible to prevent unstable operation due to charge accumulation in a part of the active layer.

[0455] As an example of a transistor, a structure with an LDD region can be applied. By providing the LDD region, it is possible to reduce the off-state current or improve the breakdown voltage (reliability) of the transistor. Also, by providing the LDD region, when operating in the saturation region, even if the voltage between the drain and source changes, the drain current does not change much, and a flat voltage-current characteristic can be obtained.

[0456] It should be noted that the above-described modifications to the connections and configurations of the terminals of the transistors can be applied not only to the circuit diagram shown in FIG. 27B but also to transistors described elsewhere in the specification or transistors illustrated in other drawings.

[0457] In the circuit MP of FIG. 27B, the first terminal of the transistor M1 is electrically connected to a wiring VE. The second terminal of the transistor M1 is electrically connected to a first terminal of the transistor M3, a first terminal of the transistor M4, and a first terminal of the transistor M5. The gate of the transistor M1 is electrically connected to a first terminal of the capacitor C1 and a first terminal of the transistor M2. The second terminal of the capacitor C1 is electrically connected to a wiring VE. The second terminal of the transistor M2 is electrically connected to a second terminal of the transistor M5 and a wiring IL. The gate of the transistor M2 is electrically connected to a wiring WL. The second terminal of the transistor M3 is electrically connected to a wiring OL, and the gate of the transistor M3 is electrically connected to a wiring X1L. The second terminal of the transistor M4 is electrically connected to a wiring OLB, and the gate of the transistor M4 is electrically connected to a wiring X2L.

[0458] A connection configuration in the circuit MCr that is different from that in the circuit MC will be described. The second terminal of the transistor M3r is electrically connected to the wiring OLB instead of the wiring OL, and the second terminal of the transistor M4r is electrically connected to the wiring OL instead of the wiring OLB. The first terminal of the transistor M1r and the first terminal of the capacitor C1r are electrically connected to the wiring VEr.

[0459] The first terminal of the transistor M1 may be electrically connected to another wiring instead of the wiring VE. Similarly, the first terminal of the transistor M1r may be electrically connected to another wiring instead of the wiring VE. The wiring VE may be the same wiring as the wiring VE. In the circuit diagrams of the other drawings, the first terminal of the transistor M1 may be electrically connected to another wiring instead of the wiring VE, and / or the first terminal of the transistor M1r may be electrically connected to another wiring instead of the wiring VE.

[0460] In the circuit HC shown in FIG. 27B, the electrical connection point between the gate of the transistor M1, the first terminal of the capacitor C1, and the first terminal of the transistor M2 is defined as a node n1.

[0461] As described above, the circuit HC has a function of holding a potential corresponding to the first data, for example. The potential is held in the circuit HC included in the circuit MC of FIG. 27B by inputting a potential from the wiring IL and writing it to the capacitor C1 when the transistors M2 and M5 are turned on, and then turning off the transistor M2. This allows the potential of the node n1 to be held as a potential corresponding to the first data. At this time, a current is input from the wiring OL, and a potential corresponding to the magnitude of the current can be held in the capacitor C1. This reduces the influence of variations in the current characteristics of the transistor M1.

[0462] In addition, since the transistor M1 holds the potential of the node n1 for a long time, it is preferable to use a transistor with low off-state current. For example, an OS transistor can be used as the transistor M1. Alternatively, a transistor with a back gate may be used as the transistor M1, and a low-level potential may be applied to the back gate to shift the threshold voltage to the positive side, thereby reducing the off-state current.

[0463] Note that the circuit configuration applicable to the circuit MP of FIG. 27A is not limited to the configuration of the circuit MP of FIG. 27B. For example, the circuit MP of FIG. 27A can be configured with the configuration of the circuit MP of FIG. 27C. The circuit MP of FIG. 27C is a modified example of the circuit MP of FIG. 27B, and has a configuration in which the electrical connections of the first terminals of the transistors M5 and M5r are modified. Specifically, in the circuit MP of FIG. 27C, the first terminal of the transistor M5 is electrically connected to the first terminal of the transistor M2, the gate of the transistor M1, and the first terminal of the capacitor C1. By configuring the circuit MP shown in FIG. 27C, the circuit MP of FIG. 27C can operate in a manner similar to the circuit MP of FIG. 27B.

[0464] <<Circuit ACTF>> Next, the circuits ACTF[1] to ACTF[n] will be described. The circuits ACTF[1] to ACTF[n] can have the circuit configuration shown in FIG. 29A, for example. FIG. 29A shows an example in which a signal z j (k) Specifically, FIG. 29A shows a circuit for generating a binary signal z j (k) 1 shows an example of an activation function calculation circuit that outputs

[0465] In FIG. 29A, the circuit ACTF[j] includes, as an example, a resistor RE, a resistor REB, and a comparator CMP. The resistors RE and REB have the function of converting current to voltage. Therefore, any element or circuit having the function of converting current to voltage is not limited to a resistor. The wiring OL[j] is electrically connected to the first terminal of the resistor RE and the first input terminal of the comparator CMP, and the wiring OLB[j] is electrically connected to the first terminal of the resistor REB and the second input terminal of the comparator CMP. The second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is electrically connected to the wiring VAL. The second terminal of the resistor RE and the second terminal of the resistor REB may be connected to the same wiring. Alternatively, they may be connected to different wirings having the same potential.

[0466] The resistance values ​​of the resistors RE and REB are preferably equal to each other. For example, it is desirable that the difference between the resistance values ​​of the resistors RE and REB is within 10% of the resistance value of the resistor RE, more preferably within 5%. However, one aspect of the present invention is not limited to this. In some cases or depending on the situation, the resistance values ​​of the resistors RE and REB may be different from each other.

[0467] For example, the wiring VAL functions as a wiring that applies a constant voltage. The constant voltage can be, for example, a high-level potential VDD, a low-level potential VSS, or a ground potential (GND). Preferably, the constant voltage is set appropriately depending on the configuration of the circuit MP. For example, the wiring VAL may be supplied with a pulse signal instead of a constant voltage.

[0468] The voltage between the first and second terminals of the resistor RE is determined according to the current flowing from the wiring OL[j]. Therefore, a voltage corresponding to the resistance value of the resistor RE and the current is input to the first input terminal of the comparator CMP. Similarly, the voltage between the first and second terminals of the resistor REB is determined according to the current flowing from the wiring OLB[j]. Therefore, a voltage corresponding to the resistance value of the resistor REB and the current is input to the second input terminal of the comparator CMP.

[0469] As an example, the comparator CMP has a function of comparing the voltages input to the first input terminal and the second input terminal, and outputting a signal from the output terminal of the comparator CMP according to the comparison result. For example, the comparator CMP can output a high-level potential from the output terminal of the comparator CMP when the voltage input to the second input terminal is higher than the voltage input to the first input terminal, and can output a low-level potential from the output terminal of the comparator CMP when the voltage input to the first input terminal is higher than the voltage input to the second input terminal. In other words, the potential output from the output terminal of the comparator CMP can be either a high-level potential or a low-level potential, so the signal z output by the circuit ACTF[j] j (k) For example, the high-level potential and the low-level potential output from the output terminal of the comparator CMP are respectively represented by the signal z j (k) In some cases, the high level potential and the low level potential output from the output terminal of the comparator CMP correspond to the signal z j (k) may correspond to "+1" and "0".

[0470] Although the circuit ACTF[j] in FIG. 29A uses resistors RE and REB, any element or circuit capable of converting current to voltage may be used. Therefore, the resistors RE and REB in the circuit ACTF[j] in FIG. 29A can be replaced with other circuit elements. For example, the circuit ACTF[j] shown in FIG. 29B is a circuit in which the resistors RE and REB included in the circuit ACTF[j] in FIG. 29A are replaced with capacitors CE and CEB. This circuit can perform substantially the same operation as the circuit ACTF[j] in FIG. 29A. Note that the capacitance values ​​of the capacitors CE and CEB are preferably equal to each other. For example, the difference between the capacitance values ​​of the capacitors CE and CEB is preferably within 10% of the capacitance value of the capacitor CE, more preferably within 5%. However, this is not a limitation of one embodiment of the present invention. Note that a circuit for initializing the charges stored in the capacitors CE and CEB may be provided. For example, a switch may be provided in parallel with the capacitor CE. That is, the second terminal of the switch may be connected to the wiring VAL, and the first terminal of the switch may be connected to the first terminal of the capacitor CE, the wiring OL[j], and the first input terminal of the comparator CMP. Alternatively, the second terminal of the switch may be connected to a wiring other than the wiring VAL, and the first terminal of the switch may be connected to the first terminal of the capacitor CE, the wiring OL[j], and the first input terminal of the comparator CMP. The circuit ACTF[j] shown in FIG. 29C is a circuit in which the resistors RE and REB included in the circuit ACTF[j] of FIG. 29A are replaced with diode elements DE and DEB, and can perform substantially the same operation as the circuit ACTF[j] of FIG. 29A. It is desirable to appropriately change the orientation (anode-cathode connection points) of the diode elements DE and DEB depending on the magnitude of the potential of the wiring VAL.

[0471] 29A to 29C, the comparator CMP included in the circuit ACTF[j] can be replaced with an operational amplifier OP. The circuit ACTF[j] shown in Fig. 29D is a circuit diagram in which the comparator CMP of the circuit ACTF[j] in Fig. 29A is replaced with an operational amplifier OP.

[0472] Furthermore, the circuit ACTF[j] of FIG. 29B may be provided with switches S01a and S01b. This allows the circuit ACTF[j] to maintain potentials corresponding to the currents input to the capacitors CE and CEB from the wiring OL[j] and wiring OLB[j], respectively. A specific example of such a circuit is shown in FIG. 29E. The first terminal of the switch S01a is electrically connected to the wiring OL[j], the second terminal of the switch S01a is electrically connected to the first terminal of the capacitor CE and the first input terminal of the comparator CMP, the first terminal of the switch S01b is electrically connected to the wiring OLB[j], and the second terminal of the switch S01b is electrically connected to the first terminal of the capacitor CEB and the second input terminal of the comparator CMP. In the circuit ACTF[j] of FIG. 29E, the potentials of the wiring OL[j] and wiring OLB[j] are input to the first input terminal and the second input terminal of the comparator CMP, respectively, by turning on the switches S01a and S01b. Then, by turning off the switches S01a and S01b, the potentials input to the first and second input terminals of the comparator CMP can be held in the capacitors CE and CEB. The switches S01a and S01b can be, for example, electrical switches such as analog switches or transistors. The switches S01a and S01b can also be, for example, mechanical switches. When transistors are used as the switches S01a and S01b, the transistors can be OS transistors or transistors having silicon in their channel formation regions (hereinafter referred to as Si transistors). Alternatively, the voltages of the capacitors CE and CEB can be controlled by controlling the periods during which the switches S01a and S01b are kept on. For example, when the currents flowing through the capacitors CE and CEB are large, shortening the periods during which the switches S01a and S01b are kept on can prevent the voltages of the capacitors CE and CEB from becoming too large.

[0473] 29A to 29C and 29E, the comparator CMP included in the circuit ACTF[j] can be, for example, a chopper-type comparator. The comparator CMP shown in FIG. 29F is a chopper-type comparator, and includes switches S02a, S02b, and S03, a capacitor CC, and an inverter circuit INV3. Similar to the switches S01a and S01b described above, the switches S02a, S02b, and S03 can be mechanical switches or transistors such as OS transistors or Si transistors.

[0474] A first terminal of the switch S02a is electrically connected to the terminal VinT, a first terminal of the switch S02b is electrically connected to the terminal VrefT, and a second terminal of the switch S02a is electrically connected to the second terminal of the switch S02b and the first terminal of the capacitor CC. The second terminal of the capacitor CC is electrically connected to the input terminal of the inverter circuit INV3 and the first terminal of the switch S03. The terminal VoutT is electrically connected to the output terminal of the inverter circuit INV3 and the second terminal of the switch S03.

[0475] The terminal VinT functions as a terminal for inputting an input potential to the comparator CMP, the terminal VrefT functions as a terminal for inputting a reference potential to the comparator CMP, and the terminal VoutT functions as a terminal for outputting an output potential from the comparator CMP. The terminal VinT can correspond to one of the first and second terminals of the comparator CMP in Figures 29A to 29C and 29E, and the terminal VrefT can correspond to the other of the first and second terminals of the comparator CMP in Figures 29A to 29C and 29E.

[0476] The circuit ACTF[j] in FIG. 29A to FIG. 29E converts a signal z j (k) The activation function ACTF[j] is a circuit that outputs the signal z j (k) Alternatively, the circuit ACTF[j] shown in FIGS. 29A to 29E may be configured to output zj (k) It is configured to output one signal, but z j (k) may be configured to output as two or more signals.

[0477] 29A to 29E is a circuit that compares two currents and outputs the result, and therefore can be applied to the circuit DTC described in embodiment 1. Alternatively, the circuit ACTF[j] may be configured to be shared with the circuit DTC described in embodiment 1.

[0478] <Example of operation of an arithmetic circuit> Next, an example of the operation of the arithmetic circuit 110 in Fig. 25 will be described. In the description of this example of the operation, the arithmetic circuit 110 shown in Fig. 30 will be used as an example.

[0479] The arithmetic circuit 110 in Fig. 30 is illustrated by focusing on the circuit located in the j-th column of the arithmetic circuit 110 in Fig. 25. In other words, the arithmetic circuit 110 in Fig. 30 is similar to the neuron N j (k) neuron N1 (k-1) Neuron N m (k-1) Signal z1 from (k-1) ~z m (k-1) and weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) 27B is applied to the circuit MP included in the array unit ALP of the arithmetic circuit 110 in Fig. 30. Also, the circuit ILD of Fig. 28 is applied to the circuit ILD of the arithmetic circuit 110 in Fig. 30.

[0480] First, in the arithmetic circuit 110, the first data w1(k-1) j (k) Or even w m (k-1) j (k) The first data w is set. i (k-1) j (k) The method of setting the first data is as follows: a predetermined potential is input to the wirings WLS[1] to WLS[m] by the circuit WLD, the circuits MP[1,j] to MP[m,j] are selected in order, and a potential, current, or the like according to the first data is supplied from the circuit ILD to the circuits HC and HCr of the circuits MC and MCr included in the selected circuit MP via the wirings IL[j] and ILB[j]. After the potential, current, or the like is supplied, the circuits MP[1,j] to MP[m,j] are deselected by the circuit WLD, and the first data w1 is supplied to the circuits MC and MCr included in each of the circuits MP[1,j] to MP[m,j]. (k-1) j (k) Or even w m (k-1) j (k) As an example, the potential, current, etc. according to the first data w1 (k-1) j (k) Or even w m (k-1) j (k) When each of the first data w1 takes a positive value, a value corresponding to the positive value is input to the circuit HC, and a value corresponding to zero is input to the circuit HCr. (k-1) j (k) Or even w m (k-1) j (k) When each of these takes a negative value, a value equivalent to zero is input to the circuit HC, and a value corresponding to the absolute value of the negative value is input to the circuit HCr. Note that, in the above, the value equivalent to zero can be, for example, the voltage applied by the wiring VEG described in FIG.

[0481] Next, the circuit XLD applies second data z1 (k-1) ~z m (k-1) As a specific example, the second data z1 is supplied to the wiring X1L[i] and the wiring X2L[i]. (k-1) is supplied.

[0482] Second data z1 input to each of the circuits MP[1,j] to MP[m,j] (k-1) ~z m (k-1) The conduction state between the circuits MC and MCr included in the circuits MP[i,j] to MP[m,j] and the wirings OL[j] and OLB[j] is determined according to the second data z i (k-1) Depending on the second data z1, the state may be one of the following: "the circuit MC and the wiring OL[j] are electrically connected, and the circuit MCr and the wiring OLB[j] are electrically connected," "the circuit MC and the wiring OLB[j] are electrically connected, and the circuit MCr and the wiring OL[j] are electrically connected," and "the circuit MC and the circuit MCr are electrically disconnected from the wiring OL[j] and the wiring OLB[j], respectively." (k-1) When the second data z1 is a positive value, a value that can bring the circuit MC and the wiring OL[j] into a conductive state and can bring the circuit MCr and the wiring OLB[j] into a conductive state is input to the wiring X1L[1]. Then, a value that can bring the circuit MC and the wiring OLB[j] into a non-conductive state and can bring the circuit MCr and the wiring OL[j] into a non-conductive state is input to the wiring X2L[1]. Then, the second data z1 (k-1)When the second data z1 is a negative value, a value that can bring the circuit MC and the wiring OLB[j] into a conductive state and can bring the circuit MCr and the wiring OL[j] into a conductive state is input to the wiring X1L[1]. Then, a value that can bring the circuit MC and the wiring OL[j] into a non-conductive state and can bring the circuit MCr and the wiring OLB[j] into a non-conductive state is input to the wiring X2L[1]. Then, the second data z1 (k-1) When the value of 0 is taken for the wiring X1L[1], a value that can bring the circuit MC and the wiring OLB[j] into a non-conductive state and can bring the circuit MCr and the wiring OL[j] into a non-conductive state is input to the wiring X1L[1]. Then, a value that can bring the circuit MC and the wiring OL[j] into a non-conductive state and can bring the circuit MCr and the wiring OLB[j] into a non-conductive state is input to the wiring X2L[1].

[0483] The second data z input to the circuit MP[i,j] i (k-1) The conduction state or non-conduction state between the circuit MC and the circuit MCr included in the circuit MP[i,j] and the wiring OL[j] and the wiring OLB[j] is determined in accordance with the first data w set in the circuit MP[i,j], and current is input and output between the circuit MC and the wiring OL[j] and the wiring OLB[j]. i (k-1) j (k) and / or second data z i (k-1) It depends on:

[0484] For example, in the circuit MP[i,j], the current flowing from the wiring OL[j] to the circuit MC or the circuit MCr is I[i,j], and the current flowing from the wiring OLB[j] to the circuit MC or the circuit MCr is I B [i,j]. Then, the current flowing from the circuit ACTF[j] to the wiring OL[j] is I out [j], and the current flowing from wiring OLB[j] to circuit ACTF[j] is I Bout If [j], then I out [j] and I Bout[j] can be expressed by the following formula:

[0485]

number

[0486] In the circuit MP[i,j], as an example, the first data w i (k-1) j (k) When is "+1", the circuit MC outputs I(+1) and the circuit MCr outputs I(-1), and the first data w i (k-1) j (k) When is "-1", the circuit MC outputs I(-1) and the circuit MCr outputs I(+1), and the first data w i (k-1) j (k) When is "0", the circuit MC emits I(-1) and the circuit MCr emits I(-1).

[0487] Furthermore, the circuit MP[i,j] receives the second data z i (k-1) is "+1", the state is "conduction between the circuit MC and the wiring OL[j], conduction between the circuit MCr and the wiring OLB[j], non-conduction between the circuit MC and the wiring OLB[j], and non-conduction between the circuit MCr and the wiring OL[j]" and the second data z i (k-1) is "-1", the state is "conduction between the circuit MC and the wiring OLB[j], conduction between the circuit MCr and the wiring OL[j], non-conduction between the circuit MC and the wiring OL[j], and non-conduction between the circuit MCr and the wiring OLB[j]" and the second data z i (k-1) When is "0", the state is assumed as follows: "there is no conduction between the circuit MC and the wiring OL[j], and between the circuit MC and the wiring OLB[j], and there is no conduction between the circuit MCr and the wiring OL[j], and between the circuit MCr and the wiring OLB[j]."

[0488] At this time, in the circuit MP[i,j], the current I[i,j] flows from the wiring OL[j] to the circuit MC or the circuit MCr, and the current I B [i,j] is as shown in the table below. In some cases, the circuit MP[i,j] may be configured so that the current amount of I(-1) is 0. The current I[i,j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OL[j]. Similarly, the current I B [i, j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OLB[j].

[0489] [Table 1]

[0490] Then, I flowing from each of the wiring OL[j] and wiring OLB[j] out [j] and I Bout By inputting each of [j] to the circuit ACTF[j], the circuit ACTF[j] can be configured as follows, for example: out [j] and I Bout [j]. The circuit ACTF[j], for example, selects a neuron N j (k) is the signal z sent to the (k+1)th layer neuron. j (k) Output.

[0491] As an example, the arithmetic circuit 110 of FIG. j (k) neuron N1 (k-1) Neuron N m (k-1) Signal z1 from (k-1) ~z m (k-1) and weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k)25. In other words, the operation circuit 110 of FIG. 25 can perform a multiplication and accumulation operation of the neuron N1 and an activation function calculation using the result of the multiplication and accumulation operation. Furthermore, by providing n rows of circuits MP in the array part ALP of the operation circuit of FIG. 30, a circuit equivalent to the operation circuit 110 of FIG. 25 can be configured. (k) Neuron N n (k) In each of the above, the product-sum operation and the calculation of the activation function using the result of the product-sum operation can be performed simultaneously.

[0492] <<Example 1 of changing circuits included in the arithmetic circuit>> Each of the above-described arithmetic circuits 110 and 130 can be changed to a circuit that performs the calculation of equation (2.3) instead of the calculation of equation (2.2). Equation (2.3) corresponds to an operation in which a bias is applied to the product-sum result of equation (2.2). Therefore, each of the arithmetic circuits 110 and 130 may be provided with a circuit that applies a bias value to the wiring OL and the wiring OLB.

[0493] The arithmetic circuit 170 shown in Fig. 31 has a circuit configuration in which circuits BS[1] to BS[n] are added to the array unit ALP of the arithmetic circuit 110 in Fig. 25. Note that, as the circuits BS[1] to BS[n], for example, the same circuit configurations as those in Fig. 27A to Fig. 27C may be applied.

[0494] The circuit BS[j] is electrically connected to the wiring OL[j], the wiring OLB[j], the wiring WBS, and the wiring XBS.

[0495] The wiring WBS functions as a wiring for supplying a signal for turning on or off the write switching elements included in the circuits BS[1] to BS[n], similar to the wirings WLS[1] to WLS[m] of the arithmetic circuit 110 in Fig. 25. Therefore, the wiring WBS is electrically connected to the circuit WLD, so that the signal can be supplied from the circuit WLD to the wiring WBS.

[0496] The wire XBS is connected to the neuron N in the same way as the wires XLS[1] to XLS[m] of the arithmetic circuit 110 in FIG. i (k-1) The second data z output from i (k-1) The wiring XBS functions as a wiring that supplies information (for example, a potential, a current value, and the like) corresponding to the wiring XBS to the circuits BS[1] to BS[n]. Therefore, when the wiring XBS is electrically connected to the circuit XLD, the information can be supplied from the circuit XLD to the wiring XBS.

[0497] The wiring XBS may also serve as a selection signal line for writing data to the circuits BS[1] to BS[n], similar to the wirings WX1L[1] to WX1L[m] of the arithmetic circuit 130 in Fig. 26. In such a configuration, the circuit WLD can supply a signal for turning on or off the writing switching elements included in the circuits BS[1] to BS[n] to the wiring WBS and the wiring XBS, respectively.

[0498] In the jth column of the array portion ALP of the arithmetic circuit 170, the amount of current flowing from the circuits MP[1,j] to MP[m,j] to the wiring OL[j] or the wiring OLB[j] can be expressed by the formula (2.5) and the formula (2.6), respectively. In addition, since each of the wiring OL[j] and the wiring OLB[j] is electrically connected to the circuit BS[j], the current flowing from the circuit BS[j] to the wiring OL[j] can be expressed by I BIAS [j], the current flowing from circuit BS[j] to wiring OLB[j] is I BIASB When [j] is used, equations (2.5) and (2.6) can be rewritten as the equations below.

[0499]

number

[0500] This allows us to calculate the bias in equation (2.3) by using I out [j] and I Bout [j] can be generated. Also, Iout [j] and I Bout [j] is input to the circuit ACTF[j], which biases the neuron N j (k) Signal z from j (k) can be generated.

[0501] 31, the circuits BS[1] to BS[n] are provided in one row in the array portion ALP, but one embodiment of the present invention is not limited to this. For example, the circuits BS[1] to BS[n] may be provided in two or more rows in the array portion ALP.

[0502] <<Example 2 of changing circuits included in the arithmetic circuit>> Here, the configuration of a circuit MP that is different from the circuit MP shown in FIGS. 27B and 27C and that can be applied to the arithmetic circuit 110 and the like will be described.

[0503] The circuit MP shown in Fig. 32 has a configuration including a memory circuit called NOSRAM (registered trademark). Note that Fig. 32 shows the entire circuit MP in order to show the electrical connection configuration of the circuit elements of the circuit HC and the circuit HCr.

[0504] The circuit MP in Fig. 32 has a configuration in which the transistor M5 and the transistor M5r are not provided in the configuration in Fig. 27B or Fig. 27C, and therefore the circuit MP in Fig. 32 is configured to write a voltage to the first terminal of the capacitance C1 of the circuit HC and the first terminal of the capacitance C1r of the circuit HCr.

[0505] For example, if the potential provided by the wiring VE is set to a low level potential and a high level potential is held at the first terminal of the capacitance C1 of the circuit HC, the transistor M1 is turned on, or if a low level potential is held at the first terminal of the capacitance C1 of the circuit HC, the transistor M1 is turned off.

[0506] Here, for example, consider a case where values ​​of "-1", "0", and "+1" are written to the circuit MP as first data. When "+1" is written to the circuit MP as first data, the potentials held in the circuits HC and HCr may be a combination of high-level potential and low-level potential. When "-1" is written to the circuit MP as first data, the potentials held in the circuits HC and HCr may be a combination of low-level potential and high-level potential. When "0" is written to the circuit MP as first data, the potentials held in the circuits HC and HCr may be a combination of low-level potential and low-level potential. Furthermore, the circuits HC and HCr may hold potentials of three or more values, or analog values, instead of two values ​​of high-level potential and low-level potential.

[0507] Next, after writing the first data to circuit MP as described above, by inputting a voltage corresponding to the second data to wiring X1L and wiring X2L as in the previous operation example, as a result of the product of the first data and the second data, a current flows (or may not flow) from wiring OL or wiring OLB to wiring VE via circuit MC, and a current flows (or may not flow) from wiring OL or wiring OLB to wiring VEr via circuit MCr.

[0508] Next, the configuration of a circuit MP that is different from the circuit MP shown in FIGS. 27B, 27C, and 32 and that can be applied to the arithmetic circuit 110 and the like will be described.

[0509] The circuit MP shown in Fig. 33A has a configuration including a memory circuit that includes elements similar to those of the load circuit LC described in Fig. 10. Note that Fig. 33 shows the entire circuit MP in order to illustrate the electrical connection configuration of the circuit elements of the circuit HC and the circuit HCr.

[0510] 33A, the circuit MC includes a circuit HC, a transistor M3, and a transistor M4, and also includes a load circuit LC2 and a transistor M8.

[0511] For the transistor M8, for example, a transistor applicable to the transistor M2 can be used, so the description of the transistor M2 should be taken into consideration for the transistor M8.

[0512] For the configurations of the transistors M3, M4, M3r, and M4r, please refer to the descriptions of the transistors M3, M4, M3r, and M4r provided elsewhere.

[0513] In circuit MC of circuit MP in Figure 33A, a first terminal of load circuit LC2 is electrically connected to a first terminal of transistor M8, a first terminal of transistor M3, and a first terminal of transistor M4, and a second terminal of load circuit LC2 is electrically connected to wiring VL. Also, a second terminal of transistor M8 is electrically connected to wiring IL, a second terminal of transistor M3 is electrically connected to wiring OL, and a second terminal of transistor M4 is electrically connected to wiring OLB. Also, a gate of transistor M8 is electrically connected to wiring WLS, a gate of transistor M3 is electrically connected to wiring X1L, and a gate of transistor M4 is electrically connected to wiring X2L.

[0514] 33A has a circuit configuration similar to that of the circuit MC. Therefore, the circuit elements of the circuit MCr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MC. The first terminal of the transistor M8r is electrically connected to the wiring ILB, the second terminal of the transistor M3r is electrically connected to the wiring OLB, and the second terminal of the transistor M4r is electrically connected to the wiring OL.

[0515] The wiring VL and wiring VLr function as wirings for supplying a constant voltage, which may be, for example, ground potential (GND) or a low potential within a range that allows the load circuits LC2 and LC2r to operate normally.

[0516] As an example, the load circuits LC2 and LC2r are circuits that can change the resistance between the first terminal and the second terminal, similar to the load circuit LC in Fig. 10. By changing the resistance between the first terminal and the second terminal of the load circuits LC2 and LC2r, the amount of current flowing between the first terminal and the second terminal of the load circuits LC2 and LC2r can be changed.

[0517] Here, a method for changing the resistance between the first and second terminals of the load circuits LC2 and LC2r in the circuit MP of FIG. 33A will be described. First, a low-level potential is input to each of the wires X1L and X2L to turn off the transistors M3, M3r, M4, and M4r. Next, a high-level potential is input to the wire WL to turn on the transistors M8 and M8r, and the potential of the wire IL (wire ILB) is changed to set the resistance between the first and second terminals of the load circuit LC2 (load circuit LC2r). For example, a potential for resetting the resistance between the first and second terminals of the load circuit LC2 (load circuit LC2r) is input to the wire IL (wire ILB), and then a potential is input to the wire IL (wire ILB) to set the resistance between the first and second terminals of the load circuit LC2 (load circuit LC2r) to a desired value. After setting the resistance value between the first and second terminals of the load circuit LC2 (load circuit LC2r) to a desired value, a low-level potential is input to the wiring WL to turn off the transistor M8 and the transistor M8r.

[0518] As the load circuit LC2 and the load circuit LC2r, for example, a resistance change element VR2 included in a ReRAM or the like can be used, as shown in Fig. 33B. Also, as the load circuit LC2 and the load circuit LC2r, for example, a load circuit LC2 including an MTJ element MR2 included in an MRAM or the like can be used, as shown in Fig. 33C. Also, as the load circuit LC2 and the load circuit LC2r, for example, a resistance element including a phase change material used in a phase change memory (PCM) or the like (here, for convenience, referred to as a phase change memory PCM2) can be used, as shown in Fig. 33D.

[0519] 33E, a ferroelectric capacitor FEC sandwiched between a pair of electrodes, such as that used in FeRAM, can be used as the load circuit LC2 and the load circuit LC2r. In this case, the line VL functions as a plate line, not as a line that applies a constant voltage.

[0520] Next, a description will be given of the configuration of a circuit MP that is different from the circuit MP shown in FIGS. 27B, 27C, 32, and 33A and that can be applied to the arithmetic circuit 110 and the like.

[0521] Figure 34A shows a circuit MP in which the circuit HC in Figure 32 is provided with an inverter loop circuit IVR instead of the transistor M1 and capacitor C1, and the circuit HCr is provided with an inverter loop circuit IVRr instead of the transistor M1r and capacitor C1r. In other words, the circuit MP in Figure 34A is configured to have an SRAM memory circuit. Note that the wiring VE and wiring VEr are omitted from the circuit MP in Figure 34A.

[0522] The inverter loop circuit IVR has an inverter circuit IV1 and an inverter circuit IV2, and the inverter loop circuit IVRr has an inverter circuit IV1r and an inverter circuit IV2r.

[0523] The output terminal of the inverter circuit IV1 is electrically connected to the input terminal of the inverter circuit IV2, the first terminal of the transistor M3, the first terminal of the transistor M4, and the first terminal of the transistor M1, and the output terminal of the inverter circuit IV2 is electrically connected to the input terminal of the inverter circuit IV1. The second terminal of the transistor M3 is electrically connected to the wiring OL, and the gate of the transistor M3 is electrically connected to the wiring X1L. The second terminal of the transistor M4 is electrically connected to the wiring OLB, and the gate of the transistor M4 is electrically connected to the wiring X2L. The second terminal ...

Claims

1. a first circuit, a second circuit, and a third circuit; the first circuit includes a current source and a first switch; the second circuit includes a first transistor, a second transistor, a third transistor, and a first capacitor; the third circuit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a second capacitor; a first terminal of the first transistor electrically connected to a control terminal of the first switch; a second terminal of the first transistor electrically connected to a first terminal of the second transistor; a second terminal of the second transistor electrically connected to a first terminal of the first capacitor; a gate of the second transistor is electrically connected to a second terminal of the first capacitor and a first terminal of the third transistor; a second terminal of the third transistor electrically connected to a write data line; a first terminal of the first switch electrically connected to an output terminal of the current source; a second terminal of the first switch electrically connected to a first terminal of the fourth transistor; a second terminal of the fourth transistor electrically connected to a first terminal of the second capacitor; a second terminal of the second capacitor is electrically connected to a wiring to which a constant voltage is supplied; a first terminal of the fifth transistor electrically connected to a first terminal of the fourth transistor; a first terminal of the sixth transistor electrically connected to a second terminal of the fifth transistor; a second terminal of the sixth transistor is electrically connected to a wiring to which the constant voltage is supplied; a first terminal of the seventh transistor electrically connected to a second terminal of the fifth transistor; a second terminal of the seventh transistor is electrically connected to a wiring through which a first current is output; a first terminal of the eighth transistor electrically connected to a second terminal of the fifth transistor; a second terminal of the eighth transistor is electrically connected to a wiring through which a second current is output; Semiconductor device.

2. In claim 1, a fourth circuit; the fourth circuit includes a latch circuit; the electrical connection between the first terminal of the first transistor and the control terminal of the first switch is established by electrically connecting a first terminal of the fourth circuit to the first terminal of the first transistor and electrically connecting a second terminal of the fourth circuit to the control terminal of the first switch. Semiconductor device.

Images