Low Dropout Regulator

Abstract

The gate region of the first OTA transistor is configured to receive a reference voltage, and the gate region of the second OTA transistor is configured to receive a voltage indicative of a load voltage. The adaptive compensation circuit includes: (i) a first compensation capacitor having a first electrode and a second electrode; (ii) a second compensation capacitor having a first electrode and a second electrode; and (iii) a first compensation transistor, wherein the second electrode of the first compensation capacitor is connected to the first region of the first compensation transistor and the first electrode of the second compensation capacitor is connected to both the second region and the gate region of the first compensation transistor. The first region of the second OTA transistor is connected to (i) a power supply voltage connection, (ii) the first electrode of the first compensation capacitor, and (iii) the gate region of the bias transistor. The second electrode of the second compensation capacitor is connected to the first region of the bias transistor.

Description

[Technical Field]

[0001] The present disclosure relates to the field of regulators, and more particularly to the field of low dropout regulators. [Background technology]

[0002] A voltage regulator can be used to provide a more stable power supply voltage. For example, a power supply, such as a battery, can be connected to a load to provide power to the load. Variations in the characteristics of the power supply and the load can cause the power supply voltage provided by the power supply to the load to fluctuate. Examples of these characteristics that may vary include load impedance, temperature, the output voltage from the battery, and the time since the two have been connected. For example, when a battery is nearly discharged, the output voltage may be half the output voltage when the battery is fully charged. A voltage regulator is designed to receive a supply voltage from a power supply and provide a load voltage to a load, where the supply voltage is intended to be relatively constant over time. It would be advantageous to provide an improved low-dropout regulator in which the load voltage from the regulator is more stable than previous low-dropout regulators, i.e., to provide better load voltage regulation. Summary of the Invention [Means for solving the problem]

[0003] Aspects of the disclosure are set out in independent claims, with optional features set out in dependent claims. Aspects of the disclosure may be provided in conjunction with one another, and features of one aspect may apply to other aspects.

[0004] In one aspect, a low dropout regulator is provided, comprising: a power supply voltage connection for receiving a power supply voltage; a load voltage output connection for supplying a load voltage to a load; a load voltage output control circuit comprising a pass transistor configured to adjust the load voltage based on a voltage at a gate region thereof; an adaptive bias circuit; and an adaptive compensation circuit. The adaptive bias circuit comprises a bias transistor configured to adjust a voltage supplied to a gate region of the pass transistor based on a voltage supplied to the gate region thereof; and an operational transconductance amplifier (OTA) circuit comprising a first OTA transistor and a second OTA transistor. The gate region of the first OTA transistor is configured to receive a reference voltage, and the gate region of the second OTA transistor is configured to receive a voltage indicative of the load voltage. The adaptive compensation circuit comprises: (i) a first compensation capacitor having a first electrode and a second electrode; (ii) a second compensation capacitor having a first electrode and a second electrode; and (iii) a first compensation transistor, wherein the second electrode of the first compensation capacitor is connected to the first region of the first compensation transistor, and the first electrode of the second compensation capacitor is connected to both the second region and the gate region of the first compensation transistor.

[0005] A first region of the second OTA transistor is connected to (i) the power supply voltage connection, (ii) a first electrode of the first compensation capacitor, and (iii) a gate region of the bias transistor. A second electrode of the second compensation capacitor is connected to the first region of the bias transistor.

[0006] Because the disclosed low-dropout regulators can have greater stability, embodiments may enable the provision of improved low-dropout regulators. That is, the disclosed low-dropout regulators may enable an output pole (to the regulator's transfer function) to be compensated (e.g., canceled) by a regulator zero. The low-dropout regulators may be provided with good phase margins over all operating conditions. The split compensation capacitors may enable improved stability and good phase margins without affecting the regulator's DC operating conditions.

[0007] A first region of the pass transistor may be connected to the supply voltage connection, and a second region of the pass transistor may be connected to the load voltage output connection. The regulator may further include a sensing circuit, the sensing circuit including a sense transistor having a gate region connected to the gate region of the pass transistor and a first region connected to the supply voltage connection. The sensing circuit may include a first current mirror connected to both the sense transistor and the adaptive compensation circuit. The first current mirror may include (i) a first electrode of the second compensation capacitor, (ii) a gate region of the first compensation transistor, and (iii) a first mirroring transistor having a first region connected to the second region of the first compensation transistor. The first current mirror may include a first mirror transistor. The second region of the sense transistor may be connected to (i) the first region of the first mirror transistor, (ii) the gate region of the first mirror transistor, and (iii) the gate region of the first mirroring transistor.

[0008] The adaptive compensation circuit may include a second compensation transistor. The first region of the first compensation transistor may be connected to the supply voltage connection via the second compensation transistor. The first region of the second compensation transistor may be coupled to the supply voltage connection, with its second region shorted to a gate region and connected to both the second electrode of the first compensation capacitor and the first region of the first compensation transistor. The adaptive compensation circuit may further include a compensation resistor disposed between the second electrode of the second compensation capacitor and the first region of the bias transistor.

[0009] The gate region of the pass transistor may be connected to the supply voltage connection via one or more resistors. The first region of the bias transistor may be connected to the supply voltage connection via one or more resistors. The regulator may further comprise a resistive transistor having a gate region connected to the gate region of the pass transistor and first and second regions coupled to the supply voltage connection. At least one of the first and second regions may be connected to the supply voltage connection via one of the one or more resistors. The gate region and the second region of the resistive transistor may be shorted. The first region of the bias transistor may be connected to the second region of the resistive transistor.

[0010] The adaptive bias circuit may include a current buffer. A gate region of the bias transistor may be connected to a power supply voltage connection, a first electrode of the first compensation capacitor, and a first region of the second OTA transistor via the current buffer. The current buffer may include a first transistor having a first region connected to (i) the power supply voltage connection, (ii) the first electrode of the first compensation capacitor, and (iii) the first region of the second OTA transistor, and a second region connected to the gate region of the bias transistor. The gate region of the first transistor of the current buffer may be connected to a gate region of a second transistor of the current buffer. The second region of the second transistor of the current buffer may be connected to a first electrode of a third compensation capacitor. The second electrode of the third compensation capacitor may be connected to the load voltage output connection. The regulator may include a tail transistor. The second region of each of the first and second OTA transistors may be connected to the first region of the tail transistor. The gate region of the tail transistor may be configured to receive a bias voltage.

[0011] The load voltage output connection may be connected to (i) a connection port for connecting the regulator to a load and (ii) a first electrode of the output capacitor. A second electrode of the output capacitor may be connected to a reference voltage, such as ground. The regulator may include a second current mirror. The second current mirror may be connected to the current buffer and the gate region of the bias transistor. The second current mirror may also be connected to the first electrode of the third compensation capacitor. The regulator may include a controlled current source configured to connect the power supply voltage connection to first regions of the first and second OTA transistors, the first electrode of the first compensation capacitor, and the gate region of the bias transistor. The controlled current source includes a first transistor having a first region coupled to the power supply voltage connection and a second region connected to the first region of the first OTA transistor, and a second transistor having a first region connected to the power supply voltage connection and a second region connected to the first electrode of the compensation capacitor, the first region of the second OTA transistor, and the gate region of the bias transistor. The gate region of the first transistor of the controlled current source may be connected to the gate region of the second transistor of the controlled current source.

[0012] In one aspect, an electrical circuit is provided that includes a load and a low-dropout regulator. The regulator is coupled to the load and configured to adjust a load voltage supplied to the load. The dropout regulator includes a voltage input connection for receiving a power supply voltage, a load voltage output circuit including a pass transistor having a first region, a second region, and a gate region, an adaptive bias circuit, and an adaptive compensation circuit. The second region of the pass transistor is coupled to the load. The pass transistor is configured to adjust the load voltage supplied to the load based on a voltage at the gate region of the pass transistor. The adaptive bias circuit includes a bias transistor configured to adjust a voltage supplied to a gate region of the pass transistor based on a voltage supplied to the gate region, and an operational transconductance amplifier (OTA) circuit including a first OTA transistor and a second OTA transistor. The gate region of the first OTA transistor is configured to receive a reference voltage, and the gate region of the second OTA transistor is configured to receive a voltage indicative of the load voltage. The adaptive compensation circuit includes (i) a first compensation capacitor having a first electrode and a second electrode, (ii) a second compensation capacitor having a first electrode and a second electrode, and (iii) a first compensation transistor, wherein the second electrode of the first compensation capacitor is connected to the first region of the compensation transistor and the first electrode of the second compensation capacitor is connected to both the second region of the compensation transistor and the gate region of the compensation transistor. The first region of the second OTA transistor is connected to (i) a power supply voltage connection, (ii) the first electrode of the first compensation capacitor, and (iii) the gate region of the bias transistor. The second electrode of the second compensation capacitor is connected to the first region of the bias transistor. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a circuit schematic diagram of an exemplary low-dropout regulator. [Figure 2] FIG. 1 is a schematic diagram illustrating the relationship between different components of an exemplary low-dropout regulator. [Figure 3]FIG. 1 is a circuit schematic diagram of an exemplary low-dropout regulator. DETAILED DESCRIPTION OF THE INVENTION

[0014] Some examples of the present disclosure will now be described, by way of example only, with reference to the drawings in which like reference numerals are used to refer to similar elements and in which:

[0015] <Summary> Disclosed herein is an example of a low-dropout regulator including an adaptive compensation circuit that provides a variable time constant for the regulator's operation. The adaptive compensation circuit includes first and second compensation capacitors separated by a first compensation resistor. A first region of the first compensation transistor is connected to the first compensation capacitor, and both the gate region and the second region of the first compensation transistor are connected to the second compensation capacitor. The disclosed regulator also includes a load voltage output control circuit for regulating a load voltage output from the regulator. An adaptive bias circuit is incorporated to control the operation of the voltage output control circuit. A sensing circuit operable to vary the time constant of the adaptive compensation circuit is also included.

[0016] The load voltage output control circuit includes a pass transistor that functions to vary the load voltage output from the regulator depending on the voltage at its gate region. The adaptive bias circuit includes a bias transistor that functions to vary the voltage at the gate region of the pass transistor depending on the voltage at its gate region. When a large voltage is applied to the gate region of the bias transistor, more current flows through the bias transistor and out of the pass transistor, causing the voltage at the gate region of the pass transistor to decrease. This causes more current to flow through the pass transistor, increasing the load voltage output from the regulator.

[0017] The adaptive bias circuit includes a voltage-controlled current source, such as a transconductance operational amplifier circuit. The voltage-controlled current source is configured to receive a load voltage and control a current through the voltage-controlled current source in dependence on the load voltage. As the load voltage increases, the current through the voltage-controlled current source also increases (and vice versa). Because the voltage-controlled current source is connected to the gate region of the bias transistor, the voltage at the gate region of the bias transistor depends on the current flowing through the voltage-controlled current source and therefore on the load voltage. As more current flows through the voltage-controlled current source (in response to an increase in the load voltage), the voltage applied to the gate region of the bias transistor decreases, which in turn decreases the voltage applied to the gate region of the pass transistor and therefore the load voltage output.

[0018] The sensing circuit is configured to control the flow of current through the adaptive compensation circuit. The sensing circuit includes a sense transistor having a gate region connected to a gate region of the pass transistor. Thus, the amount of current flowing through the sense transistor corresponds to the amount of current flowing through the pass transistor. The sensing circuit is configured to vary the current flowing through the adaptive compensation circuit in dependence on the current flowing through the sense transistor.

[0019] The adaptive compensation circuit is configured to couple with the adaptive bias circuit and the sensing circuit. A first compensation capacitor is coupled to the voltage controlled current source and the gate region of the bias transistor. A second compensation capacitor is coupled with the first region of the bias transistor. The second compensation capacitor and the second region and gate region of the first compensation transistor are coupled with the sensing circuit. Operation of the sensing circuit to control the current through the adaptive compensation circuit affects the current through the bias transistor, thereby varying the load voltage output from the regulator.

[0020] This configuration with an adaptive compensation circuit that provides the regulator with a variable time constant allows the regulator to achieve good phase margin over all operating conditions. Because the regulator is configured to provide proper output pole tracking using a load voltage output control circuit and an adaptive bias circuit, the adaptive compensation circuit with split capacitors achieves tracking of the associated zero without compromising the DC operation of the regulator. Thus, embodiments can provide a more stable low-dropout regulator.

[0021] <Specific explanation> An example of a low dropout regulator will now be described with reference to Figure 1. The function and operation of such a low dropout regulator will be described with reference to Figure 2, and additional and alternative features of such a low dropout regulator will be described later with reference to Figure 3.

[0022] 1 shows a low-dropout regulator 100. The regulator 100 includes an adaptive compensation circuit 130, which includes a first compensation capacitor 131, a second compensation capacitor 132, a first compensation transistor 133, a compensation resistor 134, and a second compensation transistor 135.

[0023] Regulator 100 includes a power supply voltage connection 101 for receiving a power supply voltage VDD. Regulator 100 also includes a load voltage output control circuit 110, which includes a load voltage output connection 112, a pass transistor 111, a third compensation capacitor 113, an output capacitor 114, and a load connection port 115. A load 116 is also shown in Figure 1. Regulator 100 also includes a first resistor 170.

[0024] The regulator 100 includes a sensing circuit 140 having a sense transistor 141, and a first current mirror 145. The first current mirror 145 includes a first mirroring transistor 146 and a first mirror transistor 147.

[0025] Regulator 100 includes an adaptive bias circuit. The adaptive bias circuit includes a voltage-controlled current source shown as an operational transconductance amplifier ("OTA") circuit 120. OTA circuit 120 includes first OTA transistor 121, second OTA transistor 122, and tail transistor 125. The adaptive bias circuit also includes bias transistor 150 and current buffer 160. Current buffer 160 includes first transistor 161 and second transistor 162. The adaptive bias circuit also includes second current mirror 180 including second mirroring transistor 181 and second mirror transistor 182. The adaptive bias circuit also includes controlled current source 190 including first transistor 191 and second transistor 192.

[0026] In regulator 100 of Figure 1, each transistor is a field effect transistor, such as a metal oxide semiconductor field effect transistor. All of the transistors in Figure 1 have a source connection (identified by an arrow) for connecting to the transistor's source region, a drain connection for connecting to the transistor's drain region, and a gate connection (between the source and drain connections) for connecting to the transistor's gate region. N-channel transistors in Figure 1 are shown with the source connection arrow pointing away from the gate region, and P-channel transistors in Figure 1 are shown with the source connection arrow pointing towards the gate region. Connections between conductors are indicated by filled circles.

[0027] In the circuit shown in FIG. 1, voltages are supplied to the circuit in three areas: a power supply voltage VDD, a reference voltage Vref, and a bias voltage VNbias. The power supply voltage VDD may be received from a DC power source such as a battery. The power supply voltage VDD is supplied to the circuit components via a power supply voltage connection 101, which is connected to the source regions of the first resistor 170, the first and second transistors 191 and 192 of the controlled current source 190, the second compensation transistor 135, the sense transistor 141, and the pass transistor 111. The gate connection of the first OTA transistor 121 is configured to receive the reference voltage. The gate connection of the tail transistor 125 is configured to receive the bias voltage.

[0028] The first OTA transistor 121 and the second OTA transistor 122 are N-channel transistors. The drain regions of the first and second OTA transistors are connected to the power supply voltage connection 101 via either of the controlled current source transistors 191 and 192. The source region of the first OTA transistor 121 is connected to the source region of the second OTA transistor 122. The connection between the source regions of the two OTA transistors is connected to the drain region of the tail transistor 125. The source region of the tail transistor 125 is connected to ground.

[0029] The first OTA transistor 121 is connected to the supply voltage connection 101 via the first transistor 191 of the controlled current source 190. The drain region of the first OTA transistor 121 is connected to the drain region of the first transistor 191 of the controlled current source 190. The first transistor 191 and the second transistor 192 of the controlled current source 190 are both P-channel transistors. The source region of the first transistor 191 of the controlled current source 190 is connected to the supply voltage connection 101, as is the source region of the second transistor 192 of the controlled current source 190. The gate region of the first transistor 191 of the controlled current source 190 is connected to the gate region of the second transistor 192 of the controlled current source 190. The second OTA transistor 122 is connected to the supply voltage connection 101 of the controlled current source 190 via the second transistor 192 of the controlled current source 190. The drain region of the second OTA transistor 122 is connected to the drain region of the second transistor 192 of the controlled current source 190.

[0030] The first transistor 191 of the controlled current source 190 is also connected to the current buffer 160. Specifically, the drain region of the first transistor 191 of the controlled current source 190 is connected to the source region of the second transistor 162 of the current buffer 160. The first transistor 161 and the second transistor 162 of the current buffer 160 are both P-channel transistors. The first transistor 191 of the controlled current source 190 is also connected to the first OTA transistor 121, so that the connection between the first OTA transistor 121 and the first transistor 191 of the controlled current source 190 is also connected to the second transistor 162 of the current buffer 160. In other words, there are two bifurcated conduction paths from the drain region of the first transistor 191 of the controlled current source 190: one path to the drain region of the first OTA transistor 121 and one path to the source region of the second transistor 162 of the current mirror.

[0031] The second transistor 192 of the controlled current source 190 is also connected to each of the current buffer 160, the compensation circuit 130, and the OTA circuit 120. Specifically, the drain region of the second transistor 192 of the controlled current source 190 is connected to the first electrode of the first compensation capacitor 131, to the source region of the first transistor 161 of the current buffer 160, and to the drain region of the second OTA transistor 122. In other words, there are conduction paths branching from the drain region of the second transistor 192 of the controlled current source 190 among a first path to the first electrode of the first compensation capacitor 131, a second path to the drain region of the second OTA transistor 122, and a third path to the source region of the first transistor 161 of the current buffer 160.

[0032] The first transistor 161 of the current buffer 160 is also connected to each of the bias transistor 150 and the second current mirror 180. Specifically, the drain region of the first transistor 161 of the current buffer 160 is connected to both the drain region of the second mirroring transistor 181 and the gate region of the bias transistor 150. The second mirroring transistor 181 and the second mirror transistor 182 are both N-channel transistors. The bias transistor 150 is an N-channel transistor.

[0033] The second transistor 162 of the current buffer 160 is also connected to each of the third compensation capacitor 113 and the second current mirror 180. Specifically, the drain region of the second transistor 162 of the current buffer 160 is connected to both the first electrode of the third compensation capacitor 113 and the drain region of the second mirror transistor 182 of the second current mirror 180. The gate and drain regions of the second mirror transistor 182 are shorted in the manner of a diode-connected transistor. The gate region of the second mirror transistor 182 and the gate region of the second mirroring transistor 181 are also interconnected. Thus, there are connections between the second transistor 162 of the current buffer 160, the third compensation capacitor 113, both the gate and drain regions of the second mirror transistor 182, and the gate region of the second mirroring transistor 181. The source regions of the second mirror transistor 182 and the second mirroring transistor 181 are each connected to ground.

[0034] The adaptive compensation circuit 130 is connected to the power supply voltage connection 101. Specifically, the source region of the second compensation transistor 135 is connected to the power supply voltage connection 101. The second compensation transistor 135 is a P-channel transistor with its gate region shorted to its drain region. The second electrode of the first compensation capacitor 131 is connected to the connection between the gate and drain regions of the second compensation transistor 135. The first compensation transistor 133 is a P-channel transistor. The drain and gate regions of the second compensation transistor 135 and the second electrode of the first compensation capacitor 131 are connected to the source region of the first compensation transistor 133. The gate and drain regions of the first compensation transistor 133 are connected to each other (e.g., diode-connected). The second region and gate region of the first compensation transistor 133 are also connected to the first electrode of the second compensation capacitor 132. Thus, the first and second compensation capacitors essentially represent a coupled compensation capacitor divided across the first compensation transistor 133.

[0035] The gate region and drain region of the first compensation transistor 133 are also connected to the drain region of the first mirroring transistor 146. The first mirroring transistor 146 and the first mirror transistor 147 of the first current mirror 145 are both N-channel transistors. The second electrode of the second compensation capacitor 132 is connected to the compensation resistor 134.

[0036] The bias transistor 150 is connected to the power supply voltage connection 101 via the first resistor 170. Specifically, the drain region of the bias transistor 150 is connected to each of the compensation resistor 134, the gate region of the sense transistor 141, the gate region of the pass transistor 111, and the first resistor 170. The pass transistor 111 and the sense transistor 141 are both P-channel transistors, and for example, the two may be identical (e.g., they may have the same width-to-length ratio). The power supply voltage connection 101 is connected to the gate region of the pass transistor 111 and the gate region of the sense transistor 141 via the first resistor 170. In other words, there is a conductive path from the power supply voltage connection 101 through the first resistor 170, which is divided into a path directed to each of the gate regions of the sense transistor 141 and the pass transistor 111, and a path directed to the drain region of the bias transistor 150 and the compensation resistor 134. The source region of the bias transistor 150 is connected to ground.

[0037] The source region of the sense transistor 141 is connected to the power supply voltage connection 101. The gate region of the sense transistor 141 is connected to the gate region of the pass transistor 111. The sense transistor 141 is connected to a first current mirror 145. The drain region of the sense transistor 141 is connected to the drain region and gate region of a first mirror transistor 147 of the first current mirror 145 (the gate region and drain region of the first mirror transistor 147 are diode-shorted). The gate region of the first mirror transistor 147 and the first mirroring transistor 146 are interconnected. The source regions of the first mirror transistor 147 and the first mirroring transistor 146 are connected to ground.

[0038] The source region of pass transistor 111 is connected to supply voltage connection 101. The drain region of pass transistor 111 is also connected to the load voltage output connection. Load voltage output connection 112 is connected to a second electrode of third compensation capacitor 113, a first electrode of output capacitor 114, and load 116. Output capacitor 114 is connected in parallel with load 116. Voltage output connection 112 is connected to load 116 via connection port 115. A second electrode of output capacitor 114 is connected to ground. In the example shown in FIG. 1, the second electrode of output capacitor 114 is connected to the output from load 116, with the connection therebetween connected to ground. Although not explicitly shown in FIG. 1, a connection is provided between the gate region of second OTA transistor 122 and load voltage output connection 112 so that second OTA transistor 122 receives the load voltage or an indication thereof.

[0039] The controlled current source 190 is configured to receive a power supply voltage VDD and provide a controlled current output. The transistors 191 and 192 of the controlled current source 190 are gate-connected to provide a consistent current output. The two transistors of the controlled current source 190 may be identical so that the current output from the drain region of each transistor is the same. The regulator 100 is configured to allow the current output from the first transistor 191 of the controlled current source 190 to flow to each of the first OTA transistor 121 and the second transistor 162 of the current buffer 160. The regulator 100 is configured to allow the current output from the second transistor 192 of the controlled current source 190 to flow to each of the first compensation capacitor 131, the second OTA transistor 122, and the first transistor 161 of the current buffer 160.

[0040] The reference voltage applied to first OTA transistor 121 may be constant, e.g., so that the amount of current drawn by first OTA transistor 121 remains constant. The first OTA resistor is configured to sink an amount of current through its drain region that is proportional to the reference voltage applied to its gate region. Similarly, the second OTA resistor is configured to sink an amount of current through its drain region that is proportional to the voltage applied to its gate region, i.e., proportional to the load voltage. The second OTA resistor is configured to sink more current through its gate region when the load voltage increases and to sink less current when the load voltage decreases. Thus, regulator 100 is configured so that the current flow between second transistor 192 of controlled current source 190, the first electrode of first compensation capacitor 131, and second transistor 162 of current buffer 160 varies depending on the load voltage. In particular, regulator 100 is configured such that the current flow from second transistor 192 of controlled current source 190 to the gate region of bias transistor 150 varies depending on the current flow through second OTA transistor 122 (and therefore depending on the load voltage). Tail transistor 125 may receive a constant bias voltage, for example, to provide a consistent current output (to ground).

[0041] Current buffer 160 is configured as a common-gate current buffer 160 (the gates of the two transistors of current buffer 160 are connected to each other). Current buffer 160 is configured to prevent components connected to the output of current buffer 160 (e.g., second current mirror 180, third compensation capacitor 113, and / or bias transistor 150) from interfering with the operation of components connected to the input to current buffer 160 (e.g., preventing the output from loading the input). Thus, current buffer 160 can be configured to prevent current flow to third compensation capacitor 113 / bias transistor 150 from interfering with current flow to first OTA transistor 121 / second OTA transistor 122.

[0042] The voltage at the gate region of bias transistor 150 depends on the amount of current drawn through second OTA transistor 122. In other words, regulator 100 is configured so that the voltage at the gate region of bias transistor 150 varies depending on the load voltage. For example, regulator 100 is configured so that when the load voltage increases, the voltage supplied to the gate region of bias transistor 150 decreases, and when the load voltage decreases, the voltage supplied to the gate region of bias transistor 150 increases.

[0043] The second current mirror 180 is configured such that the output current from the second mirroring transistor 181 (e.g., from its source region) corresponds to the output current from the second mirror transistor 182. For example, the two transistors of the second current mirror 180 may be identical (e.g., they may have the same width-to-length ratio). Therefore, the amount of current steered from the first transistor 161 of the current buffer 160 to the gate region of the bias transistor 150 also depends on the amount of current passing through the second mirror transistor 182, because the amount of current flowing from the first transistor 161 of the current buffer 160 to the second mirroring transistor 181 corresponds to the amount of current flowing through the second mirror transistor 182. The amount of current flowing through the second mirror transistor 182 also depends on the amount of current flowing to / from the first electrode of the third compensation capacitor 113.

[0044] The second compensating transistor 135 is configured to provide a unidirectional conductive path from the power supply voltage connection 101 to the source region of the first compensating transistor 133 and the second electrode of the first compensation capacitor 131. The adaptive compensation circuit 130 is configured such that the current supplied to the source region of the first compensating transistor 133 varies depending on the power supply voltage VDD and the charge on the first compensation capacitor 131. For example, if the first compensation capacitor 131 is charging, i.e., if its first electrode stores negative charge, the current flowing through the first compensating transistor 133 increases, and / or if the first compensation capacitor 131 is discharging, the current flowing through the first compensation transistor 133 decreases.

[0045] The first compensation transistor 133 is configured to provide a conductive path to each of the second compensation capacitor 132 and the first mirroring transistor 146 of the first current mirror 145. The second compensation capacitor 132 is configured to charge and discharge depending on the operating state of the mirroring transistor. If the current through the first mirroring transistor 146 increases, more current is drawn by the first mirroring transistor 146 than by the first electrode of the second compensation capacitor 132, causing the second compensation capacitor 132 to charge at a slower rate or begin to discharge at a faster rate. If the current flow through the first mirroring transistor 146 decreases, the first electrode of the second compensation capacitor 132 will accumulate more charge or lose charge at a slower rate. The magnitude and direction of the current through the compensation resistor 134 depend on the state of the second compensation capacitor 132 and, therefore, the operating state of the first mirroring transistor 146.

[0046] Compensation circuit 130 is configured to provide split capacitors such that the split capacitors effectively act in series without affecting the DC operating conditions of regulator 100. Compensation circuit 130 is configured to compensate an output pole (wp2) of the regulator transfer function with a zero (wz2) of the regulator transfer function. Compensation circuit 130 may be configured to provide a variable time constant.

[0047] The first resistor 170 is configured to provide a voltage drop between the power supply voltage VDD and the voltage supplied to the gate regions of the sense transistor 141 and the pass transistor 111, respectively.

[0048] The sensing circuit 140 is configured to regulate the flow of current away from the first plate of the first compensation transistor 133 and the second compensation capacitor 132 via the first current mirror 145. The sense transistor 141 is configured to control the flow of current from the supply voltage connection 101 through the first current mirror 145 based on the voltage applied to its gate region. The sense transistor 141 is configured so that when the voltage applied to the gate region of the sense transistor 141 increases, the current flows through the sense transistor 141 to the first current mirror 145 less, and when the voltage applied to its gate region decreases, the current flows through the sense transistor 141 to the first current mirror 145 more. The sense transistor 141 receives the supply voltage VDD (e.g., at its source connection) and is configured to selectively throughput current based on the voltage on its gate region. The sense transistor 141 provides a selective conduction path between the supply voltage connection 101 and the first current mirror 145.

[0049] First current mirror 145 is configured so that the current flow from first mirroring transistor 146 corresponds to the current flow from first mirror transistor 147. First mirroring transistor 146 may be identical to first mirror transistor 147 (e.g., have the same width-to-length ratio), and the current flow from each may be identical. First mirror transistor 147 is diode-shorted, so that the current passing through first current mirror 145 from sense transistor 141 passes through first mirror transistor 147 to ground. A corresponding (or identical, if the two transistors are identical) current then flows out through first mirroring transistor 146. The current through first mirroring transistor 146 is configured to mirror the current from sense transistor 141; for example, if the current through sense transistor 141 increases, the current through first mirroring transistor 146 also increases. The first mirroring transistor 146 is configured to draw this current from the first compensation transistor 133; for example, as the current flowing through the sense transistor 141 increases, more current is drawn from the drain region of the first compensation transistor 133 (optionally also from the first electrode of the second compensation capacitor 132, or alternatively, less current may be supplied from the first compensation transistor 133 to the first electrode of the second compensation capacitor 132).

[0050] Regulator 100 is configured such that the current flow away from the first plate of first compensation transistor 133 and second compensation capacitor 132 depends on the voltage applied to the gate region of sense transistor 141. The voltage applied to the gate region of sense transistor 141 corresponds to (e.g., may be the same as) the voltage applied to the gate region of pass transistor 111. Regulator 100 is configured such that the voltages applied to these gate regions depend on the operating state of adaptive compensation circuit 130 and the operating state of bias transistor 150. Current can flow toward or away from the connection to adaptive compensation circuit 130. The magnitude and direction of this current flow varies depending on the state of second compensation capacitor 132 (e.g., whether it is charging, being charged, or discharging), which can vary depending on the magnitude of the current through first mirroring transistor 146.

[0051] The amount of current flowing through bias transistor 150 varies depending on the voltage applied to its gate region. Regulator 100 is configured so that the outputs from both the sense transistor and the pass transistor vary depending on the voltage applied to the gate region of bias transistor 150. The voltage applied to the gate region of bias transistor 150 varies depending on the operation (amount of current drawn) of second OTA transistor 122, which in turn varies depending on the load voltage. Thus, regulator 100 is configured to adjust the output of pass transistor 111 (and thus the load voltage) based on the load voltage. For example, regulator 100 is configured so that when the load voltage increases or begins to increase, this increase causes pass transistor 111 to conduct less current, thereby decreasing (or preventing) the load voltage. Similarly, when the load voltage decreases or begins to decrease, this decrease causes pass transistor 111 to conduct more current, thereby increasing (or preventing) the load voltage.

[0052] Pass transistor 111 provides a selective conduction path between supply voltage connection 101 and load voltage output connection 112. Conduction through this path from supply voltage connection 101 to load voltage output connection 112 varies depending on the voltage on the gate region of pass transistor 111 (and thus depending on the operating state of bias transistor 150 and / or adaptive compensation circuit 130). As the voltage on the gate region of pass transistor 111 increases, pass transistor 111 conducts less current, and as the voltage on the gate region decreases, pass transistor 111 conducts more current.

[0053] The load connection port 115 is configured to provide a connection for the load 116. In some examples, the load 116 may be included as part of the regulator circuit, in which case the load connection port 115 may effectively comprise a conductor connected to an input for the load 116. In other examples, the load 116 may be a separate component to the regulator circuit, in which case the connection port 115 may comprise an electrical connection that allows the load 116 to be connected to the regulator 100 and receive a load voltage therefrom. The load connection port 115 is configured to supply a load voltage to the load 116. The load voltage output control circuit 110 is configured to supply a regulated load voltage to the load 116. The charge on the second electrode of the third compensation capacitor 113 (and therefore the current flow to / from the second electrode) varies depending on the charge supplied to the first electrode of the third compensation capacitor 113.

[0054] It will be understood that, in the context of the present disclosure, the characteristics of regulator 100 may be selected to provide a selected value for the load voltage. For example, the transistors, resistors, and / or capacitors of the circuit may be selected to provide related operating characteristics that provide an intended value for the load voltage. The capacitance value of one or more of the capacitors may be selected based on the pole compensation for which that capacitor is intended. For example, the capacitance values ​​of each of first and second compensation capacitors 113 and third compensation capacitor 113 (and the resistance value of compensation resistor 134) may be selected to provide stability for regulator 100 over a range of load currents.

[0055] The functionality of the exemplary regulator 100 will now be described with reference to FIG.

[0056] Figure 2 is a block diagram illustrating the functional relationships between different components of regulator 100. For each component in the diagram shown in Figure 2, an arrow pointing out (e.g., away from) a component indicates an output. An arrow pointing into a component indicates an input, e.g., indicating that the output of the component to which the arrow is directed may be affected by this input.

[0057] FIG. 2 shows an adaptive bias circuit (“ABC”—e.g., provided by the OTA circuit 120, bias transistor 150, current buffer 160, second current mirror 180, and controlled current source 190 of regulator 100 of FIG. 1), an adaptive compensation circuit (“ACC”—e.g., provided by the compensation circuit 130 of regulator 100 of FIG. 1), a load voltage output control circuit (“LVOCC”—e.g., provided by the output control circuit 110 and first resistor 170 of regulator 100 of FIG. 1), and a sensing circuit (“SC”—e.g., provided by the sensing circuit 140 and first resistor 170 of regulator 100 of FIG. 1).

[0058] Although not shown in FIG. 2, the components shown in FIG. 2 are supplied with a power supply voltage VDD (e.g., as supplied by power supply voltage connection 101 of regulator 100 of FIG. 1). Power supply voltage VDD may be supplied to each of ABC, ACC, LVOCC, and SC. The operation of each of these components depends, at least in part, on the power supply voltage. Furthermore, it will be understood that the operation of each of these components also depends on the operation of the other components of regulator 100.

[0059] The ABC (particularly the OTA circuit 120) also receives the load voltage as an input. The output from the OTA circuit (the current through the second OTA transistor 122) depends on the load voltage it receives, and therefore the operation of the ABC depends on the load voltage. This operation of the ABC affects the current flow to / from the first compensation capacitor 131 of the ACC (as shown by the arrow in FIG. 2). Furthermore, the current through the second OTA transistor 122 of the ABC affects the voltage applied to the gate region of the bias transistor 150 of the ABC. The voltage applied to the gate region of the bias transistor 150 affects the current flow to / from the compensation resistor 134 (as shown by the arrow in FIG. 2). The voltage applied to the gate region of the bias transistor 150 also affects the operation of the SC and LVOCC (as shown by the two arrows in FIG. 2). This is because the voltage applied to the gate region of the bias transistor 150 affects the voltage applied to the gate region of the sense transistor 141 of the SC 140 and the voltage applied to the gate region of the pass transistor 111 of the LVOCC 110.

[0060] In particular, as the load voltage increases, ABC's second OTA transistor 122 consumes more current, diverting less current to first compensation capacitor 131 and decreasing the gate voltage of bias transistor 150. As a result, less current flows through bias transistor 150, increasing the voltages applied to the gate regions of sense transistor 141 and pass transistor 111.

[0061] The operation of the SC affects the operation of the ACC. In particular, the SC affects the magnitude of current flow away from the first compensation transistor 133 and the second compensation capacitor 132 (as shown by the arrows in FIG. 2). As more current passes through the sense transistor 141 of the SC (e.g., as the gate voltage of the sense transistor 141 decreases), the SC causes more current to flow out of the first compensation transistor 133 and the second compensation capacitor 132. As a result, the current flow to / from the second electrode of the second compensation capacitor 132 through the compensation resistor 134 (and thus the voltages supplied to the gate regions of the sense transistor 141 and the pass transistor 111) changes. In this way, the operation of the SC affects the operation of the LVOCC (as shown by the arrows in FIG. 2).

[0062] Thus, the operation of SC affects the current flow away from the drain region of the first compensation transistor 133. The operation of ABC affects the current flow to / from the first compensation capacitor 131 and the compensation resistor 134. Based on these inputs to ACC, the charge stored in the two capacitors varies. Because the two capacitors behave as if they were connected in series, the total capacitance associated with ACC is the capacitance of the two capacitors connected in series. The first compensation transistor 133 operates to provide a variable resistance depending on the operation of the second compensation capacitor 132. The voltage associated with ACC affects the voltages applied to the gate regions of the sense transistor 141 and the pass transistor 111, respectively.

[0063] To further explain the functionality of regulator 100, several examples of its operation will be described with reference to Figure 1. It should be understood that, in the context of the present disclosure, low dropout regulator 100 is self-regulating. While the following operational examples are described as a series of events, it will be understood that, in reality, these events occur simultaneously as regulator 100 self-regulates.

[0064] Regulator 100 is configured to provide a consistent voltage output. Accordingly, examples will be described of how regulator 100 reacts in response to increases and decreases in the load voltage output. These examples refer to changes in VDD that cause an increase / decrease in the output voltage. It will be understood that there are multiple connections to power supply voltage connection 101. Therefore, an increase or decrease in power supply voltage VDD will affect many different components simultaneously. However, for simplicity, the following description will describe events as occurring sequentially, as this should help explain how self-regulation occurs. It will also be understood that there are other causes for an increase / decrease in the output voltage, such as depending on the load current drawn by the load.

[0065] As the power supply voltage VDD increases, the voltage supplied to the source regions of the pass transistor 111 and the sense transistor 141 also increases. The voltage supplied to the first resistor 170 also increases, and the corresponding voltage drop across the first resistor 170 also increases. As a result, the increase in the voltage at the source regions of the sense transistor 141 and the pass transistor 111 becomes greater than the voltage at the gate regions of the sense transistor 141 and the pass transistor 111. Therefore, the gate-to-source voltages of the pass transistor 111 and the sense transistor 141 increase negatively, and the output from each transistor increases. This increases the load voltage, causing the gate voltage of the second OTA transistor 122 to increase. This increases the current flowing through the second OTA transistor 122, causing the voltage at the gate region of the bias transistor 150 to decrease. Now, because less current flows through the bias transistor 150, the voltage at the gate regions of the pass transistor 111 and the sense transistor 141 increases relative to their source voltages, thereby decreasing the load voltage (e.g., returning to its intended value).

[0066] It will be appreciated that during this adjustment, the sensing circuit 140 (including the first current mirror 145), the second current mirror 180, and the adaptive compensation circuit 130 may also act to compensate the operation of the regulator 100. The output from the sense transistor 141 corresponds to the output from the pass transistor 111. As such, the first current mirror 145 outputs a larger current, thus drawing more current away from the drain region of the first compensation transistor 133 and the first electrode of the second compensation capacitor 132. This may cause the second compensation capacitor 132 to discharge, affecting the voltages supplied to the gate regions of the sense transistor 141 and the pass transistor 111. In response to the larger V, the second compensation transistor 135 and / or the first compensation capacitor 131 may operate to provide a larger input to the first compensation transistor 133. The operation of the third compensation capacitor 113 may also affect the current flow through the second mirror transistor 182. This in turn affects the current flow through the second mirroring transistor 181 and thus the voltage on the gate region of the bias transistor 150 .

[0067] If the power supply voltage VDD decreases, the opposite occurs: the load voltage may decrease, resulting in a decrease in the current through the second OTA transistor 122. This increases the voltage at the gate region of the bias transistor 150, causing more current to flow through the bias transistor 150. This in turn decreases the gate voltages of the sense and pass transistors relative to their source voltages, resulting in an increase in the load voltage.

[0068] Embodiments may provide an improved low-dropout regulator. In particular, embodiments may provide a low-dropout regulator with improved stability (e.g., better phase margin over all operating conditions). This may be evident by reference to the poles and zeros of the regulator. In particular, the output pole (wp2) may be compensated with a zero (wz2). For example, the equations for wp2 and wz2 may be derived as follows:

[0069]

number

[0070] While gmL varies with load current in the wp2 equation above and gmMPC varies with load in the wz2 equation, all other parameters remain constant with load current in both equations. Thus, by controlling CC2, (CC1_1||CC1_2), and RC, as in regulator 100 described above, regulator 100 can be stable over the entire load current range. Splitting the compensation capacitors (CC1_1 and CC1_2) to achieve this improves stability while leaving the DC operating conditions of regulator 100 unaffected. Including current buffer 160 can suppress the presence of a feedforward path and convert zeros from right-half plane zeros to left-half plane zeros (e.g., to facilitate pole cancellation). Additionally or alternatively, including first compensation transistor 133 may facilitate this conversion of zeros to left-half plane zeros.

[0071] Additional and / or alternative features of the low dropout regulator will now be described with reference to FIG.

[0072] The configuration of Figure 3 is similar to the configuration of Figure 1, like numbers indicate like elements, and these like elements will not be described again. Instead, the following description will focus on features of the configuration of Figure 3 that differ from regulator 100 of Figure 1.

[0073] FIG. 3 shows regulator 300. In addition to the components described above for regulator 100 of FIG. 1, regulator 300 of FIG. 3 includes a resistor assembly 370 having drain resistor 371, source resistor 372, and resistor transistor 373. Regulator 300 of FIG. 3, which differs from regulator 100 of FIG. 1, also includes a second current mirror assembly 380 and a load voltage output control circuit 310. Current mirror assembly 380 includes a first transistor 381, a second transistor 382, ​​a third transistor 383, and a fourth transistor 384. The output control circuit includes a first output resistor 3171, a second output resistor 3172, a third output resistor 3181, a first output transistor 3182, a current source 3191, and a second output transistor 3192.

[0074] Resistor assembly 370 replaces first resistor 170 from regulator 100 of FIG. 1 . Resistor transistor 373 is connected to each of power supply voltage connection 301, sense transistor 341, pass transistor 311, adaptive compensation circuit 330, and bias transistor 350. Resistor transistor 373 is a P-channel transistor. The gate region of resistor transistor 373 is connected to the gate region of sense transistor 341 and the gate region of pass transistor 311. The source region of resistor transistor 373 is connected to power supply voltage connection 301. The drain region of resistor transistor 373 is connected to compensation resistor 334 (and therefore the second electrode of second compensation capacitor 332) and the drain region of bias transistor 350. The drain region of resistor transistor 373 is also connected to power supply voltage connection 301. The source region of resistive transistor 373 is connected to supply voltage connection 301 via source resistor 372, and the drain region of resistive transistor 373 is connected to supply voltage connection 301 via drain resistor 371. The drain and gate regions of resistive transistor 373 are connected together (providing a diode shorted transistor).

[0075] The gate region of pass transistor 311 and the gate region of sense transistor 341 are both connected to the power supply voltage input connection 301 via resistive transistor 373. Specifically, the gate regions of each of sense transistor 341 and pass transistor 311 are connected to both the gate and drain regions of resistive transistor 373, and the source and drain regions of resistive transistor 373 are connected to the power supply voltage connection. The drain region of bias transistor 350 and compensation resistor 334 are both connected to both the gate and drain regions of resistive transistor 373 (and thus to the respective gate regions of sense transistor 341 and pass transistor 311).

[0076] The second current mirror assembly 380 is configured with two more transistors than those used in the second current mirror 180 of the regulator 100 of FIG. 1 . All of the transistors in the second current mirror assembly 380 are N-channel transistors. The second current mirror assembly 380 is connected to the current buffer 360, the bias transistor 350, and the third compensation capacitor 313. Specifically, the drain region of the first transistor 381 of the second current mirror assembly 380 is connected to the drain region of the second transistor 362 of the current buffer 360 and the first electrode of the third compensation capacitor 313. The drain region of the second transistor 382 of the second current mirror assembly 380 is connected to the drain region of the first transistor 361 of the current buffer 360 and the gate region of the bias transistor 350. The drain region of the second transistor 382 of the second current mirror assembly 380 may also be connected to the gate region of the second output transistor 3192 (as shown in FIG. 3 ).

[0077] The gate region of the first transistor 381 of the second current mirror assembly 380 is connected to the gate region of the second transistor 382 of the second current mirror assembly 380. The source region of the first transistor 381 of the second current mirror assembly 380 is connected to the drain region of the third transistor 383 of the second current mirror assembly 380. The source region of the second transistor 382 of the second current mirror assembly 380 is connected to the drain region of the fourth transistor 384 of the second current mirror assembly 380. The gate region of the third transistor 383 of the second current mirror assembly 380 is connected to the gate region of the fourth transistor 384 of the second current mirror assembly 380. The gate regions of the first and second transistors 381, 382 of the second current mirror assembly 380 are both connected to the drain region of the first transistor 381 of the second current mirror assembly 380. The drain region of the first transistor 381 of the second current mirror assembly 380 may also be connected to the respective gate regions of both the third and fourth transistors 383, 384 of the second current mirror assembly 380 (e.g., the gate regions of all four transistors of the second current mirror assembly 380 may be interconnected).

[0078] The load voltage output connection 312 is connected to a load 316 (via a connection port 315) arranged in parallel with each other, and to an output capacitor 314. The load voltage output connection 312 is also connected to other components of the voltage output control circuit 310. For example, the load voltage output connection is connected to a first output resistor 3171 and to a second output resistor 3172 via the first output resistor 3171. The load voltage output connection is connected to a third output resistor 3181 and to a first output transistor 3182 via the third output resistor 3181. The load voltage output connection is also connected to a current source 3191 and to a second output transistor 3192 via the current source 3191. The first and second output transistors 3182, 3192 are each an N-channel transistor. The load voltage output connection is connected to the drain region of the first output transistor 3182 via the third resistor 3181. The drain region of the second output transistor 3192 is connected to the load voltage output connection via the current source 3191 and is also connected to the gate region of the first output transistor 3182. The source regions of each output transistor are connected to ground.

[0079] 3, the load voltage output connection 312 is connected to the gate region of the second OTA transistor 322. Specifically, a connection is provided between the first output resistor 3171 and the second output resistor 3171 to the gate region of the second OTA transistor 322. The output control circuit 310 may be configured to adjust the voltage supplied to the second OTA transistor 322 by providing a voltage divider such that the voltage supplied to the second OTA transistor 322 is reduced relative to the load voltage. The amount of scaling (e.g., reduction) provided to the load voltage may be selected to control the maximum amount of variation in the operating conditions of the regulator 300, for example, to limit the maximum amount of change in voltage at the gate region of the pass transistor 311. For example, the values ​​of the first and second output resistors 3171 and 3172 may be selected appropriately.

[0080] In the context of this disclosure, it should be understood that the embodiments described herein are examples of low-dropout regulators of the present disclosure. However, these examples are not intended to be limiting. For example, it will be understood that the particular configuration of transistors (and their respective channel configurations) need not be considered limiting. For example, different configurations of N / P-channel transistors may be used and / or different transistors (e.g., non-FETs) may be used to provide the desired functionality. Similarly, the capacitors are shown with windings to indicate their stack-up on the circuit board (e.g., windings are on the bottom layer). However, other configurations may be used for these capacitors. In some examples, the sensing circuit 140 and the feedback it enables may instead be provided by the pass transistor 111 and the output control circuit 110. Alternatively, if a load voltage is used to regulate the second OTA transistor 122, this may instead be an indication of the load voltage, such as from the output of the sense transistor 141.

[0081] In the examples described herein, resistors have been illustrated and discussed. However, it will be understood that, in the context of the present disclosure, one or more of these resistors may have an effective resistance of zero. For example, in FIG. 3 , first resistor 3171 and second resistor 3172 may act to scale the voltage supplied to the gate region of second OTA transistor 322. However, one or more of these resistors may not provide a voltage drop (e.g., to control scaling or to provide unity scaling). Similarly, one or both of drain resistor 371 and source resistor 372 may have no resistance.

[0082] From the above discussion, it will be understood that the embodiments shown in the figures are merely exemplary and include features that may be generalized, eliminated, or substituted as described and claimed herein. Referring generally to the figures, it will be understood that schematic functional block diagrams are used to illustrate the functionality of the systems and devices described herein. However, it will be understood that functionality need not be so divided, and should not be taken to imply any particular structure of hardware other than that described and claimed below. The functionality of one or more elements shown in the figures may be further subdivided and / or distributed throughout the devices of the present disclosure. In some instances, the functionality of one or more elements shown in the figures may be combined into a single functional unit.

[0083] As will be understood by those skilled in the art in the context of this disclosure, each of the embodiments described herein can be implemented in a variety of different ways. Any feature of any aspect of the present disclosure may be combined with any of the other aspects of the present disclosure. For example, method aspects may be combined with apparatus aspects, and features described with reference to the operation of particular elements of apparatus may be provided in methods that do not use those particular types of apparatus. Furthermore, each feature of each embodiment is intended to be separable from the features with which it is described, unless other features are explicitly stated to be essential to its operation. Each of these separable features may, of course, be combined with any other features of the embodiment in which it is described, or with any other features or combinations of features of other embodiments described herein. Furthermore, equivalents and modifications not described above may be employed without departing from the invention.

[0084] Other embodiments and modifications of the present disclosure will be apparent to those skilled in the art in light of the present disclosure.

Claims

1. a supply voltage connection for receiving a supply voltage; a load voltage output connection for supplying a load voltage to a load; a load voltage output control circuit comprising a pass transistor configured to adjust the load voltage based on a voltage at its gate region; an adaptive bias circuit; an adaptive compensation circuit; Equipped with The adaptive bias circuit comprises: a bias transistor configured to adjust the voltage supplied to the gate region of the pass transistor based on a voltage supplied to the gate region; an operational transconductance amplifier (OTA) circuit including a first OTA transistor and a second OTA transistor; Equipped with a gate region of the first OTA transistor configured to receive a reference voltage and a gate region of the second OTA transistor configured to receive a voltage indicative of the load voltage; the adaptive compensation circuit comprises: (i) a first compensation capacitor having a first electrode and a second electrode; (ii) a second compensation capacitor having a first electrode and a second electrode; and (iii) a first compensation transistor, wherein the second electrode of the first compensation capacitor is connected to a first region of the first compensation transistor and the first electrode of the second compensation capacitor is connected to both a second region and a gate region of the first compensation transistor; a first region of the second OTA transistor connected to (i) the power supply voltage connection, (ii) the first electrode of the first compensation capacitor, and (iii) the gate region of the bias transistor; the second electrode of the second compensation capacitor is connected to a first region of the bias transistor; Low dropout regulator.

2. 2. The low dropout regulator of claim 1, a first region of the pass transistor connected to the supply voltage connection and a second region of the pass transistor connected to the load voltage output connection; Low dropout regulator.

3. 3. The low dropout regulator of claim 2, further comprising a sensing circuit; the sensing circuit comprises a sense transistor having a gate region connected to the gate region of the pass transistor and a first region connected to the power supply voltage connection; Low dropout regulator.

4. 4. The low dropout regulator of claim 3, the sensing circuit includes a first current mirror coupled to both the sense transistor and the adaptive compensation circuit; Low dropout regulator.

5. 5. The low dropout regulator of claim 4, the first current mirror includes: (i) the first electrode of the second compensation capacitor; (ii) the gate region of the first compensation transistor; and (iii) a first mirroring transistor having a first region connected to the second region of the first compensation transistor. Low dropout regulator.

6. 6. The low dropout regulator of claim 5, the first current mirror comprises a first mirror transistor; the second region of the sense transistor is connected to (i) the first region of the first mirror transistor, (ii) a gate region of the first mirror transistor, and (iii) a gate region of the first mirroring transistor; Low dropout regulator.

7. 7. The low dropout regulator according to claim 1, the adaptive compensation circuit comprises a second compensation transistor; the first region of the first compensation transistor is connected to the power supply voltage connection via the second compensation transistor; Low dropout regulator.

8. 8. The low dropout regulator of claim 7, a first region of the second compensation transistor connected to the power supply voltage connection, and a second region and a gate region of the second compensation transistor shorted together and connected to both the second electrode of the first compensation capacitor and the first region of the first compensation transistor; Low dropout regulator.

9. 9. The low dropout regulator according to claim 1, the adaptive compensation circuit further comprises a compensation resistor disposed between the second electrode of the second compensation capacitor and the first region of the bias transistor. Low dropout regulator.

10. 10. The low dropout regulator according to claim 1, the gate region of the pass transistor is connected to the power supply voltage connection via one or more resistors; Low dropout regulator.

11. 11. The low dropout regulator of claim 10, the first region of the bias transistor is connected to the power supply voltage connection via the one or more resistors; Low dropout regulator.

12. 12. The low dropout regulator according to claim 10 or 11, a resistive transistor having a gate region connected to the gate region of the pass transistor and first and second regions connected to the power supply voltage connection; at least one of the first and second regions is connected to the power supply voltage connection via one of the one or more resistors; Low dropout regulator.

13. 13. The low dropout regulator of claim 12, the gate region and the second region of the resistive transistor are shorted; Low dropout regulator.

14. 14. The low dropout regulator of claim 12 or 13, the first region of the bias transistor is connected to the second region of the resistor transistor; Low dropout regulator.

15. 15. The low dropout regulator of claim 1, the adaptive bias circuit comprises a current buffer; the gate region of the bias transistor is connected to the power supply voltage connection, the first electrode of the first compensation capacitor, and the first region of the second OTA transistor via the current buffer; Low dropout regulator.

16. 16. The low dropout regulator of claim 15, the current buffer comprises: (i) the power supply voltage connection; (ii) the first electrode of the first compensation capacitor; and (iii) a first transistor having a first region coupled to the first region of the second OTA transistor and a second region coupled to the gate region of the bias transistor. Low dropout regulator.

17. 17. The low dropout regulator of claim 16, the current buffer comprises a second transistor having a first region coupled to both the power supply voltage connection and a first region of the first OTA transistor; Low dropout regulator.

18. 18. The low dropout regulator of claim 17, a gate region of the first transistor of the current buffer is connected to a gate region of the second transistor of the current buffer; Low dropout regulator.

19. 19. The low dropout regulator of claim 17 or 18, a second region of the second transistor of the current buffer is connected to a first electrode of a third compensation capacitor, a second electrode of the third compensation capacitor being connected to the load voltage output connection; Low dropout regulator.

20. 20. The low dropout regulator of claim 1, the load voltage output connection is connected to (i) a connection port for connecting the low dropout regulator to the load, and (ii) a first electrode of an output capacitor; Low dropout regulator.

21. 20. The low dropout regulator of claim 15, a second current mirror; the second current mirror is connected to the current buffer and the gate region of the bias transistor; Low dropout regulator.

22. 22. A low dropout regulator according to claim 21 when dependent on claim 19, the second current mirror is also connected to the first electrode of the third compensation capacitor; Low dropout regulator.

23. 23. The low dropout regulator of claim 1, a controlled current source configured to connect the power supply voltage connection to the first regions of the first and second OTA transistors, the first electrode of the first compensation capacitor, and the gate region of the bias transistor; Low dropout regulator.

24. 24. The low dropout regulator of claim 23, The controlled current source a first transistor having a first region connected to the power supply voltage connection and a second region connected to the first region of the first OTA transistor; a second transistor having a first region connected to the power supply voltage connection and a second region connected to the first electrode of the first compensation capacitor, the first region of the second OTA transistor, and the gate region of the bias transistor; Equipped with a gate region of the first transistor of the controlled current source is connected to a gate region of the second transistor of the controlled current source; Low dropout regulator.

25. a load; and a low dropout regulator; the low-dropout regulator is coupled to the load and configured to regulate a load voltage supplied to the load; The low dropout regulator a voltage input connection for receiving a power supply voltage; a load voltage output circuit including a pass transistor having a first region, a second region, and a gate region; an adaptive bias circuit; an adaptive compensation circuit; Equipped with the second region of the pass transistor is connected to the load; the pass transistor is configured to adjust the load voltage supplied to the load based on a voltage at the gate region of the pass transistor; The adaptive bias circuit comprises: a bias transistor configured to adjust the voltage supplied to the gate region of the pass transistor based on a voltage supplied to the gate region; an operational transconductance amplifier (OTA) circuit including a first OTA transistor and a second OTA transistor; Equipped with a gate region of the first OTA transistor configured to receive a reference voltage and a gate region of the second OTA transistor configured to receive a voltage indicative of the load voltage; the adaptive compensation circuit comprises: (i) a first compensation capacitor having a first electrode and a second electrode; (ii) a second compensation capacitor having a first electrode and a second electrode; and (iii) a compensation transistor, wherein the second electrode of the first compensation capacitor is connected to a first region of the compensation transistor and the first electrode of the second compensation capacitor is connected to both a second region of the compensation transistor and a gate region of the compensation transistor; a first region of the second OTA transistor connected to (i) the power supply voltage connection, (ii) the first electrode of the first compensation capacitor, and (iii) the gate region of the bias transistor; the second electrode of the second compensation capacitor is connected to a first region of the bias transistor; Electrical circuit.

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