Matrix array detector having multiple groups of driver modules and method for implementing the same

Abstract

To provide a matrix array detector capable of reading out consecutive pixel rows or reading out a group of a plurality of pixel rows, and a usage method thereof.SOLUTION: A pixel array is matrixed along the rows and columns to generate a signal. Row conductors L(i), L(i+1), L(i+2), and L(i+3) each drive one row of pixels. Each driver module (SR_A) of a first group (A) sends a selection signal (Out_A) to one of the row conductors of the first group. Each driver module (SR_B) of a second group (B) sends a selection signal (Out_B) to one of the row conductors of the second group. The row conductors of the first and second groups are interlaced.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a matrix array detector and a method for implementing the same. The invention is useful in generating visible images, but is not limited to this technical field. For example, it is possible to generate pressure or temperature maps or two-dimensional representations of chemical or electrical potentials. These maps or representations form images of physical quantities. The invention applies in particular to active matrix array detectors used for detection purposes in imaging devices, for example TFT plates employing ionizing radiation (e.g. X-rays) (here TFT stands for "thin film transistor"). [Background technology]

[0002] In a matrix array detector, a pixel represents the basic sensitive element of the detector. Each pixel converts the physical influence it experiences into an electrical signal. The electrical signals from the various pixels are collected in a matrix array readout stage and then digitized so that they can be processed and stored to form an image. A pixel is formed by an area that is sensitive to a physical influence and emits, for example, a current of charge. The physical influence can be electromagnetic radiation that emits a flow of photons; consequently, the invention will be described using this type of radiation, with the charge current depending on the flow of photons received by the sensitive area. Generalization to any matrix array detector is straightforward.

[0003] A matrix array image detector includes row conductors, each connecting pixels in the same row, and column conductors, each connecting pixels in the same column, connected to converter circuits typically located at the ends of the matrix array (sometimes called "column legs").

[0004] Each pixel typically contains a photosensitive element (or photodetector), which may be, for example, a photodiode, photoresistor, or phototransistor. There are photosensitive matrix arrays of large size, which may have millions of pixels arranged in rows and columns. Each pixel further comprises an electronic circuit, consisting for example of switches, capacitors, and resistors, downstream of which there is an actuator. The assembly of photosensitive element and electronic circuit allows an electric charge to be generated and collected. The electronic circuit usually allows the electric charge collected in each pixel to be reset after the charge transfer. The role of the actuator is to transfer or copy the electric charge collected by the circuit into the column conductor. This transfer occurs when the actuator receives a command to do so from the row conductor. The output of the actuator corresponds to the output of the pixel. The terms "row conductor" and "column conductor" are entirely arbitrary; it is of course possible to switch between these terms.

[0005] In this type of detector, the pixel operates in two stages: an image capture stage in which the pixel's electronics accumulates the charge generated by the photosensitive element, and a readout stage in which the collected charge is transferred or replicated into the column conductors by an actuator.

[0006] During the readout phase, a readout command is sent by the row conductors to all of the actuators in the same row of the matrix array, and each pixel in this row is readout by transferring its electrical information (e.g. charge, voltage, current, frequency, etc.) to the associated column conductor.

[0007] For one image frame, rows of pixels may be selected sequentially, one after the other, in the direction of scanning the columns of the matrix array over a row selection time corresponding to a portion of the frame period, allowing appropriate signals (e.g., voltages) to be applied to the pixels in that row. Selecting a row thus corresponds to applying a high-level signal during the corresponding row selection time that controls the on-state of the switching devices of the corresponding row of pixels. Outside of the row selection time, the switching devices are maintained in an off-state by applying a suitable low-level signal. For example, if the switching devices are transistors and the applied signal is a voltage, it is conventional to use VGon to represent a voltage corresponding to a high level (and thus the on-state of the switching transistors) and VGoff to represent a voltage corresponding to a low level (and thus the off-state of the switching transistors).

[0008] The rows may be controlled by a control circuit comprising one or more shift registers in series, each of which comprises a plurality of cascade stages, each suitable for switching between high and low levels of signals applied to the actuators of the pixels of a corresponding row of the matrix array according to a series of row selection operations (e.g., vertical scanning). The control circuit may be implemented in an integrated circuit, and the same integrated circuit may comprise multiple control circuits, for example, for multiple rows in the matrix array. The integrated circuit may, for example, be outside the matrix array and connected to it by wire connection means (e.g., by a flexible ribbon cable). The control circuit may also be mounted on the plate comprising the pixels, as described in WO 2012 / 152836 A1 filed in the name of the applicant.

[0009] This allows for a reduction in the number of signals applied to the plate and therefore the size and number of flexible connectors used to connect the plate to the surrounding electronics. This integrated control circuit architecture represents a significant simplification of the detector architecture by reducing the number of parts and simplifying the manufacturing process.

[0010] However, this architecture dictates the order in which the matrix rows are driven. This order is dictated by the connections of the control circuitry and the connections of the matrix rows. In some cases, it may be desirable to change the order in which the matrix rows are controlled. More specifically, it may be desirable to group multiple pixels together in order to read them out collectively. This grouping, known in the literature as "binning," allows the signal-to-noise ratio of each element that is read out to be improved. Another advantage of grouping pixels is improved detector sensitivity. However, this grouping has a negative impact on spatial resolution.

[0011] If the information from each pixel is an electric charge, this grouping of pixels can be achieved by redistributing the electric charge from the grouped pixels onto a common capacitor (e.g., located in a converter circuit in the leg of the column). This can be achieved in detectors such as those described in WO 2012 / 152836 A1 by reading out each row of pixels sequentially. However, in such detectors, the grouping of pixels in successive rows does not make it possible to improve the detector readout speed and therefore increase the frequency of images produced by the detector. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] International Publication No. 2012 / 152836A1 Brochure Summary of the Invention [Problem to be solved by the invention]

[0013] The present invention aims to overcome all or some of the above problems by providing a detector whose control circuitry allows either conventional sequential readout or grouping of pixels belonging to successive rows, thereby increasing the readout speed. The present invention is particularly advantageous in detectors in which the control circuitry and pixels are produced on the same substrate. [Means for solving the problem]

[0014] To this end, one subject of the present invention is: an array of pixels sensitive to a physical influence and arranged in a matrix along pixel rows and columns, each pixel generating a signal according to the physical influence and the pixel rows being physically ordered; row conductors, each allowing one row of pixels to be driven; and a matrix array detector including driver modules, each associated with one row conductor (L) and adapted to send a selection signal to one of the row conductors, distributed in a number of groups interlaced according to the order of the rows of pixels; The driver modules of each group are chained together in the physical order of the row associated with that group of driver modules, and the chaining of each group of driver modules is independent of the chaining of one or more other groups of driver modules.

[0015] Advantageously, the matrix array detector further comprises a module for generating a plurality of tokens each sent to an input of a first one of the driver modules of each group of driver modules, the output of each module being connected to the input of a module of higher rank within each group of groups of driver modules, the driver modules being ordered within each group of groups in the order of the rows of pixels to the conductors to which that driver module sends its selection signals.

[0016] Advantageously, pixel and driver modules are produced on the same substrate based solely on n-type thin film transistors or solely on p-type thin film transistors.

[0017] Another subject of the invention is a method of using a matrix array detector according to the invention, in which driver modules belonging to distinct groups and connected to successive row conductors are successively do Simultaneous driving of rows of A control signal can be received or continuous do To drive the rows separately Alternating Control signal Reception possible.

[0018] The invention will be better understood and further advantages will become apparent on reading the detailed description of an embodiment thereof, given by way of example and illustrated by the accompanying drawings, in which: FIG. [Brief explanation of the drawings]

[0019] [Figure 1] 1 illustrates an exemplary matrix array of pixels that may be implemented in a detector according to the present invention. [Figure 2] 1 illustrates an exemplary detector according to the present invention. [Figure 3] 3 illustrates one exemplary embodiment of multiple driver modules that may be implemented within the detector of FIG. 2. [Figure 4] 3 illustrates another exemplary embodiment of multiple driver modules that may be implemented in the detector of FIG. 2. [Figure 5] 5 shows a detailed example of the driver module of FIG. 4. [Figure 6] An example of the operation of a detector implementing the driver modules shown in FIG. 5 and chained in only one group is shown in the form of a timing diagram. [Figure 7] An example of the operation of a detector implementing the driver modules shown in FIG. 5 and chained in two groups for individual readout of the detector's pixels is shown in the form of a timing diagram. [Figure 8]An example of the operation of a detector shown in FIG. 5 and implementing driver modules chained in two groups for a common readout of two consecutive rows of pixels is shown in the form of a timing diagram. DETAILED DESCRIPTION OF THE INVENTION

[0020] For purposes of clarity, like elements will have the same reference numbers in the various drawings.

[0021] The following description is provided with reference to a matrix array detector (called pixels) that includes a plurality of basic electronic circuits, each including an element sensitive to a physical quantity. The basic electronic circuits are pixels sensitive to optical radiation in the example described. It will be clear that the invention can be implemented with other detectors that are sensitive to any type of physical quantity that allows, for example, a pressure or temperature map to be generated.

[0022] Figure 1 shows a schematic representation of the detection area 10 of a matrix array detector. This area comprises, for ease of understanding, a matrix of 2 rows by 2 columns. Four pixels P are formed, each at the intersection of a row and a column. Of course, a real matrix array will usually be much larger and feature a large number of rows and columns. The matrix array of pixels belongs to a matrix array detector 12, which enables a digitized image to be generated.

[0023] Each pixel P comprises a photosensitive area, represented here by a photodiode D, and an electronic processing circuit, formed in the example of Fig. 1 by a single transistor T. The references of the components D and T are followed respectively by two coordinates i and i+1 defining the row rank, and two coordinates j and j+1 defining the column rank. The rows and columns are ordered in the physical order in which they occupy within the matrix array of pixels. The pixels shown are also known as 1T pixels, since each contains one transistor, the function of which will be further explained below.

[0024] It is common practice to fabricate matrix arrays of pixels containing thin film field effect transistors, known as TFTs for "thin film transistors". The TFTs may be based on metal oxides, for example transistors based on amorphous or crystalline indium, gallium and zinc oxide (known by the abbreviation IGZO). Other families of TFTs may also be employed, such as organic TFTs, amorphous silicon TFTs or polycrystalline silicon TFTs. Of this last type of TFT, some have been synthesized at low temperatures; they are known by the acronym LTPS, for "low temperature polycrystalline silicon".

[0025] Pixels P of the same column are connected to a column conductor Col, which allows information from the connected pixels to be collected, and pixels P of the same row are connected to a row conductor L, which carries a signal VG, which allows the corresponding row of pixels to be controlled.

[0026] During the image capture phase, which occurs after the reset operation, the illumination received by the photodiode D reduces the potential of its cathode. This image capture phase is followed by a readout phase in which the potential of the photodiode D is read out. To do this, the transistor T is turned on and thus acts as a switch controlled by a control signal VG applied to its gate.

[0027] A column conductor Col is used to collect information from pixels in a corresponding column when selected by a signal VG.

[0028] It is possible to implement the invention in detectors where the pixel is simpler, in particular by replacing the transistor T with a simple diode that is turned on by the signal VG. It is also possible to implement the invention in detectors where the pixel comprises multiple transistors. In particular, it is known practice to implement 3T pixels that include a reset transistor and a follower transistor for the photodiode in addition to the readout transistor mentioned above. In this type of 3T pixel, a second row conductor carries a reset signal that allows the reset transistor to be controlled.

[0029] 2 shows a schematic representation of the detector 12 as a whole. The detector 12 comprises a plate 14 forming the substrate on which the components of the detection area 10 are fabricated. A driver module 16 is arranged on this same plate 14, which sends control signals to all of the row conductors L. Alternatively, the driver module 16 can be fabricated on a different substrate than the plate 14. However, fabricating the driver module 16 on the same substrate as the pixels P makes it possible to limit the number of connections connecting the plate 14 to its surroundings.

[0030] The detector 12 includes readout circuitry 18 connected to the column conductors Col. The readout circuitry 18 is typically fabricated on a different substrate than the plates 14. The readout circuitry 18 is connected to the plates 14 by ribbon cables.

[0031] The detector 12 includes circuitry 20 that allows the driver module 16 to be driven and that allows the signals from the readout circuitry 18 to be retrieved, particularly for multiplexing.

[0032] FIG. 3 shows a first exemplary embodiment of four driver modules 16, each configured to drive a row of pixels. It is clearly understood that the present invention can be implemented for a greater number of rows of pixels. More specifically, the output Out_A(n) of a first driver module, denoted by SR_A(N), is connected to the row conductor L(i) carrying the readout signal VG for row i. The output Out_B(n) of a second driver module, denoted by SR_B(N), is connected to the row conductor L(i+1) carrying the readout signal VG for row i+1. The output Out_A(n+1) of a third driver module, denoted by SR_A(N+1), is connected to the row conductor L(i+2) carrying the readout signal VG for row i+2. The output Out_B(n+1) of a fourth driver module, denoted by SR_B(N+1), is connected to the row conductor L(i+3) carrying the readout signal VG for row i+3. The rows and driver modules are ordered in the order of FIG. 3. More specifically, for individual readout of each row of pixels, row i is read out, followed by row i+1, then row i+2, and finally row i+3, etc. As will be seen further below, the driver module is also configured to enable readout by grouping rows in consecutive pairs.

[0033] In the illustrated example, the driver modules are distributed into two groups: SR_A(N) and SR_A(N+1) in the first group A, and SR_B(N) and SR_B(N+1) in the second group B. The present invention can be implemented with many groups of driver modules. The rows are also grouped into two groups: LA for rows L(i) and L(i+2) on the one hand, and LB for rows L(i+1) and L(i+3) on the other hand. The driver module group A is associated with the rows of group LA, and the driver module group B is associated with the rows of group LB. The row groups LA and LB, and therefore the driver module groups A and B, are interlaced. More specifically, in each group, the driver modules are ordered according to the physical order of the rows of the matrix array. For the two groups of driver modules A and B, the first driver module SR_A(1) of the first group A drives the first row L(1) of the matrix array in the physical order of the rows of the matrix array. The first driver module of the second group B, SR_B(1), drives the second row L(2). The second driver module of the first group A, SR_A(2), drives the third row L(4). The second driver module of the second group B, SR_B(2), drives the fourth row L(1), and so on until the last row of the matrix array. More generally, with K groups of driver modules, using the following notation: i: the rank of the current row in the physical order of the rows of the matrix array; j: The rank of the module within that group k: the rank of the group between 1 and K, Row i is driven by a module of rank j in a group of rank k: i=(j-1)K+k.

[0034] Distributing the rows and driver modules into various groups associated with each other makes it possible to drive the groups of rows in different ways, and in particular by adapting the synchronization of the various groups of driver modules and therefore the synchronization of the driving of the groups of rows.

[0035] FIG. 3 shows an embodiment that allows a particularly simple connection of the driver modules. It is clearly understood that other connections are possible. Each driver module includes inputs In_A(n), In_B(n), In_A(n+1), In_B(n+1), respectively, that allow it to receive instructions for that module, as well as outputs Out_A(n), Out_B(n), Out_A(n+1), Out_B(n+1), respectively, that allow it to drive the associated row. In each group, the driver modules are chained together in the order of the rows associated with that group. The chaining of one group is independent of the chaining of one or more other groups of driver modules. More specifically, in the example shown, the output Out_A(n) is connected to the input In_A(n+1), and the output Out_B(n) is connected to the input In_B(n+1).

[0036] The detector 12 comprises a generation module 30 making it possible to generate a first token IN_A that is sent to the input of the first driver module SR_A(N) of group A. The generation module 30 also makes it possible to generate a second token IN_B that is sent to the input of the first driver module SR_B(N) of group B. The chaining of driver modules makes it possible for a token to propagate from one driver module to the next within the same group. More generally, the generation module 30 makes it possible to generate as many tokens as there are groups of driver modules.

[0037] In addition, the driver module receives one or more control signals N controls A of group A and one or more control signals N controls B of group B. These control signals are, for example, clocks at the speed at which a token travels from one module to another in the same group. The control signals can be generated by a generation module 30 (e.g., in circuit 20) which can be located on plate 14 or on a board separate from plate 14. The connections of the control signals between the various driver modules and from output to input between successive modules can be made on plate 14 and therefore do not require external connections.

[0038] The detector 12 can be operated in various ways by generating the signal VG for each row either sequentially in the order of the rows of the matrix array (allowing for individual readout of the pixels of the detector 12) or simultaneously in two driver modules of the same rank in two groups. In other words, the signal VG is transmitted simultaneously by the driver modules SR_A(N), SR_B(N) and then by the driver modules SR_A(N+1), SR_B(N+1), allowing for the grouping of information coming from the pixels of different rows. The selection between the two types of detector readout (either individually or by pixel group) is performed by varying the time of transmission of the tokens IN_A, IN_B and possibly the time of transmission of the driver module control signals. Simultaneous transmission of the two tokens allows for group-by-group readout. Alternate transmission of the two tokens allows for individual readout.

[0039] By distributing the driver modules into two groups, it is possible to group the readout of two rows of pixels. More generally, K groups allow grouping the readout of K rows. Grouping of rows by a submultiple of the number of groups is also possible. For example, with four groups of driver modules, it is possible to read out the matrix array individually, rather than in groups of two rows or groups of four rows, according to an offset in the transmission of the tokens and corresponding control signals of the various groups.

[0040] FIG. 4 shows another exemplary embodiment of four driver modules 16, each configured to drive a row of pixels. In this example, each driver module includes an input stage E and an output stage S. The input stage E sends an activation signal Outa or Outb for the corresponding output stage S. In case of activation by the input stage, the corresponding output stage transmits the output signal (represented here by Gateline) of the driver module. This example with two stages corresponds to the scheme described in the above-mentioned WO 2012 / 152836 A1. The transmission of a token between two consecutive driver modules of the same group is realized by an activation signal sent to the input of the input stage of the module of higher rank. The input stages of the various modules and their connections enabling the transmission of the token form a shift register. Each output stage forms an amplifier allowing the activation signal to be adapted to the characteristics of the signal VG.

[0041] Figure 5 shows a more detailed diagram of one of the driver modules of Figure 4. The integrated structure forming the row addressing device according to the present invention may essentially include transistors TFTs of a single type (i.e., p-type or n-type; n-type is preferred due to its better performance). Thus, the transistors described below may all be single-type (n- or p-type) thin film transistors (TFTs).

[0042] The structure illustrated by Figure 5 corresponds to one advantageous embodiment in which each row addressing stage n includes an input stage 50 and an output stage 51. With respect to row addressing stage n, each of the input stage 50 and output stage 51 includes most of the elements included in row addressing stage n described above with reference to Figure 3, for example. It should be noted that in the exemplary embodiment described, a row n of the matrix array is associated with each addressing device stage n. However, in alternative examples not illustrated by the figures, it is possible to envision row addressing device structures in which a given stage controls multiple rows, or in which some rows are not otherwise controlled by a stage.

[0043] Thus, the input stage 50 of the stage n of the row addressing device may be formed by a shift register including an output row that renders an activation signal Out(n) as an output. The input stage 50 may include an output transistor T30 of the input stage that transmits pulses of a clock signal at the activation output Out(n). The gate of the output transistor T30 of the input stage may be connected to an internal node of the input stage of the row addressing device, its source may be connected to the activation output Out(n), and its drain may receive a signal from the first clock CLK1. A boost capacitor C20 of the input stage may be connected between the gate and source of the output transistor T30 of the input stage. The first control transistor T10 of the input stage may precharge the gate of the output transistor T30 of the input stage. Thus, the source of the first control transistor T10 of the input stage is connected to the gate of the output transistor T30 of the input stage. The gate and drain of the first control transistor T10 of the input stage are controlled by the activation output Out(n-1) of the stage n-1 of the addressing device of the previous row n-1.

[0044] The second control transistor T20 of the input stage can discharge the gate of the output transistor T30 of the input stage. The drain of the second control transistor T20 of the input stage is therefore connected to the gate of the output transistor T30 of the input stage. The compensation capacitor C10 of the input stage can advantageously be placed between the signal from the first clock CLK1 and the signal from the second clock CLK2, which is out of phase with the first clock CLK1.

[0045] Advantageously, the discharge transistor T40 of the input stage can be connected to the activation output Out(n) of the input stage 50 of the stage n of the row addressing device. The gate of the discharge transistor T40 of the input stage is connected to the gate of the second control transistor T20 of the input stage; and also to the activation output signal Out(n+1) of the next stage n+1.

[0046] Similarly, the output stage 51 of the row addressing device stage n may be formed by a shift register including an output row signal Sn, which is rendered as an output. The output stage 51 may include an output transistor T31 of the output stage, which transmits pulses of the clock signal at the output Sn. The gate of the output transistor T31 may be connected to an internal node of the row addressing device stage, its source may be connected to the output Sn, and its drain may receive a signal from the third clock CLK3. The output stage boost capacitor C21 may be connected between the gate and source of the output transistor T31 of the output stage. The first control transistor T11 of the output stage may precharge the gate of the output transistor T31 of the output stage. Thus, the source of the first control transistor T11 of the output stage is connected to the gate of the output transistor T31 of the output stage. The gate and drain of the first control transistor T11 of the output stage are controlled by the activation output Out(n) of the input stage 50 of the addressing device stage n.

[0047] The second control transistor T21 of the output stage can discharge the gate of the output transistor T31 of the output stage. The drain of the second control transistor T21 of the output stage is therefore connected to the gate of the output transistor T31 of the output stage. The compensation capacitor C11 of the output stage can advantageously be arranged between the signal from the third clock CLK3 and the signal from the out-of-phase fourth clock CLK4. The particularity of the third and fourth clocks CLK3, CLK4 is that their duty cycles can be different and the sum of their respective periods at high level corresponds to the periods of the first and second clocks CLK1, CLK2.

[0048] Advantageously, the discharge transistor T41 of the output stage can be connected to the output Sn of the output stage 51 of the stage n of the row addressing device, which delivers the activation signal for row n. The gate of the discharge transistor T41 of the output stage is connected to the gate of the second control transistor T21 of the output stage; it is also connected to the activation output Out(n+1) of the next stage n+1.

[0049] According to another particular feature of the invention, the input stage 50 also includes an input stage reset transistor TR, the gate of which is controlled by pulses of the reset signal. The source of the input stage reset transistor TR may be connected to the source of the input stage second control transistor T20. The drain of the input stage reset transistor TR may be connected to the drain of the input stage second control transistor T20.

[0050] In the same manner, the output stage 51 also includes an output stage reset transistor TR whose gate as well as the gate of the input stage reset transistor are controlled by pulses of the reset signal. The source of the output stage reset transistor TR may be connected to the sources of the output stage second control transistor T21 and the output stage discharge transistor T41, respectively, and to the sources of the input stage second control transistor T20 and the input stage discharge transistor T40, respectively. The drain of the output stage reset transistor TR may be connected to the drain of the input stage second control transistor T21.

[0051] The reset pulse therefore makes it possible to impose an off state on the various transistors of the input stage 50 and the output stage 51 .

[0052] Additionally, the output stage 51 may include a row reset transistor TL. The row reset transistor TL is controlled via its gate by a specific signal. The drain of the row reset transistor TL is connected to the source of the output transistor T31 of the output stage. The source of the row reset transistor TL may be connected to the sources of transistors T20, T40, T21, and T41. The row reset transistor TL of stage n makes it possible to force the voltage on row n to a low state. The row reset transistor TL makes it possible to control the voltage on the row (i.e., related to the output of the output stage of the stage) and to apply a low-impedance voltage to the row, in particular during the "dead time". Specifically, in a typical manner, the operation of an X-ray detector includes, for example, a reset phase, followed by a phase of applying X-rays (or "X-window"), and then a readout phase. During the X-window period, X-rays are converted into electrons in the photodiodes; the duration of the X-window is relatively long (typically up to 3.2 seconds), and therefore the row reset transistor TL makes it possible to avoid any drift in the matrix array.

[0053] Again, advantageously, each output stage 51 may include a matrix array reset switch, for example formed by a matrix array reset transistor TLON, which allows a complete reset of the matrix array to be performed. The matrix array reset transistor TLON may be controlled by a matrix array reset signal applied to its gate and drain. The source of the matrix array reset transistor TLON may be connected to the source of the output transistor T31 of the output stage. The matrix array reset signal controlling the matrix array reset transistor TLON may be a voltage VGoff or an activation voltage VGon. When the matrix array reset transistor TLON is active, i.e. when the activation voltage VGon is applied, the activation voltage is applied to the entire matrix array.

[0054] In fact, a complete reset of the matrix array can be performed according to a sequence defined by the activation of the matrix array reset transistor TLON for a sufficient period of time, followed by the activation of the row reset transistor TL which allows the row to return to voltage VGoff.

[0055] Figure 6 shows in the form of a timing diagram the operation of the driver modules of Figure 5 arranged in a single group as described in WO 2012 / 152836 A1. A single token IN is sent to the gate and drain of the control transistor T10 of the input stage E of the first driver module. The clocks CLK1 and CLK2 are in phase opposition and have equal proportions of high and low levels. The clocks CLK3 and CLK4 are also in phase opposition and have a cycle time that is half the cycle time of the clocks CLK1 and CLK2. The high level period of clock CLK4 is longer than that of clock CLK3.

[0056] Figure 6 also shows four consecutive rows of signals Out(n). Each signal Out(n) is offset by half a cycle of clock CLK1 with respect to the previous one. Signal Gateline(n) is also shown for the same four rows. A dead time TM is observed between two high levels of two consecutive signals Gateline. This dead time corresponds to the duration of the high level of clock CLK3. A minimum duration of the high level of clock CLK3 is necessary to guarantee the charging of the gate of transistor T31. It is not possible to eliminate this dead time by directly chaining driver modules within a single group.

[0057] Conversely, by distributing the driver modules into several groups, it is possible, for each readout of a pixel, to mask the dead time between two successive modules of the same group by a high level of the signal Gateline of another group.

[0058] FIG. 7 illustrates, in the form of a timing diagram, an example of the operation of the detector 12 shown in FIG. 5 and implementing driver modules chained in two groups for individual readout of the detector's pixels. For the first group A, there is a token INA and four clocks CLK1A, CLK2A, CLK3A, and CLK4A. The clocks CLK1A and CLK2A are out of phase. The clocks CLK3A and CLK4A are also out of phase, with cycle times that are half the cycle times of the clocks CLK1 and CLK2. Unlike the clocks described using FIG. 6, the four clocks CLK1A, CLK2A, CLK3A, and CLK4A have their respective high and low levels in equal proportions.

[0059] Also shown in Figure 7 is the token INB and the four clocks CLK1B, CLK2B, CLK3B, CLK4B of group B. Relative to group A, the signals of group B are offset by a quarter of a cycle of clock CLK1A.

[0060] For group A, two signals OutA(1) and OutA(2) and two signals Gateline(1) and Gateline(3) correspond to the two consecutive driver modules of group A. The signals Gateline(1) and Gateline(3) enable driving rows of ranks 1 and 3 of the matrix array. Similarly, for group B, two signals OutB(1) and OutB(2) and two signals Gateline(2) and Gateline(4) correspond to the two consecutive driver modules of group B. The signals Gateline(2) and Gateline(4) enable driving rows of ranks 2 and 4 of the matrix array. In other words, the driver modules of group A generate the signals Gateline for the odd-numbered rows of the matrix array, and the driver modules of group B generate the signals Gateline for the even-numbered rows.

[0061] The interlacing of the two groups allows the high level period of the clock CLK3A to be extended, thus ensuring the gate of transistor T31 is charged without any dead time between two consecutive rows. Specifically, the gate of transistor T31 in the driver module of group A is charged during the high level of the signal Gateline of group B.

[0062] FIG. 8 shows, in the form of a timing diagram, another example of the operation of detector 12 implementing the driver module shown in FIG. 5, still chained in two groups and this time for the common readout of consecutive rows of pixels. In other words, consecutive even and odd rows are read out simultaneously. In the operation described with the help of FIG. 8, token INA is transmitted simultaneously with token INB. Similarly, clocks CLK1A, CLK2A, CLK3A, and CLK4A are transmitted simultaneously with corresponding clocks CLK1B, CLK2B, CLK3B, and CLK4B. It therefore follows that signals OutA(1) and OutA(2), OutA(3) and OutA(4), Gateline(1) and Gateline(2), Gateline(3) and Gateline(4) are simultaneous.

[0063] The operation of Figure 8 is similar to that of Figure 6 with a dead time TM between signals Gateline(2) and Gateline(3). To limit the duration of this dead time, the high periods of clocks CLK3A and CLK3B are shorter than the low periods of these same clocks.

[0064] The detector 12 with several groups of driver modules chained together makes it possible to select different operating modes as required, in particular individual readout of the pixels of the matrix array, while offering the possibility of eliminating any dead time between two readouts of two successive rows of the matrix array. The detector 12 also makes it possible to group signals originating from several pixels for collective readout.

[0065] Two examples of operation for the readout of a matrix array of pixels P are given. In the diagram of Fig. 1, the row conductor L is used to open-drive a transistor T(i,j). This transistor is used both to readout and to reset each pixel P(i,j). For readout and reset (e.g., individual readout and global reset), the pixels can be driven in the same way or in different ways. [Explanation of symbols]

[0066] 10 Detection Area 12 Matrix array detector 14 plates 16 Driver Module 18 Readout circuit 20 circuits 30 Generation Module 50, E input stage 51, S output stage A, B driver module group CLK1 First clock CLK2 Second clock CLK3 Third clock CLK4 4th clock CLK1A Group A clock CLK1B Group B clock C10 Input stage compensation capacitor C11 Output stage compensation capacitor C20 Input stage boost capacitor C21 Output stage boost capacitor Col column conductor D Photodiode INA and INB tokens IN_A 1st token IN_B Second token In_A, In_B, In_A(n+1), In_B(n+1) input L row conductor LA, LB Group Out_A(n) Output of the first driver module Out_A(n+1) Third driver module output Out_B(n) Output of the second driver module Out_B(n+1) Output of the fourth driver module Out(n) Activation output Outa, Outb activation signal OutA(1), OutA(2), Gateline(1), Gateline(3) Group A signals OutB(1), OutB(2), Gateline(2), Gateline(4) Group B signals P pixel SR_A(N) First driver module of group A SR_B(N) First driver module of group B Sn output T transistor TL row reset transistor TLON Matrix Array Reset Transistor TM Dead Time TR Reset Transistor T10 First control transistor of the input stage T11 First control transistor of the output stage T20 Second control transistor of the input stage T21 Second control transistor of the output stage T30 Input stage output transistor T31 Output transistor of the output stage T40 Input stage discharge transistor T41 Output stage discharge transistor VG control signal VGoff voltage VGon Activation Voltage

Claims

1. A matrix array detector, comprising: an array (10) of pixels sensitive to a physical influence and arranged in a matrix along rows and columns of pixels (P), each pixel (P) generating a signal according to a physical influence, said rows of pixels being physically ordered; - selection lines (L), each allowing one row of said pixels (P) to be activated; driver modules (SR_A, SR_B), each associated with one selection line (L) and sending a selection signal (Out_A, Out_B; Gateline) to one of said selection lines (L), said driver modules being distributed in a number of groups interlaced according to said order of said rows of pixels; 1. A matrix array detector comprising: the driver modules (SR_A, SR_B) of each group (A, B) are chained together in the order of the rows associated with that group of driver modules, and the chaining of each group of driver modules is independent of the chaining of the one or more other groups of driver modules; the matrix array detector includes a module (30) for generating a plurality of tokens (INA, INB) each of which is sent to an input (In_A(N), In_B(N)) of a first one of the driver modules (SR_A(N)) of each group (A, B); further comprising Within each group of driver modules, the outputs (Out_A(n), Out_B(n)) of each module are connected to the inputs (In_A(n+1), In_B(n+1)) of the higher-ranked module, and the driver modules are ordered within each of their groups (A, B) in the order of the rows of pixels to which the driver modules send the select signals; A matrix array detector, wherein the tokens (INA, INB) can be transmitted simultaneously, allowing for group-wise reading of pixels (P), and the tokens (INA, INB) can be transmitted alternately, allowing for individual reading of the pixels (P) in the order of the rows of the matrix.

2. 2. The matrix array detector according to claim 1, wherein the pixels (P) and the driver modules (SR_A, SR_B) are produced on the same substrate (14) based on only n-type thin film transistors or only p-type thin film transistors.

3. 3. A method of using a matrix array detector according to any one of claims 1 to 2, wherein driver modules (16) belonging to separate groups (A, B) and connected to successive selection lines (L) can receive simultaneous control signals to drive successive rows simultaneously, or can receive alternating control signals to drive successive rows separately.

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