Indication device

Abstract

To provide a novel composite oxide and a semiconductor device which has excellent electric characteristics and of which the reliability is high.SOLUTION: A composite oxide includes at least two regions 001 and 002. The region 001 contains In, Zn and an element M1 (the element M1 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be and Cu). The region 002 contains In, Zn and an element M2 (the element M2 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be and Cu). When the composite oxide is analyzed by energy dispersive X-ray spectroscopy, the element M1 in the region 001 is detected less than the element M2 in the region 002. A peripheral part of the region 001 is observed blurred by mapping analysis in the energy dispersive X-ray spectroscopy.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, relating to the manufacture or composition of matter, especially One aspect of the present invention relates to a metal oxide or a method for producing the metal oxide. One embodiment of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, a memory device, The present invention relates to a device, a driving method thereof, or a manufacturing method thereof.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices are all semiconductor devices. The semiconductor device may include a conductive device. [Background technology]

[0003] A technology for fabricating transistors using In-Ga-Zn metal oxides has been disclosed. (See, for example, Patent Document 1).

[0004] In addition, in Non-Patent Document 1, an In-Zn oxide and an In-G A structure having a two-layer stack of metal oxide with a-Zn oxide is being investigated. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-96055 [Non-patent literature]

[0006] [Non-Patent Document 1] John F. Wager, "Oxide TFTs: A Progress Report", Information Display 1 / 16, SID 2016, Jan / Feb 2016, Vol.32,No.1, p.16-21 Summary of the Invention [Problem to be solved by the invention]

[0007] In Non-Patent Document 1, in a channel-protected bottom-gate transistor, The active layer of the photodiode is a two-layer stack of indium zinc oxide and IGZO. By setting the thickness of the formed indium zinc oxide to 10 nm, high field-effect mobility ( μ=62cm 2 V -1 s -1 ) is realized. On the other hand, one of the transistor characteristics is S value (Subthreshold Swing, also known as SS) is 0.41V / deca Also, the threshold voltage (Vth), which is one of the transistor characteristics, is -2.9V, which is the so-called normally-on transistor characteristic.

[0008] In view of the above problems, an object of one embodiment of the present invention is to provide a novel metal oxide. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object is to provide a highly reliable semiconductor device. It is an object of the present invention to provide a semiconductor device having a novel structure. One of our goals is to provide the following.

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0010] One aspect of the present invention is a composite oxide having at least two regions, one of which is In, Zn, and element M1 (element M1 is Al, Ga, Si, B, Y, Ti, Fe, N i, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, or C u), and the other region contains In, Zn, and the element M 2 (Element M2 is Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, L one of a, Ce, Nd, Hf, Ta, W, Mg, V, Be, or Cu, or When the composite oxide is analyzed by energy dispersive X-ray spectroscopy, The element M1 in the region containing the element M1 is more abundant than the element M2 in the region containing the element M2. , and the original was detected by mapping analysis in energy dispersive X-ray spectroscopy. The periphery of the region including element M1 is observed to be blurred.

[0011] In the above embodiment, the two regions each independently have microparticles.

[0012] In the above embodiment, the size of the microparticles is 0.5 nm or more and 3 nm or less.

[0013] Another embodiment of the present invention is a semiconductor device comprising the above-described complex oxide, a gate, a source, and a drain, The composite oxide is characterized in that it is used as a channel region of a transistor. It is a transistor. [Effects of the Invention]

[0014] According to one embodiment of the present invention, a novel metal oxide can be provided. According to the embodiment, it is possible to provide the semiconductor device with good electrical characteristics. Alternatively, a semiconductor device having a novel configuration can be provided. Alternatively, a display device with a novel configuration can be provided.

[0015] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. , the specification, drawings, claims, etc., and It is possible to extract other effects from the claims and other descriptions. [Brief explanation of the drawings]

[0016] [Figure 1] Conceptual diagram of the structure of metal oxides. [Figure 2] 1A and 1B are schematic diagrams illustrating a transistor and distribution of energy levels in the transistor; [Figure 3] FIG. 1 is a diagram illustrating a schematic band diagram model of a transistor. [Figure 4] FIG. 1 is a diagram illustrating a schematic band diagram model of a transistor. [Figure 5] FIG. 1 is a diagram illustrating a schematic band diagram model of a transistor. [Figure 6] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 7] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 8] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 12] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 13] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 14] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 16] FIG. 2 is a diagram illustrating the range of atomic ratios of metal oxides according to the present invention. [Figure 17] 1A and 1B are diagrams illustrating an example of the configuration of a display panel. [Figure 18] 1A and 1B are diagrams illustrating an example of the configuration of a display panel. [Figure 19] 1A and 1B are diagrams illustrating a model of a metal oxide and density of states of the metal oxide according to this embodiment; [Figure 20] 1A and 1B are diagrams illustrating the local structure and density of states of a model of a metal oxide to which an impurity is added according to the present embodiment. [Figure 21] 1A and 1B are diagrams illustrating the local structure and density of states of a model of a metal oxide to which an impurity is added according to the present embodiment. [Figure 22] 1A and 1B are diagrams illustrating the local structure and density of states of a model of a metal oxide to which an impurity is added according to the present embodiment. [Figure 23] FIG. 10 is a diagram illustrating the measurement results of the XRD spectrum of a sample according to an example. [Figure 24] 1A to 1C are diagrams illustrating a cross-sectional TEM image and an electron diffraction pattern of a sample according to an example. [Figure 25] 1A to 1C are diagrams illustrating a planar TEM image, a cross-sectional TEM image, and an electron diffraction pattern of a sample according to an example. [Figure 26] 1A to 1C are diagrams illustrating a planar TEM image of a sample according to an embodiment and an image analysis image thereof. [Figure 27] FIG. 10 is a diagram illustrating a method for deriving the rotation angle of a hexagon. [Figure 28] A diagram explaining how to create a Voronoi diagram. [Figure 29] 10A and 10B are diagrams for explaining the number and ratio of shapes of Voronoi regions according to an embodiment. [Figure 30] 1A to 1C are diagrams illustrating a planar TEM image, a cross-sectional TEM image, and EDX mapping of a sample according to an embodiment. [Figure 31] FIG. 1 is a diagram illustrating EDX mapping of a sample according to an embodiment. [Figure 32] 10 is a graph showing the Id-Vg characteristics of a sample according to an example. [Figure 33] 10 is a graph showing the Id-Vg characteristics of a sample according to an example before and after +GBT stress. [Figure 34] 10A and 10B are graphs showing Id-Vg and Id-Vd characteristics of a transistor; [Figure 35] Graph showing Id-Vg characteristics and mobility curves (linear and saturated) calculated from GCA. [Figure 36] 1A to 1C are diagrams illustrating a cross-sectional TEM image and an electron diffraction pattern of a sample according to an example. [Figure 37] 1A to 1C are diagrams illustrating a planar TEM image of a sample according to an embodiment and an image analysis image thereof. [Figure 38] 10A and 10B are diagrams for explaining the number and ratio of shapes of Voronoi regions according to an embodiment. [Figure 39] 1A to 1C are diagrams illustrating a planar TEM image, a cross-sectional TEM image, and EDX mapping of a sample according to an embodiment. [Figure 40] FIG. 1 is a diagram illustrating EDX mapping of a sample according to an embodiment. [Figure 41] 1A to 1C are diagrams illustrating a planar TEM image, a cross-sectional TEM image, and EDX mapping of a sample according to an embodiment. [Figure 42] 10 is a graph showing the Id-Vg characteristics of a sample according to an example. [Figure 43]1A to 1C are diagrams illustrating a cross-sectional TEM image, EDX mapping, and atomic ratio of a sample according to an example. [Figure 44] 1A to 1C are diagrams illustrating a planar TEM image, EDX mapping, and atomic ratio of a sample according to an embodiment. [Figure 45] FIG. 2 is a diagram illustrating Id-Vg characteristics. [Figure 46] FIG. 2 is a diagram illustrating Id-Vg characteristics. [Figure 47] FIG. 10 is a diagram illustrating the calculation results of interface state density. [Figure 48] FIG. 2 is a diagram illustrating Id-Vg characteristics. [Figure 49] FIG. 10 is a diagram illustrating the calculation results of defect state density. [Figure 50] FIG. 10 is a diagram illustrating the calculation results of defect state density. [Figure 51] FIG. 10 is a graph showing Id-Vg characteristics of a transistor. [Figure 52] FIG. 10 is a diagram for explaining the proportion of each atom based on the XPS measurement results of the sample according to the example. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments will be described with reference to the drawings. It is possible to carry out the invention in various forms and in various ways without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various modifications may be made to the design and details of the present invention. The present invention should not be construed as being limited to the following description of the embodiments.

[0018] In addition, in the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The figures are merely schematic representations and are not limited to the shapes or values ​​shown in the drawings.

[0019] In addition, the ordinal numbers "first," "second," and "third" used in this specification are intended to be used to indicate a mixture of elements. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0020] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used. The relationship is used for convenience in explaining the relationship with reference to the drawings. The values ​​change depending on the direction in which each component is depicted. It is not limited to words and phrases, and can be rephrased appropriately depending on the situation.

[0021] In this specification, a transistor includes a gate, a drain, and a source. It is an element with at least three terminals. And, the drain (drain terminal, drain Between the source (source terminal, source region or drain electrode) and the source (source terminal, source region or source electrode) It has a channel region, and a current flows between the source and the drain through the channel region. In this specification and the like, the channel region is a region through which a current mainly flows. This refers to the area in which the fluid flows.

[0022] The source and drain functions may differ depending on the type of transistor used, or the circuit operation. This may be reversed if the direction of the current changes during operation. In the text, the terms source and drain may be used interchangeably. .

[0023] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as

[0024] In this specification and the like, a silicon oxynitride film is a film containing more oxygen than nitrogen as a composition. A silicon nitride film is a film that contains more nitrogen than oxygen. This refers to a film with a high content.

[0025] In addition, in this specification and the like, when explaining the configuration of the invention using drawings, the same The same reference numerals may be used in common between different drawings.

[0026] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Almost parallel" means that two straight lines are arranged at an angle of between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0027] In addition, in this specification and the like, the terms "film" and "layer" may be used interchangeably. For example, the term "conductive layer" can be replaced with "conductive film" Alternatively, for example, the term "insulating film" may be changed to " may be changed to the term "insulating layer."

[0028] Even when referred to as a "semiconductor," for example, if its conductivity is sufficiently low, it may be regarded as an "insulator." It may have such characteristics. Also, the boundary between "semiconductor" and "insulator" is ambiguous, and there may be cases where they cannot be strictly distinguished. Therefore, the "semiconductor" described in this specification may be referred to as an "insulator" in some cases. Similarly, the "insulator" described in this specification may be referred to as a "semiconductor" in some cases.

[0029] Regarding this specification, etc., "In:Ga:Zn = 4:2:3 or in the vicinity thereof" means that when In is 4 with respect to the total number of atoms, Ga is 1 or more and 3 or less (1 ≤ Ga ≤ 3), and Zn is 2 or more and 4 or less (2 ≤ Zn ≤ 4). Also, "In:Ga:Zn = 5:1:6 or in the vicinity thereof" means that when In is 5 with respect to the total number of atoms, Ga is greater than 0.1 and 2 or less (0 .1 < Ga ≤ 2), and Zn is 5 or more and 7 or less (5 ≤ Zn ≤ 7). Also, "In:Ga:Zn = 1:1:1 or in the vicinity thereof" means that when In is 1 with respect to the total number of atoms, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and 2 or less (0.1 < Zn ≤ 2).

[0030] (Embodiment 1) In this embodiment, a composite oxide, which is one aspect of the present invention, will be described. Note that the composite oxide is an oxide having a CAC (Cloud - Aligned Composite) structure. As the composite oxide, for example, there are metal oxides having a plurality of metal elements. [[ID=Z35]]

[0031] In this specification, when a composite oxide, which is one aspect of the present invention, has the function of a semiconductor, it is defined as CAC - OS (Oxide Semiconductor). ​​​​​​​​​​​

[0032] In addition, CAC-OS or CAC-metal oxide is a matrix composite ( matrix composite, or metal matrix composite It is sometimes called atrix composite.

[0033] The composite oxide of one embodiment of the present invention preferably contains at least indium. In addition to these, it is preferable that the element M (the element M is aluminum) Aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon , titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium Choose from aluminum, neodymium, hafnium, tantalum, tungsten, or magnesium. The compound may contain one or more of the above-mentioned compounds.

[0034] The composite oxide of one embodiment of the present invention preferably contains nitrogen. In one embodiment of the composite oxide, the nitrogen concentration obtained by SIMS is 1×10 16 ato ms / cm 3 or more, preferably 1 × 10 17 atoms / cm 3 Over 2×10 22 ato ms / cm 3 When nitrogen is added to the composite oxide, the band gap Therefore, in this specification and the like, one aspect of the present invention is The composite oxides similar to the above also include composite oxides to which nitrogen or the like has been added. A composite oxide having the above structure can be called a composite oxynitride (metal oxide). good.

[0035] Here, a case where the composite oxide contains indium, element M, and zinc is considered. The atomic ratios of indium, element M, and zinc in the oxide are [In], [ [M] and [Zn].

[0036] <Composition of complex oxides> FIG. 1 shows a conceptual diagram of a metal oxide, which is a composite oxide having a CAC structure in the present invention.

[0037] CAC-OS is a type of metal oxide in which the elements constituting the metal oxide are unevenly distributed, as shown in Figure 1. By this, the regions 001 and 002, each of which is mainly composed of each element, are formed, and each region is mixed. In other words, the elements that make up the metal oxide are formed in a mosaic pattern. A composition of materials unevenly distributed in sizes of 3 nm or less, preferably 3 nm or less, or in the vicinity thereof. In the following, we will discuss the case where one or more metal elements are unevenly distributed in a metal oxide. The region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 3 nm or less, Or a state where they are mixed in a size close to that size is also called a mosaic or patch state.

[0038] For example, an In-M-Zn oxide having a CAC structure is an indium oxide (hereinafter referred to as In O X1 (X1 is a real number greater than 0) ), or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (where X2, Y2, and Z2 are real numbers greater than 0.) The material is separated into oxides containing element M, etc., forming a mosaic structure. InO X1 , or In X2 Zn Y2 O Z2However, the structure distributed in the film (hereafter referred to as cloud-like structure) In this specification, the separated InO X1 , or In X2 Z n Y2 O Z2 A small amount of gallium (Ga) may be mixed in the gallium oxide to form a solid solution.

[0039] In other words, the metal oxide of one embodiment of the present invention is an In oxide, an In-M oxide, an M oxide, A small number of oxides selected from M-Zn oxide, In-Zn oxide, and In-M-Zn oxide It has at least two or more oxides or materials.

[0040] Typically, the metal oxide of one embodiment of the present invention is an In oxide, an In-Zn oxide, an In-A l-Zn oxide, In-Ga-Zn oxide, In-Y-Zn oxide, In-Cu-Zn oxide oxide, In-V-Zn oxide, In-Be-Zn oxide, In-B-Zn oxide, In- Si-Zn oxide, In-Ti-Zn oxide, In-Fe-Zn oxide, In-Ni-Z n-oxide, In-Ge-Zn oxide, In-Zr-Zn oxide, In-Mo-Zn oxide , In-La-Zn oxide, In-Ce-Zn oxide, In-Nd-Zn oxide, In- Hf-Zn oxide, In-Ta-Zn oxide, In-W-Zn oxide, and In-Mg- Zn oxide. The metal oxide may also be referred to as a composite metal oxide having multiple materials or components.

[0041] Here, we assume that the concept shown in Figure 1 is an In-M-Zn oxide with a CAC structure. In this case, region 001 is a region mainly composed of oxides containing element M, and region 002 is a region mainly composed of In. X 2ZnY2 O Z2 , or InO X1 It can be said that this is a region whose main component is The region where oxides containing element M are the main component and the region where In X2 Zn Y2 O Z2 , or InO X1 but The area containing the main component and the area containing at least Zn are unclear (blurred) at the periphery. Therefore, it may not be possible to observe a clear boundary between them.

[0042] In other words, the In-M-Zn oxide with a CAC structure is mainly composed of oxides containing element M. In X2 Zn Y2 O Z2 , or InO X1 The area where the main component is mixed Therefore, metal oxides are sometimes referred to as composite metal oxides. In this specification, for example, the atomic ratio of In to element M in region 002 is The atomic ratio of In to element M in region 001 is larger than that in region 001. The concentration of In is higher than that of

[0043] Note that metal oxides having a CAC structure do not include a laminated structure of two or more films with different compositions. For example, a film consisting of two layers, one containing In as the main component and the other containing Ga as the main component, The structure does not include:

[0044] Specifically, the CAC-OS in In-Ga-Zn oxide (among the CAC-OS In addition, In-Ga-Zn oxide may be specifically referred to as CAC-IGZO. The CAC-OS in In-Ga-Zn oxide is X1 , or In X2 Z n Y2 O Z2 The material is separated into oxides containing gallium and other materials, forming a mosaic pattern. Mosaic InO X1 , or In X2 Zn Y2 O Z2 Metal acid cloud It's a monster.

[0045] In other words, the CAC-OS in In-Ga-Zn oxide is mainly composed of oxide containing gallium. The region where In X2 Zn Y2 O Z2 , or InO X1 and the region where It is a composite metal oxide with a mixed structure. Also, the main component is an oxide containing gallium. and the region where In X2 Zn Y2 O Z2 , or InO X1 The region where is the principal component is the The edges are unclear (blurred), so a clear boundary may not be visible.

[0046] For example, in the conceptual diagram shown in Figure 1, the region 001 is composed mainly of oxide containing gallium. Area 002 corresponds to In X2 Zn Y2 O Z2 , or InO X1 The main component is The region mainly composed of oxides containing gallium and the region X2 Zn Y2 O Z 2, or InO X1 The regions each having a main component may be called nanoparticles. Nanoparticles are particles with a diameter of 0.5 nm to 10 nm, typically 1 nm to 2 nm. In addition, the nanoparticles have unclear (blurred) peripheries, so there is no clear boundary. may not be observable.

[0047] The sizes of the regions 001 and 002 were measured using energy dispersive X-ray spectroscopy (EDX) Energy Dispersive X-ray spectroscopy (Energy Dispersive X-ray spectroscopy) For example, the area 001 can be evaluated by EDX mapping of the cross-sectional image. In DX mapping, the diameter of area 001 is 0.5 nm or more and 10 nm or less, or 3n It may be observed at or below 1000 m. Also, from the center to the periphery of the region, the main component The density of the elements gradually decreases. For example, the concentration of elements shown in EDX mapping (hereafter When the amount of crystalline matter (also called abundance) decreases from the center to the periphery, the EDX map of the cross-sectional photograph In the ping, the periphery of the area is observed to be unclear (blurred). For example, InO X1 In the region where In is the main component, In atoms are distributed from the center to the periphery. Instead, the number of Zn atoms increases, and the number of In atoms increases. X2 Zn Y2 O Z2 Mainly Therefore, in EDX mapping, the GaO X3 The periphery of the region where is the main component is observed in a blurred state.

[0048] Therefore, in the region 001 or region 002 of the In-Ga-Zn oxide, [I When [n] is 1, [Ga] and [Zn] are not limited to integers. In the area 001 and the area 002, the peripheral area is unclear. However, since there is a concentration distribution of each metal element, if [In] is set to 1, [Ga] and [Zn] is not necessarily an integer. Therefore, I with regions 001 and 002 In n-Ga-Zn oxides, when [In] is set to 1, [Ga] and [Zn] are , not limited to integers.

[0049] Here, the In-M-Zn oxide is, for example, InM m Zn n O p It can be expressed in the form In this case, the region 001 included in the complex oxide of one embodiment of the present invention is InM m1 Zn n1 O p1 Similarly, the region 00 of the complex oxide of one embodiment of the present invention can be expressed as follows. 2 is InM m2 Zn n2 O p2 It can be expressed as follows. Note that the above m, n, p, m1, n1, p1, m2, n2, and p2 may be integers or non-integers.

[0050] Therefore, in this specification, InM m Zn n O p ,InM m1 Zn n1 O p1、 or In M m2 Zn n2 O p2 The In-M-Zn oxide represented by the formula is called InMZnO-based oxide. InMZnO oxides are oxides in which, in the stoichiometric ratio, when In is 1, M and Zn can be integers or non-integers. Also, within the region, the stoichiometric ratio This includes cases where there is variation.

[0051] The crystal structure of the In-Ga-Zn oxide having the CAC structure is not particularly limited. In addition, the regions 001 and 002 may have different crystal structures. good.

[0052] Here, In-Ga-Zn-O metal oxide is sometimes referred to as IGZO, but IGZO is a common name and may refer to a single compound of In, Ga, Zn, and O. An example of a Ga-Zn-O-based metal oxide is a crystalline compound. The compounds are available in single crystal, polycrystalline, or c-axis aligned crystals (CAAC). The CAAC structure is a structure in which multiple IGZO A layered crystal structure in which nanocrystals are aligned along the c-axis and connected without being oriented in the ab plane is.

[0053] On the other hand, in the CAC-OS of In-Ga-Zn oxide, the crystal structure is a secondary factor. In this specification, CAC-IGZO refers to a material containing In, Ga, Zn, and O. In metal oxides, there are multiple regions with Ga as the main component and multiple regions with In as the main component. It can be defined as a metal oxide in which the metals are randomly dispersed in a mosaic pattern. can.

[0054] For example, in the conceptual diagram shown in Figure 1, region 001 corresponds to the region containing Ga as the main component, and region Region 002 corresponds to the region containing In as the main component. The regions each containing n as a main component may be referred to as nanoparticles. The diameter is 0.5 nm or more and 10 nm or less, typically 3 nm or less. However, the peripheral areas may be unclear (blurred), making it difficult to observe clear boundaries.

[0055] The crystallinity of the CAC-OS in the In-Ga-Zn oxide was evaluated by electron diffraction. For example, in an electron diffraction pattern image, a ring-shaped area with high brightness can be In addition, multiple spots may be observed in the ring-shaped region.

[0056] From the above, it can be seen that the CAC-OS in the In-Ga-Zn oxide has a structure in which the metal elements are uniformly distributed. It has a different structure from IGZO compounds and has different properties from IGZO compounds. CAC-OS in In-Ga-Zn oxide is mainly composed of oxides containing gallium. In a certain area, X2 Zn Y2 O Z2 , or InO X1 The region where is the principal component and The structure is such that the regions containing each element as the main component are arranged in a mosaic pattern.

[0057] Here, In X2 Zn Y2 O Z2 , or InO X1 The area where is the main component is gallium. This region has higher conductivity than the region where the main component is an oxide containing In. X2 Zn Y2 O Z2 , or InO X1 The carriers flow through the area where As a result, the conductivity of the oxide semiconductor is exhibited. X2 Zn Y2 O Z2 ,Also InO X1 The region where the main component is distributed in a cloud-like shape in the oxide semiconductor allows for high High field effect mobility (μ) can be achieved. X2 Zn Y2 O Z2 , or InO X The region where 1 is the main component can be said to be a semiconductor region, with properties similar to those of a conductor.

[0058] On the other hand, the region where the main component is oxides containing gallium is In X2 Zn Y2 O Z2 ,Also InO X1 This is a region with higher insulating properties compared to the region where gallium is the main component. The distribution of regions in the oxide semiconductor that are mainly composed of oxides containing silicon reduces leakage current. This suppresses current and achieves good switching operation. a Ga b Zn c O d etc. The region where this is the main component can be said to be a semiconductor region, with properties close to those of an insulator.

[0059] Therefore, when the CAC-OS of In-Ga-Zn oxide is used in a semiconductor device, The insulating properties caused by oxides containing In X2 Zn Y2 O Z2 , or InO X1 The conductivity due to the gate insulating layer and the gate insulating layer work in a complementary manner, resulting in a high on-state current (I on ), high voltage Field-effect mobility (μ) and low off-state current (I off ) can be realized.

[0060] In addition, semiconductor devices using CAC-OS, an In-Ga-Zn oxide, have high reliability. Therefore, the CAC-OS of In-Ga-Zn oxide is expected to be used in a wide range of applications, including displays. It is ideal for a variety of semiconductor devices.

[0061] <Transistors with metal oxides> Next, a case where the above metal oxide is used as a semiconductor in a transistor will be described.

[0062] Note that by using the above metal oxide as a semiconductor in a transistor, the field-effect mobility can be increased. This makes it possible to realize a transistor with low resistance and high switching characteristics. It is possible to realize a transistor with high performance.

[0063] FIG. 2(A) is a schematic diagram of a transistor using the above metal oxide in the channel region. In 2(A), the transistor has a source, a drain, a first gate, and a second gate. The transistor has a gate, a first gate insulating portion, a second gate insulating portion, and a channel portion. The resistance of the channel of a transistor can be controlled by applying a potential to the gate. That is, the potential applied to the first gate or the second gate changes the source and drain Controls the conduction (transistor on) and non-conduction (transistor off) between It is possible.

[0064] Here, the channel portion is made up of a region 001 having a first band gap and a region 002 having a second band gap. The first area has a cloud-like CAC-OS. The band gap of the first semiconductor layer is larger than the band gap of the second semiconductor layer.

[0065] For example, an In-Ga-Zn oxide (CAC) structure can be used as the CAC-OS for the channel region. The case where an In-Ga-Zn oxide having a CAC structure is used will be explained. 01, which has a higher Ga concentration than region 002. a Ga b Zn c O d The main component is Region 002 has a higher In concentration than region 001. X2 Zn Y2 O Z2 , or InO X1 The material is separated into areas where the main component is a mosaic, In a Ga b Zn c O d and InO X1 , or In X2 Zn Y2 O Z2 is distributed in the membrane It is a cloud-like structure. a Ga b Zn c O d Area 00 with 1 is In X2 Zn Y2 O Z2 , or InO X1 is larger than the area 002 where It has a large band gap.

[0066] Here, the conduction model of the transistor shown in Figure 2(A) having a CAC-OS in the channel region is FIG. 2B shows the source and drain of the transistor shown in FIG. 2(C) is a schematic diagram illustrating the distribution of energy levels between In the transistor shown in (A), the conduction band diagram is along the solid line indicated by X-X'. In each conduction band diagram, the solid line indicates the energy at the bottom of the conduction band. f in The dashed line in the figure indicates the energy of the quasi-Fermi level of electrons. A negative voltage is applied between the gate and source as the gate voltage, and a negative voltage is applied between the source and drain. The drain voltage (V d >0) is applied.

[0067] When a negative gate voltage is applied to the transistor shown in Figure 2(A), the transistor shown in Figure 2(B) As shown in the figure, the energy C B 001 and the conduction band edge energy CB originating from region 002 002 and is formed Here, the first band gap is larger than the second band gap, so the conduction band edge Energy CB 001 The potential barrier at the bottom of the conduction band is 00 2. In other words, the maximum potential barrier in the channel The largest value is the value due to the area 001. Therefore, when CAC-OS is used for the channel part, This makes it possible to suppress leakage current and provide a transistor with high switching characteristics.

[0068] As shown in FIG. 2(C), the region 001 having the first band gap is Since the band gap is relatively wider than that of the region 002 having a band gap, the first band gap The Ec edge of the first bandgap region 001 is located at the Ec edge of the second bandgap region 002. It can be located relatively higher than the Ec edge.

[0069] For example, if the component of the region 001 having the first band gap is In-Ga-Zn oxide ( In:Ga:Zn=1:1:1 [atomic ratio]) and a region with a second band gap Let us assume that the component of region 002 is In-Zn oxide (In:Zn=2:3 [atomic ratio]). In this case, the first band gap is set to 3.3 eV or thereabouts, and the second band gap is set to 0.5 eV or thereabouts. The band gap of is 2.4 eV or close to it. The value of the band gap is The values ​​used are those obtained by measuring a single film of each material with an ellipsometer.

[0070] In the above assumption, the difference between the first band gap and the second band gap is 0.9 eV. In one aspect of the present invention, the first band gap and the second band gap The difference between the first band gap and the second band gap is at least 0.1 eV. The energy position of the valence band top originating from region 001 and the second band gap The energy position of the top of the valence band due to the region 002 may differ. The difference between the first band gap and the second band gap is preferably 0.3 eV or more, and more preferably 0.3 eV or more. It is particularly preferable that the value is 0.4 eV or more.

[0071] In addition, under the above assumption, when carriers flow during CAC-OS, the second band gap narrowband Carriers flow due to the In-Zn oxide. The first band gap, i.e., the wide band, is the In-Ga-Zn oxide side. In other words, the narrow band In-Zn oxide generates more carriers. The carriers are easily transferred to the wideband In-Ga-Zn oxide.

[0072] In the metal oxide forming the channel portion, the region 001 and the region 002 are metal oxides. The area 001 and the area 002 are irregularly distributed. The conduction band diagram on the solid line indicated by -X' is an example.

[0073] Basically, as shown in Figure 3(A), region 002 forms a band sandwiched between region 001. Alternatively, it is sufficient if the region 001 forms a band sandwiched between the regions 002. .

[0074] In addition, in the actual CAC-OS, there are two regions, 001 with the first band gap and 002 with the second band gap. The junction with the region 002, which has a gap, shows fluctuations in the aggregation morphology and composition of the region. Therefore, as shown in Figure 3(B) and Figure 3(C), the bands are discontinuous. In other words, the carrier flow during CAC-OS may be continuous. In other words, the first band gap and the second band gap are linked when good.

[0075] 4 shows the structure of the transistor shown in FIG. 2(B) in the direction indicated by X-X' of the transistor shown in FIG. 2(A). The schematic band diagram model corresponding to the schematic diagram is shown. When applying a voltage to the first gate, the same voltage is also applied to the second gate. 1 gate voltage V g As a result, a positive voltage (V g >0) is applied FIG. 4(B) shows the ON state of the first gate voltage V g Do not apply I(V g =0). g As a gate and A negative voltage (V g <0) is applied (OFF State) In the channel region, the dashed line indicates the energy at the bottom of the conduction band when no voltage is applied. The solid line shows the energy at the bottom of the conduction band when a voltage is applied. f The dashed line indicates the energy of the electron quasi-Fermi level.

[0076] A transistor having a CAC-OS channel region has a first band gap region. The region 001 and the region 002 having the second band gap interact electrically. In other words, there is a region 001 having a first band gap and a region 002 having a second band gap. Area 002 functions complementarily.

[0077] That is, as shown in FIG. 4(A), when a forward voltage is applied, the conduction band of region 002 and The conduction band of region 001 is lower than that of region 002. It is thought that a large on-current can be obtained by carriers flowing in the conduction band of region 001. On the other hand, as shown in Figure 4(B) and Figure 4(C), when a reverse voltage is applied, , the conduction band of region 001 and region 002 rises, and therefore, The current is expected to be extremely small.

[0078] 5, on the solid line indicated by X-X' of the transistor shown in FIG. 2(A), The schematic band diagram model corresponding to the schematic diagram shown in C) is shown. When a voltage is applied to the first electrode, the same voltage is simultaneously applied to the second gate electrode. 5(A) shows the first gate voltage V g As a result, a positive voltage (V g 5B shows the state where the first gate voltage (V) is applied (ON state). Pressure V g Do not apply (V g =0). g and A negative voltage (V g <0) is applied (OFF S In the channel region, the solid line indicates the energy at the bottom of the conduction band. Also, E fThe dashed line indicates the energy of the quasi-Fermi level of electrons. The difference between the energy of the conduction band minimum of 01 and the energy of the conduction band minimum of region 002 is ΔEc. Furthermore, ΔEc(Vg=0) is the value when no voltage is applied (V g =0) state ΔEc, ΔEc( Vg>0) is the voltage that turns on the transistor (V g >0) is applied. Ec, ΔEc (Vg<0) is a negative voltage (V g <0) is applied. Refers to...

[0079] As shown in FIG. 5(A), the potential (V g >0) is the first gate When applied to the terminal, ΔEc(Vg>0)<ΔEc(Vg=0). The second band gap region 002 with a lower band gap is the main conduction path, and electrons flow through it. At the same time, electrons also flow into the region 001 having the first band gap. High current driving capability in the on-state of the transistor, i.e., large on-current and high field-effect mobility You can get a degree.

[0080] On the other hand, as shown in FIG. 5(B) and FIG. 5(C), when a voltage lower than the threshold voltage is applied to the first gate, Voltage (V g By applying a voltage of 0.5 V or less, the region 001 having the first band gap is Since the second region acts as an insulator, the conduction path in the region 001 is blocked. The region 002 having a band gap is adjacent to the region 001 having a first band gap. Therefore, the region 001 with the first band gap has a second band gap in addition to itself. The second band gap region 002 electrically interacts with the first band gap region 003, forming a second band gap region 004. This blocks the conduction path in the region 002, which is connected to the channel. Therefore, ΔEc(Vg=0)<ΔEc(Vg<0). become.

[0081] As described above, by using CAC-OS in a transistor, when the transistor is operating, for example, When a potential difference occurs between the gate and the source or drain, can reduce or prevent leakage current between the drain and

[0082] Furthermore, it is preferable to use a metal oxide with a low carrier density for the transistor. Highly pure or substantially highly pure intrinsic metal oxides have fewer carrier sources, making them less likely to generate carriers. The carrier density can be reduced. Metal oxides have a low density of defect states, and therefore may also have a low density of trap states.

[0083] In addition, the charges trapped in the trap levels of metal oxides take a long time to disappear. Therefore, gold, which has a high density of trap states, Transistors with a channel region formed in a metal oxide may have unstable electrical characteristics. do.

[0084] Therefore, in order to stabilize the electrical characteristics of the transistor, it is necessary to lower the impurity concentration in the metal oxide. In addition, in order to reduce the impurity concentration in the metal oxide, it is effective to reduce the It is also preferable to reduce the impurity concentration in the film. Examples include alkaline earth metals, iron, nickel, and silicon.

[0085] Here, the influence of each impurity in the metal oxide will be described.

[0086] When metal oxides contain silicon or carbon, which are elements of Group 14, they can be easily converted into metal oxides. Defect levels are formed in the material. Therefore, the concentration of silicon and carbon in the metal oxide The concentration of silicon and carbon near the interface with the metal oxide was measured by secondary ion mass spectrometry (SIMS). : Secondary Ion Mass Spectrometry) concentration) to 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0087] In addition, when alkali metals or alkaline earth metals are contained in metal oxides, defect levels are formed. Therefore, alkali metals or alkaline earth metals may be included. Transistors using metal oxides containing SiO2 tend to be normally-on. Therefore, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the metal oxide. Specifically, the alkali metal or alkaline earth in the metal oxide obtained by SIMS The concentration of metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 ato ms / cm 3 The following applies.

[0088] In addition, the hydrogen contained in the metal oxide reacts with the oxygen that bonds with the metal atom to form water, Oxygen deficiency (V o ) may be formed. o ) hydrogen enters the In some cases, rear electrons are generated. Also, some of the hydrogen atoms bond with oxygen atoms that bond with metal atoms. It can bond with hydrogen to generate electrons, which are carriers. Transistors using oxides tend to be normally-on. It is preferable that the hydrogen content in the metal oxide is reduced as much as possible. The hydrogen concentration obtained by SIMS was 1×10 20 atoms / cm 3 Less than, preferably is 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than.

[0089] In addition, oxygen vacancies (V o ) can be reduced by introducing oxygen into metal oxides. In other words, oxygen vacancies (V o ) is supplemented with oxygen , oxygen deficiency (V o ) disappears. Therefore, by diffusing oxygen into the metal oxide, Oxygen deficiency (V o ) can be reduced and reliability can be improved.

[0090] As a method for introducing oxygen into a metal oxide, for example, a method for introducing oxygen into a metal oxide by stoichiometry may be used. It is possible to provide an oxide containing more oxygen than meets the oxygen requirement. In some materials, there is a region where oxygen exists in excess of the stoichiometric composition (hereinafter referred to as the excess oxygen region). In particular, when a metal oxide is used in a transistor, it is preferable that a metal oxide is formed on the surface of the transistor. By providing an oxide with excess oxygen regions in the underlayer film near the transistor or in the interlayer film, This can reduce oxygen vacancies in the transistor and improve reliability.

[0091] By using metal oxide with sufficiently reduced impurities in the channel region of a transistor, stable It is possible to impart specific electrical properties.

[0092] <Metal oxide film formation method> An example of a method for forming a metal oxide film will be described below.

[0093] The temperature when forming the metal oxide film is preferably set to be equal to or higher than room temperature and lower than 140°C. Note that room temperature refers not only to the case where temperature control is not performed, but also to the case where temperature control is performed, such as by cooling the substrate. This also includes cases where:

[0094] The sputtering gas may be a rare gas (typically argon), oxygen, or a mixture of a rare gas and oxygen. Mixed gas is used appropriately. In the case of mixed gas, the ratio of oxygen gas in the entire deposition gas is 0%. The content is set to 30% or less, preferably 5% or more and 20% or less.

[0095] If oxygen is included in the sputtering gas, the metal oxide film is deposited and the underlying film is also deposited. In addition, oxygen can be added to provide an excess oxygen region. For example, oxygen gas and argon gas used as sputtering gases are , the dew point is -40°C or less, preferably -80°C or less, more preferably -100°C or less, Preferably, gases purified to temperatures below -120°C are used to prevent moisture and other substances from entering the metal oxide. It is possible to prevent it from being captured as much as possible.

[0096] In addition, when forming a metal oxide film by sputtering, The member uses a cryopump to remove as much water as possible, which is an impurity for metal oxides. A high vacuum (5×10 -7 Pa to 1 x 10 -4 P It is preferable to evacuate the gas to a temperature of about 1000°C. Alternatively, a turbomolecular pump and a cold trap can be used. In combination, this prevents gases, especially those containing carbon or hydrogen, from flowing back into the chamber from the exhaust system. It is preferable to keep this in mind.

[0097] In addition, an In-Ga-Zn metal oxide target can be used as the target. For example, [In]:[Ga]:[Zn]=4:2:4.1 [atomic ratio], or [In ]:[Ga]:[Zn]=5:1:7 [atomic ratio] or a value close to that. It is preferable to use a metal oxide target.

[0098] In addition, the target may be rotated or moved in the sputtering device. For example, by swinging the magnet unit up and down and / or left and right during film formation, For example, the target can be heated at a frequency of 0.1 Hz or more to form the composite metal oxide of the present invention. Beats (also called rhythms, beats, pulses, frequencies, periods, or cycles) above 1 kHz You can also change the magnet unit by rotating or oscillating it with a 0. It is sufficient to oscillate it at a beat of 1 Hz or more and 1 kHz or less.

[0099] For example, the sputtering gas may be a rare gas with an oxygen gas ratio of about 10% and a Using a mixed gas, the substrate temperature was 130°C, and the ratio of [In]:[Ga]:[Zn] was 4:2:4. Film formation is performed by oscillating an In-Ga-Zn metal oxide target with an atomic ratio of 0.1. In this way, the metal oxide of the present invention can be formed.

[0100] As described above, the structure shown in this embodiment may be appropriately combined with structures shown in other embodiments or examples. They can be used in combination.

[0101] (Embodiment 2) In this embodiment, a semiconductor device and a manufacturing method of the semiconductor device according to one embodiment of the present invention will be described. 6 to 15.

[0102] <2-1. Configuration example 1 of semiconductor device> FIG. 6A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention. FIG. 6(B) corresponds to a cross-sectional view taken along the dashed line X1-X2 shown in FIG. 6(A). 6(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line Y1-Y2 shown in FIG. 6(A). In FIG. 6A, for simplicity, the transistor 100 Some of the components (such as an insulating film that functions as a gate insulating film) are omitted in the illustration. , the dashed dotted line X1-X2 direction is the channel length direction, and the dashed dotted line Y1-Y2 direction is the channel width direction. In the top view of the transistor, As in FIG. 6(A), some of the components may be omitted in the illustration.

[0103] The transistor 100 shown in FIGS. 6(A), 6(B), and 6(C) is a so-called top-gate structure transistor. It is a star.

[0104] The transistor 100 includes an insulating film 104 on a substrate 102 and a metal oxide film 105 on the insulating film 104. 08, an insulating film 110 on the metal oxide 108, a conductive film 112 on the insulating film 110, and an insulating The insulating film 116 is formed on the conductive film 112 , the metal oxide film 104 , and the conductive film 112 .

[0105] The metal oxide 108 has a region overlapping with the conductive film 112 with the insulating film 110 interposed therebetween. For example, the metal oxide 108 may be a mixture of In, M (wherein M is Al, Ga, Y, or Sn), and Zn and is preferably contained.

[0106] The metal oxide 108 is formed in a region where the conductive film 112 does not overlap and where the insulating film 116 is in contact with the metal oxide 108. The region 108n has the metal oxide 108 described above. The region 108n is an n-type region. The region 108n is in contact with the insulating film 116. Therefore, the nitrogen or hydrogen in the insulating film 116 is transferred to the region 108n. By adding this, the carrier density increases and the material becomes n-type.

[0107] In addition, the metal oxide 108 preferably has a region in which the atomic ratio of In is greater than the atomic ratio of M. For example, the ratio of the number of atoms of In, M, and Zn in the metal oxide 108 is set to In:M It is preferable that the ratio is approximately Zn=4:2:3.

[0108] The metal oxide 108 is not limited to the above composition. For example, the metal oxide 108 may have a composition of I The atomic ratio of n, M, and Zn may be approximately In:M:Zn=5:1:6. In the vicinity, when In is 5, M is 0.5 or more and 1.5 or less, and Zn is 5 or more and 7 or less. Including below.

[0109] The metal oxide 108 has a region in which the atomic ratio of In is greater than the atomic ratio of M, and thus the transistor The field effect mobility of the transistor 100 can be increased. The field-effect mobility of 00 is 10 cm 2 / V s More preferably, the transistor 10 0 field-effect mobility is 30 cm 2 / V s It is possible to exceed this.

[0110] For example, the above-mentioned high field effect mobility transistor is connected to a gate driver that generates a gate signal. By using this in a display device, it is possible to provide a display device with a narrow frame width (also called a narrow frame). In addition, the above-described transistor having high field effect mobility can be used as a signal line for a display device. The source driver (especially the output of the shift register of the source driver) By using it in a demultiplexer connected to the terminal, the number of wires connected to the display device can be reduced. It is possible to provide a display device that does not

[0111] On the other hand, the metal oxide 108 has a region in which the atomic ratio of In is greater than the atomic ratio of M. However, if the crystallinity of the metal oxide 108 is high, the field-effect mobility may be reduced.

[0112] The crystallinity of the metal oxide 108 can be determined by, for example, X-ray diffraction (XRD). If fraction, or transmission electron microscopy (TEM) Analysis using a transmission electron microscope It can be analyzed as follows.

[0113] First, oxygen vacancies that can be formed in the metal oxide 108 will be described.

[0114] The oxygen vacancies formed in the metal oxide 108 are problematic because they affect the transistor characteristics. For example, when oxygen vacancies are formed in the metal oxide 108, hydrogen bonds to the oxygen vacancies. When a carrier source is generated in the metal oxide 108, the metal The variation in the electrical characteristics of the transistor 100 with the oxide 108, typically the threshold voltage, Therefore, it is preferable that the metal oxide 108 has fewer oxygen vacancies. It's nice.

[0115] Therefore, in one aspect of the present invention, the insulating film in the vicinity of the metal oxide 108, specifically, the metal The insulating film 110 formed above the oxide 108 and the insulating film 110 formed below the metal oxide 108 Either one or both of the insulating films 104 contains excess oxygen. Oxygen or excess oxygen is introduced into the metal oxide 108 from either or both of the insulating film 110 and the insulating film 110. By moving the atoms, it is possible to reduce oxygen vacancies in the metal oxide.

[0116] Impurities such as hydrogen or moisture mixed into the metal oxide 108 affect the transistor characteristics. Therefore, in the metal oxide 108, hydrogen or moisture etc. The fewer the impurities, the better.

[0117] The metal oxide 108 is a metal oxide having a low impurity concentration and a low defect level density. By using this, a transistor having excellent electrical characteristics can be manufactured. Here, the low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or substantially high purity intrinsic. High purity intrinsic or substantially high purity intrinsic metal oxide Since the material has a small number of carrier generation sources, the carrier density can be reduced. Transistors with a channel region formed in metal oxide have a negative threshold voltage. Electrical characteristics (also called normally-on) are rarely observed. Qualitatively high-purity intrinsic metal oxides have low defect level density, and therefore low trap level density. In addition, high-purity intrinsic or substantially high-purity intrinsic metal oxides may be The current is extremely small, and the channel width is 1×10 6 The device has a channel length of 10 μm and a However, the voltage between the source and drain electrodes (drain voltage) is in the range of 1V to 10V. In this case, the off-state current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×10 - 13 It can achieve a characteristic of A or below.

[0118] As shown in FIGS. 6A, 6B, and 6C, the transistor 100 has a structure in which the insulating film 116 The insulating film 118 and the opening 141a formed in the insulating films 116 and 118 are connected to the region 10 A conductive film 120a electrically connected to the insulating film 8n and an opening formed in the insulating films 116 and 118 and a conductive film 120b electrically connected to the region 108n via a conductive film 141b. Good too.

[0119] In this specification and the like, the insulating film 104 is referred to as a first insulating film, and the insulating film 110 is referred to as a second insulating film. The insulating film 116 is referred to as the third insulating film, and the insulating film 118 is referred to as the fourth insulating film. The conductive film 112 may function as a gate electrode. The conductive film 120b functions as a source electrode, and the conductive film 120c functions as a drain electrode. do.

[0120] The insulating film 110 also functions as a gate insulating film. The insulating film 110 has an excess oxygen region. Therefore, oxygen vacancies that may be formed in the metal oxide 108 can be eliminated. To provide a highly reliable semiconductor device since the loss can be compensated for by excess oxygen. can be done.

[0121] In order to supply excess oxygen into the metal oxide 108, Excess oxygen may be supplied to the insulating film 104. The excess oxygen may also be supplied to region 108n. On the other hand, if the metal oxide 108 is formed on the surface of the metal oxide 108, the resistance in the region 108n becomes high, which is undesirable. By forming the insulating film 110 on the insulating film 110 side to contain excess oxygen, the insulating film 110 overlaps with the conductive film 112. This makes it possible to selectively supply excess oxygen only to the region where the oxygen is to be removed.

[0122] <2-2. Components of semiconductor device> Next, the components included in the semiconductor device of this embodiment will be described in detail.

[0123] [substrate] There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. It must be heat resistant. For example, glass substrates, ceramic substrates, quartz substrates, and surface treatment substrates are A fiber substrate or the like may be used as the substrate 102. Also, silicon or silicon carbide may be used as the material. Single crystal semiconductor substrates, polycrystalline semiconductor substrates, and compound semiconductor substrates such as silicon germanium It is also possible to apply a substrate, an SOI substrate, etc., on which a semiconductor element is provided. The substrate 102 may be a glass substrate. In this case, the 6th generation (1500mm x 1850mm) and 7th generation (1870mm x 2200 mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 2800 By using large area substrates such as 10th generation (2950mm x 3400mm), It is possible to fabricate a display device of this type.

[0124] In addition, a flexible substrate is used as the substrate 102, and the transistor 100 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100. The release layer is used to separate the semiconductor device from the substrate 102 after a part or all of the semiconductor device is completed thereon. The transistor 100 can be separated and transferred to another substrate. It can also be transferred to less rigid or flexible substrates.

[0125] [First insulating film] The insulating film 104 can be formed by a method such as sputtering, CVD, evaporation, or pulsed laser deposition (P The insulating film 104 can be formed by appropriately using a laser diode (LD) method, a printing method, a coating method, or the like. For example, a single layer or a stacked layer of an oxide insulating film or a nitride insulating film can be formed. In order to improve the interface characteristics with the metal oxide 108, the insulating film 104 At least a region in contact with the metal oxide 108 is preferably formed of an oxide insulating film. In addition, by using an oxide insulating film that releases oxygen by heating as the insulating film 104, Therefore, oxygen contained in the insulating film 104 can be transferred to the metal oxide 108. do.

[0126] The thickness of the insulating film 104 is 50 nm or more, or 100 nm or more and 3000 nm or less, or The thickness of the insulating film 104 can be set to 200 nm or more and 1000 nm or less. The amount of oxygen released from the insulating film 104 can be increased, and the insulating film 104 and the metal oxide The interface state at the interface with the metal oxide 108 and the oxygen vacancies in the metal oxide 108 are reduced. It is possible to do this.

[0127] The insulating film 104 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. Silicon, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide The insulating film 1 may be formed as a single layer or a multilayer. As the layer 04, a laminated structure of a silicon nitride film and a silicon oxynitride film is used. The insulating film 104 has a laminated structure, with a silicon nitride film on the lower layer and a silicon oxynitride film on the upper layer. By using the silicon film, oxygen can be efficiently introduced into the metal oxide 108.

[0128] [Conductive film] A conductive film 112 functions as a gate electrode, a conductive film 120a functions as a source electrode, and a conductive film 120b functions as a source electrode. The conductive film 120b that functions as a rain electrode may be made of chromium (Cr), copper (Cu), aluminum (Al), or the like. Aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tungsten Ta (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (N i), iron (Fe), cobalt (Co), or the above-mentioned metal elements The alloys can be formed using alloys containing the above-mentioned metal elements or alloys combining the above-mentioned metal elements. This can be done.

[0129] The conductive films 112, 120a, and 120b are made of an oxide containing indium and tin (In -Sn oxide), oxide containing indium and tungsten (In-W oxide), In oxides containing indium, tungsten and zinc (In-W-Zn oxides), indium and oxides containing indium and titanium (In-Ti oxides), oxides containing indium, titanium, and tin oxides containing indium and zinc (In-Ti-Sn oxides), ), oxides containing indium, tin and silicon (In-Sn-Si oxide), indium Oxide conductors such as oxides containing aluminum, gallium, and zinc (In-Ga-Zn oxide) Metal oxides can also be used.

[0130] Here, the oxide conductor will be described. In this specification and the like, the oxide conductor is referred to as OC( The oxide conductor may be, for example, When oxygen vacancies are formed in a metal oxide and hydrogen is added to the oxygen vacancies, donor states appear near the conduction band. As a result, the metal oxide becomes electrically conductive. In general, metal oxides can be called oxide conductors. On the other hand, oxide conductors have a large conduction gap, making them transparent to visible light. Therefore, oxide conductors are metal oxides that have donor levels near the band. The influence of absorption due to position is small, and the transparency to visible light is comparable to that of metal oxides.

[0131] In particular, when the conductive film 112 is made of the above-mentioned oxide conductor, excess oxygen is added to the insulating film 110. This is preferable because it can

[0132] The conductive films 112, 120a, and 120b are made of a Cu-X alloy film (X is Mn, Ni, C r, Fe, Co, Mo, Ta, or Ti) may be used. This allows for processing using a wet etching process, which reduces manufacturing costs. It becomes Noh.

[0133] Furthermore, the conductive films 112, 120a, and 120b contain titanium, among the above-mentioned metal elements. Contains one or more selected from tungsten, tantalum, and molybdenum. In particular, the conductive films 112, 120a, and 120b are preferably made of tantalum nitride films. The tantalum nitride film is electrically conductive and has high resistance to copper and hydrogen. Furthermore, the tantalum nitride film has high barrier properties. Therefore, the conductive film in contact with the metal oxide 108 or the conductive film in the vicinity of the metal oxide 108 It can be suitably used as such.

[0134] The conductive films 112, 120a, and 120b can also be formed by electroless plating. Materials that can be formed by the electroless plating method include, for example, Cu, Ni, Al, and A. Use one or more selected from the group consisting of u, Sn, Co, Ag, and Pd. In particular, the resistance of the conductive film can be reduced by using Cu or Ag. Therefore, it is preferable.

[0135] [Second insulating film] The insulating film 110 that functions as the gate insulating film of the transistor 100 is formed by plasma chemical Plasma Enhanced Chemical Vapor Deposition (PECVD) or Deposition) method, sputtering method, etc., to form a silicon oxide film, an oxide Silicon nitride film, silicon oxynitride film, silicon nitride film, aluminum oxide film, oxide hafnium tungsten oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film , magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film The insulating film 110 may have a two-layer structure or a three-layer structure. The above laminated structure may also be used.

[0136] Also, the insulating layer 104 contacts the metal oxide 108 that serves as the channel region of the transistor 100. The film 110 is preferably an oxide insulating film, and contains oxygen in excess of the stoichiometric composition. In other words, the insulating film 110 has a region having an excess oxygen content. The insulating film 110 is an insulating film that can release oxygen. To achieve this, for example, the insulating film 110 is formed in an oxygen atmosphere, or the insulating film 110 after the film formation is 10 may be heat-treated in an oxygen atmosphere.

[0137] Furthermore, when hafnium oxide is used as the insulating film 110, the following effects are achieved. Silicon has a higher dielectric constant than silicon oxide and silicon oxynitride. Compared with the case where silicon dioxide is used, the thickness of the insulating film 110 can be made larger, so that the tunnel current In other words, a transistor with a small off-state current can be produced. Furthermore, hafnium oxide, which has a crystalline structure, can be used to form an amorphous structure. It has a higher dielectric constant than hafnium oxide, which has a low off-state current. To form a transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal structure include a monoclinic system and a cubic system. are not limited to these.

[0138] Furthermore, it is preferable that the insulating film 110 has few defects. The signal observed by ESR (Electron Spin Resonance) is small. For example, the signal described above is E, which is observed at a g value of 2.001. The E' center is caused by the dangling bond of silicon. The insulating film 110 has a spin density due to the E' center of 3×10 17 spin s / cm 3 Less than or equal to 5 x 10 16 spins / cm 3 Silicon oxide film Alternatively, a silicon oxynitride film may be used.

[0139] [Metal oxides] As the metal oxide 108, the metal oxides shown above can be used.

[0140] <Atomic ratio> The metal according to the present invention will be described below with reference to FIGS. 16(A), 16(B), and 16(C). A preferred range of the atomic ratio of indium, element M, and zinc contained in the oxide will be explained. In addition, in Fig. 16(A), Fig. 16(B), and Fig. 16(C), the atomic ratio of oxygen is In addition, the number of atoms of indium, element M, and zinc contained in the metal oxide is not described. The respective terms in the ratio are [In], [M], and [Zn].

[0141] In Figures 16(A), 16(B), and 16(C), the dashed lines represent the [In]:[M] :[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):2 is n]:[M]:[Zn]=(1+α):(1-α):3, ]:[M]:[Zn]=(1+α):(1-α):4 atomic ratio, and [ The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):5 is shown. .

[0142] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=5:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=2:1:β is :[M]:[Zn]=1:1:β atomic ratio line, [In]:[M]:[Zn] = 1:2:β atomic ratio line, [In]:[M]:[Zn]=1:3:β atoms and the line where the atomic ratio is [In]:[M]:[Zn]=1:4:β. Represents in.

[0143] In addition, the [In]:[M]:[ The metal oxides with an atomic ratio of Zn=0:2:1 and those with values ​​close to this ratio have a spinel-type crystal structure. It is easy to make.

[0144] In addition, multiple phases may coexist in metal oxides (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic ratio is close to [In]:[M]:[Zn]=0:2:1, spinel Two phases, a type crystal structure and a layered crystal structure, tend to coexist. When the value of [M]:[Zn] is close to 1:0:0, the bixbyite-type crystal structure and layered When multiple phases coexist in a metal oxide, different crystal structures are likely to coexist. Grain boundaries may form between the structures.

[0145] The region A shown in FIG. 16(A) is a region of indium, element M, and zinc contained in the metal oxide. An example of a preferred range of the atomic ratio is shown.

[0146] By increasing the indium content of metal oxides, the carrier mobility (electron Therefore, metal oxides with a high indium content can The carrier mobility is higher than that of metal oxides with a low indium content.

[0147] On the other hand, when the content of indium and zinc in the metal oxide is low, the carrier mobility is low. Therefore, the atomic ratio [In]:[M]:[Zn]=0:1:0 and its vicinity When the value is (for example, region C shown in FIG. 16(C)), the insulating property is high.

[0148] Therefore, the metal oxide of one embodiment of the present invention has high carrier mobility, and is a region A in FIG. It is preferable that the atomic ratio be:

[0149] In particular, in the region B shown in FIG. 16(B), the carrier mobility is high and the reliability is high even in the region A. An excellent metal oxide with high purity can be obtained.

[0150] Region B is the region where [In]:[M]:[Zn]=4:2:3 to 4.1 and its vicinity. Nearby values ​​include, for example, [In]:[M]:[Zn]=5:3:4. Region B is [In]:[M]:[Zn]=5:1:6 and its neighboring values, [In]:[M]:[Zn]=5:1:7 and its neighboring values.

[0151] The properties of metal oxides are not uniquely determined by the atomic ratio. Even if the metal oxide is a metal oxide, the properties of the metal oxide may differ depending on the formation conditions. When depositing a film using a sputtering device, the atomic ratio of the target is different from the atomic ratio of the target. Also, depending on the substrate temperature during film formation, the film may be formed with a higher concentration of [Zn] than the target [Zn]. Therefore, the region shown is where the metal oxide has a particular property. The boundary between region A and region C is not strict. .

[0152] In addition, when the metal oxide 108 is an In-M-Zn oxide, the sputtering target It is preferable to use a target containing polycrystalline In-M-Zn oxide. The atomic ratio of the metal oxide 108 to be deposited is determined by the ratio of the metal contained in the sputtering target. This includes a ±40% variation in the atomic ratio of metal elements. For example, the ratio of the atomic ratio of metal oxides to the atomic ratio of metal oxides is 108. The composition of the sputtering target is In:Ga:Zn=4:2:4.1 [atomic ratio] In this case, the composition of the metal oxide 108 to be formed is In:Ga:Zn=4:2:3 [number of atoms] In addition, the sputtering target used for the metal oxide 108 may be When the composition of the oxide is In:Ga:Zn=5:1:7 [atomic ratio], the metal oxide film formed is The composition of 08 may be close to In:Ga:Zn=5:1:6 [atomic ratio].

[0153] The metal oxide 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using metal oxides with a wide energy gap, The off-state current of the gate 100 can be reduced.

[0154] The metal oxide 108 preferably has a non-single crystal structure. The CAAC-OS includes a polycrystalline structure, a microcrystalline structure, and an amorphous structure, as described below. In terms of structure, the amorphous structure has the highest density of defect levels.

[0155] [Third insulating film] The insulating film 116 contains nitrogen or hydrogen. For example, the insulating film 116 may be a nitride insulating film. Examples of the nitride insulating film include silicon nitride, silicon nitride oxide, and silicon oxynitride. The insulating film 116 can be formed using silicon or the like. The hydrogen concentration in the insulating film 116 is 1×1 0 22 atoms / cm 3 The insulating film 116 is preferably made of a metal oxide. Therefore, impurities in the region 108n that contacts the insulating film 116 The concentration of impurities (e.g., hydrogen) increases, which can increase the carrier density in the region 108n. .

[0156] [Fourth insulating film] The insulating film 118 can be an oxide insulating film. The insulating film 118 can be a stacked film of an oxide insulating film and a nitride insulating film. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, oxide Hafnium oxide, gallium oxide, Ga-Zn oxide, or the like may be used.

[0157] The insulating film 118 is a film that functions as a barrier film for hydrogen, water, and the like from the outside. It is preferable.

[0158] The thickness of the insulating film 118 is 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less. It can be as follows:

[0159] <2-3. Transistor configuration example 2> Next, regarding the transistors having different structures from those shown in FIGS. 6(A), (B), and (C), the transistors shown in FIG. Explain using B)(C).

[0160] 7A is a top view of the transistor 150, and FIG. 7B is a diagram showing the transistor 150 along the dashed line in FIG. 7A. 7(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 7(A). is.

[0161] The transistor 150 shown in FIGS. 7A, 7B, and 7C includes a conductive film 106 over a substrate 102, The insulating film 104 on the conductive film 106, the metal oxide 108 on the insulating film 104, and the metal oxide 1 08, an insulating film 110 on the insulating film 110, a conductive film 112 on the insulating film 110, an insulating film 104, a metal oxide 108 and an insulating film 116 on the conductive film 112.

[0162] Note that the metal oxide 108 is the same as that of the transistor 100 shown in FIGS. The transistor 150 shown in FIGS. 7A, 7B, and 7C has the same structure as the transistor shown above. In addition to the configuration of the star 100, it has a conductive film 106 and an opening 143.

[0163] The opening 143 is provided in the insulating films 104 and 110. The conductive film 106 has the opening 143. 43, the conductive film 106 is electrically connected to the conductive film 112. The same potential is applied to the conductive film 106 and the conductive film 12. Alternatively, the opening 143 may not be provided and the conductive film 112 may be provided with a different potential. For example, the conductive film 106 may be formed of a light-shielding material. This can suppress light from below from being irradiated onto the second region.

[0164] In addition, in the case of the transistor 150, the conductive film 106 is a first gate electrode (bottom The conductive film 112 functions as a second gate electrode (also referred to as a top gate electrode). The insulating film 104 functions as a first gate insulating film. The insulating film 110 functions as a second gate insulating film.

[0165] The conductive film 106 is made of the same material as the conductive films 112, 120a, and 120b described above. In particular, the conductive film 106 can be formed of a material containing copper, thereby reducing the resistance. For example, the conductive film 106 may be a titanium nitride film or a titanium nitride film. A copper film is provided on a tungsten film or a copper film. b is a laminated structure in which a copper film is provided on a titanium nitride film, a tantalum nitride film, or a tungsten film; In this case, the transistor 150 is preferably used as a pixel transistor and a driver transistor of the display device. By using the conductive film 106 and the conductive film 120 in either one or both of the drive transistors, a, and the parasitic capacitance occurring between the conductive film 106 and the conductive film 120b Therefore, the conductive film 106, the conductive film 120a, and the conductive film 12 0b as the first gate electrode, source electrode, and drain electrode of transistor 150; In addition to being used as a power supply wiring for a display device, a signal supply wiring, or a connection wiring, It can also be used for lines, etc.

[0166] Thus, the transistor 150 shown in FIGS. 7(A), (B), and (C) is the same as the transistor described above. Unlike the transistor 100, the metal oxide 108 has conductive films above and below it that function as gate electrodes. As shown in the transistor 150, the semiconductor device of one embodiment of the present invention has the following structure: A plurality of gate electrodes may be provided.

[0167] As shown in FIGS. 7B and 7C, the metal oxide 108 functions as a first gate electrode. and a conductive film 112 functioning as a second gate electrode. The gate electrode is sandwiched between two conductive films that function as gate electrodes.

[0168] The length of the conductive film 112 in the channel width direction is equal to the length of the metal oxide 108 in the channel width direction. The metal oxide 108 is longer than the conductive layer 110 in the channel width direction. The conductive film 112 and the conductive film 106 are covered with the insulating film 104 and The metal oxide 108 is connected to the insulating film 110 through the opening 143. One of the side surfaces in the channel width direction faces the conductive film 112 with the insulating film 110 sandwiched therebetween. .

[0169] In other words, the conductive films 106 and 112 are formed in the openings provided in the insulating films 104 and 110. The region connected at the portion 143 and positioned outside the side edge of the metal oxide 108 is Has.

[0170] With this structure, the metal oxide 108 included in the transistor 150 can be A conductive film 106 functioning as a first gate electrode and a conductive film functioning as a second gate electrode 112. Like transistor 150, The electric field of the first gate electrode and the second gate electrode forms a metal oxide film on which a channel region is formed. The device structure of the transistor that electrically surrounds the compound 108 is called Surrounded c This can be called a channel (S-channel) structure.

[0171] Since the transistor 150 has an S-channel structure, the conductive film 106 or the conductive An electric field is effectively applied to the metal oxide 108 to induce a channel through the film 112. Therefore, the current driving capability of the transistor 150 is improved, and high on-current characteristics are achieved. In addition, since the on-current can be increased, The transistor 150 can be miniaturized. Since the transistor has a structure in which the conductive film 106 and the conductive film 112 surround the This can increase the mechanical strength of the rotor 150.

[0172] In the channel width direction of the transistor 150, the opening 143 of the metal oxide 108 An opening different from the opening 143 may be formed on the side where the opening is not formed.

[0173] As shown in the transistor 150, a transistor is provided with a semiconductor film sandwiched therebetween. When a pair of gate electrodes are connected, one gate electrode is connected to a signal A and the other gate electrode is connected to a signal B. A fixed potential Vb may be applied to the electrodes. A signal A may be applied to one gate electrode and a signal B may be applied to the other gate electrode. A signal B may be applied to the gate electrode. A fixed potential Va is applied to one of the gate electrodes. The other gate electrode may be given a fixed potential Vb.

[0174] The signal A is, for example, a signal for controlling the conductive state or the non-conductive state. It is a digital signal that takes on two types of potential: potential V1 or potential V2 (V1>V2). For example, the potential V1 may be set to a high power supply potential, and the potential V2 may be set to a low power supply potential. Signal A may be an analog signal.

[0175] The fixed potential Vb is, for example, a potential for controlling the threshold voltage VthA of a transistor. The fixed potential Vb may be the potential V1 or the potential V2. This is preferable because it is not necessary to provide a separate potential generating circuit for generating Vb. The fixed potential Vb may be a potential different from the potential V1 or the potential V2. As a result, the gate-source voltage V The drain current when gs is 0V is reduced, and the leakage current of the circuit having the transistor is reduced. For example, the fixed potential Vb may be set lower than the low power supply potential. In some cases, the threshold voltage VthA can be lowered by increasing the fixed potential Vb. As a result, the drain current is improved when the gate-source voltage Vgs is at a high power supply potential, For example, the fixed potential Vb can be set to a low voltage. It may be higher than the source potential.

[0176] The signal B is, for example, a signal for controlling the conductive state or the non-conductive state. It is a digital signal that takes on two types of potential: potential V3 or potential V4 (V3>V4). For example, the potential V3 may be set to a high power supply potential, and the potential V4 may be set to a low power supply potential. Signal B may be an analog signal.

[0177] If signal A and signal B are both digital signals, signal B has the same digital value as signal A. In this case, the on-state current of the transistor is improved, and the transistor is effectively In this case, the potential V1 and the potential V2 of the signal A can be increased. The potential V2 may be different from the potentials V3 and V4 in the signal B. For example, The gate insulating film corresponding to the gate to which signal B is input corresponds to the gate to which signal A is input. If the gate insulating film is thicker than the gate insulating film, the potential amplitude of signal B (V3-V4) is V1-V2) to prevent the transistor from turning on or off. The influence of signal A on the conduction state must be equal to the influence of signal B on the conduction state. It may be possible.

[0178] If signal A and signal B are both digital signals, signal B will have a different digital value than signal A. In this case, the transistors can be controlled by signals A and B separately. For example, when a transistor is an n-channel transistor, If the signal is a channel type, then only if signal A is at potential V1 and signal B is at potential V3 When the signal A is at potential V2 and the signal B is at potential V4, When only one transistor is in a non-conducting state, the functions of a NAND circuit, NOR circuit, etc. can be achieved with one transistor. In addition, the signal B is a signal for controlling the threshold voltage VthA. For example, the signal B may be a period during which the circuit having the transistor is operating and a period during which the signal B is The signal B may be a signal whose potential is different from that during the period when the circuit is not operating. In this case, signal B may be a signal with a different potential according to the operation mode. In some cases, the potential may not be switched very frequently.

[0179] If both signal A and signal B are analog signals, signal B is an analog signal with the same potential as signal A. signal, an analog signal obtained by multiplying the potential of signal A by a constant, or by adding a constant to the potential of signal A. In this case, the on-current of the transistor increases. This may improve the operating speed of a circuit that includes a transistor. In this case, the transistors are controlled by signals A and B. This can be done separately, and higher functionality may be achieved.

[0180] Signal A may be a digital signal and signal B may be an analog signal. Signal A may be an analog signal and signal B a digital signal.

[0181] When a fixed potential is applied to both gate electrodes of a transistor, the transistor is treated as a resistor element. For example, if a transistor is an n-channel In the case of a transistor, the fixed potential Va or the fixed potential Vb can be increased (decreased). In some cases, the effective resistance of the resistor can be lowered (raised). By making Vb high (low), the In some cases, an effective resistance lower (higher) than that expected may be obtained.

[0182] The other configurations of the transistor 150 are the same as those of the transistor 100 shown above. , has a similar effect.

[0183] An insulating film may be further formed on the transistor 150. The transistor 150 shown in FIG. 1 is formed over the conductive films 120a and 120b and the insulating film 118. It has a membrane 122.

[0184] The insulating film 122 has a function of planarizing unevenness due to transistors and the like. The material 122 may be an insulating material and may be made of an inorganic or organic material. Inorganic materials include silicon oxide films, silicon oxynitride films, silicon nitride oxide films, silicon nitride films, and silicon nitride films. Examples of the organic material include silicon film, aluminum oxide film, and aluminum nitride film. Examples of the material include photosensitive resin materials such as acrylic resin and polyimide resin.

[0185] <2-4. Transistor configuration example 3> Next, regarding a configuration different from that of the transistor 150 shown in FIGS. 7A, 7B, and 7C, FIG. 8 will be described. This will be used to explain.

[0186] 8A and 8B are cross-sectional views of the transistor 160. The top view is the same as that of the transistor 150 shown in FIG. 7A. is omitted.

[0187] The transistor 160 shown in FIGS. 8A and 8B has a stacked structure of the conductive film 112. The shape of the insulating film 110 and the shape of the insulating film 110 are different from those of the transistor 150.

[0188] The conductive film 112 of the transistor 160 is a conductive film 112_1 on the insulating film 110 and a conductive film 112_2 on the insulating film 110. For example, the conductive film 112_1 may be an oxide film. By using a conductive film, excess oxygen can be added to the insulating film 110. The conductive film may be formed by sputtering in an atmosphere containing oxygen gas. The oxide conductive film may be formed of, for example, an oxide containing indium and tin, or a tungsten oxide. Oxides containing tungsten and indium, oxides containing tungsten, indium and zinc oxides containing titanium and indium; oxides containing titanium, indium, and tin; oxides containing indium and zinc, oxides containing silicon, indium, and tin, in Examples of the oxide include oxides containing dium, gallium, and zinc.

[0189] 8B, in the opening 143, the conductive film 112_2 and the conductive film 112_3 are When forming the opening 143, a conductive film that becomes the conductive film 112_1 is formed. After this, an opening 143 is formed, thereby making it possible to obtain the shape shown in FIG. 8(B). When an oxide conductive film is used as the conductive film 112_1, the conductive film 112_2 and the conductive film 106 By using a structure in which the conductive film 112 and the conductive film 106 are connected, the connection resistance between the conductive film 112 and the conductive film 106 can be reduced. This can be done.

[0190] The conductive film 112 and the insulating film 110 of the transistor 160 have a tapered shape. More specifically, the lower end of the conductive film 112 is formed outside the upper end of the conductive film 112. The lower end of the insulating film 110 is formed outside the upper end of the insulating film 110. The lower end of the conductive film 112 is formed at approximately the same position as the upper end of the insulating film 110 .

[0191] The conductive film 112 and the insulating film 110 of the transistor 160 are tapered, Compared with the case where the conductive film 112 and the insulating film 110 of the transistor 160 are rectangular, the insulating film 116 This is preferable because it can improve the covering property.

[0192] The other configurations of the transistor 160 are the same as those of the transistor 150 described above. , has a similar effect.

[0193] <2-5. Manufacturing method of semiconductor device> Next, an example of a method for manufacturing the transistor 150 shown in FIGS. 9 to 11. Note that FIGS. 9 to 11 show a method for manufacturing the transistor 150. 1A and 1B are cross-sectional views in the channel length direction and the channel width direction illustrating a method for manufacturing a semiconductor device according to the present invention.

[0194] First, the conductive film 106 is formed on the substrate 102. Next, the conductive film 106 is formed on the substrate 102. An insulating film 104 is formed on the insulating film 104, and a metal oxide film is then formed on the insulating film 104. The metal film is processed into islands to form metal oxide 108a (see FIG. 9(A)).

[0195] The conductive film 106 can be formed by selecting the above-described material. In this case, the conductive film 106 is formed by depositing tungsten with a thickness of 50 nm using a sputtering apparatus. A laminated film of the film and a copper film having a thickness of 400 nm is formed.

[0196] The conductive film to be formed into the conductive film 106 can be processed by wet etching or dry etching. Either one or both of the wet etching methods may be used. After etching the copper film by etching method, the tungsten film is etched by dry etching method. The conductive film is processed by etching to form a conductive film 106 .

[0197] The insulating film 104 can be formed by a method such as sputtering, CVD, evaporation, or pulsed laser deposition (P The layer can be formed by appropriately using a laser diode (LD) method, a printing method, a coating method, or the like. As the insulating film 104, a silicon nitride film having a thickness of 400 nm was deposited using a PECVD apparatus. A silicon oxynitride film having a thickness of 50 nm is formed.

[0198] After the insulating film 104 is formed, oxygen may be added to the insulating film 104. The oxygen to be added may be an oxygen radical, an oxygen atom, an oxygen atomic ion, an oxygen molecular ion, etc. The methods of addition include ion doping, ion implantation, and plasma treatment. In addition, after forming a film for suppressing oxygen desorption on the insulating film 104, Oxygen may be added to the insulating film 104.

[0199] The film for suppressing the desorption of oxygen mentioned above includes indium, zinc, gallium, tin, and aluminum. , chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungste The insulating film can be formed using a conductive film or a semiconductor film having one or more of the following:

[0200] In addition, when oxygen is added by plasma treatment, the oxygen is excited by microwaves to form high-density oxygen. By generating plasma, the amount of oxygen added to the insulating film 104 can be increased.

[0201] When forming the metal oxide 108a, an inert gas (for example, helium) may be added to the oxygen gas. Gases such as argon gas and xenon gas may be mixed. The ratio of oxygen gas to the total deposition gas when forming a (hereinafter also referred to as oxygen flow ratio) The content is 0% or more and 30% or less, preferably 5% or more and 20% or less.

[0202] The metal oxide 108a is formed under the conditions of a substrate temperature of not less than room temperature and not more than 180°C. Alternatively, the substrate temperature may be set to a temperature between room temperature and 140° C. For example, if the plate temperature is set to be equal to or higher than room temperature and lower than 140° C., productivity is increased, which is preferable.

[0203] The thickness of the metal oxide 108a is 3 nm or more and 200 nm or less, preferably 3 nm or less. The thickness may be set to m or more and 100 nm or less, and more preferably 3 nm or more and 60 nm or less.

[0204] As the substrate 102, a large glass substrate (for example, 6th to 10th generation) is used. In this case, the substrate temperature during the deposition of the metal oxide 108a is set to 200° C. or more and 300° C. or less. In this case, the substrate 102 may be deformed (distorted or warped). When using the above, the substrate temperature during the deposition of the metal oxide 108a is set to 200°C or higher than room temperature. By setting the temperature to less than ° C., deformation of the glass substrate can be suppressed.

[0205] In addition, the sputtering gas must be highly purified. The oxygen gas or argon gas used has a dew point of -40°C or less, preferably -80°C or less, more preferably Preferably, a gas purified to a temperature of -100°C or less, more preferably -120°C or less, is used. This can prevent moisture and the like from being absorbed into the metal oxide as much as possible.

[0206] In addition, when forming a metal oxide film by sputtering, The member uses a cryopump to remove as much water as possible, which is an impurity for metal oxides. A high vacuum (5×10) was created using a vacuum pump of the adsorption type.-7 Pa to 1 x 10 -4 It is preferable to exhaust the gas to a pressure of about 100 Pa. , the partial pressure of gas molecules equivalent to HO (gas molecules equivalent to m / z = 18) in the chamber 1×10 -4 Pa or less, preferably 5 x 10 -5 It is preferable to set it to Pa or less.

[0207] In this embodiment, the conditions for forming the metal oxide 108a are as follows.

[0208] The conditions for forming the metal oxide 108a were as follows: The metal oxide 108a is formed by a sputtering method. The flow rate ratio can be set appropriately. In addition, the pressure inside the chamber is set to 0.6 Pa, 2500W AC power is supplied to the metal oxide target placed inside the sputtering system. By this, an oxide film is formed.

[0209] The formed metal oxide film is processed into the metal oxide 108a by wet etching. Either or both of the dry etching method and the dry etching method may be used.

[0210] After the metal oxide 108a is formed, a heat treatment is performed to dehydrogenate the metal oxide 108a. The temperature of the heat treatment is typically 150° C. or higher, so that the distortion of the substrate is prevented. The temperature is below the melting point, or 250°C or higher and 450°C or lower, or 300°C or higher and 450°C or lower.

[0211] Heat treatment is carried out using rare gases such as helium, neon, argon, xenon, krypton, or nitrogen. Alternatively, heating in an inert atmosphere followed by heating in an oxygen atmosphere may be performed. It is also possible to heat the material in an inert atmosphere or an oxygen atmosphere containing hydrogen, water, etc. The treatment time may be from 3 minutes to 24 hours.

[0212] The heat treatment can be performed using an electric furnace, an RTA device, or the like. Therefore, the heat treatment can be performed at a temperature above the distortion point of the substrate for a short period of time. This can reduce processing time.

[0213] The metal oxide is formed as a film while being heated, or the metal oxide is formed and then subjected to heat treatment. In the metal oxide, the hydrogen concentration obtained by SIMS is 5 × 10 19 atoms / cm 3 or less, or 1 x 10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 or less, or 1 x 10 18 atoms / cm 3 or less, or 5 x 10 17 atom s / cm 3 or less, or 1 x 10 16 atoms / cm 3 It can be as follows:

[0214] Next, an insulating film 110_0 is formed on the insulating film 104 and the metal oxide film 108a (FIG. 9( See B).

[0215] The insulating film 110_0 is a silicon oxide film or a silicon oxynitride film formed by plasma chemical It is formed using a plasma-enhanced chemical vapor deposition (PECVD) system or simply a plasma CVD system. In this case, the source gas may be a deposition gas containing silicon and an oxidizing gas. Representative examples of deposition gases containing silicon include silane, disilane, and the like. Examples of oxidizing gases include silane, trisilane, and fluorinated silane. Examples of oxidizing gases include oxygen, ozone, and monoxide. Examples include dinitrogen and nitrogen dioxide.

[0216] In addition, the flow rate of the oxidizing gas is set to 20 times the flow rate of the deposition gas for the insulating film 110_0. The pressure in the processing chamber is set to 100 Pa or greater but less than 100 times, or 40 times or greater but less than 80 times. By using a PECVD device with a pressure of less than 50 Pa or less, nitroxide with a small amount of defects can be obtained. A silicon dioxide film can be formed.

[0217] In addition, as the insulating film 110_0, a film was placed in the evacuated processing chamber of the PECVD apparatus. The substrate is kept at 280°C or higher and 400°C or lower, and raw material gas is introduced into the processing chamber. The pressure is 20 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 250 Pa or less. By supplying high frequency power to the electrodes installed in the processing chamber, the dense oxide shell is formed. A silicon film or a silicon oxynitride film can be formed.

[0218] The insulating film 110_0 may be formed by a PECVD method using microwaves. Microwaves refer to the frequency range from 300MHz to 300GHz. The electron energy is low and the power used to accelerate the electrons is low. The proportion of molecules that are absorbed is small, so it can be used to dissociate and ionize more molecules, and Therefore, it is possible to excite a high-intensity plasma (high-density plasma). The deposition is less damaged by plasma, and an insulating film 110_0 with fewer defects can be formed. can.

[0219] The insulating film 110_0 can be formed by a CVD method using organic silane gas. The organic silane gas is ethyl silicate (TEOS: chemical formula Si(OC2H5)4). , tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetra Siloxane (TMCTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethylcyclotetrasiloxane dimethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), Silicon-containing compounds such as dimethylaminosilane (SiH(N(CH3)2)3) By using the CVD method with organic silane gas, it is possible to obtain highly insulating films with high coating properties. A velum 110_0 can be formed.

[0220] In this embodiment, a PECVD apparatus is used to form the insulating film 110_0, and an oxide film having a thickness of 100 nm is formed. A silicon nitride film is formed.

[0221] Next, a mask is formed by lithography at a desired position on the insulating film 110_0. By etching the insulating film 110_0 and a part of the insulating film 104, the conductive film 106 is reached. An opening 143 is formed (see FIG. 9(C)).

[0222] The opening 143 can be formed by either wet etching or dry etching. In this embodiment, a dry etching method is used. Then, an opening 143 is formed.

[0223] Next, a conductive film 112 is formed on the conductive film 106 and the insulating film 110_0 so as to cover the opening 143. In addition, when a metal oxide film is used as the conductive film 112_0, for example, When the film 112_0 is formed, oxygen may be added to the insulating film 110_0 (FIG. 9(D)). reference).

[0224] In FIG. 9(D), the oxygen added to the insulating film 110_0 is schematically represented by an arrow. In addition, the conductive film 112_0 is formed so as to cover the opening 143. 106 and the conductive film 112_0 are electrically connected.

[0225] When a metal oxide film is used as the conductive film 112_0, the conductive film 112_0 is formed by is preferably formed by sputtering in an atmosphere containing oxygen gas. By forming the conductive film 112_0 in an atmosphere containing oxygen gas, the insulating film 110_ Oxygen can be suitably added to the conductive film 112_0. The method is not limited to sputtering, and other methods, such as ALD, may also be used.

[0226] In this embodiment, the conductive film 112_0 is formed by sputtering. 100nm In-Ga-Zn oxide IGZO film (In:Ga:Zn=4:2:4 1 (atomic ratio)). Also, before the formation of the conductive film 112_0 or the conductive film 112 After the insulating film 110_0 is formed, oxygen addition treatment may be performed in the insulating film 110_0. The method for this can be the same as the oxygen addition treatment that can be performed after the insulating film 104 is formed. That's fine.

[0227] Next, a mask 140 is formed at a desired position on the conductive film 112_0 by a lithography process. (See Figure 10(A)).

[0228] Next, etching is performed from above the mask 140 to remove the conductive film 112_0 and the insulating film 110_ After the conductive film 112_0 and the insulating film 110_0 are processed, the mask 140 By processing the conductive film 112_0 and the insulating film 110_0, an island-shaped conductive film 112 and an island-shaped insulating film 110 are formed (see FIG. 10(B)).

[0229] In this embodiment, the conductive film 112_0 and the insulating film 112_1 are formed by dry etching. Process 10_0.

[0230] Note that when the conductive film 112_0 and the insulating film 110_0 are processed, the conductive film 112 is formed so as not to overlap with the insulating film 110_0. The thickness of the metal oxide 108a in the conductive film 112_0 may be reduced. When processing the insulating film 110_0, the insulating film 10 in the region where the metal oxide 108a does not overlap is In addition, the thickness of the conductive film 112_0 and the insulating film 110_0 may be reduced. During this process, an etchant or etching gas (e.g., chlorine) is introduced into the metal oxide 108a. The conductive film 112_0 or the insulating film 110_0 is doped with a metal or a metal-containing material. It may be added to the oxide 108.

[0231] Next, the insulating film 116 is formed over the insulating film 104, the metal oxide film 108, and the conductive film 112. Note that by forming the insulating film 116, part of the metal oxide 108a in contact with the insulating film 116 The metal oxide 108a overlapping with the conductive film 112 becomes a region 108n. This is referred to as metal oxide 108 (see FIG. 10(C)).

[0232] The insulating film 116 can be formed by selecting the above-described material. In this case, a silicon nitride oxide film having a thickness of 100 nm is deposited as the insulating film 116 using a PECVD apparatus. In addition, when forming the silicon nitride oxide film, a plasma treatment and a forming The two steps of plasma treatment and film formation are carried out at a temperature of 220°C. Argon gas at a flow rate of 100 sccm and nitrogen gas at a flow rate of 1000 sccm were introduced into the chamber. The pressure in the chamber was set to 40 Pa, and the RF power source (27.12 MHz) was turned on. A power of 1000 W is supplied. For the film formation process, silane gas is used at a flow rate of 50 sccm. Nitrogen gas with a flow rate of 5000 sccm and ammonia gas with a flow rate of 100 sccm were mixed in the chamber. The pressure in the chamber was set to 100 Pa, and the RF power supply (27.12 MH z) is supplied with 1000W of power.

[0233] By using a silicon nitride oxide film as the insulating film 116, the region 1 in contact with the insulating film 116 Nitrogen or hydrogen in the silicon nitride oxide film can be supplied to the insulating film. By setting the temperature at which the insulating film 116 is formed to the above temperature, excess oxygen contained in the insulating film 110 is evaporated to the outside. It is possible to suppress the release of the gas into the body.

[0234] Next, the insulating film 118 is formed over the insulating film 116 (see FIG. 11A).

[0235] The insulating film 118 can be formed by selecting the above-mentioned material. In this case, a silicon oxynitride film having a thickness of 300 nm is deposited as the insulating film 118 using a PECVD apparatus. A film is formed.

[0236] Next, a mask is formed by lithography at a desired position on the insulating film 118, and then the insulating film 1 18 and a part of the insulating film 116 are etched to form an opening 14 reaching the region 108n. 1a and 141b are formed (see FIG. 11(B)).

[0237] The insulating film 118 and the insulating film 116 can be etched by wet etching or Either one or both of the dry etching method and the dry etching method may be used. The insulating film 118 and the insulating film 116 are processed by dry etching.

[0238] Next, a conductive film is formed on the region 108n and the insulating film 118 so as to cover the openings 141a and 141b. The conductive film is then processed into a desired shape to form conductive films 120a and 120b. (See FIG. 11(C)).

[0239] The conductive films 120a and 120b can be formed by selecting the above-mentioned materials. In this embodiment, the conductive films 120a and 120b are formed by a sputtering device. A laminated film of a tungsten film having a thickness of 50 nm and a copper film having a thickness of 400 nm is formed.

[0240] The conductive films 120a and 120b are processed by wet etching. In this embodiment, either one or both of the etching method and the dry etching method may be used. After etching the copper film by wet etching, the tongue is removed by dry etching. The stainless steel film is etched to form conductive films 120a and 120b. .

[0241] Subsequently, an insulating film 122 is formed to cover the conductive films 120a and 120b and the insulating film 118. .

[0242] Through the above steps, the transistor 150 shown in FIGS. 7A, 7B, and 7C can be manufactured. can.

[0243] The films (insulating films, metal oxide films, conductive films, etc.) constituting the transistor 150 include: In addition to the above-mentioned forming methods, sputtering, chemical vapor deposition (CVD), vacuum deposition, and pulse deposition are also available. It can be formed by using a photolithographic laser deposition (PLD) method or an ALD method. The film can be formed by a sputtering method, a plasma deposition method, or a printing method. Chemical vapor deposition (PECVD) is a typical method, but thermal CVD is also acceptable. An example of such a method is metal organic chemical vapor deposition (MOCVD).

[0244] In the thermal CVD method, the chamber is kept at atmospheric pressure or reduced pressure, and the source gas and oxidant are simultaneously mixed in the chamber. The film is formed by sending the gas into the chamber, reacting it near or on the substrate, and depositing it on the substrate. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that defects are not generated due to damage.

[0245] Thermal CVD methods such as MOCVD can be used to form films such as the above-mentioned conductive films, insulating films, and metal oxide films. It can be formed.

[0246] For example, when forming a hafnium oxide film using a film formation device that uses ALD, the solvent and Liquid containing hafnium precursor (hafnium alkoxide, tetrakisdimethylamide hafnium) Hf (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide ) hafnium amide) as a raw material gas and ozone ( Two types of gases are used:

[0247] In addition, when forming an aluminum oxide film using a film formation device that uses ALD, the solvent and Liquid containing aluminum precursor (trimethylaluminum (TMA, Al(CH3)3) Two types of gases are used: vaporized raw material gas (such as HCl) and oxidizing agent (H2O). Examples include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum. Minium tris(2,2,6,6-tetramethyl-3,5-heptanedionate) be.

[0248] In addition, when forming a silicon oxide film using a film forming device that uses ALD, The silane is adsorbed onto the surface to be coated, and oxidizing gas (O2, nitrous oxide) radicals are supplied. and reacts with the adsorbate.

[0249] In addition, when forming a tungsten film using a film formation device that uses ALD, WF6 gas is used. and B2H6 gas are introduced sequentially to form an initial tungsten film, and then WF6 gas and H2 The tungsten film is formed using SiH4 gas instead of B2H6 gas. It may be used.

[0250] In addition, metal oxide films, such as In-Ga-Zn-O films, can be formed using a film formation system that utilizes ALD. In the case of a thin film, an In-O layer is formed using In(CH3)3 gas and O3 gas, and then Then, a GaO layer is formed using Ga(CH3)3 gas and O3 gas, and then Zn(CH 3) The ZnO layer is formed using O2 gas and O3 gas. In addition, it is possible to form an In-Ga-O layer, an In-Zn-O layer, a Ga- A mixed compound layer such as a Zn-O layer may be formed. Note that in place of O3 gas, an inert gas such as Ar may be used. H2O gas obtained by bubbling water with an acid gas may be used, but O3 gas containing no H may also be used. It is preferable to use a sachet.

[0251] <2-6. Transistor configuration example 4> 12A is a top view of the transistor 300A, and FIG. 12B is a top view of the transistor 300A. 12(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. This corresponds to a cross-sectional view taken along the dashed line Y1-Y2 shown in FIG. In order to avoid complication, some of the components of the transistor 300A ( The insulating film that functions as a gate insulating film, etc., is omitted in the illustration. The X2 direction is sometimes called the channel length direction, and the dashed dotted line Y1-Y2 direction is sometimes called the channel width direction. Note that the top views of the transistors in the following drawings are the same as those in FIG. For example, some of the components may be omitted in the illustration.

[0252] The transistor 300A shown in FIG. 12 includes a conductive film 304 on a substrate 302 and a An insulating film 306 on the conductive film 304, an insulating film 307 on the insulating film 306, and a A metal oxide 308, a conductive film 312a on the metal oxide 308, and a conductive film 312b on the metal oxide 308. The transistor 300A has a conductive film 312b. On the metal oxide 308, insulating films 314, 316 and 318 are formed. It will be established.

[0253] In the transistor 300A, the insulating films 306 and 307 are The insulating films 314, 316, and 318 function as gate insulating films for the transistor 3. In addition, in the transistor 300A, the conductive film The film 304 functions as a gate electrode, and the conductive film 312a functions as a source electrode. The conductive film 312b functions as a drain electrode.

[0254] In this specification and the like, the insulating films 306 and 307 are referred to as first insulating films, and the insulating films 314 and 3 The insulating film 16 may be referred to as a second insulating film, and the insulating film 318 may be referred to as a third insulating film.

[0255] The transistor 300A shown in FIG. 12 has a channel-etched transistor structure. The metal oxide of one embodiment of the present invention can be suitably used for a channel-etch transistor. Cut.

[0256] <2-7. Transistor configuration example 5> 13A is a top view of the transistor 300B, and FIG. 13B is a top view of the transistor 300B. 13(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 13(C). 1(A) corresponds to a cross-sectional view taken along the dashed dotted line Y1-Y2.

[0257] The transistor 300B shown in FIG. 13 includes a conductive film 304 on a substrate 302 and a An insulating film 306 on the conductive film 304, an insulating film 307 on the insulating film 306, and a A metal oxide 308, an insulating film 314 on the metal oxide 308, and an insulating film 314 on the insulating film 314. 16 and the metal oxide film 314 through the opening 341 a provided in the insulating film 314 and the insulating film 316. 308, and a conductive film 312a electrically connected to the insulating film 314 and the insulating film 316. and a conductive film 312b electrically connected to the metal oxide 308 through an opening 341b. In addition, on the transistor 300B, more specifically, the conductive films 312a, 312b, and An insulating film 318 is provided on the insulating film 316 .

[0258] In the transistor 300B, the insulating films 306 and 307 are The insulating films 314 and 316 function as gate insulating films for the metal oxide 308. The insulating film 318 functions as a protective insulating film for the transistor 300B. In the transistor 300B, the conductive film 304 functions as a gate electrode. The conductive film 312a functions as a source electrode, and the conductive film 312b functions as a has a function as a drain electrode.

[0259] The transistor 300A shown in FIG. 12 has a channel-etched structure. On the other hand, the transistor 300B shown in FIGS. 13(A), 13(B), and 13(C) has a channel protection structure. The metal oxide of one embodiment of the present invention can also be suitably used in a channel protective transistor. It is possible.

[0260] <2-8. Transistor configuration example 6> 14(A) is a top view of the transistor 300C, and FIG. 14(B) is a top view of the transistor 300C. 14(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 14(C). 1(A) corresponds to a cross-sectional view taken along the dashed dotted line Y1-Y2.

[0261] The transistor 300C shown in FIG. 14 is the same as the transistor 300 shown in FIGS. The shape of the insulating films 314 and 316 differs from that of the transistor 300B. The insulating films 314 and 316 are provided in island shapes on the channel region of the metal oxide 308. The other configurations are similar to those of the transistor 300B.

[0262] <2-9. Transistor configuration example 7> 15(A) is a top view of the transistor 300D, and FIG. 15(B) is a top view of the transistor 300D. 15(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 15(C). 1(A) corresponds to a cross-sectional view taken along the dashed dotted line Y1-Y2.

[0263] The transistor 300D shown in FIG. 15 includes a conductive film 304 over a substrate 302 and a An insulating film 306 on the conductive film 304, an insulating film 307 on the insulating film 306, and a A metal oxide 308, a conductive film 312a on the metal oxide 308, and a conductive film 312b on the metal oxide 308. the metal oxide 308 and the insulating film 314 on the conductive films 312a and 312b; , an insulating film 316 on the insulating film 314, an insulating film 318 on the insulating film 316, and an insulating film 318 on the insulating film 318. The conductive film 320a and the conductive film 320b are also included.

[0264] In the transistor 300D, the insulating films 306 and 307 are The insulating films 314, 316, and 318 function as the first gate insulating film of the transistor. It also functions as a second gate insulating film for the transistor 300D. In the above, the conductive film 304 functions as a first gate electrode, and the conductive film 320a functions as a second gate electrode. The conductive film 320b functions as a second gate electrode, and is also used as a pixel electrode in a display device. The conductive film 312a functions as a source electrode. 312b functions as a drain electrode.

[0265] As shown in FIG. 15(C), the conductive film 320b is formed by insulating films 306, 307, 314, and 3 16, 318 are provided with openings 342b, 342c connected to the conductive film 304. Therefore, the conductive film 320b and the conductive film 304 are given the same potential.

[0266] In the transistor 300D, openings 342b and 342c are provided, and the conductive film 32 0b and the conductive film 304 are connected to each other, but the present invention is not limited to this. For example, Only one of the openings 342b and 342c is formed, and the conductive film 32 0b and the conductive film 304 are connected, or the openings 342b and 342c are not provided. Alternatively, the conductive film 320b may not be connected to the conductive film 304. In the case where the conductive film 320b is not connected to the conductive film 304, the conductive film 320b and the conductive film 304 are Each of them can be given a different potential.

[0267] The conductive film 320b is formed through the openings 342a provided in the insulating films 314, 316, and 318. The conductive film 312b is connected to the conductive film 312b via the conductive film 312b.

[0268] The transistor 300D has the S-channel structure described above.

[0269] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0270] (Embodiment 3) In this embodiment, the semiconductor device of one embodiment of the present invention is used for a display portion of a display device or the like. An example of a display panel that can be used in this manner will be described with reference to FIGS. 17 and 18. The display panel has both a reflective liquid crystal element and a light emitting element, and can be used in both a transmissive mode and a reflective mode. The display panel can display both the metal and the liquid crystal display. The oxide and the transistor including the metal oxide are used as a pixel transistor of a display device. Or to a driver that drives a display device, or an LSI that supplies data to a display device, etc. It can be suitably used.

[0271] <Example of display panel configuration> 17 is a perspective schematic diagram of a display panel 600 according to an embodiment of the present invention. 17, the substrate 651 and the substrate 661 are bonded together. It is indicated by a dashed line.

[0272] The display panel 600 includes a display portion 662, a circuit 659, wiring 666, and the like. For example, a circuit 659, a wiring 666, a conductive film 663 functioning as a pixel electrode, and the like are provided. In addition, Figure 17 shows an example where IC 673 and FPC 672 are mounted on board 651. Therefore, the configuration shown in FIG. 17 is a display panel 600, an FPC 672, and an IC It can also be said to be a display module having 673.

[0273] The circuit 659 can be, for example, a circuit that functions as a scanning line driver circuit.

[0274] The wiring 666 has a function of supplying signals and power to the display portion 662 and the circuit 659. Signals and power are input from the outside via FPC 672 or from IC 673 to wiring 666. .

[0275] In addition, in FIG. 17, a substrate 651 is provided by a COG (Chip On Glass) method or the like. The example in which the IC 673 is provided is shown. The IC 673 is, for example, a scanning line driving circuit or Alternatively, an IC having a function as a signal line driver circuit or the like can be applied. In some cases, the circuit functions as a scanning line driver circuit and a signal line driver circuit. The circuit that functions as the signal line driver circuit is provided externally, and the display panel is connected to the FPC672. When inputting a signal to drive the 600, the configuration without IC673 is Also, IC673 can be mounted on a FP board by using a COF (Chip On Film) method or the like. It may be implemented in C672.

[0276] 17 shows an enlarged view of a part of the display unit 662. The display unit 662 has a plurality of displays. The conductive film 663 included in the element is arranged in a matrix. It has a reflective function and functions as a reflective electrode of the liquid crystal element 640, which will be described later.

[0277] 17, the conductive film 663 has an opening. A light emitting element 660 is provided on the plate 651 side. Light from the light emitting element 660 is incident on the opening of the conductive film 663. It is ejected to the substrate 661 side through the opening.

[0278] <Example of cross-sectional configuration> FIG. 18 shows a part of the area including the FPC 672, the circuit 659, and the like of the display panel shown in FIG. and a part of the area including the display unit 662 are cut away. Here is an example.

[0279] The display panel has an insulating film 620 between a substrate 651 and a substrate 661. Between the insulating film 620 and the light-emitting element 660, the transistor 601, the transistor 605, and the The insulating film 620 and the substrate 661 are connected to each other through a liquid crystal layer 606 and a coloring layer 634. The substrate 661 and the insulating film 620 are bonded to each other by an adhesive layer 641. The substrate 651 and the insulating film 620 are bonded together via an adhesive layer 642 .

[0280] The transistor 606 is electrically connected to the liquid crystal element 640, and the transistor 605 is The transistor 605 and the transistor 606 are both electrically connected to the element 660. Since the insulating film 620 is formed on the surface of the substrate 651, these can be formed using the same process. It can be made.

[0281] The substrate 661 is provided with a colored layer 631, a light-shielding film 632, an insulating film 621, and a liquid crystal element 640. A conductive film 613 functioning as a conducting electrode, an alignment film 633b, an insulating film 617, etc. are provided. The insulating film 617 functions as a spacer to maintain the cell gap of the liquid crystal element 640. do.

[0282] The insulating film 620 is provided on the substrate 651 side with an insulating film 681, an insulating film 682, an insulating film 683, and an insulating film 684. The insulating film 681 has insulating layers such as 684 and insulating film 685. The insulating film 682, the insulating film 683, and the insulating film 684 function as a gate insulating layer of the transistor. The insulating film 684 is covered with an insulating film 685. The insulating films 684 and 685 function as planarization layers. Here, insulating films 682, 683, and 684 are used as insulating layers covering transistors and the like. Although the example shows a case where the membrane 684 has three layers, the present invention is not limited to this and may have four or more layers. The insulating film 684 serving as a planarizing layer may be a single layer or a two-layer. , it does not have to be provided if not required.

[0283] In addition, the transistors 601, 605, and 606 are partially gate-coupled. a conductive film 654 which functions as a gate, and a conductive film 65 which functions as a source or a drain. 2, a semiconductor film 653. Here, multiple layers obtained by processing the same conductive film are The same hatching pattern is used.

[0284] The liquid crystal element 640 is a reflective liquid crystal element. The liquid crystal element 640 is made up of a conductive film 635, a liquid crystal layer 6 12, and a conductive film 613 are laminated. A conductive film 663 that reflects visible light is provided in contact with the opening 655. The conductive film 635 and the conductive film 613 contain a material that transmits visible light. An alignment film 633 a is provided between the liquid crystal layer 612 and the conductive film 635 . An alignment film 633b is provided between the substrate 661 and the polarizer 656. It has.

[0285] In the liquid crystal element 640, the conductive film 663 has a function of reflecting visible light, and the conductive film 613 The light incident from the substrate 661 side is polarized by the polarizing plate 656. The light is transmitted through the conductive film 613 and the liquid crystal layer 612, and is reflected by the conductive film 663. The light passes through the conductive film 612 and the conductive film 613 again and reaches the polarizer 656. The orientation of the liquid crystal is controlled by applying a voltage between the conductive film 635 and the conductive film 613. The optical modulation can be controlled, i.e., the intensity of the light emitted through the polarizer 656. In addition, the colored layer 631 absorbs light outside of a specific wavelength range. As a result, the extracted light becomes, for example, red light.

[0286] The light emitting element 660 is a bottom emission type light emitting element. A laminated structure in which a conductive film 643, an EL layer 644, and a conductive film 645b are laminated in this order from the 620 side. In addition, a conductive film 645a is provided to cover the conductive film 645b. The conductive film 643 and the conductive film 645a contain a material that reflects visible light. The light emitted from the light emitting element 660 passes through the colored layer 634, the insulating film 620, the opening 655, and the insulating film 620. , and is emitted to the substrate 661 side through the conductive film 613 and the like.

[0287] Here, as shown in FIG. 18, a conductive film 635 that transmits visible light is provided in the opening 655. In this way, even in the area overlapping with the opening 655, the other area Since the liquid crystal is oriented in the same way as in the case of the liquid crystal layer, poor alignment of the liquid crystal occurs at the boundary between these regions, resulting in unintended This can prevent the leakage of bright light.

[0288] Here, a linear polarizer may be used as the polarizer 656 disposed on the outer surface of the substrate 661. However, a circular polarizer can also be used. For example, a linear polarizer and a 1 / 4 wavelength polarizer can be used as a circular polarizer. A laminate of retardation films can be used, which can suppress external light reflection. In addition, the cell gap of the liquid crystal element used in the liquid crystal element 640 can be adjusted depending on the type of polarizer. By adjusting the orientation, driving voltage, etc., a desired contrast can be achieved. stomach.

[0289] An insulating film 647 is provided on the insulating film 646 that covers the end portion of the conductive film 643. The insulating film 647 acts as a spacer to prevent the insulating film 620 and the substrate 651 from getting closer than necessary. The EL layer 644 and the conductive film 645a are also used as a shielding mask (metal mask ) is used to form the mask, in order to prevent the mask from coming into contact with the surface to be formed. The insulating film 647 may function as a spacer. It's okay.

[0290] One of the source and drain of the transistor 605 is connected to the light-emitting element 66 through a conductive film 648. 0 is electrically connected to the conductive film 643.

[0291] One of the source and drain of the transistor 606 is connected to the conductive film 663 through the connection portion 607. The conductive film 663 and the conductive film 635 are provided in contact with each other, and are electrically connected to each other. Here, the connection portion 607 is electrically connected through an opening provided in the insulating film 620. This is a portion that connects the conductive layers provided on both sides of the insulating film 620 together.

[0292] A connection portion 604 is provided in the area where the substrate 651 and the substrate 661 do not overlap. The connecting portion 604 is electrically connected to the FPC 672 via the connecting layer 649. The upper surface of the connecting portion 604 is the same as the conductive film 635. The conductive layer obtained by processing the conductive film is exposed. 672 can be electrically connected via a connection layer 649.

[0293] A connection portion 687 is provided in a portion of the area where the adhesive layer 641 is provided. 7, a conductive layer obtained by processing the same conductive film as the conductive film 635 and a conductive film A part of the wiring is electrically connected by a connector 686. Therefore, the wiring is formed on the substrate 661 side. A signal or a signal input from an FPC 672 connected to the substrate 651 side is input to the conductive film 613. A potential can be applied via connection 687.

[0294] The connector 686 may be, for example, a conductive particle. The surface of particles such as organic resin or silica coated with a metal material can be used. It is preferable to use nickel or gold as the metal material, as this can reduce the contact resistance. It uses particles coated with layers of two or more metal materials, such as nickel coated with gold. It is preferable that the connector 686 is made of a material that is elastically or plastically deformable. In this case, the connectors 686, which are conductive particles, are preferably arranged as shown in FIG. In this way, the connector 686 and the electrical This increases the contact area with the conductive layer that is directly connected, reducing contact resistance and preventing connection failures. The occurrence of defects can be suppressed.

[0295] The connector 686 is preferably disposed so as to be covered with the adhesive layer 641. For example, The connectors 686 may be dispersed in the previous adhesive layer 641 .

[0296] FIG. 18 shows an example of a circuit 659 in which a transistor 601 is provided. .

[0297] In FIG. 18, a transistor 601 and a transistor 605 are shown as examples in which a channel is formed. The semiconductor film 653 is sandwiched between two gates. The other gate is a conductive film overlapping the semiconductor film 653 via an insulating film 682. By adopting such a configuration, the threshold voltage of the transistor In this case, two gates are connected and the same signal is applied to them. Such a transistor may be driven by supplying a It is possible to increase the field effect mobility compared to conventional transistors, and increase the on-current. As a result, a circuit capable of high-speed operation can be fabricated. By using a transistor with a large on-current, it is possible to reduce the area occupied by the Even if the number of wires increases when the display panel is made larger or higher resolution, each wire This makes it possible to reduce signal delay in the display, thereby suppressing display unevenness.

[0298] Note that the transistors included in the circuit 659 and the transistors included in the display portion 662 are the same. The plurality of transistors included in the circuit 659 may all have the same structure. Alternatively, transistors of different structures may be used in combination. The plurality of transistors in 62 may all have the same structure, or may have different structures. A combination of transistors may also be used.

[0299] At least one of the insulating films 682 and 683 covering the transistors is resistant to water, hydrogen, etc. It is preferable to use a material in which impurities are difficult to diffuse. The insulating film 683 can function as a barrier film. It is possible to effectively suppress the diffusion of impurities into the transistor from the outside. This makes it possible to realize a highly reliable display panel.

[0300] On the substrate 661 side, an insulating film 621 is provided to cover the colored layer 631 and the light-shielding film 632. The insulating film 621 may also function as a planarizing layer. Since the surface of the conductive film 613 can be made approximately flat, the alignment state of the liquid crystal layer 612 can be made uniform. .

[0301] An example of a method for manufacturing the display panel 600 will be described. A conductive film 635, a conductive film 663, and an insulating film 620 are formed in this order on the plate. After forming the capacitor 605, the transistor 606, the light emitting element 660, etc., The substrate 651 and the support substrate are bonded together. Then, the separation layer and the insulating film 620 are bonded together, and the separation layer and the conductive film are bonded together. The support substrate and the release layer are removed by peeling at the respective interfaces of the film 635. Separately, a substrate on which a colored layer 631, a light-shielding film 632, a conductive film 613, etc. have been formed in advance is used. Then, the liquid crystal is dropped onto the substrate 651 or the substrate 661, and the liquid crystal is applied to the adhesive layer 641. By bonding the substrate 651 and the substrate 661 together, the display panel 600 can be manufactured. Cut.

[0302] For the peeling layer, a material that causes peeling at the interface with the insulating film 620 and the conductive film 635 is appropriately selected. In particular, when a layer containing a high melting point metal material such as tungsten is used as the release layer, A layer containing an oxide of the metal material is stacked, and a silicon nitride film is used as an insulating film 620 on the peeling layer. It is preferable to use a layer of silicon, silicon oxynitride, silicon nitride oxide, etc. When a high melting point metal material is used for the peeling layer, the temperature at which the subsequent layers are formed can be increased. This allows the concentration of impurities to be reduced, thereby realizing a highly reliable display panel.

[0303] The conductive film 635 is made of an oxide or nitride such as a metal oxide or a metal nitride. When metal oxides are used, hydrogen, boron, phosphorus, nitrogen, and other At least one of the impurity concentration and the amount of oxygen vacancies is A material having a higher thermal conductivity than the conductive film 635 may be used.

[0304] <About each component> The following describes each of the components shown above. A description of configurations having similar functions will be omitted.

[0305] [Adhesive layer] The adhesive layer may be a photo-curable adhesive such as an ultraviolet curable adhesive, a reaction-curable adhesive, or a heat-curable adhesive. Various curing adhesives such as elastomeric adhesives and anaerobic adhesives can be used. epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide Resin, PVC (Polyvinyl Chloride) Resin, PVB (Polyvinyl Butyral) Resin, EV A (ethylene vinyl acetate) resins, etc. In particular, epoxy resins, etc., which have high moisture permeability, A material with low viscosity is preferable. Two-component resin may also be used. An adhesive sheet or the like may also be used. It's fine.

[0306] The resin may also contain a desiccant. For example, an alkaline earth metal oxide (oxide Use a substance that absorbs water by chemical adsorption, such as calcium or barium oxide. Alternatively, materials such as zeolite and silica gel can absorb moisture by physical adsorption. If a desiccant is included, impurities such as moisture may penetrate into the element. This is preferable because it can prevent the occurrence of such a problem and improve the reliability of the display panel.

[0307] In addition, by mixing a filler with a high refractive index or a light scattering material into the resin, it is possible to improve the light extraction efficiency. For example, titanium oxide, barium oxide, zeolite, silica Co, etc. can be used.

[0308] [Connection layer] The connection layer is made of anisotropic conductive film (ACF). tive Film) and Anisotropic Conductive Paste (ACP) Inductive Paste) can be used.

[0309] [Colored layer] Materials that can be used for the coloring layer include metal materials, resin materials, pigments, and dyes. Examples of such materials include resin materials.

[0310] [Light blocking layer] Materials that can be used for the light-shielding layer include carbon black, titanium black, gold, Examples of the light-shielding layer include metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. The film may be a film containing a resin material, or may be a thin film made of an inorganic material such as a metal. For example, a laminated film of a film containing a material of a colored layer may be used as the light-shielding layer. A film containing a material used for a color layer that transmits light of a certain color and a material used for a color layer that transmits light of another color are used. By using the same material for the colored layer and the light-shielding layer, This is preferable because it allows the equipment to be standardized and the process to be simplified.

[0311] This concludes the explanation of each component.

[0312] <Example of manufacturing method> Here, an example of a method for manufacturing a display panel using a flexible substrate will be described.

[0313] Here, display elements, circuits, wiring, electrodes, optical components such as colored layers and light-shielding layers, and insulating layers, etc. For example, the element layer includes a display element. In addition to the display elements, wiring electrically connecting to the display elements, transistors used in pixels and circuits, etc. The device may include an element.

[0314] In addition, in this case, when the display element is completed (the manufacturing process is completed), the element layer is supported. A flexible member that supports the substrate is called a substrate. This also includes extremely thin films of 10 nm or more and 300 μm or less.

[0315] A typical method for forming an element layer on a flexible substrate having an insulating surface is as follows. There are two methods listed below. One is to form the element layer directly on the substrate. The other method is to form an element layer on a support substrate different from the substrate, and then peel the element layer from the support substrate. , a method of transferring an element layer onto a substrate. In addition to the above method, an element layer is formed on a non-flexible substrate, and the substrate is thinned by polishing or the like. Another method is to make the material flexible by using a

[0316] If the material constituting the substrate has heat resistance to the heat applied in the process of forming the element layer, It is preferable to form the element layer directly on the substrate, since this simplifies the process. When the element layer is formed while the substrate is fixed to the support substrate, it is easy to transport the element within and between devices. This is preferable because it makes things easier.

[0317] In addition, when a method of forming an element layer on a support substrate and then transferring the element layer to the substrate is used, the support substrate is first formed. A release layer and an insulating layer are stacked over a substrate, and an element layer is formed over the insulating layer. The element layer is then transferred to the substrate. A material that causes peeling to occur at the interface between the peeling layer and the insulating layer or within the peeling layer may be selected. In this method, a material with high heat resistance is used for the support substrate and the peeling layer, so that the element layer can be formed easily. This allows for an increase in the upper limit of the temperature at which the device can be formed, thereby enabling the formation of a device layer having more reliable devices. This is preferable because it can be done easily.

[0318] For example, a layer containing a high melting point metal material such as tungsten and an acid of the metal material are used as the peeling layer. A layer containing a silicon oxide, a silicon nitride, or a silicon dioxide is stacked as an insulating layer on a peeling layer. It is preferable to use a stack of a plurality of layers of silicon oxynitride, silicon nitride oxide, or the like.

[0319] The element layer and the support substrate can be separated by applying a mechanical force or by etching the separation layer. Examples include chipping or infiltrating a liquid into the peeled interface. Alternatively, the difference in thermal expansion between the two layers that form the peel interface can be utilized by heating or cooling. Peeling may be performed by

[0320] Furthermore, if peeling can be achieved at the interface between the support substrate and the insulating layer, it is not necessary to provide a peeling layer.

[0321] For example, glass is used as the support substrate, and an organic resin such as polyimide is used as the insulating layer. At this time, a part of the organic resin is locally heated using a laser beam or the like. The peeling occurs when a sharp object is used to physically cut or penetrate a part of the organic resin. A starting point may be formed, and peeling may be performed at the interface between the glass and the organic resin. For this purpose, it is preferable to use a photosensitive material, since it is easy to form shapes such as openings. The laser light is, for example, light in the wavelength range from visible light to ultraviolet light. For example, light having a wavelength of 200 nm or more and 400 nm or less, preferably light having a wavelength of 2 Light with a wavelength of 50 nm or more and 350 nm or less can be used. In particular, excimer lasers with a wavelength of 308 nm can be used. It is preferable to use a laser because it has excellent productivity. Solid-state UV lasers (also called semiconductor UV lasers) such as UV lasers with a wavelength of 355 nm, which is a harmonic (U) may also be used.

[0322] Alternatively, a heat generating layer is provided between the support substrate and the insulating layer made of organic resin, and the heat generating layer is heated. The heat generating layer may be formed by passing a current through the heat generating layer. Materials that generate heat when current flows, materials that generate heat by absorbing light, and materials that generate heat by applying a magnetic field. For example, the heat generating layer may be made of: The material can be selected from semiconductors, metals, and insulators.

[0323] In the above-mentioned method, the insulating layer made of organic resin can be used as a substrate after peeling. This can be done.

[0324] The above is a description of the method for manufacturing a flexible display panel.

[0325] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0326] (Fourth embodiment) In this embodiment, a metal oxide according to one embodiment of the present invention will be described.

[0327] The metal oxide of one embodiment of the present invention is a metal oxide containing In (indium) and M (M is Al, Ga, Y, or represents Sn.) and Zn (zinc). In particular, M is Ga (gallium). In the following description, M is assumed to be Ga.

[0328] Here, silicon (Si), boron (B), and Or, we will explain the case where carbon (C) is present.

[0329] <Calculation model and calculation method> First, a model of the amorphous state of In-Ga-Zn oxide without impurities is used as a reference. A model with one Si atom added to the reference model, and a model with one B atom added Calculations were performed using the model with one C atom added and a model with one C atom added.

[0330] Specifically, as a reference crystal model, the [In]:[Ga]: Model 700 with [Zn]:[O]=1:1:1:4 was used. It is composed of 12 atoms.

[0331] Strictly speaking, the In-M-Zn oxide with the CAC structure is not in an amorphous state. On the other hand, the In-M-Zn oxide with CAC structure has the In- It has lower crystallinity than M-Zn oxide. Therefore, it reduces the influence of the crystal structure and allows us to confirm the bonding state. For convenience, an amorphous state model was used to estimate the crystal structure.

[0332] In addition, in the model 700, Si atoms, B atoms, or C atoms are present as impurities. The interstitial site of Model 700 is assigned one Si atom, one B atom, or one C atom. The atoms were placed in the model 700, which consisted of 112 atoms. Therefore, the impurity concentration in the model is approximately 7×10 20 [pcs / cm 3 ] is equivalent to

[0333] In FIG. 20(A), when Si exists as an impurity, one Si atom is divided into four The local structure 702 is an extracted view of the vicinity of Si from the model bonded to an O atom. (C) A model in which one Si atom is bonded to three O atoms and one Ga atom. 7 shows a local structure 704 extracted from the vicinity of Si.

[0334] When B exists as an impurity, one B atom is bonded to three O atoms. The local structure 706 extracted from the model around the B atom is shown in Fig. 21(A). The local structure 708 extracted from the vicinity is shown in FIG. 21(C).

[0335] When C exists as an impurity, one C atom is connected to two O atoms and one The local structure 710 extracted from the vicinity of the C atom in the model bonded to the Ga atom is shown in Figure 22(A). From the model in which one C atom is bonded to one O atom and one Ga atom, A local structure 712 obtained by extracting the vicinity is shown in FIG. 22(C).

[0336] The specific calculation contents are shown below. In addition, the atomic relaxation calculations are performed using the first-principles electronic structure calculation package. -VASP(Vienna ab initio simulation packa The calculation conditions are shown in the table below.

[0337] [Table 1]

[0338] <About density of states> FIG. 19(B) shows the density of states in FIG. 19(A). The Luminescence level (the highest energy level occupied by electrons) is 0 eV on the horizontal axis. As shown in Figure 19(B), electrons occupy the upper edge of the valence band, and the electrons are in the gap level. It was confirmed that there was no rank.

[0339] In addition, the density of states diagram when one Si atom is added as an impurity is shown in Fig. 20(B), and 20(B) and 20(D). Note that FIG. 20(B) shows the local structure 702 shown in FIG. 20(A). FIG. 20(D) shows the density of states when the local structure 704 shown in FIG. 20(C) is 4 shows the density of states diagram for the case where

[0340] In both Figure 20(B) and Figure 20(D), when Si atoms are mixed in, the Fermi level Therefore, the Si atoms are located in the In-Ga-Zn oxide. It was suggested that carriers are generated (also called n-generation).

[0341] Furthermore, the density of states when one B atom is added as an impurity is shown in Fig. 21(B), and 21(B) and 21(D). Note that FIG. 21(B) shows the local structure 706 shown in FIG. 21(A). FIG. 21(D) shows the density of states when the local structure 708 shown in FIG. 21(C) is 4 shows the density of states diagram for the case where

[0342] In both Figure 21(B) and Figure 21(D), when B atoms are mixed in, the Fermi level is shifted to the conduction band. Therefore, the B atoms are located within the In-Ga-Zn oxide. It was suggested that rear is generated (also called n-ization).

[0343] In addition, the density of states diagram when one C atom is added as an impurity is shown in Fig. 22(B), and 22(D). Note that FIG. 22(B) shows a sample having the local structure 710 shown in FIG. 22(A). FIG. 22(D) shows the density of states when the local structure 712 shown in FIG. 22(C) is 10 shows a density of states diagram for the case where

[0344] In both Figure 22(B) and Figure 22(D), when C atoms are mixed in, the Fermi level is shifted to the conduction band. Therefore, the carbon atoms are located within the In-Ga-Zn oxide. It was suggested that rear is generated (also called n-ization).

[0345] This is because the electronegativity of Si and B is closer to that of In, Ga, and Zn than to that of O. , Si atoms, and B atoms exist as cations in In-Ga-Zn oxide. This is highly probable, and it is therefore assumed that carriers are generated.

[0346] In addition, the electronegativity of C is between that of In, Ga, Zn and O, so it is compatible with metals and O. Although it bonds, it is assumed that it is more likely to exist as a cation.

[0347] Also, Si, B, and C atoms are more abundant than In, Ga, and Zn atoms. , and the bond with O atoms is strong. Therefore, when Si atoms, B atoms, and C atoms are mixed in, The O atoms that were bonded to In, Ga, and Zn atoms are now bonded to Si, B, and and C atoms. Therefore, it is speculated that a deep level corresponding to an oxygen vacancy is formed. .

[0348] The structures and methods described in this embodiment may be combined as appropriate with structures and methods described in other embodiments. It can be used in combination. [Example]

[0349] In this example, various measurement methods were used to measure the metal oxide film formed on a substrate, which is one embodiment of the present invention. The results of measurements on Sample 1A and Sample 2A will be described. Sample 1B, Sample 1C, Sample 1D, Sample 1E, Sample 1F, Sample 1G, Sample 1H, and Sample 1 J was created.

[0350] <Sample composition and preparation method> Hereinafter, Sample 1A, Sample 1B, Sample 1C, Sample 1D, Sample 1E, Samples 1F, 1G, 1H, and 1J will be described. J has a substrate and a metal oxide on the substrate.

[0351] The samples 1A to 1J were prepared by varying the temperature and oxygen flow rate during the deposition of the metal oxide films. The ratios of the metal oxide films in Samples 1A to 1J were prepared under different conditions. The temperature and oxygen flow rate are shown.

[0352] [Table 2]

[0353] Next, the method for preparing each sample will be described.

[0354] First, a glass substrate was used as the substrate. Subsequently, using a sputtering apparatus, a 100 nm thick In-Ga-Zn oxide was formed as a metal oxide on the substrate. The film formation conditions were such that the pressure inside the chamber was 0.6 Pa, and a metal oxide target (In :Ga:Zn = 4:2:4.1 [atomic ratio]) was used for the target. Also, by supplying 2500 W of AC power to the metal oxide target installed inside the sputtering apparatus, [[ID=1I]] the metal oxide was formed into a film.

[0355] Note that, as the conditions for forming the metal oxide film, the film formation temperature and oxygen flow rate shown in the above table ratio were used to obtain Samples 1A to 1J.

[0356] Through the above steps, Samples 1A to 1J of this example were prepared.

[0357] <Analysis by X-ray Photoelectron Spectroscopy> In this section, the results of X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy) measurements performed on Sample 1A, Sample 1D, and Sample 1J will be described. Note that PHI's Quantera SXM was used. Also, the conditions were such that the X-ray source was monochromatic Al (1486.6 eV), the detection area was a circular area with a diameter of 100 μm and the detection depth was 4 nm to 5 nm when the extraction angle was 45°. Also, the measurement spectrum was detected with the In3d5 / 2 peak, Ga3d peak, Zn3p peak, and O1s peak as the correction standards respectively. Based on the detected peaks, the ratio of each atom [atomic %] was calculated.

[0358] Figure 52 shows the results of XPS analysis. The pie chart shown in Figure 52 is normalized with the atomic ratio of In being 4.

[0359] From Figure 52, when the atomic ratio of In is normalized to an integer, the atomic ratios of Ga and Zn are not integers. That is, it was found that when the atomic ratio of In is normalized to an integer, the atomic ratios of Ga and Zn are non-integers.

[0360] Also, in Sample 1A, Sample 1D, and Sample 1J, the atomic ratio of Ga in the formed metal oxide is smaller than the atomic ratio of Ga in the metal oxide used for the target. For example, in Sample 1J, the atomic ratio of Zn in the formed metal oxide is [Zn]=3.21, which is smaller than the atomic ratio of Zn in the metal oxide used for the target, which is [Zn]=4.1. Also, the atomic ratio of Zn in the formed metal oxide is [Zn]=3.70 in Sample 1A and [Zn =3.62 in Sample 1D, and it was found that they are smaller. Therefore, in Sample 1J where the film formation temperature is the highest, a tendency for a lower proportion of Zn in the formed metal oxide was confirmed. This is thought to be due to the volatilization of Zn during heat-assisted film formation.

[0361] <Analysis by X-ray diffraction> In this section, the results of X-ray diffraction (XRD) measurement of the metal oxide on the glass substrate will be described. As the XRD apparatus, D8 ADVANCE manufactured by Bruker was used. Also, the conditions were θ / 2θ scan by the Out-of-plane method, with the scan range being 15 deg. to 50 deg. and the step width being 0 .02 degrees, and the scanning speed was set to 3.0 degrees per minute.

[0362] Fig. 23 shows the results of measuring the XRD spectrum using the Out-of-plane method. .

[0363] The XRD spectrum shown in Fig. 23 has a higher peak intensity near 2θ = 31° by increasing the substrate temperature during film formation or increasing the ratio of the oxygen gas flow rate during film formation. Also, the peak near 2θ = 31° is derived from a crystalline IGZO compound (also referred to as CAAC-IGZO) oriented along the c-axis with respect to the direction substantially perpendicular to the formed surface or the upper surface. It has been found that. Furthermore, the XRD spectrum shown in Fig. 23 did not show distinct peaks as the substrate temperature during film formation was lower or the oxygen gas flow rate ratio was smaller. Therefore, it was found that samples with a lower substrate temperature during film formation or a smaller oxygen gas flow rate ratio did not show any orientation in the a-b plane direction and the c-axis direction of the measurement region. It has been found that. . <C

[0364] Also, the XRD spectrum shown in Fig. 23 did not show distinct peaks as the substrate temperature during film formation was lower or the oxygen gas flow rate ratio was smaller. Therefore, it was found that samples with a lower substrate temperature during film formation or a smaller oxygen gas flow rate ratio did not show any orientation in the a-b plane direction and the c-axis direction of the measurement region. 量比が小さいほど、明確なピークが現れなかった。従って、成膜時の基板温度が低い、ま たは、酸素ガス流量比が小さい試料は、測定領域のa-b面方向、およびc軸方向の配向 は見られないことが分かった。

[0365] <TEM Images and Electron Diffraction> In this section, the results of observing and analyzing Sample (1A), Sample (1D), and Sample (1J) using HAADF (High-Angle Annular Dark Field)-STEM (Scanning Transmission Electron Microscope) will be described (hereinafter, the images obtained by HAADF-STEM will also be referred to as TEM images). e Annular Dark Field)-STEM(Scanning Tran smission Electron Microscope)によって観察、および解 析した結果について説明する(以下、HAADF-STEMによって取得した像は、TE M像ともいう。)。

[0366] Also, in this section, Sample (1A), Sample (1D), and Sample (1J) were observed with an electron beam having a probe diameter of 1 nm (also called nanobeam electron beam) to obtain an electron diffraction pattern. We will explain about this.

[0367] The planar TEM images were observed using a spherical aberration correction function. The M images were taken using an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. The electron beam was irradiated at an acceleration voltage of 200 kV with a beam diameter of approximately 0.1 nmφ.

[0368] The electron diffraction pattern was observed from the 0-second position to the 35-second position while irradiating the electron beam. The experiment was carried out while moving the object at a constant speed.

[0369] Figure 24(A) shows a cross-sectional TEM image of sample 1A, and Figure 24(B) shows the electron diffraction pattern of sample 1A. The results are shown in Fig. 24(C) and Fig. 24(D). The results of the 1D electron diffraction pattern are shown in Figure 24(E). FIG. 24(F) shows the electron diffraction pattern of sample 1J.

[0370] Here, for example, for a CAAC-OS having InGaZnO4 crystals, When an electron beam with a probe diameter of 300 nm is incident on the InGaZnO4 crystal, ) planes, the diffraction pattern contains spots due to the The CAAC-OS has a c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface on which it is formed or the upper surface. On the other hand, for the same sample, when the probe diameter was 300 nm perpendicular to the sample surface, When an electron beam is incident on the CAAC-O, a ring-shaped diffraction pattern is observed. It can be seen that S has no orientation along the a-axis and b-axis.

[0371] In addition, metal oxides with microcrystals (especially those with functions equivalent to semiconductors) are called nano crystalline oxide semiconductor. c-OS) using an electron beam with a large probe diameter (for example, 50 nm or more) When electron diffraction is performed, a diffraction pattern resembling a halo pattern is observed. For metal oxides with a small probe diameter (e.g., less than 50 nm), When performing electron diffraction, bright spots are observed. When nanobeam electron diffraction is performed on oxides, a circular (ring-shaped) area of ​​high brightness is observed. In addition, multiple bright spots may be observed in the ring-shaped area. do.

[0372] As shown in FIG. 24(A), the cross-sectional TEM observation of Sample 1A revealed that it was composed of nanocrystals. Also, as shown in Figure 24(B), The electron diffraction pattern for sample 1A shows a circular (ring-shaped) pattern of high brightness. In addition, multiple spots were observed in the ring-shaped area.

[0373] As shown in FIG. 24(C), the cross-sectional TEM observation of sample 1D revealed that it had a CAAC structure and As shown in Figure 24(D), the electron diffraction pattern for sample 1D was As a result of the turn, a bright area was observed in a circular (ring-like) pattern. In addition, several spots were observed in the ring-like region. A few diffraction patterns were also observed.

[0374] On the other hand, as shown in FIG. 24(E), the cross-sectional TEM observation of Sample 1J revealed that it had a CAAC structure. As shown in FIG. 24(F), the layered arrangement of sample 1J was clearly observed. The electron diffraction pattern shows that the spots originating from the (009) plane are clearly observed. Ta.

[0375] The features observed in the cross-sectional TEM images and planar TEM images described above are due to the This is a one-sided view of the oxide structure.

[0376] Next, the sample 1A is irradiated with an electron beam having a probe diameter of 1 nm (also called a nano-beam electron beam). The electron diffraction pattern obtained by irradiating the sample with light is shown in FIG.

[0377] In the planar TEM image of sample 1A shown in FIG. 25(A), black spots a1, a2, and a3 The electron diffraction patterns indicated by black dots a1, a2, and a3 were observed. The observation was performed by moving the sample at a constant speed from the 0-second position to the 35-second position while irradiating it with an electron beam. The results for black spot a1 are shown in Figure 25(C), the results for black spot a2 are shown in Figure 25(D), and the results for black spot a3 are shown in Figure 25(E). The results for black point a3 are shown in Figure 25(E), the results for black point a4 are shown in Figure 25(F), and the results for black point a5 are shown in Figure 25(G). 25(G).

[0378] From Figure 25(C), Figure 25(D), Figure 25(E), Figure 25(F), and Figure 25(G), A ring-shaped area of ​​high brightness was observed. In addition, multiple spots were observed in the ring-shaped area. Done.

[0379] In addition, in the cross-sectional TEM image of sample 1A shown in FIG. 25(B), black spots b1, b2, and Observe the electron diffraction patterns indicated by dot b3, black dot b4, and black dot b5. The results of the black dot b1 are shown in Fig. 25(H), the results of the black dot b2 are shown in Fig. 25(I), the results of the black dot b3 are shown in Fig. 25(J), the results of the black dot b4 are shown in Fig. 25(K), and the results of the black dot b5 are shown in Fig. 25(L).

[0380] From Fig. 25(H), Fig. 25(I), Fig. 25(J), Fig. 25(K), and Fig. 25(L), a region with high brightness was observed in a ring shape. Also, a plurality of spots were observed in the ring-shaped region. were observed.

[0381] That is, it was found that Sample 1A has an nc structure and clearly different properties from both the amorphous metal oxide and the single crystal structure metal oxide.

[0382] From the above, the electron diffraction patterns of Sample 1A and Sample 1D have a region with high brightness in a ring shape and a plurality of bright spots in the ring region. Therefore, it was found that Sample 1A is a metal oxide whose electron diffraction pattern shows microcrystals and has no orientation in the plane direction and the cross-section direction. Also, it was found that Sample 1D is a mixture of an nc structure and a CAAC structure. was found.

[0383] On the other hand, the electron diffraction pattern of Sample 1J has spots due to the (009) plane of the InGaZnO4 crystal. Therefore, it was found that Sample 1J has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0384] <Image analysis of TEM image> In this section, the results of observing and analyzing Samples 1A, 1C, 1D, 1F, and 1G by HAADF-STEM will be described.

[0385] ​​​​The results of image analysis of the planar TEM image are explained below. The planar TEM image was obtained using spherical convergence. The planar TEM images were taken using a JEOL atomic microscope. A high-resolution analytical electron microscope, JEM-ARM200F, was used, with an accelerating voltage of 200 kV and a beam diameter of The electron beam was irradiated with a diameter of approximately 0.1 nm.

[0386] Figure 26 shows the average values ​​of Sample 1A, Sample 1C, Sample 1D, Sample 1F, Sample 1G, and Sample 1J. These are surface TEM images and images obtained by image processing of planar TEM images. The left image shows a planar TEM image, and the right image shows an image processed version of the planar TEM image shown on the left.

[0387] The image processing and image analysis methods will be explained. First, as image processing, The planar TEM image was subjected to fast Fourier transform (FFT). The FFT image was then processed using a 2.8 nm (orm) filter. - 1 to 5.0 nm -1 Then, the masked FFT The image is then subjected to an inverse fast Fourier transform (IFFT). The FFT-filtered image was obtained by performing a transform process.

[0388] As part of the image analysis, first, grid points were extracted from the FFT filtered image. The following steps were performed: First, the noise in the FFT filtered image was removed. To remove noise, the brightness within a radius of 0.05 nm was averaged using the following formula: It smoothed out.

[0389]

number

[0390] where S_Int(x,y) is the smoothed luminance at the coordinate (x,y), and r is It indicates the distance between coordinates (x, y) and coordinates (x', y'), and Int(x', y') indicates the distance between coordinates ( This indicates the brightness at x', y'. When r is 0, the calculation is performed assuming r is 1.

[0391] Next, we searched for lattice points. The lattice point conditions were to search for all lattice point candidates within a radius of 0.22 nm. The coordinates were chosen to be brighter than the 0.22 radius. If the difference is within nm, the frequency of false detection of lattice points due to noise can be reduced. In the TEM image, there is a certain distance between the lattice points, so there are two or more lattices within a radius of 0.22 nm. It is unlikely to contain any points.

[0392] Next, extract the coordinates with the highest brightness within a radius of 0.22 nm from the extracted grid point candidate. The grid point candidates were extracted repeatedly and updated until no new grid point candidates appeared. The coordinates at which the coordinates become equal are recognized as lattice points. Similarly, the coordinates at which the coordinates become equal are recognized as lattice points. By recognizing new grid points at positions farther away than the target, grid points can be recognized in the entire range. The obtained multiple grid points are collectively called a grid point group.

[0393] Next, we will explain how to derive the angles of the hexagonal lattice from the extracted lattice points, as shown in Figure 27(A). The schematic diagrams shown in FIG. 27(B) and FIG. 27(C) and the flowchart shown in FIG. 27(D) First, a reference grid point is determined, and the six nearest grid points are calculated as follows: The wires were then knotted together to form a hexagonal lattice (see step S101 in FIGS. 27(A) and 27(D)). Then, the average distance from the reference lattice point, which is the center point of the hexagonal lattice, to each lattice point, which is the vertex, is calculated. The average value R was calculated. The calculated R was used as the distance to each vertex, and the regular hexagon with the reference grid point as the center point was calculated. A hexagon was formed (see step S102 in FIG. 27(D)). At this time, each vertex of the regular hexagon The distances to the nearest neighboring lattice points are distance d1, distance d2, distance d3, and distance d4. , distance d5 and distance d6 (see step S103 in FIG. 27(B) and FIG. 27(D)). Next, rotate the regular hexagon from 0° to 60° in 0.1° increments around the center point. The average deviation between the rotated regular hexagon and the hexagonal lattice [D=(d1+d2+d3+d4+d5+d 6) / 6] was calculated (see step S104 in FIG. 27(D)). Then, the average deviation D The rotation angle θ of the regular hexagon when is the smallest was calculated and used as the angle of the hexagonal lattice (Figure 27(C ), FIG. 27(D) step S105).

[0394] Next, in the observation range of the planar TEM image, the ratio of the hexagonal lattice angle to 30° was the highest. The average value of the angle of the hexagonal lattice within a radius of 1 nm was adjusted to be Next, the planar TEM image obtained through image processing was analyzed to determine the hexagonal lattice structure of the region. The image was processed from the planar TEM image shown in Figure 26. The planar TEM image shown in Figure 26 was analyzed by the above-mentioned method, and the In other words, the image obtained by image processing of a planar TEM image shows the FF of the planar TEM image. In the T-filtered image, specific wavenumber regions are color-coded to identify the specific wavenumber regions. This is an image in which the orientation of the grid points has been extracted.

[0395] As can be seen from Figure 26, in Sample 1A and Sample 1D, where nc is observed, the orientation of the hexagons is random. It was found that the particles were distributed in a mosaic pattern. In addition, a layered structure was observed in the cross-sectional TEM image. In the sample 1J, the hexagons had the same orientation over a wide area of ​​several tens of nanometers. Sample 1D was found to have a random mosaic nc structure and the same nc structure as sample 1J. It was found that there are areas where the same direction is observed over a wide area.

[0396] Furthermore, as shown in FIG. 26, the lower the substrate temperature during film formation or the smaller the oxygen gas flow rate ratio, The orientation of the hexagons is random, and areas that are distributed in a mosaic pattern tend to appear. I found out that...

[0397] Thus, by analyzing the planar TEM image, the hexagonal lattice structure of CAAC-OS was clearly observed. It is possible to evaluate boundaries where angles change.

[0398] Next, a Voronoi diagram was created from the lattice points of sample 1A. Each grid point is closest to the area surrounding it. , the schematic diagrams shown in Figures 28(A), 28(B), 28(C) and 28(D), and The method for creating a Voronoi diagram will be explained in detail using the flowchart shown in FIG. 28(E). .

[0399] First, a group of lattice points was extracted using the method shown in FIG. 27 (FIG. 28(A) and FIG. 28(B)). (E) See step S111. Next, adjacent grid points are connected by line segments (see FIG. 28(B)). ) and step S112 in Figure 28(E). Next, draw the perpendicular bisectors of each line segment. (See step S113 in Figures 28(C) and 28(E).) Next, three perpendicular bisects are The points where the lines intersect are extracted (see step S114 in FIG. 28(E)). These points are called Voronoi points. Next, adjacent Voronoi points are connected by line segments (Fig. 28(D) and Fig. 28(E)). (See step S115.) At this time, the polygonal region surrounded by the line segments is called a Voronoi region. Using the above method, we were able to create a Voronoi diagram.

[0400] Figure 29 shows the results of the measurements in Sample 1A, Sample 1C, Sample 1D, Sample 1F, Sample 1G, and Sample 1J. The bar graph shows the percentage of Voronoi regions whose shapes are either quadrilateral or nonagonal. The number of Voronoi regions for each sample that are either quadrilateral or nonagonal is shown. The table shows the percentage of Voronoi regions for each sample that are either quadrilateral or nonagonal.

[0401] As can be seen from Figure 29, the proportion of hexagonal structures is high in sample 1J with high crystallinity, and sample 1A with low crystallinity. It was confirmed that the proportion of hexagons tends to be lower in the sample 1D. The value was between that of sample 1J and sample 1A. Therefore, from Figure 29, it can be seen that the difference in film formation conditions It was confirmed that the crystalline state of metal oxides differs greatly.

[0402] Therefore, as can be seen from FIG. 29, the lower the substrate temperature during film formation or the smaller the oxygen gas flow rate ratio, It was confirmed that the crystallization was low and the proportion of hexagons tended to be low.

[0403] <Elemental analysis> In this article, we will discuss energy dispersive X-ray spectroscopy (EDX). EDX mapping was obtained and evaluated using X-ray spectroscopy. The results of elemental analysis of sample 1A will be explained. The elemental analysis equipment used was the JED-2000 energy dispersive X-ray analyzer manufactured by JEOL Ltd. 2300T. A Si drift detector is used to detect the X-rays emitted from the sample. There are.

[0404] In EDX measurement, each point in the analysis area of ​​the sample is irradiated with an electron beam, and the resulting The energy and frequency of characteristic X-rays of the material are measured, and an EDX spectrum corresponding to each point is obtained. In this example, the peaks in the EDX spectrum at each point are determined as electron transitions to the L shell of the In atom, G Electron transition to the K shell of an a atom, electron transition to the K shell of a Zn atom, and electron transition to the K shell of an O atom The ratio of each atom at each point is calculated. By performing this on the atomic ratios, it is possible to obtain EDX mapping that shows the distribution of the ratios of each atom. can.

[0405] Figure 30 shows TEM images and EDX mapping of the cross section and plane of sample 1A. In EDX mapping, the more elements are measured in a range, the brighter the measurement becomes. The ratio of elements is shown by light and dark, with the darker the element the less it is. The magnification of the X-mapping was 7.2 million times.

[0406] Figure 30(A) is a cross-sectional TEM image, and Figure 30(E) is a planar TEM image. Figure 30(B) is a cross-sectional , and Fig. 30(F) is the EDX mapping of In atoms in the plane. The ratio of In atoms to all atoms in the EDX mapping shown in (B) is 9.28 to The range was 33.74 [atomic%]. In the EDX mapping shown in Figure 30(F), The ratio of In atoms to the total atoms in the sample ranged from 12.97 to 38.01 atomic %. The range was set.

[0407] Also, Figure 30(C) shows the cross section, and Figure 30(G) shows the EDX map of Ga atoms in the plane. In addition, the ratio of Ga atoms to all atoms in the EDX mapping shown in FIG. The ratio of the atoms was set to the range of 1.18 to 18.64 [atomic%]. The ratio of Ga atoms to total atoms in EDX mapping ranges from 1.72 to 19.82[ atomic%] range.

[0408] Also, Figure 30(D) shows the cross section, and Figure 30(H) shows the EDX map of Zn atoms in the plane. In addition, the ratio of Zn atoms to all atoms in the EDX mapping shown in Figure 30(D) is The ratio of the atoms was set to the range of 6.69 to 24.99 [atomic%]. The ratio of Zn atoms to total atoms in EDX mapping ranged from 9.29 to 28.32 atomic%] range.

[0409] 30(A), 30(B), 30(C), and 30(D) are the results of the specimen 1A. The cross section shows the same area. and FIG. 30(H) show the same area on the plane of sample 1A.

[0410] Figure 31 shows enlarged EDX mapping of the cross section and the plane of sample 1A. FIG. 31(A) is an enlarged view of a part of FIG. 30(B). FIG. 31(C) is an enlarged view of a part of FIG. 30(D). FIG. 31(D) is an enlarged view of a part of FIG. 30(F). FIG. 31(E) is an enlarged view of a part of FIG. FIG. 31(F) is a partial enlarged view of FIG. 30(H). be.

[0411] In the EDX mapping shown in Figures 31(A), 31(B), and 31(C), the images show A relative distribution of light and dark is visible, and it appears that each atom in sample 1A exists with its own distribution. Here, the solid lines shown in Figures 31(A), 31(B), and 31(C) We focused on the area surrounded by the square and the area surrounded by the dashed line.

[0412] In FIG. 31(A), the area enclosed by the solid line contains many relatively bright areas, and the area enclosed by the dashed line contains many relatively bright areas. It was confirmed that the area surrounded by the solid line in Figure 31(B) contains many relatively dark areas. The area surrounded by the dashed line contains many relatively dark areas, and the area surrounded by the dashed line contains many relatively bright areas. It was confirmed that this was the case.

[0413] In other words, the area surrounded by the solid line is the area where the In atoms are relatively abundant, and the area surrounded by the dashed line is the area where the In atoms are relatively abundant. It was confirmed that this was an area with relatively few children. In the range, the lower area is a relatively bright area and the upper area is a relatively dark area. Therefore, the area enclosed by the solid line is the In X2 Zn Y2 O Z2 ,Also is InO X1 It was found that the main components were

[0414] The area surrounded by the solid line is the area where the number of Ga atoms is relatively small, and the area surrounded by the dashed line is the area where the number of Ga atoms is relatively small. In Figure 31(C), the area surrounded by the dashed line shows that there are relatively many children. In this case, the left area is a relatively dark area and the right area is a relatively bright area. Therefore, the area enclosed by the dashed line is GaO X3, or Ga X4 Zn Y4 O Z4 It was found that the main components were

[0415] Similarly, in the EDX mapping shown in Figures 31(D), 31(E), and 31(F), Even so, we paid attention to the areas surrounded by solid lines and the areas surrounded by dashed lines.

[0416] In FIG. 31(D), the area enclosed by the solid line contains many relatively bright areas, and the area enclosed by the dashed line contains many relatively bright areas. It was confirmed that the area surrounded by the solid line in Figure 31(E) contains many relatively dark areas. The area surrounded by the dashed line contains many relatively dark areas, and the area surrounded by the dashed line contains many relatively bright areas. It was confirmed that this was the case.

[0417] In other words, the area surrounded by the solid line is a region where the In atoms are relatively abundant and the Ga atoms are relatively few. In Figure 31(F), in the area surrounded by the solid line, It is clear that the lower region is a relatively dark region and the upper region is a relatively bright region. Therefore, the area enclosed by the solid line is X2 Zn Y2 O Z2 , or InO X1 etc. It was found that this is the region where is the main component.

[0418] The area surrounded by the dashed line is a region where the number of In atoms is relatively small, and the number of Ga atoms is relatively large. In Figure 31(F), the area enclosed by the dashed line is the right area. It can be seen that the area on the right is a relatively dark area, and the area on the left is a relatively bright area. Therefore, the area enclosed by the dashed line is GaO X3 , or Ga X4 Zn Y4 O Z4Main components include It was found that this was an area where

[0419] Also, from Figure 31, the distribution of In atoms is relatively more uniform than that of Ga atoms, InO X1 The region where is the main component is In X2 Zn Y2 O Z2 Through the region where is the main component , and appear to be connected to each other. X2 Zn Y2 O Z2 , or InO X1 It is assumed that the area where the main component is is formed by spreading out like a cloud. Cut.

[0420] Thus, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 In-Ga-Zn oxide with a structure in which the regions in which The material can be called CAC-IGZO.

[0421] Also, in FIG. 31, GaO X3 The region where is the main component, and In X2 Zn Y2 O Z2 , or InO X1 The size of the region where is the main component is 0.5 nm or more and 10 nm or less, or It was observed to be between 1 nm and 3 nm.

[0422] From the above, CAC-IGZO has a structure different from that of IGZO compounds in which metal elements are uniformly distributed. It was found that the CAC-IG compound has different properties from the IGZO compound. ZO is GaO X3 The region where In is the main component.X2 Zn Y2 O Z2 , or InO X1 The regions where each element is the main component are separated into two phases, and the regions where each element is the main component are formed in a mosaic pattern. It was confirmed that the compound has the following structure:

[0423] Therefore, when CAC-IGZO is used in semiconductor devices, GaO X3 The properties resulting from , In X2 Zn Y2 O Z2 , or InO X1 The properties resulting from this work in a complementary manner. This results in a high on-state current (I on ), high field-effect mobility (μ), and low off-state current ( I off ) can be expected to be realized. In addition, semiconductor elements using CAC-IGZO Therefore, CAC-IGZO is suitable for a variety of applications, including displays. It is ideal for semiconductor devices.

[0424] This embodiment may be any of the other embodiments, at least some of which are described herein, or any other embodiment. It can be implemented in appropriate combination with the examples. [Example]

[0425] In this example, a transistor 150 including a metal oxide 108 according to one embodiment of the present invention is In this example, the metal oxide 1 was used. As the transistor 150 having the .O8, Sample 2A, Sample 2B, Sample 2C, Sample 2D, Sample Nine types of transistors were fabricated: Sample 2E, Sample 2F, Sample 2G, Sample 2H, and Sample 2J. Ta.

[0426] <Sample composition and preparation method> In the following, Sample 2A, Sample 2B, Sample 2C, Sample 2D, Sample 2E, Samples 2F, 2G, 2H, and 2J will be described. 6 by the manufacturing method described in the second embodiment and FIGS. 9 to 11. A transistor 150 having the following structure was fabricated.

[0427] The samples 2A to 2J were prepared by varying the temperature and the acid concentration during the deposition of the metal oxide 108. The metal oxide composition of Samples 2A to 2J was measured under different conditions. The temperature and oxygen flow rate during film formation are shown.

[0428] [Table 3]

[0429] Each sample was prepared by the method described in the second embodiment. In the film formation step 108, the target is a metal oxide target (In:Ga:Zn= The atomic ratio was 4:2:4.1.

[0430] The channel length of the transistor 150 is 2 μm, and the channel width is 3 μm (hereinafter, L / W= 2 / 3μm), or the channel length is 2μm and the channel width is 50μm (hereafter referred to as L / W = 2 / 50 μm).

[0431] <Transistor electrical characteristics> Next, the Id of the transistors (L / W=2 / 3 μm) of Samples 2A to 2J fabricated above was measured. The Id-Vg characteristics of the transistor were measured under the following conditions: The voltage applied to the conductive film 112 functioning as the gate electrode (hereinafter referred to as gate voltage (Vg)) and a voltage (hereinafter referred to as a voltage) applied to the conductive film 106 functioning as the second gate electrode. The back gate voltage (Vbg) is changed from -10V to +10V in 0.25V steps. The voltage applied to the conductive film 120a functioning as the source electrode (hereinafter, Source voltage (V s ) is set to 0V (comm), and the conductive layer that functions as the drain electrode The voltage applied to the conductive film 120b (hereinafter also referred to as drain voltage (Vd)) was set to 0.1 V and It was set to 20V.

[0432] [Transistor Id-Vg characteristics] Here, we will explain the drain current-gate voltage characteristics (Id-Vg characteristics) of a transistor. FIG. 34A is a graph illustrating an example of the Id-Vg characteristics of a transistor. In FIG. 34(A), for ease of understanding, the active layer of the transistor is made of polycrystalline silicon. In FIG. 34(A), the vertical axis is Id and the horizontal axis is V. g, respectively.

[0433] As shown in FIG. 34(A), the Id-Vg characteristics can be roughly divided into three regions. The first region is the OFF region, and the second region is the subthreshold region. The third region is the ON region. The subthreshold region and the on region are called the on-region. The boundary gate voltage is called the threshold voltage (Vth).

[0434] The characteristics of a transistor are the drain current in the off region (also called the off current or Ioff). It is desirable that the drain current (also called the on-current or Ion) in the on region is high. In addition, the on-state current of a transistor is often measured using the field-effect mobility as an index. The field-effect mobility will be described in detail later.

[0435] In addition, to operate the transistor at a low voltage, the Id It is desirable that the slope of the -Vg characteristics is steep. Id-Vg characteristics in the subthreshold region As an index showing the magnitude of change in The S value is expressed by the following formula (2):

[0436]

number

[0437] The S value is the gate capacitance required to change the drain current by one order of magnitude in the subthreshold region. The smaller the S value, the faster the on / off switching operation. It can be done steeply.

[0438] [Transistor Id-Vd characteristics] Next, we will explain the drain current-drain voltage characteristics (Id-Vd characteristics) of a transistor. FIG. 34B is a graph illustrating an example of the Id-Vd characteristics of a transistor. In FIG. 34(B), the vertical axis represents Id and the horizontal axis represents Vd.

[0439] As shown in Figure 34(B), the ON region is further divided into two regions. The first region is the linear region, and the second region is the saturation region. The linear region is when the drain current is The saturation region increases as the drain voltage increases. The drain current does not change significantly. In accordance with the vacuum tube, the linear region may be referred to as the triode region, and the saturation region may be referred to as the pentode region, respectively.

[0440] Also, the linear region may refer to a state where Vg is large with respect to Vd (Vd < Vg). Also, the saturation region may refer to a state where Vd is large with respect to Vg (Vg < Vd). However, in reality, it is necessary to consider the threshold voltage of the transistor. Therefore, a state where the difference between Vg or the threshold voltage of the transistor is large with respect to Vd (Vd < Vg - Vt h) may be regarded as the linear region. Similarly, a state where the value obtained by subtracting the threshold voltage of the transistor from Vg is small with respect to Vd (Vg - Vth < Vd) may be regarded as the saturation region.

[0441] In the Id-Vd characteristics of the transistor, a characteristic in which the current in the saturation region is constant is sometimes expressed as " good saturation". The goodness of the saturation of the transistor is particularly important for applications to organic EL displays. For example, by using a transistor with good saturation as the transistor of the pixel of an organic EL display, even if the drain voltage changes, the change in the brightness of the pixel can be suppressed.

[0442] [Analysis Model of Drain Current] Next, an analysis model of the drain current will be described. As an analysis model of the drain current, an analytical formula of the drain current based on the Gradual channel approximation (GCA) is known and is represented by the following formula (3) based on GCA.

[0443] [Equation] ​​

[0444] In equation (3), the upper part is the drain current equation in the linear region, and the lower part is the drain current equation in the saturation region. In equation (3), Id is the drain current, μ is the active layer mobility, L is the transistor channel length, W is the transistor channel width, Cox is the gate Vg is the gate voltage, Vd is the drain voltage, and Vth is the threshold voltage of the transistor. and , respectively.

[0445] [Field-effect mobility] Next, the field-effect mobility will be explained. As mentioned above, the on-region of a transistor is divided into the linear region and the saturation region. Based on the characteristics of each region, the analytical formula for the drain current based on GCA is When it is necessary to distinguish between , and linear mobility, saturation mobility, respectively. The linear mobility is expressed by the following equation (4), The sum mobility is expressed by the following equation (5).

[0446]

number

[0447]

number

[0448] In this specification, the curve calculated from Equation (4) and Equation (5) is referred to as a mobility curve. Figure 35 shows the mobility curve calculated from the analytical expression for the drain current based on GCA. In addition, in FIG. 35, the Id-Vg characteristics when Vd=10V are shown assuming that GCA is effective, and The linear mobility and saturation mobility curves are shown superimposed on each other.

[0449] In Figure 35, the Id-Vg characteristics are calculated from the analytical formula for the drain current based on GCA. The shape of the mobility curve provides clues to understanding the internal workings of a transistor. .

[0450] FIG. 32 shows the Id-Vg characteristics and field-effect mobility of Samples 2A to 2J, respectively. The solid line shows Id when Vd is 20V, and the dashed line shows Id when Vd is 0.1V. The dashed line indicates the field effect mobility. In FIG. 32, the first vertical axis represents Id [A]. The second vertical axis is the field effect mobility (μFE [cm 2 / V s ]), the horizontal axis is Vg [V], The field effect mobility is calculated from the value measured with Vd set to 20 V. did.

[0451] As shown in FIG. 32, the characteristics of Samples 2A to 2J are on ), field effect transition It was confirmed that the field-effect mobility, especially in the saturated region, differs. Regarding the shape of the mobility, the maximum saturation mobility and the field effect of the rising characteristic near 0 V It was found that the shape of the fruit mobility was significantly different.

[0452] From Figure 32, it can be seen that the lower the substrate temperature during film formation or the smaller the oxygen flow rate during film formation, the higher the Low on-state current (I on ) was also found to be observed. Similarly, the rise near 0 V was In particular, the maximum value of the field-effect mobility in sample 2A was 70 cm 2 / V s It was confirmed that the value was close to

[0453] <Gate bias-thermal stress test (GBT test)> Next, the transistors (L / W=2 / 50 μm) of Samples 2A to 2J fabricated as described above were The reliability was evaluated using the GBT test.

[0454] The GBT test conditions in this example were: and a voltage applied to the conductive film 106 functioning as the second gate electrode (hereinafter referred to as the gate voltage The voltage (Vg) is set to ±30 V, and the conductive film 120a functioning as the source electrode and the conductive film 120b functioning as the drain electrode are set to ±30 V. The voltage (hereinafter referred to as the voltage) applied to the conductive film 120b functioning as the drain electrode , drain voltage (Vd), source voltage (V s ) is called 0V (COMMON The stress temperature was set to 60°C, the stress application time was set to 1 hour, and the measurement environment was set to in two environments: a work environment and a light irradiation environment (irradiated with approximately 10,000 lx of light from a white LED). , respectively.

[0455] That is, the conductive film 120a functioning as the source electrode of the transistor 150 and the conductive film 120b functioning as the drain electrode The conductive film 120b functioning as the electrode is set to the same potential, and the conductive film 120b functioning as the first gate electrode is set to the same potential. The conductive film 112 and the conductive film 106 functioning as the second gate electrode are provided with a conductive film 113 functioning as a source electrode. The conductive film 120a serving as a drain electrode and the conductive film 120b serving as a drain electrode are set at a constant potential different from each other. The voltage was applied for 1 hour (here, 1 hour).

[0456] In addition, the conductive film 112 functioning as a first gate electrode and the conductive film 113 functioning as a second gate electrode are The potential applied to the conductive film 106 is a potential applied to the conductive film 120a functioning as a source electrode and a potential applied to the conductive film 120b functioning as a drain electrode. A case where the potential is higher than the potential of the conductive film 120b functioning as an electrode was defined as a positive stress. A conductive film 112 serving as a first gate electrode and a conductive film 113 serving as a second gate electrode are formed. The potential applied to the film 106 is a conductive film 120a functioning as a source electrode and a conductive film 120b functioning as a drain electrode. When the potential is lower than that of the conductive film 120b, which functions as a negative stress, the stress is negative. ,In accordance with the measurement environment, Plus GBT (dark), Minus GBT (dark), Plus G Reliability evaluation was performed under four conditions: BT (light irradiation), and negative GBT (light irradiation). .

[0457] In addition, Plus GBT (Dark) is called PBTS (Positive Bias Temperature The following is a description of the negative GBT (Dark Stress). NBTS (Negative Bias Temperature Stress) Let's use PBITS (Positive Bias Illu) as the positive GBT (light irradiation). mination Temperature Stress) minus GBT ( Negative Bias Illumination Te Temperature Stress).

[0458] The GBT test results for Samples 2A to 2J are shown in FIG. 33. In FIG. 33, the vertical axis represents The change in the threshold voltage of the transistor (ΔVth) is shown.

[0459] From the results shown in FIG. 33, the transistors included in Samples 2A to 2J were The change in threshold voltage (ΔVth) was within ±3 V. It can be seen that the transistors included in Samples 2A to 2J have high reliability.

[0460] Therefore, even if the IGZO film has low crystallinity, it has the same defect level as the IGZO film with high crystallinity. It is presumed that a film with low level density is produced.

[0461] This embodiment may be any of the other embodiments, at least some of which are described herein, or any other embodiment. It can be implemented in appropriate combination with the examples. [Example]

[0462] In this example, various measurement methods were used to measure the metal oxide film formed on a substrate, which is one embodiment of the present invention. The results of measurements on Sample 3A and Sample 3B are described below. Sample 3D and Sample 3J were prepared.

[0463] <Sample composition and preparation method> Samples 3A, 3D, and 3J according to one embodiment of the present invention will be described below. Sample 3A, Sample 3D, and Sample 3J each include a substrate and a metal oxide on the substrate.

[0464] The temperatures at which the metal oxide films were formed for Sample 3A, Sample 3D, and Sample 3J were respectively: The sample was prepared under different conditions of the flow rate of oxygen and the flow rate ratio of oxygen. The temperature and oxygen flow rate ratio during metal oxide film formation are shown in Table J.

[0465] [Table 4]

[0466] Next, the method for preparing each sample will be described.

[0467] First, a glass substrate was used as the substrate. Subsequently, using a sputtering apparatus, on the substrate a 100-nm-thick In-Ga-Zn metal oxide was formed as the metal oxide. The film-forming conditions were such that the pressure in the chamber was 0.6 Pa, and for the target, a metal oxide target ( In:Ga:Zn = 1:1:1.2 [atomic ratio]) was used. Also, by supplying 2500 W of AC power to the metal oxide target installed in the sputtering apparatus, the metal oxide was formed into a film.

[0468] Note that as the conditions for forming the metal oxide film, the film-forming temperature and oxygen flow rate shown in the above table were used to obtain Sample 3A, Sample 3D, and Sample 3J.

[0469] Through the above steps, Sample 3A, Sample 3D, and Sample 3J of this example were fabricated.

[0470] '<TEM Image and Electron Diffraction> In this section, the results of observing and analyzing Sample 3A, Sample 3D, and Sample 3J by TEM will be described.

[0471] Also, in this section, the results of obtaining electron diffraction patterns by irradiating Sample 3A, Sample 3D, and Sample 3J with an electron beam (also referred to as a nano-beam electron beam) with a probe diameter of 1 nm will be described.

[0472] Note that the planar TEM image was observed using the spherical aberration correction function. Also, for taking the HAADF-STEM image, a JEOL JEM-ARM200F atomic resolution analytical electron microscope manufactured by JEOL Ltd. was used, and an electron beam with an acceleration voltage of 200 kV and a beam diameter of approximately 0.1 nmφ was irradiated.

[0473] The electron diffraction pattern was observed from the 0-second position to the 35-second position while irradiating the electron beam. The experiment was carried out while moving the object at a constant speed.

[0474] Figure 36(A) shows a cross-sectional TEM image of sample 3A, and Figure 36(B) shows the electron diffraction pattern of sample 3A. The results are shown in Figure 36(C) and Figure 36(D). The results of the 3D electron diffraction pattern are shown in Figure 36(E). FIG. 36(F) shows the electron diffraction pattern of sample 3J.

[0475] As shown in FIG. 36(A), microcrystals were observed in the sample 3A by cross-sectional TEM observation. As shown in FIG. 36(B), the electron diffraction pattern for sample 3A shows a circle. A bright area was observed in a ring-like pattern. The spot was observed.

[0476] As shown in Figure 36(C), the cross-sectional TEM observation of sample 3D revealed a CAAC structure and As shown in Figure 36(D), the electron diffraction pattern for sample 3D was As a result of the turn, a bright area was observed in a circular (ring-like) pattern. In addition, several spots were observed in the ring-like region. A few diffraction patterns were also observed.

[0477] On the other hand, as shown in FIG. 36(E), the cross-sectional TEM observation of Sample 3J revealed that it had a CAAC structure. As shown in FIG. 36(F), the layered arrangement of sample 3J was clearly observed. The electron diffraction pattern obtained is a diffraction pattern containing spots due to the (009) plane. was seen.

[0478] In addition, the features observed in the cross-sectional TEM image and the plan-view TEM image as described above are a one-sided view of the metal oxide structure.

[0479] From the above, the electron diffraction patterns of Sample 3A and Sample 3D have bright regions in a ring shape and a plurality of bright spots in the ring region. Therefore, Sample 3A and Sample 3D have electron diffraction patterns that are metal oxides with microcrystals and have no orientation in the planar direction and the cross-sectional direction. Also, it was found that Sample 3D is a mixed material of nc structure and CAAC structure.

[0480] On the other hand, the electron diffraction pattern of Sample 3J has spots resulting from the (009) plane of the InGaZnO4 crystal. Therefore, it was found that Sample 3J has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper

[0481] <Image Analysis of TEM Image> In this section, the results of observing and analyzing Sample 3A, Sample 3D, and Sample 3J by HAADF-STEM will be described.

[0482] The results of the image analysis of the plan-view TEM image will be described. The plan-view TEM image was observed using a spherical aberration correction function. For the拍摄 of the plan-view TEM image, a JEOL JEM-ARM200F atomic resolution analytical electron microscope manufactured by JEOL Ltd. was used, and an electron beam with an acceleration voltage of 200 kV and a beam diameter of about 0.1 nmφ was irradiated.

[0483] Figure 37(A) is the plan-view TEM image of Sample 3A, and Figure 37(B) is the plan-view TEM image of Sample 3A The processed images are shown in Fig. 37(C) and Fig. 37(D). Figure 37(E) shows a planar TEM image of sample 3J. FIG. 37(F) shows a processed planar TEM image of sample 3J.

[0484] The planar TEM images shown in Figures 37(B), 37(D), and 37(F) were processed. The images obtained were the planar TEM images shown in Figures 37(A), 37(C), and 37(E). This is an image that shows the shading according to the angle of the hexagonal lattice, obtained by image analysis using the method explained in Example 1. In other words, the image obtained by image processing of a planar TEM image is the same as the FFT filtered image of a planar TEM image. By dividing the specific wavenumber region and assigning shading to the region, the grid of each specific wavenumber region can be determined. This is an image in which the orientation of the child points has been extracted.

[0485] As can be seen from Figure 37, in Sample 3A and Sample 3D, where nc is observed, the orientation of the hexagons is random. It was found that the particles were distributed in a mosaic pattern. In addition, a layered structure was observed in the cross-sectional TEM image. In the sample 3J, the hexagons had the same orientation over a wide area of ​​several tens of nanometers. Sample 3D was found to have a random mosaic nc structure and the same nc structure as sample 3J. It was found that there are areas where the same direction is observed over a wide area.

[0486] Furthermore, as shown in FIG. 37, the lower the substrate temperature during film formation or the smaller the oxygen gas flow rate ratio, The orientation of the hexagons is random, and areas that are distributed in a mosaic pattern tend to appear. I found out that...

[0487] Thus, by analyzing the planar TEM image, the hexagonal lattice structure of CAAC-OS was clearly identified. It is possible to evaluate boundaries where angles change.

[0488] Next, a Voronoi diagram was created from the lattice points of Sample 3A. was obtained by the method described.

[0489] FIG. 38(A) shows sample 3A, FIG. 38(B) shows sample 3D, and FIG. 38(C) and sample 3J show The bar graph shows the percentage of Voronoi regions in the image that are either quadrilateral or nonagonal. The number of Voronoi regions of each sample whose shape is either a square or a nonagon is shown. The table shows the percentage of Voronoi regions for each sample that are either quadrilateral or nonagonal.

[0490] As can be seen from Figure 38, the proportion of hexagonal structures is high in sample 3J with high crystallinity, and sample 3A with low crystallinity. It was confirmed that the proportion of hexagons tends to be lower in the 3D sample. The value was between that of sample 3J and sample 3A. Therefore, from Figure 38, it can be seen that the difference in film formation conditions It was confirmed that the crystalline state of metal oxides differs greatly.

[0491] Therefore, as can be seen from FIG. 38, the lower the substrate temperature during film formation or the smaller the oxygen gas flow rate ratio, It was confirmed that the crystallization was low and the proportion of hexagons tended to be low.

[0492] <Elemental analysis> In this article, we will discuss energy dispersive X-ray spectroscopy (EDX). EDX mapping was obtained and evaluated using X-ray spectroscopy. The results of elemental analysis of sample 3A will be explained. The elemental analysis equipment used was the JED-2000 energy dispersive X-ray analyzer manufactured by JEOL Ltd. 2300T. A Si drift detector is used to detect the X-rays emitted from the sample. There are.

[0493] In EDX measurement, each point in the analysis area of ​​the sample is irradiated with an electron beam, and the resulting The energy and frequency of characteristic X-rays of the material are measured, and an EDX spectrum corresponding to each point is obtained. In this example, the peaks in the EDX spectrum at each point are determined as electron transitions to the L shell of the In atom, G Electron transition to the K shell of an a atom, electron transition to the K shell of a Zn atom, and electron transition to the K shell of an O atom The ratio of each atom at each point is calculated. By performing this on the atomic ratios, it is possible to obtain EDX mapping that shows the distribution of the ratios of each atom. can.

[0494] Figure 39 shows TEM images and EDX mapping of the cross section and plane of sample 3A. In EDX mapping, the more elements are measured in the range, the brighter the measurement becomes. The ratio of elements is shown by light and dark, with the darker the element the less it is. The magnification of the X-mapping was 7.2 million times.

[0495] Figure 39(A) is a cross-sectional TEM image, and Figure 39(E) is a planar TEM image. Figure 39(B) is a cross-sectional , and Fig. 39(F) is the EDX mapping of In atoms in the plane. The ratio of In atoms to all atoms in the EDX mapping shown in (B) is 8.64 to 1.04. In the EDX mapping shown in Figure 39(F), The ratio of In atoms to all atoms in the sample ranges from 5.76 to 34.69 atomic%. It was surrounded by

[0496] Also, Figure 39(C) shows the cross section, and Figure 39(G) shows the EDX map of Ga atoms in the plane. In addition, the ratio of Ga atoms to all atoms in the EDX mapping shown in FIG. The ratio of the atoms was set to the range of 2.45 to 25.22 [atomic%]. The ratio of Ga atoms to total atoms in EDX mapping ranges from 1.29 to 27.64[ atomic%] range.

[0497] Also, Figure 39(D) shows the cross section, and Figure 39(H) shows the EDX map of Zn atoms in the plane. In addition, the ratio of Zn atoms to all atoms in the EDX mapping shown in Figure 39(D) is The ratio of the atoms was set to the range of 5.05 to 23.47 [atomic%]. The ratio of Zn atoms to total atoms in EDX mapping ranged from 3.69 to 27.86[ atomic%] range.

[0498] 39(A), 39(B), 39(C), and 39(D) are the results of the specimen 3A. The cross section shows the same area. and FIG. 39(H) show the same area on the plane of sample 3A.

[0499] Figure 40 shows an enlarged view of EDX mapping of the cross section of sample 3A. ) is an enlarged view of a part of FIG. 39(B). FIG. 40(B) is an enlarged view of a part of FIG. 39(C). Figure 40(C) is an enlarged view of a portion of Figure 39(D).

[0500] In the EDX mapping shown in Figure 40(A), Figure 40(B), and Figure 40(C), the images show A relative distribution of light and dark is visible, and it appears that each atom exists with its own distribution in sample 3A. Here, the solid lines shown in Figures 40(A), 40(B), and 40(C) We focused on the area surrounded by the square and the area surrounded by the dashed line.

[0501] In Figure 40(A), the area enclosed by the solid line contains many relatively dark areas, and the area enclosed by the dashed line contains many relatively dark areas. , it was confirmed that it contains many relatively bright areas. The area surrounded by the dashed line contains many relatively bright areas, and the area surrounded by the dashed line contains many relatively dark areas. It was confirmed that this was the case.

[0502] In other words, the area surrounded by the solid line is the area where the In atoms are relatively abundant, and the area surrounded by the dashed line is the area where the In atoms are relatively abundant. It was confirmed that this was an area with relatively few children. In the range, the upper area is a relatively bright area and the lower area is a relatively dark area. Therefore, the area enclosed by the solid line is the In X2 Zn Y2 O Z2 ,Also InO X1 It was found that the main components were

[0503] The area surrounded by the solid line is the area where the number of Ga atoms is relatively small, and the area surrounded by the dashed line is the area where the number of Ga atoms is relatively small. It was confirmed that this was an area with a relatively large number of children. In this case, the right area is a relatively bright area, and the left area is a dark area. In addition, in the area enclosed by the dashed line at the bottom of Figure 40(C), the upper left area is relatively It was confirmed that the area in the lower right corner was a bright area, and the area in the lower right corner was a dark area. The area enclosed by the line is GaO X3 , or Ga X4 Zn Y4 O Z4 In the area where the main components are I discovered something.

[0504] Also, from Figures 40(A), 40(B), and 40(C), the distribution of In atoms is The atoms are relatively uniformly distributed, and X1 The region where is the main component is In X2 Zn Y2 O Z2 It appears that they are connected to each other through the area where In this way, X2 Zn Y2 O Z2 , or InO X1 The area where is the main component is It can be assumed that it is formed in a loud, spreading manner.

[0505] Thus, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 In-Ga-Zn oxide with a structure in which the regions in which The material can be called CAC-IGZO.

[0506] Also, in Figures 40(A), 40(B), and 40(C), GaO X3 is the main component The region where In X2 Zn Y2 O Z2 , or InO X1 The size of the region where is the principal component The observed size was 0.5 nm to 10 nm or 1 nm to 3 nm.

[0507] On the other hand, Figure 41 shows the TEM images and EDX maps of the cross section and plane of sample 3J. In EDX mapping, the more elements are measured in a range, the brighter the image becomes. The ratio of elements is shown by light and dark, with the darker the measured element, the less it is. The magnification of the EDX mapping was 7.2 million times.

[0508] Figure 41(A) is a cross-sectional TEM image, and Figure 41(E) is a planar TEM image. Figure 41(B) is a cross-sectional , and Fig. 41(F) is the EDX mapping of In atoms in the plane. The ratio of In atoms to all atoms in the EDX mapping shown in (B) is 9.70 to In the EDX mapping shown in FIG. The ratio of In atoms to all atoms in the sample ranges from 9.16 to 35.76 atomic%. It was surrounded by

[0509] Also, Figure 41(C) shows the cross section, and Figure 41(G) shows the EDX map of Ga atoms in the plane. In addition, the ratio of Ga atoms to all atoms in the EDX mapping shown in FIG. The ratio of the atoms was set to the range of 8.23 ​​to 31.95 [atomic%]. The ratio of Ga atoms to total atoms in EDX mapping ranges from 8.21 to 28.86[ atomic%] range.

[0510] Also, Figure 41(D) shows the cross section, and Figure 41(H) shows the EDX map of Zn atoms in the plane. In addition, the ratio of Zn atoms to all atoms in the EDX mapping shown in FIG. The ratio of the atoms was set to the range of 5.37 to 25.92 [atomic%]. The ratio of Zn atoms to total atoms in EDX mapping ranged from 7.86 to 24.36[ atomic%] range.

[0511] 41(A), 41(B), 41(C), and 41(D) are the results of sample 3J. The cross section shows the same area. and FIG. 41(H) show the same area on the plane of sample 3J.

[0512] In Figure 41(A), a group of crystals with lateral growth is clearly observed, and in Figure 41(E), a group of hexagonal crystals is observed. Null structured crystals with an angle of 120° were observed.

[0513] EDX mapping of In atoms and Zn atoms shown in Figure 41(B) and Figure 41(D) Looking at the image, we observed a row of bright spots, as shown by the white lines. In Figure 41(F) and Figure 41(H), the angle between these lines is approximately 120°. It has a hexagonal structure, and in Fig. 41(B) and Fig. 41(D), Fig. 41(A) As shown in Figure 41(C) and Figure 41(G), No such tendency was observed for Ga atoms.

[0514] The resolution of EDX is generally affected by the presence or absence of regularity in the atomic arrangement. When the electron arrangement is regular, the atoms are aligned in a straight line relative to the direction of the beam incidence. The incident electrons are channeled and propagated, so that the atomic columns can be separated. When the regularity of the rows is low, the atomic rows fluctuate relative to the direction of the beam incidence, and the incident electrons This means that the spatial resolution is reduced and the image obtained is blurred. It may be observed in this state.

[0515] In other words, CAAC is not as crystalline as a single crystal, so the beam spreads and the EDX It is thought that the resolution of the HAADF-STEM was not as high as that of the HAADF-STEM, and the images were observed in a blurred state. Also, as can be seen from Figure 39, the beam of the CAC appears to be expanded, so The atom can be judged to be a nanoparticle with a broad periphery.

[0516] From the above, CAC-IGZO has a structure different from that of IGZO compounds in which metal elements are uniformly distributed. It was found that the CAC-IG compound has different properties from the IGZO compound. ZO is GaO X3 The region where In is the main component. X2 Zn Y2 O Z2 , or InO X1 The regions where each element is the main component are separated into two phases, and the regions where each element is the main component are formed in a mosaic pattern. It was confirmed that the compound has the following structure:

[0517] Therefore, when CAC-IGZO is used in semiconductor devices, GaO X3 The properties resulting from , In X2 Zn Y2 O Z2 , or InO X1 The properties resulting from this work in a complementary manner. This results in a high on-state current (I on ), high field-effect mobility (μ), and low off-state current ( It is expected that a semiconductor device using CAC-IGZO will achieve a high Ioff. Therefore, CAC-IGZO is suitable for a variety of applications, including displays. It is ideal for semiconductor devices.

[0518] This embodiment may be any of the other embodiments, at least some of which are described herein, or any other embodiment. It can be implemented in appropriate combination with the examples. [Example]

[0519] In this example, a transistor 150 including a metal oxide 108 according to one embodiment of the present invention is In this example, the metal oxide 1 was used. As the transistor 150 having the .O8, Sample 4A, Sample 4B, Sample 4C, Sample 4D, Sample Nine types of transistors were fabricated: Sample 4E, Sample 4F, Sample 4G, Sample 4H, and Sample 4J. Ta.

[0520] <Sample composition and preparation method> Hereinafter, Sample 4A, Sample 4B, Sample 4C, Sample 4D, Sample 4E, Samples 4F, 4G, 4H, and 4J will be described. 6 by the manufacturing method described in the second embodiment and FIGS. 9 to 11. A transistor 150 having the following structure was fabricated.

[0521] The samples 4A to 4J were prepared by varying the temperature and the acid concentration during the deposition of the metal oxide 108. The metal oxide composition of Samples 4A to 4J was measured under different conditions. The temperature and oxygen flow rate during film formation are shown.

[0522] [Table 5]

[0523] Each sample was prepared by the method described in the second embodiment. In the film formation step 108, the target is a metal oxide target (In:Ga:Zn= Atomic ratio of 1:1:1.2 was used.

[0524] The channel length of the transistor 150 is 2 μm, and the channel width is 3 μm (hereinafter, L / W= 2 / 3 μm).

[0525] <Transistor Id-Vg characteristics> Next, the Id of the transistors (L / W=2 / 3 μm) of Samples 4A to 4J fabricated as described above was measured. The Id-Vg characteristics of the transistor were measured under the following conditions: The voltage applied to the conductive film 112 functioning as the gate electrode (hereinafter referred to as gate voltage (Vg)) and a voltage (hereinafter referred to as a voltage) applied to the conductive film 106 functioning as the second gate electrode. The back gate voltage (Vbg) is changed from -10V to +10V in 0.25V steps. The voltage applied to the conductive film 120a functioning as the source electrode (hereinafter, Source voltage (V s ) is set to 0V (comm), and the conductive layer that functions as the drain electrode The voltage applied to the conductive film 120b (hereinafter also referred to as drain voltage (Vd)) was set to 0.1 V and It was set to 20V.

[0526] FIG. 42 shows the Id-Vg characteristics and field-effect mobility of Samples 4A to 4J, respectively. The solid line shows Id when Vd is 20 V, and the dashed line shows Id when Vd is 0.1 V. The dashed line shows the field-effect mobility calculated from the measured value when Vd was 20 V, and the dotted line shows the field-effect mobility calculated from the measured value when Vd was 20 V. indicates the field-effect mobility calculated from the value measured when Vd was 0.1 V. In the graph, the first vertical axis represents Id [A] and the second vertical axis represents field-effect mobility (μFE [cm 2 / Vs ]) and the horizontal axis represents Vg [V].

[0527] As shown in FIG. 42, the transistors 150 of Samples 4A to 4J have normally-off characteristics. As shown in FIG. 42, the characteristics of Samples 4A to 4J are as follows: on), and it can be confirmed that the field-effect mobility, especially in the saturated region, is different. In particular, the shape of the field-effect mobility is shown in the maximum saturated mobility value and the rising edge near 0 V. It was found that the shape of the field-effect mobility rise characteristics was significantly different.

[0528] From Figure 42, the lower the substrate temperature during film formation or the smaller the oxygen flow rate during film formation, the lower the It was found that the field-effect mobility at Vg was significantly improved. The maximum field effect mobility is 40 cm 2 / V s It was confirmed that the value was close to that of High mobility means that the device is suitable for high-speed driving at low voltage, and is suitable for display It was found that this material can be expected to be applied to a variety of semiconductor devices, including

[0529] Also, from FIG. 42, the field-effect mobility is measured when Vd is 20 V (dashed line), A different behavior was observed when Vd was 0.1 V (dotted line). The value measured at 0 V (dashed line) shows that the field-effect mobility increased as Vg increased. This is thought to be due to the effect of heat generated by the transistor. In the values ​​measured by the above method (dotted line), in the high Vg range, The values ​​almost overlap with the ideal saturated mobility curve.

[0530] This embodiment may be any of the other embodiments, at least some of which are described herein, or any other embodiment. It can be implemented in appropriate combination with the examples. [Example]

[0531] In this example, a metal oxide film according to one embodiment of the present invention formed on a substrate was analyzed using an energy By using dispersive X-ray spectroscopy (EDX) to obtain and evaluate EDX mapping The results of elemental analysis of the sample are described below. The energy dispersive X-ray analyzer JED-2300T manufactured by JEOL Ltd. was used. A Si drift detector was used to detect the X-rays emitted from the sample.

[0532] <Sample composition and preparation method> In this example, Sample 5A was prepared. Sample 5A consisted of a substrate, a metal oxide on the substrate, and , has.

[0533] Next, a method for preparing the sample will be described.

[0534] First, a glass substrate was used as the substrate. Then, a sputtering device was used to deposit a thin film on the substrate. A 100 nm thick In-Ga-Zn oxide was formed as a metal oxide on the substrate. The pressure in the chamber was set to 0.6 Pa, and the sputtering gas was A The target was a metal oxide target under an O2 atmosphere with a flow rate of 30 sccm. (In:Ga:Zn=4:2:4.1 [atomic ratio]) was used. By supplying 2500W of AC power to the metal oxide target placed in the chamber, An oxide film was formed.

[0535] Through the above steps, Sample 5A of this example was fabricated.

[0536] <Measurement results> In EDX measurement, each point in the analysis area of ​​the sample is irradiated with an electron beam, and the resulting The energy and frequency of characteristic X-rays of the material are measured, and an EDX spectrum corresponding to each point is obtained. In this example, the peaks in the EDX spectrum at each point are determined as electron transitions to the L shell of the In atom, G Electron transition to the K shell of an a atom, electron transition to the K shell of a Zn atom, and electron transition to the K shell of an O atom The ratio of each atom at each point is calculated. By performing this on the atomic ratios, it is possible to obtain EDX mapping that shows the distribution of the ratios of each atom. can.

[0537] FIG. 43 shows the measurement results for the cross section of sample 5A. EM images, Figure 43(B) and Figure 43(C) show EDX mapping of the cross section. In EDX mapping, the more elements are measured in a range, the brighter the area becomes. The ratio of elements is shown by light and dark, with the darker the amount of element, the less the amount. The ping magnification was set to 7.2 million times. C) shows the same area in the cross section of sample 5A.

[0538] Figure 43(B) shows EDX mapping of In atoms in the cross section. The ratio of In atoms to total atoms in the EDX maps shown ranges from 12.11 to 40. The range was set to 30 [atomic %]. Also, Figure 43(C) shows the E of Ga atoms in the cross section. It should be noted that the EDX mapping for all atoms in the EDX mapping shown in Figure 43(C) The ratio of Ga atoms was set in the range of 0.00 to 13.18 [atomic %].

[0539] In the EDX mapping shown in Figure 43(B) and Figure 43(C), the image shows relative brightness and darkness. In sample 5A, In atoms and Ga atoms exist with a distribution. Here, in the range of the highest luminance in Figure 43(B) from the highest luminance to the top 25%, The five areas enclosed by lines (area 901, area 902, area 903, area 904, and area 9 05) were extracted. In addition, in the range of the top 25% from the high brightness in Figure 43(C), The five surrounding regions (region 906, region 907, region 908, region 909, and region 910) ) were extracted. In addition, the range of the top 75% and top 25% from the high brightness in Figure 43(B) was , and in the range of the top 75% or more and the top 25% or less from the high brightness in Figure 43(C), The five areas enclosed by (area 911, area 912, area 913, area 914, and area 91 5) was extracted.

[0540] That is, the regions 901 to 905 are regions that contain a relatively large number of In atoms. The regions 906 to 910 are regions containing a relatively large number of Ga atoms. Regions 911 to 915 are regions containing In atoms and Ga atoms on average.

[0541] In Figure 43(C), the area where Ga atoms are relatively abundant, that is, the five areas surrounded by dashed lines (areas 906, region 907, region 908, region 909, and region 910) are shown in FIG. In other words, the region with a relatively large number of Ga atoms has a relatively large number of In atoms. It was estimated to be relatively small.

[0542] Therefore, the ratio of each element in the regions 901 to 915 shown in FIG. 43(B) is The area surrounded by the black lines (area 901, area 902, area 903, area 904, and and region 905) are regions with relatively many In atoms and relatively few Ga atoms. In addition, the area enclosed by the dashed lines (area 906, area 907, area 908, area 909) , and region 910) are regions with relatively few In atoms and many Ga atoms. Done.

[0543] Next, Fig. 44 shows the measurement results on the plane of sample 5A. TEM images of the sample, and Fig. 44(B) and Fig. 44(C) show EDX mapping in the plane. 44(A), 44(B), and 44(C) are diagrams showing the structure of the sample 5A on a plane. The same range of regions was shown.

[0544] Figure 44(B) shows the EDX mapping of In atoms on a plane. The ratio of In atoms to total atoms in the EDX maps shown ranges from 12.11 to 43. The range was 80 [atomic %]. Also, Figure 44(C) shows the E of Ga atoms on the plane. It should be noted that the EDX mapping for all atoms shown in Figure 44(C) is The ratio of Ga atoms was set in the range of 0.00 to 14.83 [atomic %].

[0545] In the EDX mapping shown in Figure 44(B) and Figure 44(C), the image shows the relative brightness and darkness. In sample 5A, In atoms and Ga atoms exist with a distribution. Here, in the range of the highest luminance in Figure 44(B) or above, the upper 25% , the five areas surrounded by black lines (area 921, area 922, area 923, area 924, and area In addition, in the range of the top 25% or more from the high brightness in Figure 44(C), , the five ranges enclosed by dashed lines (area 926, area 927, area 928, area 929, and area In addition, the top 75% and top 25% of the high brightness areas in Figure 44(B) were extracted. In the lower range, and in the range of the top 75% or more and the top 25% or less from the high brightness in Figure 44(C), The five areas surrounded by white lines (area 931, area 932, area 933, area 934, and Region 935) was extracted.

[0546] First, in Figure 44(C), the area where Ga atoms are relatively abundant, that is, the five areas surrounded by dashed lines, (Area 926, area 927, area 928, area 929, and area 930) are shown in FIG. In B), a relatively dark region was observed. In other words, the region with a relatively large number of Ga atoms is the region with a relatively large number of In atoms. It was estimated that the number of children was relatively small.

[0547] Therefore, the ratio of each element in the region 921 to the region 935 shown in FIG. 44(B) is The area surrounded by the black lines (area 921, area 922, area 923, area 924, and and region 925) are regions with relatively many In atoms and relatively few Ga atoms. In addition, the area enclosed by the dashed lines (area 926, area 927, area 928, area 929) , and region 930) are regions with relatively few In atoms and many Ga atoms. Done.

[0548] From Figure 43(D) and Figure 44(D), it can be seen that the In atoms are 25 atomic % or more and 60 atomic % or less. It was found that the distribution was in the range of 3atoms or less. It was found that the distribution ranged from ic% to 40 atomic%.

[0549] It can be assumed that the region with a relatively high concentration of In atoms has a relatively high conductivity. Therefore, it can be assumed that the region with a relatively large number of In atoms has relatively high insulating properties. When carriers flow through the region, conductivity is generated, resulting in high field-effect mobility (μ). On the other hand, the region with a relatively large number of Ga atoms has a distribution in the metal oxide. This is thought to have suppressed leakage current and achieved good switching operation.

[0550] In other words, when a metal oxide having a CAC structure is used in a semiconductor device, the The insulating properties due to the In atoms and the conductivity due to the In atoms work in a complementary manner, resulting in a high on-state current. It can be said that high current (Ion) and high field-effect mobility (μ) were achieved.

[0551] This embodiment may be any of the other embodiments, at least some of which are described herein, or any other embodiment. It can be implemented in appropriate combination with the examples. [Example]

[0552] In this example, a transistor 150 including a metal oxide 108 according to one embodiment of the present invention is In this example, the metal oxide 108 was The transistor 150 includes Samples 6A, 6B, 6C, 6D, and 6E. Nine types of transistors were fabricated: Sample 6A, Sample 6B, Sample 6C, Sample 6D, Sample 6E, Sample 6F, Sample 6G, Sample 6H, and Sample 6J.

[0553] <Sample composition and preparation method> Samples 6A to 6J according to one embodiment of the present invention will be described below. Sample 6J was fabricated by the method described in the second embodiment and in FIGS. A transistor 150 having the structure shown in FIG. 6 was fabricated.

[0554] The samples 6A to 6J were prepared by varying the temperature during the formation of the metal oxide 108 and the The oxygen flow rate was varied. The target was a metal oxide target (In:Ga:Zn=1:1:1.2 [atomic ratio] The table below shows the temperature and acid used during metal oxide film formation for Samples 6A to 6J. The element flow rate ratio is shown.

[0555] [Table 6]

[0556] Each sample was fabricated by the fabrication method described in the second embodiment.

[0557] The channel length of the transistor 150 is 2 μm, and the channel width is 3 μm (hereinafter, L / W= 2 / 3μm), or the channel length is 2μm and the channel width is 50μm (hereafter referred to as L / W = 2 / 50 μm).

[0558] <Evaluation of shallow defect levels using transistor characteristics> [Method for evaluating the density of shallow defect states] The shallow defect states (hereinafter referred to as sDOS) of metal oxides are used as semiconductors. It can also be estimated from the electrical characteristics of the transistor. The density of the interface states is evaluated, and the number of electrons trapped in the interface states, N t rap How to predict subthreshold leakage current when explain.

[0559] Number of electrons trapped in the interface state N trap is, for example, the drain current of a transistor - Measured values ​​of gate voltage (Id-Vg) characteristics and drain current-gate voltage (Id-Vg) characteristics The evaluation can be carried out by comparing the calculated values ​​of the

[0560] Figure 45 shows the calculated results for the source voltage Vs = 0V and the drain voltage Vd = 0.1V. The ideal Id-Vg characteristics obtained and the actually measured Id-Vg characteristics of the transistor are compared. Among the measurement results of the transistor, the drain current Id is easily measured at 1 × 10 -13 Only values ​​above A are plotted.

[0561] Compared to the ideal Id-Vg characteristics calculated by calculation, the actual Id-Vg characteristics are The change in drain current Id with respect to the energy of the conduction band minimum (E This is thought to be because electrons are trapped in shallow interface states located near the interface. Here, the Fermi distribution function is used to estimate the trapping in shallow interface states (unit area, Number of electrons (per unit energy) N trap By taking this into consideration, the density of the interface states can be calculated more precisely. degree N it can be estimated.

[0562] First, the electrons trapped in the interface trap states are measured using the schematic Id-Vg characteristics shown in FIG. Number of electrons N trap The dashed line indicates the trap level obtained by calculation. The dashed line shows the ideal Id-Vg characteristics without any offset. The change in gate voltage Vg when it changes from Id2 to Id3 is ΔV id The solid line represents the actual measurement. The solid line shows the Id-Vg characteristics of the transistor. When the drain current changes from Id1 to Id2, The change in gate voltage Vg is expressed as ΔV exWhen the drain current is Id1 and Id2, The potentials at the target interfaces are φ it1 , φ it2 The change amount is Δφ it Tosu do.

[0563] In Figure 46, the measured value has a smaller slope than the calculated value, so ΔV ex is always ΔV id twist At this time, ΔV ex and ΔV id The difference in the electron transport rate to the shallow interface states Therefore, the charge change due to the trapped electrons is amount ΔQ trap can be expressed by the following equation (6).

[0564]

number

[0565] C tg is the combined capacitance of the insulator and semiconductor per area. Also, ΔQ trap is a truck Number of electrons (per unit area, per unit energy) N trap Using Eq. (7), It can also be expressed as: where q is the elementary charge.

[0566]

number

[0567] Equation (6) and Equation (7) can be solved simultaneously to obtain Equation (8).

[0568]

number

[0569] Next, the limit Δφ of Eq. (8)it By taking 0, we can obtain equation (9).

[0570]

number

[0571] That is, using the ideal Id-Vg characteristics, the measured Id-Vg characteristics, and equation (9), The number of trapped electrons in trap It is possible to estimate the drain current and The relationship with the potential at the interface can be determined by the above calculation.

[0572] Also, the number of electrons per unit area and unit energy, N trap and the density of interface states N it is an expression The relationship is as shown in (10).

[0573]

number

[0574] where f(E) is the Fermi distribution function. N obtained from Eq. (9) trap to the equation (1 0), N it is determined. it Devices that have been configured Transfer characteristics including Id<0.1pA can be obtained by calculation using a simulator. .

[0575] Next, equation (9) is applied to the measured Id-Vg characteristics shown in Figure 45, and N trap The results of extracting The results are shown by white circles in Figure 47. Here, the vertical axis of Figure 47 is the distance from the minimum conduction band Ec of the semiconductor to the The maximum value is the lumi energy Ef. Looking at the dashed line, it is located just below Ec. (10)N itAssuming the tail distribution of Equation (11), the non-linear distribution is shown by the dashed line in Figure 47. Always good trap can be fitted, and the conduction band edge The trap density N ta =1.67×10 13 cm -2 / eV, characteristic decay energy W ta =0.105 eV was obtained.

[0576]

number

[0577] Next, the obtained fitting curve of the interface state was subjected to calculation using a device simulator. The results of back-calculating the Id-Vg characteristics are shown in Figure 48(A) and Figure 48(B). 48(B). In FIG. 48(A), when the drain voltage Vd is 0.1V and 1.8V, The Id-Vg characteristics obtained by the calculation and the drain voltage Vd of 0.1V and 1.8V 48(B) shows the Id-Vg characteristics of the transistor measured in the case of 10 is a graph showing the logarithm of the drain current Id at 48(A).

[0578] The calculated curve and the plot of the actual measured values ​​are almost identical. Therefore, it is possible to use this method as a method for calculating the density of shallow defect states. ,It can be seen that the above method is quite reasonable.

[0579] [Evaluation results of shallow defect level density] Next, by comparing the measured electrical characteristics with the ideal calculated values ​​based on the above method, Sample 6A, Sample 6B, Sample 6C, Sample 6D, Sample 6E, Sample 6F, Sample 6G, Sample 6 The shallow defect level densities of H and sample 6J were measured.

[0580] Figure 49 shows sample 6A, sample 6B, sample 6C, sample 6D, sample 6E, sample 6F, sample 6G, and sample 6G. The results of calculating the average values ​​of the shallow defect level densities of Sample 6H and Sample 6J are shown.

[0581] As shown in FIG. 49, the smaller the oxygen flow rate ratio during film formation of the metal oxide 108, and The lower the temperature during the process, the lower the peak value of the shallow defect density. Understood.

[0582] As described above, Samples 6A to 6J are substrates in which metal oxide films with low defect level densities are formed. In particular, the metal oxide film formed under the conditions of low temperature and low oxygen flow rate was By using a nitride film, oxygen permeability is improved, and the amount of oxygen that diffuses during the transistor manufacturing process is reduced. As a result, oxygen vacancies in the metal oxide film and at the interface between the metal oxide film and the insulating film occur. This is presumably because defects in the

[0583] This embodiment may be any of the other embodiments, at least some of which are described herein, or any other embodiment. It can be implemented in appropriate combination with the examples. [Example]

[0584] In this example, a transistor 150 including a metal oxide 108 according to one embodiment of the present invention is In this example, the metal oxide 108 was As the transistor 150 having the above structure, Samples 7A, 7B, 7C, 7D, and 7E are used. Nine types of transistors were fabricated: Sample 7A, Sample 7B, Sample 7C, Sample 7D, Sample 7E, Sample 7F, Sample 7G, Sample 7H, and Sample 7J.

[0585] <Sample composition and preparation method> Samples 7A to 7J according to one embodiment of the present invention will be described below. Sample 7J was fabricated by the method described in the second embodiment and in FIGS. A transistor 150 having the structure shown in FIG. 6 was fabricated.

[0586] The samples 7A to 7J were prepared by varying the temperature during the formation of the metal oxide 108 and the temperature during the formation of the metal oxide 108. The oxygen flow rate was varied. The target was a metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) The table below shows the temperature and acid used during metal oxide film formation for Samples 7A to 7J. The element flow rate ratio is shown.

[0587] [Table 7]

[0588] Each sample was fabricated by the fabrication method described in the second embodiment.

[0589] The channel length of the transistor 150 is 2 μm, and the channel width is 3 μm (hereinafter, L / W= 2 / 3μm), or the channel length is 2μm and the channel width is 50μm (hereafter referred to as L / W = 2 / 50 μm).

[0590] <Evaluation of shallow defect levels using transistor characteristics> [Method for evaluating the density of shallow defect states] The shallow defect levels of metal oxides 108 are used as the electric field of transistors that use metal oxides as semiconductors. The calculation method was the same as that described in the previous example. The density of the interface states of the transistor was evaluated, and in addition to the density of the interface states, the Number of trapped electrons N trap When the subthreshold leakage current is taken into consideration, predicted the flow.

[0591] [Evaluation results of shallow defect level density] Next, by comparing the measured electrical characteristics with the ideal calculated values ​​based on the above method, Sample 7A, Sample 7B, Sample 7C, Sample 7D, Sample 7E, Sample 7F, Sample 7G, Sample 7 The shallow defect level densities of H and sample 7J were measured.

[0592] Figure 50 shows sample 7A, sample 7B, sample 7C, sample 7D, sample 7E, sample 7F, sample 7G, and sample 7G. The results of calculating the average values ​​of the shallow defect level densities of Sample 7H and Sample 7J are shown.

[0593] As shown in FIG. 50, the smaller the oxygen flow rate ratio during film formation of the metal oxide 108, and The lower the temperature during the process, the lower the peak value of the shallow defect density. Understood.

[0594] As described above, Samples 7A to 7J are the substrates in which metal oxide films with low defect level densities are formed. In particular, the metal oxide film formed under the conditions of low temperature and low oxygen flow rate was By using a nitride film, oxygen permeability is improved, and the amount of oxygen that diffuses during the transistor manufacturing process is reduced. As a result, oxygen vacancies in the metal oxide film and at the interface between the metal oxide film and the insulating film occur. This is presumably because defects in the

[0595] This embodiment may be any of the other embodiments, at least some of which are described herein, or any other embodiment. It can be implemented in appropriate combination with the examples. [Example]

[0596] In this example, a transistor 150 including a metal oxide 108 according to one embodiment of the present invention is In this example, the metal oxide 1 was used. As the transistor 150 having 08, the transistor of Sample 8A was fabricated.

[0597] <Sample composition and preparation method> In the following, a sample 8A according to one embodiment of the present invention will be described. A transistor having the structure of FIG. 6 can be fabricated by the fabrication method described in Embodiment 2 and FIGS. 9 to 11. We created 150.

[0598] The table below shows the temperature and oxygen flow rate ratio during deposition of the metal oxide 108 for Sample 8A.

[0599] [Table 8]

[0600] Sample 8A was fabricated by the fabrication method described in the second embodiment. In the film formation process of the object 108, the target is a metal oxide target (In:Ga:Zn = 5:1:7 [atomic ratio]) was used.

[0601] The channel length of the transistor 150 is 3 μm, and the channel width is 50 μm (hereinafter, L / W = 3 / 50 μm).

[0602] <Transistor Id-Vg characteristics> Next, the Id-Vg characteristics of the transistor (L / W=3 / 50 μm) of sample 8A fabricated above were measured. The Id-Vg characteristics of the transistor were measured under the following conditions: a voltage (hereinafter also referred to as gate voltage (Vg)) applied to the conductive film 112 that functions as an electrode; and a voltage applied to the conductive film 106 functioning as a second gate electrode (hereinafter referred to as a back gate Apply a voltage (also called Vbg) from -10V to +10V in 0.25V steps. In addition, the voltage applied to the conductive film 120a functioning as the source electrode (hereinafter referred to as the source voltage) Pressure (V s ) is set to 0 V (comm), and the conductive film 12 The voltage applied to 0b (hereinafter referred to as drain voltage (Vd)) was set to 0.1V and 20V. did.

[0603] Figure 51 shows the Id-Vg characteristics and field-effect mobility of Sample 8A. The dashed line indicates Id when Vd is 20V, and the dashed line indicates Id when Vd is 0.1V. In FIG. 51, the first vertical axis represents Id [A], and the second vertical axis represents is the field-effect mobility (μFE [cm 2 / V s ]) and the horizontal axis represents Vg [V]. The field effect mobility was calculated from the value measured when Vd was set to 20V.

[0604] In Figure 51, the upper limit of Id during measurement is set to 1 mA. Under the condition of Vd=20V, Id exceeds this upper limit when Vg=7.5V. Therefore, in Figure 51, the field effect mobility estimated from the Id-Vg characteristics is The range of Vg=7.5V or less is clearly indicated.

[0605] As shown in FIG. 51, the transistor fabricated in this example has good electrical characteristics. The characteristics of the transistor shown in FIG. 51 are shown in Table 9.

[0606] [Table 9]

[0607] Thus, the transistor fabricated in this example has a field effect mobility of 100 cm 2 / Vs This is a high value comparable to that of transistors using low-temperature polysilicon. This is an astonishing characteristic for a transistor using the metal oxide 108.

[0608] As shown in Table 9, sample 8A is used when the gate voltage of the transistor is greater than 0 V and less than or equal to 10 V. The maximum field-effect mobility in the range of 60 cm 2 / Vs or more 150cm 2 / Vs less A first region, a second region in which the threshold voltage is −1 V or more and 1 V or less, and an S value in which A third region where the off-state current is less than 0.3 V / decade and the off-state current is less than 1×10 -12 A / cm 2 and a fourth region where the maximum field effect mobility of the transistor is μFE( max), and the field effect mobility value at a gate voltage of 2 V is expressed as μFE( When expressed as μFE(max) / μFE(Vg=2V), μFE(max) / μFE(Vg=2V) is greater than or equal to 1 and less than 2. It becomes full.

[0609] The characteristics of the above transistor are obtained by using the metal oxide 108 described above. By using the metal oxide 108 for the semiconductor layer of the transistor, the carrier mobility is high. Therefore, it is possible to simultaneously realize the function of providing a high switching characteristic and the function of providing a high switching characteristic.

[0610] This embodiment may be any of the other embodiments, at least some of which are described herein, or any other embodiment. It can be implemented in appropriate combination with the examples. [Explanation of symbols]

[0611] 001 area 002 Area 100 transistors 102 Circuit Board 104 insulating film 106 Conductive film 108 Metal Oxides 108a Metal oxide 108n area 110 insulating film 110_0 Insulating film 112 Conductive film 112_0 Conductive film 112_1 Conductive film 112_2 Conductive film 116 Insulating film 118 insulating film 120a Conductive film 120b Conductive film 122 insulating film 140 Mask 141a opening 141b opening 143 Opening 150 transistors 160 transistors 300A transistor 300B transistor 300C transistor 300D transistor 302 Substrate 304 Conductive film 306 Insulating film 307 Insulating Film 308 Metal Oxides 312a Conductive film 312b Conductive film 314 Insulating film 316 Insulating Film 318 Insulating Film 320a Conductive film 320b Conductive film 341a opening 341b opening 342a opening 342b opening 342c opening 600 display panel 601 Transistor 604 Connection 605 Transistor 606 Transistor 607 Connection 612 Liquid crystal layer 613 Conductive film 617 Insulating Film 620 insulating film 621 Insulating film 623 Conductive Film 631 Colored layer 632 Light-shielding film 633a Alignment film 633b Alignment film 634 Colored layer 635 Conductive film 640 Liquid Crystal Devices 641 Adhesive layer 642 Adhesive layer 643 Conductive Film 644 EL layer 645a Conductive film 645b Conductive film 646 Insulating Film 647 Insulating Film 648 Conductive Film 649 Connection Layer 651 Circuit Board 652 Conductive film 653 Semiconductor Film 654 Conductive film 655 Aperture 656 Polarizing Plate 659 circuits 660 Light-emitting element 661 Circuit Board 662 Display section 663 Conductive Film 666 Wiring 672 FPC 673 IC 681 Insulating Film 682 insulating film 683 Insulating Film 684 insulating film 685 insulating film 686 Connector 687 Connection 700 model 702 Local Structure 704 Local Structure 706 Local Structure 708 Local Structure 710 Local Structure 712 Local Structure 901 area 902 area 903 area 904 area 905 area 906 area 907 area 908 area 909 area 910 area 911 area 912 areas 913 area 914 area 915 area 920 areas 921 area 922 areas 923 areas 924 areas 925 areas 926 areas 927 areas 928 areas 929 areas 930 area 931 area 932 areas 933 areas 934 areas 935 areas

Claims

1. A display unit is provided on a substrate, and a driver is provided to drive the display unit. the display unit includes a first transistor; the driver includes a second transistor; the first transistor and the second transistor each have a metal oxide film in a channel formation region; the metal oxide film is a single layer and has first and second regions mixed in a mosaic pattern within the metal oxide film; the first region includes In, Ga, and Zn; the second region includes In, Ga, and Zn; the first region is a region in which the concentration of In shown in an energy dispersive X-ray spectroscopy mapping image is higher than that of the second region, the second region is a region in which a Ga concentration shown in an energy dispersive X-ray spectroscopy mapping image is higher than that of the first region, The display device, wherein the metal oxide film has microcrystals.

2. A display unit is provided on a substrate, and a driver is provided to drive the display unit. the display unit includes a first transistor; the driver includes a second transistor; the first transistor and the second transistor each have a metal oxide film in a channel formation region; the metal oxide film is a single layer and has first and second regions mixed in a mosaic pattern within the metal oxide film; the first region includes In, Ga, and Zn; the second region includes In, Ga, and Zn; the first region is a region in which the concentration of In shown in an energy dispersive X-ray spectroscopy mapping image is higher than that of the second region, the second region is a region in which a Ga concentration shown in an energy dispersive X-ray spectroscopy mapping image is higher than that of the first region, The display device, wherein the metal oxide film has a region in which a plurality of spots are observed in a ring-shaped region in an electron diffraction pattern.

Images