METHOD OF OPERATING A NON-VOLATILE MEMORY DEVICE FOR PROGRAMMING MULTI-PAGE DATA - Patent application

Abstract

To provide a method for operating a nonvolatile memory device for programming multi-page data.SOLUTION: An operation method includes: a step of receiving multi-page data from a memory controller; a step of programming first page data in a first memory cell coupled to a word line adjacent to a selection word line; a step of reading, based on a first sensing value and a second sensing value, previous page data previously saved in a second memory cell coupled to the selection word line after the first page data was programmed; and a step of programming, with a fail bit number calculated through comparison between a first bit of the previous page data read based on the first sensing value and a second bit of the previous page data read based on the second sensing value, in the second memory cell, the second page data included in the previous page data and the multi-page data read from the second memory cell.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to a method of operating a non-volatile memory device for programming multi-page data. [Background technology]

[0002] Semiconductor memory is divided into volatile memory devices such as SRAM and DRAM, in which stored data disappears when the power supply is cut off, and non-volatile memory devices such as flash memory devices, PRAM, MRAM, RRAM, and FRAM, in which stored data is retained even when the power supply is cut off.

[0003] Among nonvolatile memory devices, flash memory devices can perform program operations in units of pages or word lines. Flash memory devices can program data corresponding to multiple pages (hereinafter referred to as multi-page data) into memory cells connected to selected word lines. In this case, each memory cell can store multiple bits.

[0004] When a high program voltage is applied to a selected word line during a program process for multi-page data, degradation may occur in memory cells connected to word lines adjacent to the selected word line. To reduce this degradation, a program technique is used in which some pages of the multi-page data are programmed first and the remaining pages are programmed later during one program cycle for multi-page data. This program technique may reduce the reliability of the flash memory device due to the level of errors that occur during a program operation related to some pages of data. Summary of the Invention [Problem to be solved by the invention]

[0005] SUMMARY OF THE INVENTION An object of the present invention is to provide a program operation method for a nonvolatile memory device for improving the reliability of the nonvolatile memory device. [Means for solving the problem]

[0006] According to an embodiment of the present invention, a method for operating a nonvolatile memory device for programming multi-page data includes receiving the multi-page data from a memory controller; programming first page data of the multi-page data into first memory cells connected to a word line adjacent to a selected word line; after programming the first page data, reading previous page data pre-stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value; and programming the previous page data read from the second memory cells and second page data of the multi-page data into the second memory cells based on a first fail bit number calculated by comparing a first bit of the previous page data read based on the first sensing value with a second bit of the previous page data read based on the second sensing value.

[0007] According to an embodiment of the present invention, a method for operating a nonvolatile memory device for programming multi-page data includes receiving first page data of the multi-page data from a memory controller; programming the first page data into memory cells connected to a selected word line; receiving second page data of the multi-page data from the memory controller after programming the first page data; reading the first page data stored in the memory cells based on a first sensing value and a second sensing value after receiving the second page data; and programming the first page data and the second page data read from the memory cells based on a first number of fail bits calculated by comparing a first bit of the first page data read based on the first sensing value and a second bit of the first page data read based on the second sensing value into the memory cells.

[0008] According to an embodiment of the present invention, a method for operating a nonvolatile memory device for programming multi-page data includes receiving the multi-page data from a memory controller; programming at least one page data of the multi-page data into first memory cells connected to a word line adjacent to a selected word line; after programming the at least one page data, reading at least one previous page data pre-stored in a second memory cell connected to the selected word line based on a first read voltage and a second read voltage; if the number of failed cells having threshold voltages of the first read voltage and the second read voltage among the second memory cells is less than a reference value, programming the at least one previous page data read from the second memory cell and the remaining page data of the multi-page data into the second memory cells; and if the number of failed cells is equal to or greater than the reference value, transmitting status information indicating a program failure for the multi-page data to the memory controller.

[0009] According to an embodiment of the present invention, the memory device includes a memory cell array including first memory cells connected to a first word line and second memory cells connected to a second word line adjacent to the first word line; a control logic circuit configured to program first page data of the multi-page data into the second memory cells in response to a program command for multi-page data from a memory controller; a page buffer unit configured to read previous page data pre-stored in the first memory cells based on a first sensing value and a second sensing value; and a fail bit calculator configured to calculate a first number of fail bits by comparing a first bit of the previous page data read based on the first sensing value with a second bit of the previous page data read based on the second sensing value, wherein the control logic circuit is further configured to program the second page data of the multi-page data and the previous page data read from the first memory cells according to the first number of fail bits into the first memory cells. [Effects of the Invention]

[0010] According to an embodiment of the present invention, a nonvolatile memory device may determine an error level of some page data programmed in a previous or current program cycle while performing a program operation related to multi-page data, and perform a program operation related to the multi-page data based on the determined error level, thereby improving the reliability of the programmed multi-page data. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram illustrating a memory system according to an embodiment of the present invention; [Figure 2] FIG. 2 is a block diagram illustrating an example of the memory controller of FIG. [Figure 3] 2 is a block diagram illustrating an example of the nonvolatile memory device of FIG. 1; [Figure 4]1 is a circuit diagram illustrating an example of a memory block according to an embodiment of the present invention; [Figure 5A] 1 is a diagram illustrating a programming method for multi-page data according to an embodiment of the present invention; [Figure 5B] 1 is a diagram illustrating a programming method for multi-page data according to an embodiment of the present invention; [Figure 6A] 1 is a diagram illustrating a programming method for multi-page data according to an embodiment of the present invention; [Figure 6B] 1 is a diagram illustrating a programming method for multi-page data according to an embodiment of the present invention; [Figure 7] 5B is a flowchart illustrating a program operation involving multi-page data in the nonvolatile memory device of FIG. 1 according to the program technique of FIGS. 5A and 5B. [Figure 8] 8 is a diagram illustrating an operation of reading previous page data in the multi-page program operation of FIG. 7; [Figure 9A] 10 is a diagram showing a method of reading previous page data based on two read voltages. [Figure 9B] 9B is a diagram illustrating an example of applying the read voltage of FIG. 9A to a selected word line. [Figure 9C] 10 is a diagram showing a method for reading previous page data based on two sensing points in time. [Figure 10] 4 is a diagram illustrating an example of a fail bit calculator of FIG. 3; [Figure 11] 11 is a diagram illustrating an example of the number of fail bits calculated by the operation of the fail bit calculator of FIG. 10; [Figure 12] 8 is a flowchart illustrating an exemplary operation of the nonvolatile memory device of FIG. 1 when the number of fail bits calculated in FIG. 7 is equal to or greater than a first reference value. [Figure 13] 13 illustrates an example of adjusting two sensing values ​​according to the operation of the nonvolatile memory device of FIG. [Figure 14]13 is a timing diagram illustrating an exemplary operation of the nonvolatile memory device according to the flowchart of FIG. 12. [Figure 15] 8 is a flowchart illustrating an exemplary operation of the nonvolatile memory device of FIG. 1 when the number of fail bits calculated in FIG. 7 is equal to or greater than a first reference value. [Figure 16] 16 is a flowchart illustrating an exemplary operation of the memory system of FIG. 1 according to the flowchart of FIG. 15. [Figure 17] 17 is a timing diagram illustrating an exemplary operation of the nonvolatile memory device according to the flowcharts of FIGS. 15 and 16. FIG. [Figure 18A] 1 is a diagram illustrating a programming method for multi-page data according to an embodiment of the present invention; [Figure 18B] 1 is a diagram illustrating a programming method for multi-page data according to an embodiment of the present invention; [Figure 19] 18C is a flowchart illustrating a program operation involving multi-page data in the nonvolatile memory device of FIG. 1 according to the program technique of FIGS. 18A and 18B. [Figure 20] 19 is a flowchart illustrating an exemplary operation of the nonvolatile memory device of FIG. 1 when the number of fail bits calculated in FIG. 19 is equal to or greater than a first reference value. [Figure 21] 21 is a timing diagram illustrating an exemplary operation of a nonvolatile memory device according to the flowchart of FIG. 20. [Figure 22] 19 is a flowchart illustrating an exemplary operation of the nonvolatile memory device of FIG. 1 when the number of fail bits calculated in FIG. 19 is equal to or greater than a first reference value. [Figure 23] 23 is a timing diagram illustrating an exemplary operation of a nonvolatile memory device according to the flowcharts of FIGS. 19 and 22. [Figure 24] 1 is an exemplary cross-sectional view of a memory device according to an embodiment of the present invention; [Figure 25] 1 is a block diagram illustrating an SSD system to which a memory device according to an embodiment of the present invention is applied; DETAILED DESCRIPTION OF THE INVENTION

[0012] The following description of the preferred embodiments of the present invention is given in such a clear and detailed manner that those skilled in the art can easily practice the present invention.

[0013] 1 is a block diagram illustrating an exemplary memory system according to an embodiment of the present invention. Referring to FIG. 1, the memory system 10 may include a memory controller 100 and a non-volatile memory device 200. The memory system 10 may be included in or attached to an electronic device such as a personal computer, a server, a data center, a smartphone, a tablet PC, an autonomous vehicle, a portable game console, or a wearable device. For example, the memory system 10 may be implemented as a storage device such as a solid state drive (SSD).

[0014] The memory controller 100 may control the overall operation of the nonvolatile memory device 200. Specifically, the memory controller 100 may control the nonvolatile memory device 200 by providing a control signal CTRL, a command CMD, and / or an address ADDR to the nonvolatile memory device 200. In an exemplary embodiment, the memory controller 100 may control the nonvolatile memory device 200 to store or output data DATA in response to a request from an external host.

[0015] The nonvolatile memory device 200 may operate under the control of the memory controller 100. In an exemplary embodiment, the nonvolatile memory device 200 may output data DATA stored under the control of the memory controller 100 or may store data DATA provided by the memory controller 100.

[0016] The nonvolatile memory device 200 may include a memory cell array 210 and a fail bit calculator 220. The memory cell array 210 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the present invention is not limited thereto, and the memory cells may be resistive random access memory (RRAM) cells, ferroelectric random access memory (FRAM) cells, phase change random access memory (PRAM) cells, thyristor random access memory (TRAM) cells, or magnetic random access memory (MRAM) cells. Hereinafter, embodiments of the present invention will be described focusing on an embodiment in which the memory cells are NAND flash memory cells.

[0017] In an exemplary embodiment, each of the memory cells included in the memory cell array 210 can store N-bit data (N is a positive integer). If N is 1, the memory cell may be referred to as a single level cell (SLC). If N is 2 or greater, the memory cell may be referred to as a multi-level cell (MLC). For example, if N is 3, the memory cell may be referred to as a triple level cell (TLC). For example, if N is 4, the memory cell may be referred to as a quadruple level cell (QLC).

[0018] In an exemplary embodiment, the nonvolatile memory device 200 can program multiple pages of data into memory cells connected to a single word line. In this case, each memory cell connected to a word line can store two or more bits. For example, in the TLC mode, the nonvolatile memory device 200 can program three pages of data into memory cells. In the QLC mode, the nonvolatile memory device 200 can program four pages of data into memory cells.

[0019] In an exemplary embodiment, the nonvolatile memory device 200 may perform a program operation related to multi-page data (hereinafter referred to as a multi-page program operation) through one program cycle. One program cycle for the multi-page program operation may include a program operation related to at least one page data of the multi-page data and a program operation related to the remaining page data. That is, the nonvolatile memory device 200 may perform the multi-page program operation through multiple program operations.

[0020] The nonvolatile memory device 200 may read data DATA from memory cells connected to one word line. In this case, the nonvolatile memory device 200 may read data DATA (i.e., page data) stored in memory cells in page units. In an exemplary embodiment, the nonvolatile memory device 200 may read page data stored in memory cells connected to the same word line based on two sensing values ​​(i.e., a first sensing value through a first sensing operation and a second sensing value through a second sensing operation). For example, the nonvolatile memory device 200 may read page data from a specific memory cell based on a first read voltage having a first level to sense a first bit, and read page data from the specific memory cell based on a second read voltage having a second level to sense a second bit. In an exemplary embodiment, the read operation based on the two sensing values ​​is performed together with the above-described multiple program operations in one program cycle for a multi-page program operation.

[0021] The fail bit calculator 220 may calculate the number of fail bits (hereinafter referred to as the number of fail bits) of page data programmed into memory cells based on page data read based on two sensing values. Here, a fail bit is also a bit of page data that is estimated to be different from a bit of original page data. That is, an error level of the programmed page data may be determined based on the calculated number of fail bits. For example, the fail bit calculator 220 may calculate the number of fail bits by comparing a first bit of page data read based on a first sensing value (hereinafter referred to as the first sensing data) with a second bit of page data read based on a second sensing value (hereinafter referred to as the second sensing data).

[0022] In an exemplary embodiment, the fail bit calculator 220 may calculate the number of fail bits of the programmed page data during the multi-page program operation. In this case, the calculated number of fail bits may be used to improve the reliability of the multi-page data being programmed. This may improve the reliability of the nonvolatile memory device 200.

[0023] An embodiment of a multi-page program operation using the calculated number of fail bits will now be described in detail.

[0024] Figure 2 is a block diagram illustrating an example of the memory controller of Figure 1. Referring to Figures 1 and 2, the memory controller 100 may include a processor 110, a RAM 120, an error correction code (ECC) circuit 130, a host interface circuit 140, and a memory interface circuit 150.

[0025] The processor 110 may control various operations of the memory controller 100. The RAM 120 may also be used as an operating memory, buffer memory, or cache memory for the memory controller 100. Various information, data, or instructions contained in the RAM 120 may be executed or managed by the processor 110.

[0026] In an exemplary embodiment, the RAM 120 may include a flash translation layer (FTL). The flash translation layer (FTL) may act as an interface between the host HOST and the nonvolatile memory device 200. For example, the flash translation layer (FTL) may perform address translation to convert logical addresses managed by the host HOST into physical addresses recognizable in the nonvolatile memory device 200. That is, the physical storage space of the nonvolatile memory device 200 may be managed by the flash translation layer (FTL). In an exemplary embodiment, the flash translation layer (FTL) may be stored in the RAM 120, and the flash translation layer (FTL) stored in the RAM 120 may be executed by the processor 110.

[0027] The ECC circuit 130 is configured to detect and correct errors in the data DATA output from the nonvolatile memory device 200. For example, the ECC circuit 130 may generate an error correction code for the data DATA to be stored in the nonvolatile memory device 200. The generated error correction code may be stored in the nonvolatile memory device 200 together with the data DATA. When the data DATA is output from the nonvolatile memory device 200, the ECC circuit 130 detects and corrects errors in the data DATA output from the nonvolatile memory device 200 using the error correction code for the data DATA.

[0028] The host interface circuit 140 supports communication between the memory controller 100 and a host HOST. In an exemplary embodiment, the host interface circuit 140 may support at least one of various interfaces such as USB (Universal Serial Bus), SCSI (Small Computer System Interface), PCI express, ATA, PATA (Parallel ATA), SATA (Serial ATA), SAS (Serial Attached SCSI), UFS (Universal Flash Storage), and NVMe (Nonvolatile Memory Express).

[0029] The memory interface circuit 150 supports communication between the memory controller 100 and the non-volatile memory device 200. In an exemplary embodiment, the memory interface circuit 150 can support a NAND interface.

[0030] 3 is a block diagram illustrating an example of the nonvolatile memory device of FIG. 1. Referring to FIG. 1 and FIG. 3, the nonvolatile memory device 200 may include a memory cell array 210, a fail bit calculator 220, a row decoder 230, a page buffer unit 240, an input / output circuit 250, and a control logic circuit 260.

[0031] The memory cell array 210 may include a plurality of memory blocks BLK1 to BLKz (where z is a positive integer). Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells. The memory cell array 210 may be connected to the page buffer unit 240 through bit lines BL and to the row decoder 230 through word lines WL, string selection lines SSL, and ground selection lines GSL.

[0032] In an exemplary embodiment, the memory cell array 210 may include a three-dimensional memory cell array, which may include multiple NAND strings. Each NAND string may include memory cells coupled to a word line stacked vertically on a substrate. U.S. Patent Publication Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and 2011 / 0233648 are incorporated herein by reference. In an exemplary embodiment, the memory cell array 210 may include a two-dimensional memory cell array, which may include multiple NAND strings arranged along rows and columns.

[0033] The row decoder 230 receives an address ADDR from the memory controller 100. The row decoder 230 decodes the address ADDR and controls the voltages of the word lines WL, the string select lines SSL, and the ground select lines GSL based on the decoded address ADDR. For example, during a program operation, the row decoder 230 applies a program voltage and a program verify voltage to the selected word line, and during a read operation, the row decoder 230 applies a read voltage to the selected word line.

[0034] The page buffer unit 240 includes a plurality of page buffers PB1 to PBn (n is an integer equal to or greater than 3), each of which may be connected to a memory cell via a plurality of bit lines BL. The page buffer unit 240 may select at least one of the bit lines BL under the control of the control logic circuit 260. The page buffer unit 240 operates as a write driver or a sense amplifier depending on the operation mode. For example, during a program operation, the page buffer unit 240 may apply a bit line voltage corresponding to data DATA to be programmed to a selected bit line. During a read operation, the page buffer unit 240 may sense a current or voltage of a selected bit line to read data DATA stored in a memory cell. The page buffer unit 240 is configured to temporarily store data DATA to be programmed or data DATA read from a memory cell.

[0035] In an exemplary embodiment, during a read operation, the page buffer unit 240 may read page data stored in memory cells connected to one word line based on two sensing values, thereby temporarily storing first sensing data corresponding to the first sensing value and second sensing data corresponding to the second sensing value.

[0036] The input / output circuit 250 provides data DATA received from the memory controller 100 to the page buffer unit 240 via the data line DL, or provides data DATA received from the page buffer unit 240 via the data line DL to the memory controller 100. In an exemplary embodiment, signals such as a command CMD, an address ADDR, or a control signal CTRL shown in FIG. 3 may be received through the input / output circuit 250.

[0037] The control logic circuit 260 may control various operations of the nonvolatile memory device 200. For example, the control logic circuit 260 may control each component of the nonvolatile memory device 200 so that the nonvolatile memory device 200 performs various operations (e.g., a program operation, a read operation, an erase operation, etc.) based on a command CMD or a control signal CTRL from the memory controller 100.

[0038] The fail bit calculator 220 may calculate the number of fail bits of the data DATA programmed in the memory cells based on the data DATA read from the memory cells through the page buffer unit 240. That is, the number of fail bits of the programmed page data may be calculated through the fail bit calculator 220. In an exemplary embodiment, the fail bit calculator 220 may calculate the number of fail bits by comparing the first sensing data and the second sensing data read through the page buffer unit 240. The calculated number of fail bits may be provided to the control logic circuit 260.

[0039] In an exemplary embodiment, the control logic circuit 260 may control a multi-page program operation based on the number of fail bits. For example, the control logic circuit 260 may determine an error level of previously programmed page data based on the number of fail bits of the previously programmed page data while performing the multi-page program operation. The control logic circuit 260 may control the multi-page program operation based on the determined error level.

[0040] 4 is a circuit diagram illustrating an example of a memory block according to an embodiment of the present invention. Referring to FIG. 4, a memory block BLK corresponds to one of the memory blocks BLK1 to BLKz in FIG. 3. The memory block BLK includes NAND strings NS11 to NS33, and each NAND string (e.g., NS11) may include a string select transistor SST, a plurality of memory cells MCs, and a ground select transistor GST connected in series.

[0041] NAND strings NS11, NS21, and NS31 are located between a first bit line BL1 and a common source line CSL, NAND strings NS12, NS22, and NS32 are located between a second bit line BL2 and the common source line CSL, and NAND strings NS13, NS23, and NS33 are located between a third bit line BL3 and the common source line CSL. String select transistors SST may be connected to corresponding string select lines SSL1 to SSL3. Memory cells MCs may be connected to corresponding word lines WL1 to WL8, respectively. Ground select transistors GST may be connected to corresponding ground select lines GSL1 to GSL3. String select transistors SST may be connected to corresponding bit lines BL1 to BL3, and ground select transistors GST may be connected to a common source line CSL. The numbers of NAND strings, word lines, bit lines, ground select lines, and string select lines may vary depending on the embodiment.

[0042] 5A through 23, multi-page program operations according to various embodiments of the present invention will be described. For convenience of explanation, it is assumed that the multi-page program operation according to the embodiments of the present invention involves programming three page data PD1 through PD3 (i.e., programming in TLC mode) based on an address ADDR indicating a first word line WL1 (i.e., the first word line WL1 is the selected word line). However, the present invention is not limited thereto, and the present invention may also be applied to a multi-page program operation for four or more page data.

[0043] 5A and 5B are diagrams illustrating a programming technique for multi-page data according to an embodiment of the present invention. The operations of FIGS. 5A and 5B may be performed in one program cycle for a multi-page program operation. For convenience of explanation, it is assumed that the memory cells connected to the first word line WL1 have stored one previous page of data PDp in the previous program cycle. That is, one previous page of data PDp among three pages of data programmed in the previous program cycle may be previously stored in the memory cells connected to the first word line WL1. The horizontal axis of the scatter diagram shown in FIG. 5B represents the threshold voltage of the memory cells, and the vertical axis represents the number of memory cells.

[0044] 3, 5A, and 5B, the nonvolatile memory device 200 may receive first through third page data PD1 through PD3. In an exemplary embodiment, the received first through third page data PD1 through PD3 may be stored in a page buffer unit 240 of the nonvolatile memory device 200.

[0045] The nonvolatile memory device 200 may program one page of data (e.g., first page data PD1) among the first through third page data PD1-PD3 to memory cells coupled to a second word line WL2, which is an unselected word line (hereinafter referred to as an unselected program operation PGM_unsel). For example, the second word line WL2 may also be a word line adjacent to the first word line WL1. As shown in FIG. 5B, the nonvolatile memory device 200 may perform the unselected program operation PGM_unsel to place the memory cells coupled to the second word line WL2 in one of an erased state E and a programmed state P01. In the unselected program operation PGM_unsel, an unselected program verify voltage VF01 may be used to verify the programmed state P01. When the unselected program operation PGM_unsel for the second word line WL2 is completed, the memory cells connected to the second word line WL2 are in a state of storing the first page data PD1, and the memory cells connected to the first word line WL1 are in a state of storing the previous page data PDp.

[0046] After the unselect program operation PGM_unsel, the nonvolatile memory device 200 may read previous page data PDp from memory cells connected to the first word line WL1 (hereinafter referred to as a previous page data read operation RD_pre). As shown in FIG. 5B, each memory cell storing the previous page data PDp has one of an erased state E and a programmed state P01. The nonvolatile memory device 200 may read the previous page data PDp by performing the previous page data read operation RD_pre using a read voltage VRD01.

[0047] After the previous page data read operation RD_pre, the nonvolatile memory device 200 may perform a program operation (hereinafter referred to as a selective program operation PGM_sel) on memory cells connected to the first word line WL1 based on the second page data PD2, the third page data PD3, and the previous page data PDp. As shown in FIG. 5B, by performing the selective program operation PGM_sel, memory cells connected to the first word line WL1 that have the erased state E may have the erased state E and one of the first through third program states P1 through P3, and memory cells that have the program state P01 may have one of the fourth through seventh program states P4 through P7. In the selective program operation PMG_sel, first through seventh program verify voltages VF1 through VF7 may be used to verify the first through seventh program states P1 through P7.

[0048] When the selective program operation PGM_sel is completed, the memory cells connected to the first word line WL1 can store the second page data PD2, the third page data PD3, and the previous page data PDp, and the memory cells connected to the second word line WL2 can store the first page data PD1.

[0049] 6A and 6B are diagrams illustrating a programming technique for multi-page data according to an embodiment of the present invention. The operations of FIGS. 6A and 6B may be performed in one program cycle for a multi-page program operation. For convenience of explanation, it is assumed that the memory cells connected to the first word line WL1 have stored two previous page data PDp1 and PDp2 in a previous program cycle. That is, of the three page data programmed in the previous program cycle, two page data PDp1 and PDp2 may be pre-stored in the memory cells connected to the first word line WL1. The horizontal axis of the scatter diagram shown in FIG. 6B represents the threshold voltage of the memory cells, and the vertical axis represents the number of memory cells.

[0050] 3, 6A, and 6B, the nonvolatile memory device 200 may receive first through third page data PD1 through PD3. The nonvolatile memory device 200 may program two of the first through third page data PD1 through PD3 (e.g., first and second page data PD1 and PD2) into memory cells connected to a second word line WL2, which is an unselected word line. As shown in FIG. 6B, the nonvolatile memory device 200 may perform an unselect program operation PGM_unsel to place the memory cells connected to the second word line WL2 in one of the erase state E and first through third unselected program states P01 through P03. During the unselect program operation PGM_unsel, first through third unselected program verify voltages VF01 through VF03 may be used to verify the unselected program states P01 through P03. When the unselected program operation PGM_unsel for the second word line WL2 is completed, the memory cells connected to the second word line WL2 store the first and second page data PD1 and PD2, and the memory cells connected to the first word line WL1 store the first and second previous page data PDp1 and PDp2.

[0051] After the unselected program operation PGM_unsel, the nonvolatile memory device 200 can read the first and second previous page data PDp1 and PDp2 from the memory cells connected to the first word line WL1. As shown in FIG. 6B, each of the memory cells storing the first and second previous page data PDp1 and PDp2 has an erased state E or one of the first through third unselected program states P01 through P03. The nonvolatile memory device 200 can read the first and second previous page data PDp1 and PDp2 by performing a previous page data read operation RD_pre using the first through third read voltages VRD01 through VRD03.

[0052] After the previous page data read operation RD_pre, the nonvolatile memory device 200 may perform a program operation on memory cells connected to the first word line WL1 based on the third page data PD3, the first previous page data PDp1, and the second previous page data PDp2. As shown in FIG. 6B, by performing the selective program operation PGM_sel, memory cells connected to the first word line WL1 that have the erased state E may have one of the erased state E and the first program state P1, and memory cells that have the first program state P01 may have one of the second and third program states P2 and P3. Similarly, memory cells that have the second unselected program state P02 may have one of the fourth and fifth program states P4 and P5, and memory cells that have the third unselected program state P03 may have one of the sixth and seventh program states P6 and P7.

[0053] When the selective program operation PGM_sel is completed, the memory cells connected to the first word line WL1 can store the third page data PD3, the first previous page data PDp1, and the second previous page data PDp2, and the memory cells connected to the second word line WL2 can store the first page data PD1 and the second page data PD2.

[0054] In an exemplary embodiment, the first word line WL1, which is a selected word line, is a word line located closer to the substrate, and the second word line WL2, which is an unselected word line, is also a word line located farther from the substrate. However, the present invention is not limited thereto. For example, the first word line WL1 is a word line located farther from the substrate, and the second word line WL2 is also a word line located closer to the substrate.

[0055] As described above, the multi-page programming technique according to embodiments of the present invention may include an operation of programming at least one page of data among the multiple pages of data into memory cells connected to unselected word lines adjacent to a selected word line (i.e., an unselected program operation PGM_unsel) and an operation of programming the remaining page of data into memory cells connected to the selected word line (i.e., a selective program operation PGM_sel). For example, first page of data may be programmed into memory cells connected to unselected word lines adjacent to a selected word line, and then second and third page of data may be programmed into memory cells connected to the selected word line. In this case, at least one previous page of data previously stored in memory cells connected to the selected word line may be read, and a selective program operation PGM_sel may be performed based on the at least one previous page of data read and the remaining page of data. According to this programming technique, the reliability of the page data programmed through the selective program operation PGM_sel may be reduced due to an error level generated during a program operation related to the previous page data in a previous program cycle.

[0056] Hereinafter, a multi-page program operation for improving the reliability of the program technique described with reference to Figures 5A to 6B will be described in detail with reference to Figures 7 to 17. For convenience of explanation, the multi-page program operation will be described mainly with reference to an embodiment in which an unselect program operation PGM_unsel is performed on one page of data, as shown in Figures 5A and 5B.

[0057] 7 is a flowchart showing a program operation for multi-page data of the nonvolatile memory device of FIG. 1 according to the program techniques of FIG. 5A and FIG. 5B. Referring to FIG. 1, FIG. 3, and FIG. 7, in step S201, the nonvolatile memory device 200 may receive multi-page data from the memory controller 100. For example, the nonvolatile memory device 200 may further receive an address ADDR corresponding to a selected word line and a program command CMD for the multi-page data from the memory controller 100 along with the multi-page data.

[0058] In operation S202, the nonvolatile memory device 200 may program one page of data among the multiple pages of data to memory cells connected to unselected word lines. For example, the first page of data PD1 may be programmed to the second word line WL2.

[0059] In operation S203, the nonvolatile memory device 200 may read previous page data previously stored in memory cells connected to a selected word line based on the first and second sensing values. For example, the nonvolatile memory device 200 may apply a first read voltage to the selected word line to read the previous page data, and then apply a second read voltage to the selected word line to read the previous page data. As another example, the nonvolatile memory device 200 may read the previous page data by applying a specific read voltage (e.g., a read voltage having a predetermined level) to the selected word line and detecting a voltage or current at a sensing node of the page buffer unit 240 at a first sensing time point and a second sensing time point. Specifically, the nonvolatile memory device 200 may read the previous page data by applying a specific read voltage to the selected word line and developing the sensing node of the page buffer unit 240 during a first development time and a second development time. Accordingly, the page buffer unit 240 can store the first sensing data read based on the first sensing value and the second sensing data read based on the second sensing value.

[0060] In operation S204, the nonvolatile memory device 200 may calculate the number of fail bits based on a first bit of the previous page data (i.e., the first sensing data) read based on the first sensing value and a second bit of the previous page data (i.e., the second sensing data) read based on the second sensing value. For example, the fail bit calculator 220 may compare the first bit with the second bit to determine the number of different bits. The fail bit calculator 220 may calculate the determined number of bits as the number of fail bits.

[0061] In step S205, the nonvolatile memory device 200 may determine whether the number of fail bits is less than a first reference value. Here, the first reference value is a reference value for determining whether to continue performing the multi-page program operation. For example, step S205 may also be performed by the control logic circuit 260.

[0062] If the number of fail bits is less than the first reference value (i.e., if it is determined that the error level of the programmed previous page data is low), in operation S206, the nonvolatile memory device 200 may program the remaining page data of the read previous page data and the multi-page data to memory cells connected to the selected word line. For example, the read previous page data may be data read based on the first sensing value or the second sensing value. As another example, the read previous page data may be data read based on a preset read voltage.

[0063] If the number of fail bits is equal to or greater than the first reference value (i.e., if it is determined that the error level of the programmed previous page data is not low), the nonvolatile memory device 200 may perform step S211 or step S231. Step S211 will be described below with reference to FIG. 12, and step S231 will be described below with reference to FIG. 15. For example, the nonvolatile memory device 200 may treat the multi-page program operation as a failure, correct errors in the read previous page data, or re-read the previous page data based on other sensing values.

[0064] 8 is a diagram illustrating an operation of reading previous page data in the multi-page program operation of FIG 7. Referring to FIG 3 and FIG 8, NAND strings NS1 to NSn may be connected to page buffers PB1 to PBn via bit lines BL1 to BLn, respectively. The NAND strings NS1 to NSn may be included in the memory cell array 210, and the page buffers PB1 to PBn may be included in the page buffer unit 240.

[0065] The NAND strings NS1 to NSn may include ground select transistors GST1 to GSTn, memory cells MC11 to MCn8, and string select transistors SST1 to SSTn. The ground select transistors GST1 to GSTn may be connected to a common source line CSL and a ground select line GSL, and the memory cells MC11 to MCn8 may be connected to word lines WL1 to WL8. The string select transistors SST1 to SSTn may be connected to a string select line SSL and bit lines BL1 to BLn.

[0066] 8, the first word line WL1 is a selected word line and the second word line WL2 is an unselected word line. In this case, the memory cells MC11 to MCn1 connected to the first word line WL1 are in a state where the previous page data has been programmed, and the memory cells MC12 to MCn2 connected to the second word line WL2 are in a state where one page data of the multi-page data has been programmed according to step S202 of FIG.

[0067] 7, when previous page data is read from the memory cells MC11 to MCn1 connected to the first word line WL1 based on the first and second sensing values, first sensing data PDS1 and second sensing data PDS2 may be stored in the page buffers PB1 to PBn. The first sensing data PDS1 may be stored in the first latches L1s of the page buffers PB1 to PBn, and the second sensing data PDS2 may be stored in the second latches L2s of the page buffers PB1 to PBn. For example, the first sensing data PDS1 and the second sensing data PDS2 may each be n-bit data. In this case, bits PDS1[1:n] of the first sensing data PDS1 may be stored in the first latches L1s of the page buffers PB1 to PBn, respectively, and bits PDS2[1:n] of the second sensing data PDS2 may be stored in the second latches L2s of the page buffers PB1 to PBn, respectively. For example, a bit PDS1[1] of the first sensing data PDS1 output from the memory cell MC11 based on the first sensing value may be stored in the first latch L1 of the first page buffer PB1, and a bit PDS2[1] of the second sensing data PDS2 output from the memory cell MC11 based on the second sensing value may be stored in the second latch L2 of the first page buffer PB1. Similarly, a bit PDS1[n] of the first sensing data PDS1 output from the memory cell MCn1 based on the first sensing value may be stored in the first latch L1 of the n-th page buffer PBn, and a bit PDS2[n] of the second sensing data PDS2 output from the memory cell MCn1 based on the second sensing value may be stored in the second latch L2 of the n-th page buffer PBn.

[0068] FIG. 9A illustrates a method for reading previous page data based on two read voltages. The horizontal axis of the scatter diagram in FIG. 9A represents the threshold voltage of a memory cell, and the vertical axis represents the number of memory cells. Referring to FIG. 9A, when previous page data is programmed into memory cells, the distribution of memory cells in a normal program state and a program-fail state are illustrated. The normal program state indicates a state in which the error level of the programmed previous page data is relatively low, and the program-fail state indicates a state in which the error level of the programmed previous page data is relatively high. As described with reference to FIG. 5B, each memory cell storing previous page data can have one of an erased state E and a program state P01.

[0069] In both the program-successful and program-failed states, a first read voltage VS1 may be applied to a selected word line (i.e., the first word line WL1) of FIG. 8 to read previous page data based on the first sensing value, and a second read voltage VS2 may be applied to the selected word line to read previous page data based on the second sensing value. The first read voltage VS1 is lower than the reference read voltage VRD, and the second read voltage VS2 is higher than the reference read voltage VRD. The reference read voltage VRD is also a voltage for reading previous page data in a general read operation performed based on one sensing value. For example, the reference read voltage VRD may correspond to the read voltage VRD01 of FIG. 5B and have a preset level. However, the present invention is not limited thereto, and the level of the first read voltage VS1 or the second read voltage VS2 may be the same as the level of the reference read voltage VRD.

[0070] In the case of a normal program state, the threshold voltages of memory cells having the erased state E and memory cells having the program state P01 are different from each other. For example, as shown in FIG. 9A, the highest threshold voltage of memory cells having the erased state E is lower than the first read voltage VS1, and the lowest threshold voltage of memory cells having the program state P01 is higher than the second read voltage VS2. In this case, there are no memory cells having threshold voltages between the first read voltage VS1 and the second read voltage VS2. That is, the bits of the previous page data read based on the first read voltage VS1 and the bits of the previous page data read based on the second read voltage VS2 are identical to each other. In this way, a memory cell having the erased state E can be determined as a memory cell in which a first bit (e.g., “1”) is stored by both the first read voltage VS1 and the second read voltage VS2 (hereinafter referred to as an erased cell), and a memory cell having the programmed state P01 can be determined as a memory cell in which a second bit (e.g., “0”) is stored by both the first read voltage VS1 and the second read voltage VS2 (hereinafter referred to as a programmed cell). In this case, the number of fail bits can be calculated as 0.

[0071] In the case of a program failure state, some of the threshold voltages of memory cells having the erased state E and some of the threshold voltages of memory cells having the programmed state P01 may be the same. That is, some of the threshold voltages of memory cells having the erased state E may overlap some of the threshold voltages of memory cells having the programmed state P01. For example, as shown in FIG. 9A, the highest threshold voltage of memory cells having the erased state E is greater than the first read voltage VS1, and the lowest threshold voltage of memory cells having the programmed state P01 is less than the second read voltage VS2. In this case, memory cells having threshold voltages between the first read voltage VS1 and the second read voltage VS2 may exist. That is, some of the bits of the previous page data read based on the first read voltage VS1 may differ from some of the bits of the previous page data read based on the second read voltage VS2. For example, among memory cells having an erased state E, a bit detected based on the first read voltage VS1 is different from a bit detected based on the second read voltage VS2 in a memory cell having a threshold voltage higher than the first read voltage VS1. Furthermore, among memory cells having a programmed state P01, a bit detected based on the first read voltage VS1 is different from a bit detected based on the second read voltage VS2. Thus, among memory cells having an erased state E, a memory cell having a threshold voltage lower than the first read voltage VS1 can be identified as an erased cell, and a memory cell having a threshold voltage higher than the first read voltage VS1 can be identified as a memory cell in which different bits are stored based on the first read voltage VS1 and the second read voltage VS2 (hereinafter referred to as a failed cell). Furthermore, among memory cells having a programmed state P01, a memory cell having a threshold voltage higher than the second read voltage VS2 can be identified as a programmed cell, and a memory cell having a threshold voltage lower than the second read voltage VS2 can be identified as a failed cell. That is, the failed cells are also memory cells that have threshold voltages of the first read voltage VS1 and the second read voltage VS2.In this case, the calculated number of failed bits is also the same as the number of failed cells.

[0072] 9B is a diagram illustrating an example of applying the read voltages of FIG. 9A to a selected word line. Referring to FIG. 9B, as described with reference to FIG. 9A, read voltages VS1 and VS2 may be applied to a first word line WL1 (i.e., a selected word line) based on two sensing values. For example, a first read voltage VS1 and a second read voltage VS2 may be sequentially applied to the first word line WL1 to perform first and second sensing. The number of fail bits may be calculated based on the first and second sensing.

[0073] 9C is a diagram showing a method for reading previous page data based on two sensing points. The horizontal axis of the graph in FIG. 9C represents time, and the vertical axis represents the voltage of the sensing node of the page buffer unit 240 of FIG. 3 for detecting bits stored in the memory cell. Referring to FIG. 9C, the voltage change of the sensing node during the precharge period and the development period for reading previous page data programmed in the memory cell is shown. The voltage change of the sensing node during the development period also varies depending on the threshold voltage of the memory cell.

[0074] To read previous page data in a program-successful state and a program-failed state, the reference read voltage VRD of FIG. 9A may be applied to the selected word line (i.e., the first word line WL1) of FIG. 8. In this case, the sensing node voltage may be compared to the reference voltage Vr at a first sensing time tS1 to read previous page data based on a first sensing value, and the sensing node voltage may be compared to the reference voltage Vr at a second sensing time tS2 to read previous page data based on a second sensing value. If the sensing node voltage is greater than the reference voltage Vr, the memory cell is identified as a programmed cell, and if the sensing node voltage is less than the reference voltage Vr, the memory cell is identified as an erased cell. That is, the first sensing time tS1 may correspond to the first read voltage VS1 of FIG. 9A, and the second sensing time tS2 may correspond to the second read voltage VS2.

[0075] The first sensing time tS1 is earlier than the reference sensing time tRD, and the second sensing time tS2 is later than the reference sensing time tRD. That is, the first sensing time tS1 is earlier than the reference sensing time tRD, and the second sensing time tS2 is later than the reference sensing time tRD. The reference sensing time tRD is a sensing time for reading previous page data in a general read operation performed based on one sensing value, and is also a preset value. However, the present invention is not limited thereto, and the first sensing time tS1 or the second sensing time tS2 may be the same as the reference sensing time tRD.

[0076] In a normal programming state, each memory cell may be identified as either a programmed cell or an erased cell. For example, as shown in FIG. 9C, if the sensing node voltage is greater than the reference voltage Vr at the first sensing time tS1 and the second sensing time tS2, the memory cell may be identified as a programmed cell. If the sensing node voltage is less than the reference voltage Vr at the first sensing time tS1 and the second sensing time tS2, the memory cell may be identified as an erased cell. In this case, the number of fail bits may be calculated as 0.

[0077] In the case of a program failure, each memory cell may be classified as one of a programmed cell, an erased cell, and a failed cell. For example, as shown in FIG. 9C, if the sensing node voltage is greater than the reference voltage Vr at the first sensing time tS1 and the second sensing time tS2, the memory cell may be classified as a programmed cell. If the sensing node voltage is less than the reference voltage Vr at the first sensing time tS1 and the second sensing time tS2, the memory cell may be classified as an erased cell. If the sensing node voltage is greater than the reference voltage Vr at the first sensing time tS1 and less than the reference voltage Vr at the second sensing time tS2, the memory cell may be classified as a failed cell. In this case, the calculated number of failed bits is also the number of failed cells.

[0078] 10 is a diagram illustrating an example of the fail bit calculator of FIG. 3. Referring to FIG. 10, the fail bit calculator 220 may include first through n-th comparators 221-22n and a counter 270. The comparators 221-22n may receive the first sensing data PDS1 and the second sensing data PDS2 stored in the first latch L1s and the second latch L2s of the page buffers PB1-PBn of FIG. 8. For example, the first comparator 221 may receive the first bit PDS1[1] of the first sensing data and the first bit PDS2[1] of the second sensing data, and the second comparator 222 may receive the second bit PDS1[2] of the first sensing data and the second bit PDS2[2] of the second sensing data. Similarly, the n-th comparator 22n may receive the n-th bit PDS1[n] of the first sensing data and the n-th bit PDS2[n] of the second sensing data.

[0079] Each of the comparators 221 to 22n can compare two received bits and output a comparison result. For example, the first comparator 221 can compare the first bit PDS1[1] of the first sensing data with the first bit PDS2[1] of the second sensing data and output a first comparison result CR1. The second comparator 222 can compare the second bit PDS1[2] of the first sensing data with the second bit PDS2[2] of the second sensing data and output a second comparison result CR2. Similarly, the nth comparator 22n can compare the nth bit PDS1[n] of the first sensing data with the nth bit PDS2[n] of the second sensing data and output an nth comparison result CRn. Each of the comparators 221 to 22n can output a first value (e.g., "0") as a comparison result if the two bits are identical, and can output a second value (e.g., "1") as a comparison result if the two bits are different from each other. For example, each of the comparators 221 to 22n can be embodied by an XOR gate, but the present invention is not limited to this.

[0080] The counter 270 may calculate the number of fail bits FBN based on the comparison results CR1 to CRn. In an exemplary embodiment, the counter 270 may calculate the number of fail bits FBN by counting the number of specific values ​​(e.g., “1”) indicating that two bits are different from each other among the comparison results CR1 to CRn. The calculated number of fail bits FBN may be provided to the control logic circuit 260. The control logic circuit 260 may perform a multi-page program operation based on the calculated number of fail bits FBN.

[0081] 11 is a diagram illustrating an example of the number of fail bits calculated by the operation of the fail bit calculator of FIG. 10. For convenience of explanation, it is assumed that there are seven memory cells MC11 to MCn1 (i.e., n is 7) connected to the selected word line (i.e., the first word line WL1) of FIG. 8. Referring to FIGS. 10 and 11, the fail bit calculator 220 may receive first sensing data PDS1 read from the memory cells MC11 to MC71 based on the first sensing value and second sensing data PDS2 read from the memory cells MC11 to MC71 based on the second sensing value. For example, as shown in FIG. 11, the first sensing data PDS1 is "0101111" and the second sensing data PDS2 is "0010111." In this case, the fail bit calculator 220 can compare the first sensing data PDS1 and the second sensing data PDS2 to obtain a comparison result CR of "0111000." The fail bit calculator 220 can count the number of "1"s in the comparison result CR, which indicate that two bits read from each of the memory cells MC11 to MC71 are different from each other, and calculate the number of fail bits FBN. As a result, the number of fail bits FBN can be calculated as "3."

[0082] 12 is a flowchart illustrating an exemplary operation of the nonvolatile memory device of FIG. 1 when the number of fail bits calculated in FIG. 7 is equal to or greater than a first reference value. Referring to FIGS. 1 and 12, when the calculated number of fail bits is equal to or greater than the first reference value, in operation S211, the nonvolatile memory device 200 may re-read previous page data previously stored in memory cells connected to the selected word line based on the first and second corrected sensing values. Here, the first and second corrected sensing values ​​may be determined through an algorithm within the nonvolatile memory device 200 so that the error level of the previously programmed page data can be more accurately determined. For example, the first corrected sensing value may be different from the first sensing value (e.g., the first sensing value used in operation S204), and the second corrected sensing value may be different from the second sensing value (e.g., the second sensing value used in operation S204).

[0083] In operation S212, the nonvolatile memory device 200 may calculate the number of fail bits based on the first bit of the previous page data read based on the first corrected sensing value and the second bit of the previous page data read based on the second corrected sensing value. As described with reference to FIGS. 8 to 11, the nonvolatile memory device 200 may calculate the number of fail bits corresponding to the previous page data that has been re-read.

[0084] In operation S213, the nonvolatile memory device 200 may determine whether the calculated number of fail bits is less than a first reference value. For example, the first reference value may be the same as the first reference value in operation S205, but the present invention is not limited thereto. If the calculated number of fail bits is less than the first reference value (i.e., if the error level of the reread previous page data is determined to be relatively low), in operation S214, the nonvolatile memory device 200 may program the reread previous page data and the remaining page data of the multi-page data to memory cells connected to the selected word line.

[0085] If the calculated number of fail bits is equal to or greater than the first reference value (i.e., if the error level of the re-read previous page data is determined to be relatively high), in operation S215, the nonvolatile memory device 200 may transmit program failure information to the memory controller 100. For example, the nonvolatile memory device 200 may transmit status information indicating a program failure to the memory controller 100 in response to a status information request from the memory controller 100.

[0086] In operation S216, the nonvolatile memory device 200 may update the read or program setting values. For example, the nonvolatile memory device 200 may extract characteristic information of the memory blocks or memory dies while performing operations S211 through S215 on various word lines (e.g., the first through eighth word lines WL1 through WL8 in FIG. 8) and various memory blocks. The nonvolatile memory device 200 may update the read setting values ​​(e.g., read voltage, development time, or sensing time point) or program setting values ​​(e.g., program voltage or program verify voltage) based on the extracted characteristic information. For example, the nonvolatile memory device 200 may decrease or increase the read voltage, development time, or sensing time point based on the extracted characteristic information of the memory blocks or memory dies. The nonvolatile memory device 200 may decrease or increase the program voltage or program verify voltage based on the extracted characteristic information of the memory blocks or memory dies. 5B, the unselected program verify voltage VF01 or the program voltage in the unselected program operation PGM_unsel may be changed, or the read voltage VRD01 in the previous page data read operation RD_pre may be changed. In an exemplary embodiment, step S216 may be omitted.

[0087] As described above, if it is determined that the error level of the programmed previous page data is relatively high, the nonvolatile memory device 200 may adjust the two sensing values ​​and re-read the previous page data. That is, the nonvolatile memory device 200 may change the read conditions and re-read the previous page data to re-acquire the previous page data and determine the error level of the acquired previous page data.

[0088] 13 illustrates an example of adjusting two sensing values ​​according to the operation of the nonvolatile memory device of FIG. 12. That is, an example of obtaining a first corrected sensing value and a second corrected sensing value will be described with reference to FIG. 13. Referring to FIG. 13, a scatter plot of memory cells previously programmed with page data PDp (i.e., memory cells connected to a selected word line) is illustrated. The horizontal axis of the scatter plot represents threshold voltage, and the vertical axis represents the number of memory cells. Each memory cell previously programmed with page data PDp may have one of an erased state E and a programmed state P01.

[0089] To adjust the two sensing values, the nonvolatile memory device 200 may obtain the corrected reference read voltage VRD' by adjusting the reference read voltage VRD used in a general read operation (i.e., a read operation performed based on one sensing value) as described with reference to FIG. 9A. For example, the nonvolatile memory device 200 may obtain the corrected reference read voltage VRD' by performing a valley search operation to search for a valley in the threshold voltage distribution formed by memory cells. As another example, the nonvolatile memory device 200 may obtain the corrected reference read voltage VRD' by adjusting the reference read voltage VRD according to the program state of the memory cells connected to the unselected word lines. For example, if the memory cells connected to the unselected word lines have a program state, the nonvolatile memory device 200 may increase the reference read voltage VRD to obtain the corrected reference read voltage VRD', and if the memory cells connected to the unselected word lines have an erased state, the nonvolatile memory device 200 may decrease the reference read voltage VRD to obtain the corrected reference read voltage VRD'.

[0090] As shown in FIG. 13, the first and second sensing values ​​may be adjusted by adjusting the reference read voltage VRD. For example, as described with reference to FIG. 9A, when a read operation is performed based on two read voltages, the first and second read voltages VS1 and VS2 corresponding to the reference read voltage VRD may be adjusted to the first and second corrected read voltages VS1' and VS2'. For example, when the corrected reference read voltage VRD' is smaller than the reference read voltage VRD, the first and second corrected read voltages VS1' and VS2' are smaller than the first and second read voltages VS1 and VS2. As another example, when the corrected reference read voltage VRD' is larger than the reference read voltage VRD, the first and second corrected read voltages VS1' and VS2' are larger than the first and second read voltages VS1 and VS2, respectively.

[0091] For example, as described with reference to FIG. 9C, when a read operation is performed based on two sensing points, the reference read voltage VRD may be adjusted to adjust the two sensing values. For example, when a corrected reference read voltage VRD' is applied to a selected word line, the first sensing point tS1 may correspond to the first corrected read voltage VS1', and the second sensing point tS2 may correspond to the second corrected read voltage VS2'. However, the present invention is not limited thereto, and the reference read voltage VRD may be kept the same, and the first sensing point tS1 or the second sensing point tS2 may be adjusted.

[0092] As described above, when the reference read voltage VRD is adjusted to the corrected reference read voltage VRD', the number of fail bits for the previous page data PDp read based on the two corrected sensing values ​​may be reduced. As a result, the nonvolatile memory device 200 may perform a multi-page program operation based on the previous page data having a reduced error level. As a result, the reliability of the multi-page program operation may be improved.

[0093] FIG. 14 is a timing diagram illustrating an exemplary operation of the nonvolatile memory device according to the flowchart of FIG. 12. Referring to FIGS. 1 and 14, in operation S221, the nonvolatile memory device 200 may receive multi-page data from the memory controller 100. For example, the nonvolatile memory device 200 may receive the multi-page data via a data input command. In operation S222, the nonvolatile memory device 200 may receive a program command from the memory controller 100. The nonvolatile memory device 200 may perform a program operation on the received multi-page data in response to the program command. For example, the nonvolatile memory device 200 may receive an address to which the multi-page data is to be programmed along with a data input command or a program command from the memory controller 100. However, the present invention is not limited to performing operation S222 after operation S221. For example, if a channel for transmitting commands and addresses and a channel for transmitting and receiving data are separated, operations S221 and S222 may be performed in parallel. Alternatively, the program command may be received in step S222, and then the multi-page data may be received in step S221.

[0094] While performing steps S221 and S222, the nonvolatile memory device 200 may transmit a ready / busy signal nR / B indicating a ready state (e.g., a high level) to the memory controller 100. In an exemplary embodiment, the nonvolatile memory device 200 may receive a program setup command before receiving multi-page data and may receive a program confirm command after receiving multi-page data.

[0095] At operation S223, the nonvolatile memory device 200 may perform an unselect program operation PGM_unsel. For example, the nonvolatile memory device 200 may program one page of data among multiple pages of data into memory cells connected to unselected word lines. At operation S224, the nonvolatile memory device 200 may perform a first previous page data read operation RD1_pre. For example, the nonvolatile memory device 200 may read previous page data previously stored in memory cells connected to the selected word line based on the first and second sensing values. At operation S225, the nonvolatile memory device 200 may perform a second previous page data read operation RD2_pre. For example, the nonvolatile memory device 200 may re-read the previous page data based on the first and second corrected sensing values. In this case, as described with reference to FIG. 12, operation S225 is performed when the number of fail bits for the previous page data is equal to or greater than a first reference value. In operation S226, the nonvolatile memory device 200 may perform a selected program operation PGM_sel. For example, the nonvolatile memory device 200 may program the remaining page data of the re-read previous page data and the multi-page data to memory cells connected to the selected word line. While performing operations S223 and S226, the nonvolatile memory device 200 may transmit a ready / busy signal nR / B indicating a busy state (e.g., a low level) to the memory controller 100. That is, the ready / busy signal nR / B may maintain a busy state during the multi-page program operation according to an embodiment of the present invention (i.e., during one program cycle).

[0096] 15 is a flowchart illustrating an exemplary operation of the nonvolatile memory device of FIG. 1 when the number of fail bits calculated in FIG. 7 is equal to or greater than a first reference value. Referring to FIGS. 1 and 15, when the calculated number of fail bits is equal to or greater than the first reference value, the nonvolatile memory device 200 determines whether the number of fail bits is less than a second reference value in operation S231. Here, the second reference value is a reference value for determining whether to correct errors in the previous page data and is greater than the first reference value. That is, in operation S231, the nonvolatile memory device 200 can determine whether errors in the previous page data are at a level at which they can be corrected.

[0097] If the number of fail bits is less than the second reference value (i.e., if the errors in the previous page data are determined to be at a correctable level), in operation S232, the nonvolatile memory device 200 may transmit the read previous page data to the memory controller 100. For example, the read previous page data may be data read based on the first sensing value or the second sensing value as described with reference to Figures 9A and 9C. However, the present invention is not limited thereto, and the read previous page data may also be data read based on the reference read voltage VRD and the reference sensing time tRD.

[0098] In operation S233, the nonvolatile memory device 200 may receive previously corrected page data from the memory controller 100. The previously corrected page data may be generated by correcting errors in the previous page data transmitted to the memory controller 100. For example, errors in the previous page data transmitted to the memory controller 100 may be corrected by the ECC circuit 130 of FIG.

[0099] In operation S234, the nonvolatile memory device 200 may program the remaining page data of the previously corrected page data and the multi-page data into memory cells connected to the selected word line. This may complete the multi-page program operation. In another embodiment, the nonvolatile memory device 200 may program the remaining page data of the previously corrected page data and the multi-page data into other memory cells instead of programming the remaining page data into memory cells connected to the selected word line. In this case, the other memory cells may be included in a memory block different from the memory block into which the previous page data was programmed.

[0100] If the number of fail bits FBN is equal to or greater than the second reference value (i.e., if the error in the previous page data is determined to be at an uncorrectable level), in operation S235, the nonvolatile memory device 200 may transmit program failure information to the memory controller 100. For example, the nonvolatile memory device 200 may transmit status information indicating a program failure to the memory controller 100 in response to a status information request from the memory controller 100.

[0101] As described above, if the number of fail bits FBN determines that the error in the read previous page data is correctable, the nonvolatile memory device 200 transmits the previous page data to the memory controller 100, and the error in the previous page data is corrected by the memory controller 100. As a result, a multi-page program operation is performed based on the error-corrected previous page data (i.e., the previously corrected page data), which may improve the reliability of the multi-page data programmed by the multi-page program operation. However, the present invention is not limited to this, and errors in the read previous page data may be corrected within the nonvolatile memory device 200.

[0102] In an exemplary embodiment, steps S231 through S235 are performed when it is determined in step S213 of Figure 12 that the number of fail bits is equal to or greater than the first reference value. That is, if the error level of the previous page data re-read by the read conditions (e.g., read voltage and sensing time) changed within the nonvolatile memory device 200 does not decrease (i.e., the number of fail bits of the previous page data is equal to or greater than the first reference value), the memory controller 100 may correct the error in the previous page data.

[0103] 16 is a flowchart illustrating an exemplary operation of the memory system of FIG. 1 according to the flowchart of FIG. 15. Specifically, FIG. 16 illustrates an exemplary operation of the memory controller 100 and the nonvolatile memory device 200 when the number of fail bits is less than a second reference value. Referring to FIG. 16, when the number of fail bits is less than the second reference value, the nonvolatile memory device 200 transmits a ready / busy signal nR / B indicating a ready state to the memory controller 100 and a read fail flag (RFF) indicating a read failure to the memory controller 100 in step S11. For example, the nonvolatile memory device 200 transmits the read fail flag RFF to the memory controller 100 in response to a status information request from the memory controller 100, but the present invention is not limited thereto.

[0104] In step S12, the memory controller 100 transmits a suspend command (CMD) to the nonvolatile memory device 200 in response to the ready / busy signal nR / B and the read failure flag RFF from the nonvolatile memory device 200. In step S13, the memory controller 100 transmits a data output command (Dout CMD) to the nonvolatile memory device 200 to output the previous page data PDp. In step S14, the nonvolatile memory device 200 transmits the previous page data PDp to the memory controller 100 in response to the data output command (Dout CMD).

[0105] At step S15, the memory controller 100 corrects errors in the previous page data PDp from the nonvolatile memory device 200. As a result, the previous corrected page data PDpc is generated. At step S16, the memory controller 100 may transmit the previous corrected page data PDpc along with a data input command Din CMD to the nonvolatile memory device 200. At step S17, the memory controller 100 transmits a resume command Resume CMD to the nonvolatile memory device 200. At step S18, in response to the resume command Resume CMD, the nonvolatile memory device 200 performs a select program operation PGM_sel based on the previous corrected page data PDpc, as described with reference to FIG. 15. This completes the multi-page program operation.

[0106] In an exemplary embodiment, the abort command transmission operation of step S12 may be omitted. In this case, the memory controller 100 may transmit the data output command Dout CMD to the nonvolatile memory device 200 in response to the ready / busy signal nR / B and the read failure flag RFF from the nonvolatile memory device 200.

[0107] Figure 17 is a timing diagram illustrating an exemplary operation of the nonvolatile memory device according to the flowcharts of Figures 15 and 16. Referring to Figures 1, 16, and 17, steps S241 to S244 correspond to steps S221 to S224 of Figure 14, and therefore, a duplicated description will be omitted below.

[0108] In operation S245, the nonvolatile memory device 200 may output the read previous page data PDp. The output previous page data PDp may be transmitted to the memory controller 100. For example, the nonvolatile memory device 200 may transmit the previous page data PDp stored in the page buffer unit 240 of FIG. 3 to the memory controller 100 in response to a data output command from the memory controller 100.

[0109] In operation S246, the nonvolatile memory device 200 may receive previously corrected page data PDpc from the memory controller 100. For example, the nonvolatile memory device 200 may store the previously corrected page data PDpc in the page buffer unit 240 in response to a data input command from the memory controller 100. In operation S247, the nonvolatile memory device 200 may receive a resume command Resume CMD from the memory controller 100. While operations S245 to S247 are being performed, the ready / busy signal nR / B may be in a ready state. For example, the ready / busy signal nR / B may have a high level.

[0110] In operation S248, the nonvolatile memory device 200 may perform a select program operation PGM_sel. For example, the nonvolatile memory device 200 may program the previously corrected page data PDpc and the remaining page data of the multi-page data into memory cells connected to the selected word line. While operation S248 is being performed, the ready / busy signal nR / B may be in a busy state. For example, the ready / busy signal nR / B may have a low level. After operation S248, the ready / busy signal nR / B may be changed to a ready state.

[0111] As described above, when error correction is performed on the previous page data PDp in the memory controller 100, the ready / busy signal nR / B output from the nonvolatile memory device 200 in one program cycle may be changed from a busy state to a ready state and then changed back to a busy state.

[0112] 18A and 18B are diagrams illustrating a programming technique for multi-page data according to an embodiment of the present invention. In one programming cycle for a multi-page programming operation, the operations of FIGS. 18A and 18B are performed. The horizontal axis of the scatter diagram shown in FIG. 18B represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells.

[0113] 3, 18A, and 18B, the nonvolatile memory device 200 may receive first page data PD1. In an example embodiment, the received first page data PD1 may be stored in the page buffer unit 240 of the nonvolatile memory device 200.

[0114] The nonvolatile memory device 200 may program first page data PD1 to memory cells connected to a selected word line, a first word line WL1 (hereinafter referred to as a first program operation PGM1). As shown in FIG. 18B, the nonvolatile memory device 200 may perform the first program operation PGM1 so that the memory cells connected to the first word line WL1 have one of an erase state E and a program state P01. During the first program operation PGM1, a program verify voltage VF01 may be used to verify the program state P01. When the first program operation PGM1 for the first word line WL1 is completed, the memory cells connected to the first word line WL1 store the first page data PD1.

[0115] After the first program operation PGM1, the nonvolatile memory device 200 may receive the remaining page data (i.e., the second page data PD2 and the third page data PD3) of the multi-page data. In an exemplary embodiment, the received second and third page data PD2 and PD3 may be stored in the page buffer unit 240 of the nonvolatile memory device 200.

[0116] After the remaining page data PD2 and PD3 are received, the nonvolatile memory device 200 can read the first page data PD1 from the memory cells connected to the first word line WL1 (hereinafter referred to as the intermediate read operation RD_mid). As shown in FIG. 18B, each memory cell storing the first page data PD1 has one of the erased state E and the programmed state P01. The nonvolatile memory device 200 can read the first page data PD1 by performing the intermediate read operation RD_mid using the read voltage VRD01.

[0117] After the intermediate read operation RD_mid, the nonvolatile memory device 200 may perform a program operation (hereinafter referred to as the second program operation PGM2) on memory cells connected to the first word line WL1 based on the second page data PD2, the third page data PD3, and the read first page data PD1. As shown in FIG. 18B, by performing the second program operation PGM2, memory cells connected to the first word line WL1 that have the erased state E have the erased state E and one of the first through third program states P1 through P3, and memory cells that have the program state P01 have one of the fourth through seventh program states P4 through P7. In the second program operation PMG2, first through seventh program verify voltages VF1 through VF7 may be used to verify the first through seventh program states P1 through P7. When the second program operation PGM2 is completed, the memory cells connected to the first word line WL1 can store the first to third page data PD1 to PD3.

[0118] 18A and 18B illustrate that one page of data (e.g., first page data PD1) is programmed in the first program operation PGM1 and the remaining page of data (e.g., second and third page data PD2 and PD3) is programmed in the second program operation PGM2, but the present invention is not limited thereto. For example, two pages of data (e.g., first page data PD1 and second page data PD2) are programmed in the first program operation PGM1, and the remaining page of data (e.g., third page data PD3) is programmed in the second program operation PGM2. Alternatively, one page of data (e.g., first page data PD1) is programmed in the first program operation PGM1, one page of data (e.g., second page data PD2) is programmed in the second program operation PGM2, and the remaining page of data (e.g., third page data PD3) is programmed in an additional program operation.

[0119] As described above, the multi-page program operation according to the embodiment of the present invention can program at least one page of data among the multi-page data into memory cells connected to a selected word line, and then program the remaining page data into memory cells connected to the selected word line (i.e., a first program operation PGM1 is followed by a second program operation PGM2). In this case, at least one page of data stored in the memory cells connected to the selected word line is read, and a second program operation PGM2 is performed based on the read at least one page of data and the remaining page data. According to this programming technique, the reliability of the page data programmed through the second program operation PGM2 is reduced due to the error level generated during the first program operation PGM1.

[0120] A multi-page program operation for improving the reliability of the program technique of Figures 18A and 18B will be described in detail below with reference to Figures 19 to 23. For convenience of explanation, the multi-page program operation will be described based on an embodiment in which a first program operation PGM1 is performed on one page of data as shown in Figures 18A and 18B.

[0121] 19 is a flowchart illustrating a program operation for multi-page data of the nonvolatile memory device of FIG. 1 according to the program techniques of FIG. 18A and FIG. 18B. Referring to FIG. 1, FIG. 3, and FIG. 19, in step S251, the nonvolatile memory device 200 may receive a first page of data among the multi-page data from the memory controller 100. For example, the nonvolatile memory device 200 may further receive an address ADDR corresponding to a selected word line and a program command CMD for the first page of data from the memory controller 100 along with the first page of data.

[0122] In operation S252, the nonvolatile memory device 200 may program the first page of data into memory cells connected to the selected word line.

[0123] In operation S253, the nonvolatile memory device 200 may receive the remaining page data of the multi-page data from the memory controller 100. For example, the nonvolatile memory device 200 may further receive, from the memory controller 100, an address ADDR corresponding to the selected word line and a program command CMD for the remaining page data, along with the remaining page data.

[0124] In operation S254, the nonvolatile memory device 200 may read the first page data stored in the memory cells connected to the selected word line based on the first and second sensing values. For example, as described with reference to FIGS. 8 through 9C, the nonvolatile memory device 200 may read the first page data based on the first and second read voltages or based on the first and second sensing time points.

[0125] In operation S255, the nonvolatile memory device 200 may calculate the number of fail bits based on a first bit of the first page data (i.e., first sensing data) read based on the first sensing value and a second bit of the second page data (i.e., second sensing data) read based on the second sensing value. For example, as described with reference to FIGS. 10 and 11, the nonvolatile memory device 200 may compare the first bit and the second bit through the fail bit calculator 220 to determine the number of different bits, and calculate the determined number of different bits as the number of fail bits.

[0126] In operation S256, the nonvolatile memory device 200 may determine whether the number of fail bits is less than a first reference value. If the number of fail bits is less than the first reference value (i.e., if it is determined that the error level of the programmed first page data is low), in operation S257, the nonvolatile memory device 200 may program the read first page data and the remaining page data into memory cells connected to the selected word line. For example, the read first page data may be data read based on the first sensing value or the second sensing value. As another example, the read first page data may be data read based on a read voltage having a predetermined level (e.g., the reference read voltage VRD of FIG. 9A).

[0127] If the number of fail bits is equal to or greater than the first reference value (i.e., if it is determined that the error level of the previously programmed page data is not low), the nonvolatile memory device 200 may perform step S261 or step S281. Step S261 will be described below with reference to FIG. 20, and step S281 will be described below with reference to FIG. 22. For example, the nonvolatile memory device 200 may treat the multi-page program operation as a failure, re-read the first page data based on another sensing value, or correct the error in the read first page data.

[0128] 20 is a flowchart illustrating an exemplary operation of the nonvolatile memory device of FIG. 1 when the number of fail bits calculated in FIG. 19 is equal to or greater than the first reference value. Steps S261 to S266 of FIG. 20 correspond to steps S211 to S216 of FIG. 12, and therefore, detailed description thereof will be omitted below.

[0129] 1 and 20, as described with reference to FIG. 19, if the calculated number of fail bits is equal to or greater than the first reference value, the nonvolatile memory device 200 may re-read the first page data stored in the memory cells connected to the selected word line based on the first corrected sensing value and the second corrected sensing value in operation S261. In operation S262, the nonvolatile memory device 200 may calculate the number of fail bits based on the first bit of the first page data read based on the first corrected sensing value and the second bit of the first page data read based on the second corrected sensing value.

[0130] In operation S263, the nonvolatile memory device 200 determines whether the calculated number of fail bits is less than a first reference value. If the calculated number of fail bits is less than the first reference value (i.e., if the error level of the reread first page data is determined to be relatively low), the nonvolatile memory device 200 may program the reread first page data and the remaining page data into memory cells connected to the selected word line in operation S264. If the calculated number of fail bits is equal to or greater than the first reference value (i.e., if the error level of the reread first page data is determined to be relatively high), the nonvolatile memory device 200 may transmit program fail information to the memory controller 100 in operation S265.

[0131] In step S266, the nonvolatile memory device 200 may update a read or program setting value. For example, the nonvolatile memory device 200 may extract characteristic information of a memory block or a memory die while performing steps S261 through S265, and update a read setting value (e.g., a read voltage) or a program setting value (e.g., a program voltage or a program verify voltage) based on the extracted characteristic information. In an exemplary embodiment, step S266 may be omitted.

[0132] If it is determined that the error level of the programmed first page data is relatively high as described above, the nonvolatile memory device 200 may adjust the two sensing values ​​and re-read the first page data. That is, the nonvolatile memory device 200 may perform a multi-page program operation based on the first page data having a reduced error level by changing the read conditions and re-reading the first page data. This may improve the reliability of the multi-page program operation.

[0133] 21 is a timing diagram illustrating an exemplary operation of the nonvolatile memory device according to the flowchart of FIG. 20. Referring to FIGS. 1 and 21, in operation S271, the nonvolatile memory device 200 receives a first program command PGM CMD1 from the memory controller 100. The first program command PGM CMD1 is a program command for first page data. Thus, the nonvolatile memory device 200 may receive the first page data along with the first program command PGM CMD1. The nonvolatile memory device 200 may receive a first address to which the first page data is to be programmed along with the first program command PGM CMD1. In operation S271, the ready / busy signal nR / B may indicate a ready state.

[0134] At step S272, the nonvolatile memory device 200 performs a first program operation PGM1 on the first page data in response to the first program command. At step S272, the ready / busy signal nR / B indicates a busy state. At step S273, the nonvolatile memory device 200 receives a second program command PGM CMD2 from the memory controller 100. The second program command PGM CMD2 is also a program command for the remaining page data of the multi-page data. Accordingly, the nonvolatile memory device 200 receives the remaining page data together with the second program command PGM CMD2. The nonvolatile memory device 200 also receives a second address, to which the remaining page data is to be programmed, together with the second program command PGM CMD2. In this case, the second address is different from the first address. At step S273, the ready / busy signal nR / B indicates a ready state.

[0135] At operation S274, the nonvolatile memory device 200 may perform a first intermediate read operation RD1_mid. For example, the nonvolatile memory device 200 may read first page data stored in memory cells connected to the selected word line based on the first and second sensing values. At operation S275, the nonvolatile memory device 200 performs a second intermediate read operation RD2_mid. For example, the nonvolatile memory device 200 may re-read the first page data based on the first and second corrected sensing values. In this case, as described with reference to FIG. 20, operation S275 is performed when the number of fail bits for the first page data is equal to or greater than a first reference value.

[0136] In operation S276, the nonvolatile memory device 200 performs a second program operation PGM2 on the remaining page data. For example, the nonvolatile memory device 200 may program the re-read first page data and the remaining page data into memory cells connected to the selected word line.

[0137] The nonvolatile memory device 200 may transmit a ready / busy signal nR / B indicating a ready state to the memory controller 100 while performing steps S271 and S273, and may transmit a ready / busy signal nR / B indicating a busy state to the memory controller 100 while performing steps S272, S274 to S276.

[0138] Figure 22 is a flowchart illustrating an exemplary operation of the nonvolatile memory device of Figure 1 when the number of fail bits calculated in Figure 19 is equal to or greater than the first reference value. Steps S281 to S285 of Figure 22 correspond to steps S231 to S235 of Figure 15, and therefore will not be described in detail below.

[0139] 1 and 22, if the calculated number of fail bits is equal to or greater than the first reference value, the nonvolatile memory device 200 determines whether the number of fail bits is less than a second reference value in operation S281. The second reference value is a reference value for determining whether to correct errors in the first page data, and is greater than the first reference value.

[0140] If the number of fail bits is less than the second reference value (i.e., if the errors in the first page data are determined to be at a correctable level), in operation S282, the nonvolatile memory device 200 may transmit the read first page data to the memory controller 100. In operation S283, the nonvolatile memory device 200 may receive first corrected page data from the memory controller 100. The first corrected page data may be generated by correcting errors in the first page data transmitted to the memory controller 100. In operation S284, the nonvolatile memory device 200 may program the first corrected page data and the remaining page data into memory cells connected to the selected word line. This may complete the multi-page program operation.

[0141] If the number of fail bits is equal to or greater than the second reference value (i.e., if it is determined that the error correction of the first page data is not possible), the nonvolatile memory device 200 may transmit program failure information to the memory controller 100 in operation S285.

[0142] As described above, if it is determined that the error in the first page data from which the number of fail bits has been read is correctable, the nonvolatile memory device 200 transmits the first page data to the memory controller 100, and the error in the first page data may be corrected by the memory controller 100. As a result, a multi-page program operation may be performed based on the error-corrected first page data (i.e., first corrected page data), thereby improving the reliability of the multi-page data programmed by the multi-page program operation. However, the present invention is not limited to this, and errors in the read first page data may be corrected within the nonvolatile memory device 200.

[0143] In an exemplary embodiment, steps S281 through S285 are performed when it is determined that the number of fail bits is equal to or greater than the first reference value in step S263 of Figure 20. That is, if the error level of the first page data read by the memory controller 100 does not decrease due to read conditions (e.g., read voltage and sensing time point) changed within the nonvolatile memory device 200 (i.e., if the number of fail bits of the first page data is equal to or greater than the first reference value), errors in the first page data read by the memory controller 100 may be corrected.

[0144] Figure 23 is a timing diagram illustrating an exemplary operation of the nonvolatile memory device according to the flowcharts of Figures 19 and 22. Referring to Figures 1 and 23, steps S291 to S294 correspond to steps S271 to S274 of Figure 21, and therefore, a duplicated description will be omitted below.

[0145] In operation S295, the nonvolatile memory device 200 may output the read first page data PD1. The output first page data PD1 may be transmitted to the memory controller 100. For example, if the number of fail bits of the read first page data PD1 in operation S274 is less than the second reference value, the nonvolatile memory device 200 transmits a ready / busy signal nR / B indicating a ready state and a read fail flag RFF indicating a read failure to the memory controller 100, as described with reference to FIG. 16. The memory controller 100 transmits a data output command Dout to the nonvolatile memory device 200 in response to the ready / busy signal nR / B and the read fail flag RFF from the nonvolatile memory device 200. The nonvolatile memory device 200 transmits the first page data PD1 stored in the page buffer unit 240 to the memory controller 100 in response to the data output command Dout from the memory controller 100.

[0146] In operation S296, the nonvolatile memory device 200 receives the first corrected page data PD1c from the memory controller 100. For example, as described with reference to FIG. 16, the nonvolatile memory device 200 stores the first corrected page data PD1c in the page buffer unit 240 in response to the data input command Din from the memory controller 100. In operation S297, the nonvolatile memory device 200 may receive a resume command Resume CMD from the memory controller 100. While operations S295 to S297 are being performed, the ready / busy signal nR / B is also in a ready state. That is, the ready / busy signal nR / B may maintain the ready state for these three steps.

[0147] In operation S298, the nonvolatile memory device 200 performs a second program operation PGM2. For example, the nonvolatile memory device 200 may program the first corrected page data PD1c and the remaining page data into memory cells connected to the selected word line. While operation S298 is being performed, the ready / busy signal nR / B is also in a busy state. After operation S298, the ready / busy signal nR / B may be changed to a ready state.

[0148] 24 is an exemplary cross-sectional view of a memory device according to an embodiment of the present invention. Referring to FIG. 24, memory device 300 also has a C2C (Chip to Chip) structure. The C2C structure refers to fabricating an upper chip including a cell region CELL on a first wafer, fabricating a lower chip including a peripheral circuit region PERI on a second wafer different from the first wafer, and then connecting the upper and lower chips to each other by a bonding method. The bonding method refers to a method of electrically connecting a bonding metal formed on the top metal layer of the upper chip to a bonding metal formed on the top metal layer of the lower chip to each other. For example, if the bonding metal is formed of copper (Cu), the bonding method can be Cu-Cu bonding, and the bonding metal can also be formed of aluminum or tungsten.

[0149] Each of the peripheral circuit region PERI and the cell region CELL of the memory device 300 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0150] The peripheral circuit region PERI may include a first substrate 410, an interlayer insulating layer 415, a plurality of circuit elements 420a, 420b, and 420c formed on the first substrate 410, first metal layers 430a, 430b, and 430c coupled to the plurality of circuit elements 420a, 420b, and 420c, respectively, and second metal layers 440a, 440b, and 440c formed on the first metal layers 430a, 430b, and 430c. In an exemplary embodiment, the first metal layers 430a, 430b, and 430c may be formed of tungsten, which has a relatively high resistance, and the second metal layers 440a, 440b, and 440c may be formed of copper, which has a relatively low resistance.

[0151] Although only first metal layers 430a, 430b, and 430c and second metal layers 440a, 440b, and 440c are illustrated herein, the present invention is not limited thereto, and at least one more metal layer may be formed on second metal layers 440a, 440b, and 440c. At least a portion of the one or more metal layers formed on second metal layers 440a, 440b, and 440c may be formed of aluminum, which has a lower resistance than copper, which forms second metal layers 440a, 440b, and 440c.

[0152] The interlayer insulating layer 415 is disposed on the first substrate 410 to cover the plurality of circuit elements 420a, 420b, 420c, the first metal layers 430a, 430b, 430c, and the second metal layers 440a, 440b, 440c, and may include an insulating material such as silicon oxide or silicon nitride.

[0153] Lower bonding metals 471b and 472b may be formed on the second metal layer 440b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 471b and 472b in the peripheral circuit region PERI are electrically connected to the upper bonding metals 371b and 372b in the cell region CELL by bonding, and the lower bonding metals 471b and 472b and the upper bonding metals 371b and 372b may be formed of aluminum, copper, tungsten, or the like.

[0154] The cell region CELL may provide at least one memory block. The cell region CELL may include a second substrate 310 and a common source line 320. A plurality of word lines 331-338; 330 may be stacked on the second substrate 310 along a vertical direction (Z-axis direction) on the upper surface of the second substrate 310. A string selection line and a ground selection line may be disposed above and below the word line 330, respectively, and a plurality of word lines 330 may be disposed between the string selection line and the ground selection line.

[0155] In the bit line bonding region BLBA, the channel structure CH may extend vertically to the top surface of the second substrate 310 and penetrate the word lines 330, the string select lines, and the ground select lines. For example, the channel structure CH may extend along the Z-axis direction. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c may also be a bit line contact, and the second metal layer 360c may also be a bit line. In this specification, the second metal layer 360c is also referred to as a bit line. In an exemplary embodiment, the bit line 360c extends along a first direction (Y-axis direction) parallel to the top surface of the second substrate 310.

[0156] In an exemplary embodiment, a region in which the channel structure CH and the bit line 360c are disposed may be defined as a bit line bonding region BLBA. The bit line 360c may be electrically connected to circuit elements 420c that provide the page buffer 393 in the peripheral circuit region PERI through the bit line bonding region BLBA. For example, the bit line 360c may be connected to upper bonding metals 371c and 372c in the cell region CELL, and the upper bonding metals 371c and 372c may be connected to lower bonding metals 471c and 472c that are connected to the circuit elements 420c of the page buffer 393.

[0157] In the word line bonding region WLBA, the word line 330 may extend in a second direction (X-axis direction) parallel to the top surface of the second substrate 310 and be connected to a plurality of cell contact plugs 341-347; 340. The word line 330 and the cell contact plug 340 may be connected to each other at pads, at least some of which extend to different lengths in the second direction. A first metal layer 350b and a second metal layer 360b may be sequentially connected to the upper portion of the cell contact plug 340 connected to the word line 330. The cell contact plug 340 may be connected to the peripheral circuit region PERI in the word line bonding region WLBA through upper bonding metals 371b and 372b of the cell region CELL and lower bonding metals 471b and 472b of the peripheral circuit region PERI.

[0158] The cell contact plug 340 may be electrically coupled to a circuit element 420b that provides a row decoder 394 in the peripheral circuit region PERI. In an exemplary embodiment, the operating voltage of the circuit element 420b that provides the row decoder 394 may also be different from the operating voltage of the circuit element 420c that provides the page buffer 393. For example, the operating voltage of the circuit element 420c that provides the page buffer 393 may be higher than the operating voltage of the circuit element 420b that provides the row decoder 394.

[0159] A common source line contact plug 380 may be disposed in the external pad bonding region PA. The common source line contact plug 380 may be formed of a conductive material such as metal, metal compound, or polysilicon and may be electrically connected to the common source line 320. A first metal layer 350a and a second metal layer 360a may be sequentially stacked on the common source line contact plug 380. For example, the region where the common source line contact plug 380, the first metal layer 350a, and the second metal layer 360a are disposed may be defined as the external pad bonding region PA. In the external pad bonding region PA, the lower metal pattern 473a of the peripheral circuit region PERI may be electrically connected to the upper bonding metals 71a and 372a of the cell region CELL using a bonding method.

[0160] Meanwhile, input / output pads 305 and 405 may be disposed in the external pad bonding area PA. A lower insulating film 401 covering the lower surface of the first substrate 410 may be formed under the first substrate 410, and a first input / output pad 405 may be formed on the lower insulating film 401. The first input / output pad 405 may be connected to at least one of a plurality of circuit elements 420a, 420b, and 420c disposed in the peripheral circuit area PERI through a first input / output contact plug 403 and may be separated from the first substrate 410 by the lower insulating film 401. In addition, a side insulating film may be disposed between the first input / output contact plug 403 and the first substrate 410 to electrically separate the first input / output contact plug 403 from the first substrate 410.

[0161] An upper insulating film 301 covering the upper surface of the second substrate 310 may be formed on the upper surface of the second substrate 310, and a second I / O pad 305 may be disposed on the upper insulating film 301. The second I / O pad 305 may be connected to at least one of a plurality of circuit elements 420a, 420b, and 420c disposed in the peripheral circuit region PERI through a second I / O contact plug 303. For example, the second I / O contact plug 303 may be connected to the circuit element 420a through a lower bonding metal 472a.

[0162] According to the embodiment, the second substrate 310 and the common source line 320 are not disposed in the region where the second I / O contact plug 303 is disposed. In addition, the second I / O pad 305 does not overlap with the word line 330 in the third direction (Z-axis direction). The second I / O contact plug 303 is separated from the second substrate 310 in a direction parallel to the top surface of the second substrate 310 and may be connected to the second I / O pad 305 through an interlayer insulating layer in the cell region CELL.

[0163] Depending on the embodiment, the first I / O pad 405 and the second I / O pad 305 may be selectively formed. For example, the memory device 300 may include only the first I / O pad 405 disposed on the first substrate 410, or only the second I / O pad 305 disposed on the second substrate 310. Alternatively, the memory device 300 may include both the first I / O pad 405 and the second I / O pad 305.

[0164] In each of the external pad bonding area PA and bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, the metal pattern of the uppermost metal layer exists as a dummy pattern, or the uppermost metal layer is empty.

[0165] In the memory device 300, a lower metal pattern 473a having the same shape as the upper metal pattern 372a may be formed in the uppermost metal layer of the peripheral circuit region PERI in the external pad bonding region PA, corresponding to the upper metal pattern 372a formed in the uppermost metal layer of the cell region CELL. The lower metal pattern 473a formed in the uppermost metal layer of the peripheral circuit region PERI is not connected to a separate contact in the peripheral circuit region PERI. Similarly, in the external pad bonding region PA, an upper metal pattern having the same shape as the lower metal pattern in the peripheral circuit region PERI is formed in the uppermost metal layer of the cell region CELL, corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI.

[0166] Lower bonding metals 471b and 472b may be formed on the second metal layer 240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 471b and 472b in the peripheral circuit region PERI may be electrically connected to the upper bonding metals 371b and 372b in the cell region CELL by bonding.

[0167] In addition, in the bit line bonding region BLBA, an upper metal pattern 392 having the same shape as the lower metal pattern 452 may be formed in the uppermost metal layer of the cell region CELL in correspondence with the lower metal pattern 452 formed in the uppermost metal layer of the peripheral circuit region PERI. No contact is formed on the upper metal pattern 392 formed in the uppermost metal layer of the cell region CELL.

[0168] In an exemplary embodiment, the memory cell array 210 of FIG. 3 may be disposed in the cell region CELL, and the fail bit calculator 220, row decoder 230, page buffer unit 240, input / output circuit 250, and control logic circuit 260 of FIG. 3 may be disposed in the peripheral circuit region PERI. Thus, the memory device 300 may perform a multi-page program operation as described with reference to FIGS. 1 through 23. For example, while performing the multi-page program operation, the memory device 300 may read a previous page of data (or one page of data among multiple pages) stored in a memory cell connected to a selected word line among the word lines 330 based on two sensing values. For example, the read data may be transferred to the page buffer 393 through the upper bonding metal 372c and the lower bonding metal 472c. The memory device 300 may determine an error level of the read previous page data and, by changing read conditions according to the determined error level, re-read the previous page data or correct the error in the read previous page data. For example, the memory device 300 may transmit previous page data to the memory controller through the first I / O pad 405 or the second I / O pad 305, and receive error-corrected previous page data from the memory controller through the first I / O pad 405 or the second I / O pad 305. This may improve the reliability of a multi-page program operation performed by the memory device 300.

[0169] 25 is a block diagram illustrating an SSD system to which a memory device according to an embodiment of the present invention is applied. Referring to FIG. 25, an SSD system 1000 includes a host 1100 and an SSD 1200.

[0170] The SSD 1200 transmits and receives a signal SGL to and from the host 1100 through a signal connector 1201, and receives a power supply PWR through a power supply connector 1202. The SSD 1200 may include an SSD controller 1210, a plurality of flash memories 1221 to 122m, an auxiliary power supply 1230, and a buffer memory 1240. The plurality of flash memories 1221 to 122m may be connected to the SSD controller 1210 through a plurality of channels, respectively.

[0171] The SSD controller 1210 can control a plurality of flash memories 1221-122m in response to a signal SIG received from the host 1100. The SSD controller 1210 can store a signal generated internally or transmitted externally (e.g., a signal SGL received from the host 1100) in the buffer memory 1240. The SSD controller 1210 can correspond to the memory controller 100 described above with reference to FIGS. 1 to 23.

[0172] The plurality of flash memories 1221-122m are operated under the control of the SSD controller 1210. The auxiliary power supply 1230 is connected to the host 1100 via the power connector 1202. Each of the plurality of flash memories 1221-122m may correspond to the nonvolatile memory device 200 described above with reference to FIGS. 1 through 23. For example, while performing a multi-page program operation, each of the plurality of flash memories 1221-122m may read previous page data (or one page data of the multi-page data) stored in memory cells connected to a selected word line based on two sensing values. Each of the plurality of flash memories 1221-122m may determine an error level of the read previous page data and change read conditions according to the determined error level to re-read the previous page data or correct errors in the read previous page data. This may improve the reliability of the multi-page program operation performed by each of the plurality of flash memories 1221-122m.

[0173] The auxiliary power supply 1230 may be connected to the host 1100 through a power connector 1202. The auxiliary power supply 1230 may receive and charge a power supply PWR from the host 1100. The auxiliary power supply 1230 may provide power to the SSD 1200 when power supply from the host 1100 is not smooth.

[0174] The above is a specific example for carrying out the present invention. The present invention may include not only the above-described examples, but also examples that are simply modified or can be easily modified. Furthermore, the present invention may include techniques that can be easily implemented by modifying the examples. Therefore, the scope of the present invention should not be limited to the above-described examples, but should be determined not only by the following claims but also by equivalents of the claims of the present invention. [Explanation of symbols]

[0175] 10 Memory System 100 Memory Controller 200 Non-volatile memory device 210 memory cell array 220 Fail Bit Calculator

Claims

1. 1. A method of operating a non-volatile memory device for programming multi-page data, comprising: receiving the multi-page data including first and second page data from a memory controller; programming the first page of data among the multi-page data into first memory cells connected to an unselected word line adjacent to a selected word line; After programming the first page data, reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value; calculating a first number of fail bits by comparing a first bit of the previous page data read based on the first sensing value with a second bit of the previous page data read based on the second sensing value; programming second page data of the previous page data read from the second memory cells according to the first number of fail bits and the multi-page data received from the memory controller to the second memory cells; The multi-page data is data programmed in a current program cycle, and the previous page data is data previously stored in the second memory cells in a previous program cycle.

2. receiving a program command for the multi-page data from the memory controller; 2. The method of claim 1, wherein the programming of the first page of data is performed in response to the program command.

3. 3. The method of claim 1, wherein the step of reading the previous page data includes applying a first read voltage having a level corresponding to the first sensing value to the selected word line, and applying a second read voltage having a level corresponding to the second sensing value to the selected word line.

4. 3. The method of claim 1, wherein the step of reading the previous page data includes the steps of: sensing a voltage of a sensing node at a first sensing time corresponding to the first sensing value; and sensing a voltage of the sensing node at a second sensing time corresponding to the second sensing value.

5. 5. The method of claim 1, wherein the second page of data is programmed into the second memory cells if the first number of fail bits is less than a first reference value.

6. if the first number of fail bits is equal to or greater than the first reference value, re-reading the previous page data from the second memory cell based on a first corrected sensing value different from the first sensing value and a second corrected sensing value different from the second sensing value; 6. The operating method of claim 5, further comprising: if a second number of fail bits calculated by comparing a third bit of the previous page data read based on the first correction sensing value with a fourth bit of the previous page data read based on the second correction sensing value is less than the first reference value, programming the previous page data read again from the second memory cells and the second page data received from the memory controller to the second memory cells.

7. 7. The method of claim 6, further comprising transmitting status information indicating a program failure for the multi-page data to the memory controller if the second number of fail bits is equal to or greater than the first reference value.

8. 7. The operating method of claim 6, wherein a ready / busy signal transmitted from the nonvolatile memory device to the memory controller maintains a busy state while a program operation related to the first page data, a read operation based on the first sensing value and the second sensing value, a read operation based on the first corrected sensing value and the second corrected sensing value, and a program operation related to the second page data are performed.

9. transmitting the previous page data read from the second memory cells to the memory controller if the first number of fail bits is equal to or greater than the first reference value and is less than a second reference value that is greater than the first reference value; receiving previous corrected page data generated by correcting an error in the read previous page data from the memory controller; 6. The method of claim 5, further comprising: programming the previously corrected page data and the second page data into the second memory cells.

10. The step of transmitting the read previous page data to the memory controller comprises: transmitting a ready / busy signal indicating a ready state and a read failure flag to the memory controller; receiving a data output command for the previous page data from the memory controller after transmitting the ready / busy signal and the read failure flag; and transmitting the read previous page data to the memory controller in response to the data output command.

11. further comprising receiving a resume command from the memory controller; 10. The method of claim 9, wherein programming the previously corrected page data and the second page data into the second memory cells is performed in response to the resume command.

12. a ready / busy signal transmitted from the nonvolatile memory device to the memory controller indicates a busy state while a program operation related to the first page data, a read operation based on the first sensing value and the second sensing value, and a program operation related to the second page data are performed; 12. The method of claim 11, wherein the ready / busy signal indicates a ready state while the previous page data transmission operation, the previous corrected page data reception operation, and the resume command reception operation are performed.

13. 10. The method of claim 9, further comprising transmitting status information indicating a program failure for the multi-page data to the memory controller if the first number of fail bits is equal to or greater than the second reference value.

14. 1. A method of operating a non-volatile memory device for programming multi-page data, comprising: receiving a first page of data from a memory controller; programming the first page of data into memory cells connected to a selected word line; receiving second page data of the multi-page data from the memory controller after programming the first page data; After receiving the second page data, reading the first page data stored in the memory cell based on the first sensing value and the second sensing value; calculating a first number of fail bits by comparing a first bit of the first page data read based on the first sensing value with a second bit of the first page data read based on the second sensing value; programming the first page data read from the memory cells according to the first number of fail bits and the second page data received from the memory controller into the memory cells; if the first number of fail bits is equal to or greater than a first reference value, re-reading the first page data from the memory cells based on a first corrected sensing value different from the first sensing value and a second corrected sensing value different from the second sensing value; and programming the first page data and the second page data read from the memory cells again to the memory cells when a second number of fail bits calculated by comparing a third bit of the first page data read based on the first correction sensing value with a fourth bit of the first page data read based on the second correction sensing value is less than the first reference value.

15. 15. The method of claim 14, wherein reading the first page of data comprises applying a first read voltage having a level corresponding to the first sensing value to the selected word line, and applying a second read voltage having a level corresponding to the second sensing value to the selected word line.

16. 15. The method of claim 14, wherein reading the first page data comprises sensing a voltage of a sensing node at a first sensing time corresponding to the first sensing value, and sensing a voltage of the sensing node at a second sensing time corresponding to the second sensing value.

17. 15. The method of claim 14, wherein if the first number of fail bits is less than a first reference value, the second page of data is programmed into the memory cells.

18. 15. The method of claim 14, further comprising transmitting status information indicating a program failure for the multi-page data to the memory controller if the second number of fail bits is equal to or greater than the first reference value.

19. 1. A method of operating a non-volatile memory device for programming multi-page data, comprising: receiving the multi-page data from a memory controller; programming at least one page of data among the multiple page data into first memory cells connected to unselected word lines adjacent to a selected word line; After programming the at least one page of data, reading at least one previous page of data previously stored in a second memory cell connected to the selected word line based on a first read voltage and a second read voltage; programming the at least one previous page data read from the second memory cells and the remaining page data of the multi-page data received from the memory controller into the second memory cells when the number of failed cells having a threshold voltage between the first read voltage and the second read voltage is less than a reference value; transmitting status information indicating a program failure for the multi-page data to the memory controller if the number of the failed cells is equal to or greater than the reference value; The multi-page data is data programmed in a current program cycle, and the previous page data is data previously stored in the second memory cells in a previous program cycle.

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