Power Conversion Device

Abstract

To reduce restrictions on a hardware design.SOLUTION: A power conversion device includes: a plurality of semiconductor elements connected in parallel to each other; a plurality of gate drivers corresponding to the plurality of semiconductor elements respectively, and supplying a drive voltage to the corresponding semiconductor elements; and a control unit for supplying a gate command corresponding to the drive voltage to each of the plurality of gate drivers based on a carrier wave. The plurality of semiconductor elements are set in a conductive state at different timing in an operation period Tz.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a power conversion device. [Background technology]

[0002] Power conversion devices are used in a variety of devices and systems to realize a variety of applications. The conversion capacity of power conversion devices is on the rise in response to market demand. In order to increase the conversion capacity, it is desirable to increase the current capacity of the semiconductor elements that are essential for power conversion. In some cases, this can be achieved by simply replacing the semiconductor elements in the power conversion device with semiconductor elements that have a higher current rating. However, when replacing the semiconductor elements alone is not sufficient, it is necessary to increase the overall current rating of the power conversion device by connecting multiple semiconductor elements in parallel or connecting multiple power conversion units in parallel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-137263 [Patent Document 2] International Publication No. 2020 / 161945 [Patent Document 3] Japanese Patent Application Laid-Open No. 2017-208916 Summary of the Invention [Problem to be solved by the invention]

[0004] The hardware design constraints of the power conversion device are reduced. [Means for solving the problem]

[0005] The power conversion device of the embodiment includes: a brake resistor unit provided between a first node and a second node; and a plurality of resistors provided between the brake resistor unit and the second node, each connected in series to the brake resistor unit and between the brake resistor unit and the second node. a plurality of semiconductor elements connected in parallel with each other; The aforementioned a plurality of gate drivers corresponding to the plurality of semiconductor elements, respectively, and supplying drive voltages to the corresponding semiconductor elements; Onea control unit that supplies gate commands corresponding to the drive voltages to each of the plurality of gate drivers based on a carrier wave, and the plurality of semiconductor elements Brake resistor During the operation period of In synchronization with the periodic waveform of the carrier wave, They are set to a conductive state at different times. In each of a plurality of portions included in the operation period, only one semiconductor element among the plurality of semiconductor elements that is set to a conductive state passes a current output from the brake resistor unit. . [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a circuit diagram showing a configuration example of a power conversion device according to a first embodiment. [Figure 2] FIG. 3 is a waveform diagram showing an example of the operation of the power conversion device according to the first embodiment. [Figure 3] FIG. 4 is a circuit diagram showing a configuration example of a power conversion device according to a second embodiment. [Figure 4] FIG. 6 is a waveform diagram showing an example of the operation of the power conversion device according to the second embodiment. [Figure 5] FIG. 10 is a circuit diagram showing a modified example of the power conversion device according to the embodiment. [Figure 6] FIG. 10 is a waveform diagram showing a modified example of the power conversion device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] A power conversion device according to an embodiment will be described with reference to FIGS.

[0008] Hereinafter, the present embodiment will be described in detail with reference to the drawings. In the following description, elements having the same functions and configurations are designated by the same reference numerals. In addition, in each of the following embodiments, when components (e.g., circuits, wiring, various voltages and signals, etc.) that are given reference symbols with distinguishing numbers / letters at the end do not need to be distinguished from each other, descriptions (reference symbols) with the numbers / letters at the end omitted are used.

[0009] [Embodiment] A power conversion device according to an embodiment will be described with reference to FIGS.

[0010] (1) First embodiment The configuration and operation of the power conversion device of the first embodiment will be described with reference to FIGS.

[0011] (a) Configuration example FIG. 1 is a circuit diagram showing an example of the configuration of a power conversion device 100 according to this embodiment.

[0012] As shown in FIG. 1, the power conversion device 100 of this embodiment includes a plurality of semiconductor elements 1 (1a, 1b, 1c), a plurality of gate drivers 2 (2a, 2b, 2c), a brake resistor unit 3, a control unit 4, a voltage detection unit 5, a current detection unit 6, and a DC power supply 9.

[0013] The semiconductor elements 1 and the brake resistor unit 3 are connected between a high-potential side wiring (also called a DC link) of a DC power supply 9 and a low-potential side wiring of the DC power supply. The high-potential side wiring is electrically connected to a positive terminal 90 of the DC power supply 9 via a connection node (also called a connection point, connection terminal, or simply node) ND1. The low-potential side wiring is electrically connected to a negative terminal (ground) 91 of the DC power supply 9 via a connection node ND3.

[0014] Three semiconductor elements 1 (1a, 1b, 1c) are provided in the power conversion device 100. Each semiconductor element 1 includes a switching element 10 such as an IGBT (Insulated Gate Bipolar Transistor) and a rectifying element 11 such as a diode. The semiconductor element 1 may also include a field effect transistor (not shown) such as a MOS (Metal-Oxide-Semiconductor) transistor.

[0015] One of the two terminals of each semiconductor element 1 is connected to a connection node ND2. The other of the two terminals of each semiconductor element 1 is connected to a connection node ND3. The connection node ND3 is connected to a ground 91.

[0016] The three semiconductor elements 1a, 1b, and 1c are connected in parallel to one another between the connection node ND2 and the connection node ND3, thereby forming three parallel current paths within the power conversion device 100. The parallel-connected semiconductor elements 1 share an inter-terminal potential between the two connection nodes ND2 and ND3.

[0017] When each semiconductor element 1 is in a conductive state, a current of a certain magnitude according to the characteristics of the semiconductor element 1 flows.

[0018] The multiple gate drivers 2 (2a, 2b, 2c) are connected to the multiple semiconductor elements 1 in a one-to-one relationship. That is, one gate driver 2 is connected to a corresponding one of the multiple semiconductor elements 1. In this embodiment, three gate drivers 2 are provided in the power conversion device 100. Each gate driver 2 supplies a gate drive voltage (gate signal) to the corresponding semiconductor element 1 in response to a gate command GC, which will be described later.

[0019] The brake resistor unit 3 is connected in series to the plurality of semiconductor elements 1 via a connection node ND2 between a connection node ND1 and a connection node ND3. One of the two terminals of the brake resistor unit 3 is connected to a positive terminal 90 of a DC power supply 9 via the connection node ND1. The other of the two terminals of the brake resistor unit 3 is connected to one terminal of each of the plurality of semiconductor elements 1 via the connection node ND2. The brake resistor unit 3 includes a plurality of resistive elements (not shown). In addition to the resistive elements, the brake resistor unit 3 may further include a capacitive element (not shown) and an inductive element (not shown). The component consisting of the brake resistor unit 3 and the plurality of semiconductor elements 1 is also called a power conversion circuit.

[0020] The brake resistor 3 functions as a load for the power conversion device 100. The brake resistor 3 outputs a current I1. The magnitude (flow rate) of the current I1 can be controlled depending on the conduction state of the semiconductor element 1. The current I1 flowing through the brake resistor 3 causes the brake resistor 3 to generate Joule heat. For example, the heat generated by the brake resistor 3 allows the power conversion device 100 to consume the supplied power. In this way, the power conversion device 100 can perform thermoelectric conversion. The magnitude of the current I1 can be limited depending on the rated value (e.g., current rating) of the power conversion device 100, etc.

[0021] The control unit 4 controls the operation of the plurality of semiconductor elements 1 via the gate driver 2. For example, the control unit 4 generates a PWM (Pulse Width Modulation) carrier wave to control the energization periods (also called conduction periods) of the plurality of semiconductor elements 1. The PWM carrier wave is, for example, a signal including a plurality of triangular waves (triangular pulses) that are periodically output. The energization periods of the semiconductor elements 1 correspond to the periods during which the semiconductor elements 1 are turned on.

[0022] The control unit 4 generates gate commands GC (GCa, GCb, GCc) to control the conductive state (ON state) and non-conductive state (OFF state) of each semiconductor element 1. The control unit 4 outputs the generated gate commands GC to each gate driver 2. For example, when setting the corresponding semiconductor element 1 to a conductive state (ON state, energized state), the control unit 4 sets the signal level of the gate command GC to a first level (e.g., "H" level). When setting the corresponding semiconductor element 1 to a non-conductive state (OFF state, non-energized state), the control unit 4 sets the signal level of the gate command GC to a second level (e.g., "L" level) different from the first level.

[0023] The control unit 4 controls the pulse shape (e.g., pulse width) of the gate command GC to be generated based on the comparison result between the PWM carrier wave and the conduction ratio of the semiconductor device 1 in accordance with the supplied command power CP. The conduction ratio is determined by various controls such as PI control of the voltage and current in the power conversion device 100. The conduction ratio is a value indicating the ratio of the conduction period of the semiconductor device 1 to a certain period of the PWM carrier wave.

[0024] For example, the control unit 4 has a control processor (not shown), a memory (not shown), a counter (not shown), etc. The control unit 4 may include an arithmetic circuit configured to realize various functions by software or a combination of software and hardware. The control unit 4 can control the operation timing of the semiconductor element 1 based on a sequence set by software.

[0025] The voltage detection unit 5 detects a voltage corresponding to the potential difference between the connection node ND1 and the connection node (earth) ND3. The voltage detection unit 5 can measure and acquire the voltage value of the detected voltage. The voltage detection unit 5 transmits a signal S1 indicating the voltage value of the detected voltage to the control unit 4. The voltage detection unit 5 is connected in parallel to the plurality of semiconductor elements 1 and the brake resistor unit 3 between the connection node ND1 and the connection node ND3.

[0026] The current detection unit 6 detects the current I1 output from the brake resistor unit 3. For example, the current I1 is supplied to the current detection unit 6 via the semiconductor element 1. The current detection unit 6 can measure and acquire the current value of the detected current I1. The current detection unit 6 transmits a signal S2 indicating the current value of the detected current I1 to the control unit 4.

[0027] For example, the power conversion device 100 is electrically connected to an external device 200 such as a processor. The power conversion device 100 of this embodiment can communicate with the external device 200. The power conversion device 100 receives a signal related to a command power CP from the external device 200. The command power CP is a signal indicating the power (e.g., power consumption) to be converted by the brake resistor unit 3.

[0028] For example, the power conversion device 100 is connected to an electric motor 300. The electric motor 300 is connected to wheels (not shown). The electric motor 300 receives a power supply voltage (electric power) that has been converted from DC to AC by a power conversion device (not shown) such as a three-phase inverter circuit. The electric motor 300 generates torque according to the supplied power supply voltage. The electric motor 300 applies energy according to the torque to the wheels. When the supply of the power supply voltage to the electric motor 300 is cut off (for example, when the wheels are decelerating or stopped), the electric motor 300 generates regenerative power according to the rotation of the electric motor 300.

[0029] The power conversion device 100 adjusts the DC voltage of the DC power supply 9 and supplies it to the brake resistor unit 3. The power conversion device 100 can receive regenerated power from the electric motor 300. The power conversion device 100 can consume the regenerated power generated by the electric motor 300 through thermoelectric conversion by the brake resistor unit 3.

[0030] 1 corresponds to a regenerative braking circuit (brake chopper circuit) that controls power consumption by the braking resistor 3. In the power conversion device 100 as a regenerative braking circuit, for example, the semiconductor element 1 is also called a brake chopper element.

[0031] The internal configuration of the power conversion device 100 is not limited to the above-mentioned components, and other components may be further provided within the device 100, or some of the above-mentioned components may be excluded from the device 100. For example, one or more of the voltage detection unit 5, the current detection unit 6, and the DC power supply 9 may be external components of the power conversion device 100. Furthermore, various signals such as the gate command GC, the gate signal, and the command power CP may be electrical signals supplied via wiring, or optical signals supplied via a photocoupler.

[0032] In the power conversion device 100 of this embodiment, the semiconductor elements 1 connected in parallel between the two connection nodes ND2 and ND3 are turned on at different times during a certain operation period. In other words, in the power conversion device 100 of this embodiment, the conduction periods of the semiconductor elements 1 do not overlap with each other.

[0033] (b) Example of operation FIG. 2 is a waveform diagram showing an example of the operation of the power conversion device 100 of the first embodiment.

[0034] The waveform diagram of FIG. 2 shows a timing chart of switching of the plurality of semiconductor elements 1 of the power conversion device 100.

[0035] The timing chart of the switching of the semiconductor element 1 in Figure 2 shows the time progression of the PWM carrier generated by the control unit 4 in Figure 1 and the gate commands GC (GCa, GCb, GCc) output from the control unit 4 to the three parallel semiconductor elements 1a, 1b, 1c.

[0036] The operation of the power conversion device of this embodiment will be described with reference to FIG.

[0037] 1, the voltage between connection nodes ND1 and ND3 is detected by a voltage detection unit 5, and the current (flow current) I1 output from the brake resistor unit 3 is detected by a current detection unit 6. A signal S1 relating to the voltage value of the detected voltage and a signal S2 relating to the current value of the current I1 are supplied to a control unit 4.

[0038] The control unit 4 multiplies the voltage value of the voltage (value indicated by the signal S1) by the current value of the energizing current I1 (value indicated by the signal S2) to calculate the power consumption generated in the power conversion device (dynamic braking circuit) 100.

[0039] The control unit 4 receives a command power CP from the external device 200. For example, the received command power CP indicates a value according to the drive state (for example, deceleration or stop) required of the electric motor 300.

[0040] 2, the control unit 4 generates a PWM carrier wave CW to generate and control a gate command GC of the semiconductor element 1. For example, a period Tz from time ta to time tb is an operation period Tz of one cycle (one sequence) in which the conduction / non-conduction of the multiple semiconductor elements 1 connected in parallel is sequentially controlled. The power conversion device 100 repeatedly executes multiple operation periods Tz.

[0041] In this embodiment, the operating period Tz is divided into multiple parts (sections) according to the number of semiconductor elements 1. If the number of semiconductor elements 1 connected in parallel between the connection node ND2 and the connection node ND3 is N, the period Tz is divided into N parts, where N is a natural number equal to or greater than 2. For example, the lengths (Tz / N) of the N divided parts of the operating period Tz are equal to each other. Each operating period Tz includes multiple periods CY corresponding to the multiple triangular waves of the PWM carrier wave CW according to the number of current paths connected in parallel (e.g., the number of semiconductor elements 1 connected in parallel).

[0042] When the number of semiconductor elements 1 connected in parallel is three as in this embodiment, one operating period Tz includes three cycles of the triangular wave. That is, the operating period Tz includes three portions corresponding to the periods subject to control of the three semiconductor elements 1. The number of semiconductor elements 1 connected in parallel may be two, four or more.

[0043] The control unit 4 determines the conduction ratios DF (DF1, DF2) of one or more corresponding semiconductor elements 1 through various types of control (for example, PI control) so that the calculated power consumption matches the command power CP given to the control unit 4. The ratio of the conduction period (period of conduction) of the semiconductor elements 1 to a certain cycle CY of the PWM carrier wave CW is set according to the conduction ratio DF. The time corresponding to the cycle CY assigned to each semiconductor element 1 is also called the control target period.

[0044] The control unit 4 compares the PWM carrier wave CW with the duty ratio DF1 during a certain operating period Tz. This allows the control unit 4 to generate a gate command GC having a desired pulse width (period of "H" level). The control unit 4 supplies the generated gate command GC to the corresponding gate driver 2. The gate driver 2 supplies a gate drive voltage to the corresponding semiconductor device 1 in response to the "H" level signal of the supplied gate command GC. In the gate commands GCa, GCb, and GCc for the duty ratio DF1, the "H" level signals have certain pulse widths Wa1, Wb1, and Wc1, respectively. This allows the corresponding semiconductor element 1 to conduct.

[0045] As shown in FIG. 2, the control unit 4 switches one semiconductor element 1 to be compared with the conduction ratio for each cycle CY of the generated triangular PWM carrier wave CW. For example, in an operating period Tz including three periods CYa, CYb, and CYc of a PWM carrier wave CW, semiconductor element 1a is the subject of control for its conduction state during the first period CYa, semiconductor element 1b is the subject of control for its conduction state during the second period CYb, and semiconductor element 1c is the subject of control for its conduction state during the third period CYc.

[0046] In a period CYa, the current I1 depends only on the semiconductor element 1a in the conductive state and is substantially unaffected by the semiconductor elements 1b and 1c in the non-conductive state. In a period CYb following the period CYa, the current I1 depends only on the semiconductor element 1b in the conductive state and is substantially unaffected by the semiconductor elements 1a and 1c in the non-conductive state. In a period CYc following the period CYb, the current I1 depends only on the semiconductor element 1c in the conductive state and is substantially unaffected by the semiconductor elements 1a and 1b in the non-conductive state.

[0047] In this manner, in this embodiment, the control unit 4 repeatedly switches the three semiconductor elements 1 between the conductive state and the non-conductive state, with three cycles of the PWM carrier wave CW being one operation period Tz.

[0048] As a result, in the power conversion device 100 of this embodiment, during a cycle CY in which one of the semiconductor elements 1 is conducting, there are no conducting elements among the remaining semiconductor elements 1. That is, in the power conversion device 100 of this embodiment, one semiconductor element 1 is conducting alone during one cycle CY.

[0049] For example, if the duty ratios of the semiconductor elements 1 are the same, the conduction periods (pulse widths of the gate command GC) Wa1, Wb1, and Wc1 of the parallel-connected semiconductor elements 1 can be made substantially the same length. As a result, in this embodiment, all of the parallel-connected semiconductor elements 1 share the same generated loss, and can equally share the required load.

[0050] The conduction ratio of the semiconductor device 1 changes depending on the magnitude of the command power CP. The pulse width of the gate command GC is controlled depending on the change in the conduction ratio. For example, if the conduction ratio becomes a lower value depending on the command power CP, the pulse width of the gate command GC becomes narrower. On the other hand, when the conduction ratio becomes higher according to the command power CP, as in the case of the conduction ratio DF2 in Fig. 2, the pulse widths Wa2, Wb2, and Wc2 of the gate commands GCa, GCb, and GCc become wider. In this case, the falling edge of a certain gate command (e.g., gate command GCa) may be aligned at substantially the same timing as the rising edge of another gate command (e.g., gate command GCb) adjacent in time.

[0051] The semiconductor device 1 operates at a response speed that includes a certain amount of delay in response to the rising and falling edges of the gate command GC. That is, the semiconductor device 1 effectively operates after a certain delay time has elapsed since receiving the rising edge of the gate command GC. The semiconductor device 1 also stops operating after a certain delay time has elapsed since receiving the falling edge of the gate command GC.

[0052] Therefore, even if the rising edge of one gate command GC is aligned with the falling edge of another gate command GC according to the set conduction ratio DF2, there is substantially no overlap between the effective conduction periods of the two semiconductor elements 1. In this way, in each operation period Tz, the semiconductor elements 1 operate independently of each other in mutually different cycles CY.

[0053] As described above, in this embodiment, the section in which each semiconductor element 1 bears a load is one-third of the operating period Tz. Therefore, even if the current I1 flows through one semiconductor element 1 in each cycle CY, the load applied to the semiconductor element 1 can be tolerated within the withstand voltage range of the semiconductor element 1 based on the rated value of the power conversion device 100.

[0054] (c) Summary When increasing the conversion capacity of a power conversion device by connecting multiple semiconductor elements in parallel to increase the current rating, it is desirable to match the dynamic characteristics of each semiconductor element, the characteristics of the gate driver, and the circuit impedance between circuits. If these match conditions are not met, the current flowing through multiple semiconductor elements operating simultaneously will not be shared equally, which can lead to problems such as heat concentration in certain semiconductor elements. This increases the risk of failure of the power conversion device.

[0055] In the product design of power conversion equipment, such uneven loads on each semiconductor element must be taken into consideration, and it becomes necessary to provide a margin for the current capacity of the semiconductor elements and / or the number of parallel connections from the perspective of derating. Alternatively, to match circuit impedance, it becomes necessary to optimize the design of the structural layout of the semiconductor elements and / or the connecting conductors. These requirements may conflict with the miniaturization and space-saving design of the device. As a result, the competitiveness of power conversion equipment products may decline overall.

[0056] According to this embodiment, in a circuit configuration in which a plurality of semiconductor elements 1 are connected in parallel, restrictions on hardware design related to the dynamic characteristics of each semiconductor element 1, the characteristics of the gate driver 2, and matching of circuit impedances are eliminated.

[0057] The power conversion device 100 of this embodiment includes a parallel-connected circuit in which a current I1 is shared by a plurality of semiconductor elements 1 that are set to a conductive state independently of each other. This allows the power conversion device 100 of this embodiment to equalize the load on each semiconductor element 1 even in a situation where hardware design is difficult, such as when the semiconductor elements 1 are arranged closely to each other.

[0058] As described above, the power conversion device 100 of this embodiment divides the period (e.g., the energization period) to be controlled equally for the multiple semiconductor elements 1a, 1b, and 1c connected in parallel in one current path under the control of the control unit 4. Then, the power conversion device 100 of this embodiment issues a conduction command to each of the semiconductor elements 1a, 1b, and 1c individually.

[0059] In this embodiment, since only one semiconductor element 1 is conductive during each cycle CY of a certain period Tz, the current I1 is uniquely determined without considering uneven characteristics among the multiple semiconductor elements 1 connected in parallel. Therefore, in the power conversion device 100 of this embodiment, the conduction periods and current I1 of all the semiconductor elements 1 connected in parallel are the same, and the generated losses are shared. Therefore, the power conversion device 100 of this embodiment can equally share the load generated among the multiple semiconductor elements 1 during the operating period Tz.

[0060] As described above, according to this embodiment, the above-mentioned restrictions on hardware design are eliminated, and simple control of the semiconductor elements 1 connected in parallel by software becomes possible.

[0061] As a result, the power conversion device of this embodiment can reduce restrictions on the hardware design of the power conversion device.

[0062] (2) Second embodiment A power conversion device according to the second embodiment will be described with reference to FIGS.

[0063] (a) Configuration example FIG. 3 is a circuit diagram showing an example of the configuration of the power conversion device 100 of this embodiment.

[0064] The power conversion device 100 shown in FIG. 3 includes a plurality of power conversion units 7 (7a, 7b, 7c).

[0065] For example, three power conversion units 7a, 7b, and 7c are provided in the power conversion device 100.

[0066] Power conversion unit 7a includes a semiconductor element 1a, a gate driver 2a, a control unit 4a, a voltage detection unit 5a, and a current detection unit 6a. Power conversion unit 7b includes a semiconductor element 1b, a gate driver 2b, a control unit 4b, a voltage detection unit 5b, and a current detection unit 6b. Power conversion unit 7c includes a semiconductor element 1c, a gate driver 2c, a control unit 4c, a voltage detection unit 5c, and a current detection unit 6c.

[0067] For example, in each power conversion unit 7, the current detection unit 6 is provided between the connection node ND2 and the semiconductor device 1. In the example of FIG. 3, the voltage detection unit 5 is connected to the connection node ND3 without going through the current detection unit 6.

[0068] The three power conversion units 7a, 7b, and 7c are commonly connected to one brake resistor section 3.

[0069] The power conversion device 100 of this embodiment corresponds to a dynamic braking circuit that controls the power consumption in the braking resistor section 3, similar to the above-described embodiments.

[0070] In the power conversion device 100 of this embodiment, each of the multiple semiconductor elements 1 is provided independently for each power conversion unit 7, and an individual control unit 4 is provided for each of the multiple semiconductor elements 1. Note that each power conversion unit 7 may include multiple semiconductor elements 1 connected in parallel.

[0071] Within each power conversion unit 7, each control unit 4 (4a, 4b, 4c) controls the operation of the corresponding semiconductor element 1 (1a, 1b, 1c) based on various information such as the detection results of the voltage detection unit 5 (5a, 5b, 5c), the detection results of the current detection unit 6 (6a, 6b, 6c), and the command power CP. Each of the plurality of control units 4 generates a PWM carrier wave CW (CWa, CWb, CWc). Each of the PWM carrier waves CWa, CWb, CWc includes a plurality of triangular waves with a certain period.

[0072] One of the multiple control units 4 generates a synchronization signal SS1 and transmits the generated synchronization signal SS1 to the other control units 4. For example, in this embodiment, the control unit 4a generates the synchronization signal SS1. The control unit 4a transmits the generated synchronization signal SS1 to the control units 4b and 4c. The control units 4b and 4c receive the synchronization signal SS1.

[0073] The synchronization signal SS1 is a signal for controlling the operation timing between the multiple power conversion units 7. For example, the synchronization signal SS1 is a square-shaped pulse signal having a rising edge and a falling edge. The carrier waves of each power conversion unit 7 are synchronized with the timing of the rising edge or falling edge of the synchronization signal SS1, and the phases of the carrier waves are aligned.

[0074] (b) Operation FIG. 4 is a waveform diagram showing an example of the operation of the power conversion device 100 of this embodiment. The waveform diagram of FIG. 4 shows a timing chart of switching of the plurality of semiconductor elements 1 in the plurality of power conversion units 7 of the power conversion device 100.

[0075] The timing chart of the switching of the semiconductor element 1 in Figure 4 shows the time progression of the PWM carrier waves CWa, CWb, CWc generated by each of the control units 4a, 4b, 4c in Figure 3, the gate commands GCa, GCb, GCc output from each control unit 4a, 4b, 4c to the semiconductor elements 1a, 1b, 1c, and the synchronization signal SS1.

[0076] In the power conversion device 100 of FIG. 3, the power conversion unit 7a obtains the voltage value of the voltage between the nodes ND1 and ND3 by the voltage detection unit 5a, and obtains the current value of the current I1 flowing through the brake resistor unit 3 by the current detection unit 6a.

[0077] The control unit 4a multiplies the acquired voltage value (value indicated by signal S1) by the current value (value indicated by signal S2) to calculate the power consumption of the power conversion device 100. The control unit 4a determines the conduction ratio DFa for the semiconductor element 1a using PI control or the like so that this power consumption matches the command power CP given to the control unit 4a from the external device 200. The control unit 4a compares the PWM carrier wave CWa with the conduction ratio DFa to generate a gate command GCa for the semiconductor element 1a.

[0078] Similarly, in power conversion unit 7b, control unit 4b calculates power consumption based on the voltage value acquired by voltage detection unit 5b and the current value acquired by current detection unit 6b. Control unit 4b determines a conduction ratio DFb for semiconductor device 1b based on the calculated power consumption and command power CP. Control unit 4b compares PWM carrier wave CWb with the conduction ratio DFb to generate gate command GCb for semiconductor device 1b.

[0079] In the power conversion unit 7c, the control unit 4c calculates the power consumption based on the voltage value acquired by the voltage detection unit 5c and the current value acquired by the current detection unit 6c. The control unit 4c determines the conduction ratio DFc for the semiconductor device 1c based on the calculated power consumption and the command power CP. The control unit 4c compares the PWM carrier wave CWc with the conduction ratio DFc to generate the gate command GCc for the semiconductor device 1c.

[0080] 4, for the PWM carrier wave CWa generated by the control unit 4a, the control unit 4a predetermines that only the cycle CYa within the operating period Tz is a cycle subject to conduction control of the semiconductor element 1a (control period). In the other cycles CYb and CYc within the period T1, the control unit 4a ignores the semiconductor element 1a as a control target and does not cause the semiconductor element 1a to be conductive.

[0081] Similarly, control unit 4b controls the conduction state of semiconductor element 1b only for period CYb of PWM carrier wave CWb, while control unit 4c controls the conduction state of semiconductor element 1c only for period CYc of PWM carrier wave CWc.

[0082] In this embodiment, since the control units 4a, 4b, and 4c belong to different power conversion units 7a, 7b, and 7c, it is assumed that the control units 4a, 4b, and 4c have different control processors. In this case, the phases of the PWM carrier waves CWa, CWb, and CWc generated independently by the control units 4a, 4b, and 4c do not necessarily match.

[0083] Therefore, in this embodiment, the control unit 4a is set as the master device, and the control units 4b and 4c are set as sub-devices. The control unit 4a of the power conversion unit 7a generates a pulse-like synchronization signal SS1, for example, at the start timing of the cycle CYa of the PWM carrier wave CW. The control unit 4a transmits the generated synchronization signal SS1 to the control units 4b and 4c in the other power conversion units 7b and 7c. In response to the received synchronization signal SS1, the control units 4b and 4c correct the phases of the corresponding PWM carrier waves CWb and CWc so that the first cycle CYa starts based on the timing of the synchronization signal SS1. For example, the multiple PWM carrier waves CWa, CWb, and CWc are controlled by the respective control units 4a, 4b, and 4c so that their phases are aligned at the timing of the rising edge of the synchronization signal SS1.

[0084] As a result, the power conversion device 100 of this embodiment can align the phases of the multiple PWM carrier waves CWa, CWb, and CWc at timing synchronized with the synchronization signal SS1.

[0085] The phases of the multiple PWM carrier waves CWa, CWb, and CWc may be aligned with the timing of the falling edge of the synchronization signal SS1.

[0086] As in the first embodiment, in this embodiment, the semiconductor elements 1 of each power conversion unit 7 are set to the conductive state at mutually different timings (cycles CY). That is, in a cycle CYa of the operating period Tz, only the semiconductor element 1a is set to the conductive state during a period corresponding to an "H" level gate command GCa from the control unit 4a. In a cycle CYb following the cycle CYa, only the semiconductor element 1b is set to the conductive state during a period corresponding to an "H" level gate command GCb from the control unit 4b. Furthermore, in a cycle CYc following the cycle CYb, only the semiconductor element 1c is set to the conductive state during a period corresponding to an "H" level gate command GCc from the control unit 4c.

[0087] As described above, in the power conversion device 100 of this embodiment, when the corresponding control units 4a, 4b, and 4c are independent processors for the multiple semiconductor elements 1a, 1b, and 1c connected in parallel to one current path (the path between the connection node ND1 and the earth 91), a common synchronization signal SS1 is supplied to the control units 4a, 4b, and 4c to align the phases of the PWM carrier waves CW. This allows the power conversion device 100 of this embodiment to synchronize the switching timings of the multiple semiconductor elements 1 controlled by different PWM carrier waves CW.

[0088] As a result, in this embodiment, as in the first embodiment, the current-carrying periods and currents I1 of all the parallel-connected semiconductor elements 1 are the same, and the generated losses are shared. Therefore, the multiple semiconductor elements 1 can equally share the load generated in the power conversion device 100.

[0089] Therefore, the power conversion device 100 of this embodiment eliminates hardware design constraints such as the dynamic characteristics of the parallel-connected semiconductor elements 1, the characteristics of the gate driver 2, and circuit impedance matching, and enables simple control of the parallel-connected semiconductor elements 1 by software.

[0090] As described above, the power conversion device 100 of this embodiment can reduce restrictions on the hardware design of the power conversion device.

[0091] (3) Modifications A modification of the power conversion device of the embodiment will be described with reference to FIGS.

[0092] FIG. 5 is a circuit diagram showing a modified example of the power conversion device of the second embodiment.

[0093] 5, the synchronization signal SS1x is supplied from the external device 200 to the power conversion device 100. In the power conversion device 100, a plurality of control units 4 receive the synchronization signal SS1x from the external device 200.

[0094] Similar to the examples of FIGS. 3 and 4, the multiple control units 4 correct the phases of the multiple PWM carrier waves based on the synchronization signal SS1x.

[0095] Even in this case, the power conversion device 100 of the modified example of FIG. 5 can achieve substantially the same operation as that described in the second embodiment.

[0096] FIG. 6 is a waveform diagram showing a modified example of the operation of the power conversion device 100. In FIG.

[0097] 6, the value of the conduction ratio DF3 may change during a certain operating period Tz. In this case, the value of the conduction ratio DF3 to be compared differs for each of the multiple semiconductor elements 1. As a result, the pulse widths Wa3, Wb3, and Wc3 of the multiple gate commands GCa, GCb, and GCc differ for each of the corresponding semiconductor elements 1a, 1b, and 1c.

[0098] For example, the value of the duty ratio DF3 in cycle CYa is higher than the values ​​of the duty ratio DF3 in cycles CYb and CYc. The value of the duty ratio DF3 in cycle CYb is lower than the value of the duty ratio DF3 in cycle CYa, but higher than the value of the duty ratio DF3 in cycle CYc. In this case, the pulse width Wa3 in cycle CYa is wider than the pulse widths Wb3 and Wc3 in cycles CYb and CYc. The pulse width Wa2 in cycle CYb is narrower than the pulse width Wa3 in cycle CYa, but wider than the pulse width Wc3 in cycle CYc.

[0099] 6, even if the pulse widths Wa3, Wb3, and Wc3 of the gate commands GCa, GCb, and GCc within the operation period Tz are different, the on and off switching of the multiple semiconductor elements 1 is controlled so that the semiconductor elements 1 are turned on at different timings. Thus, in this modification as well, the conduction periods of the multiple semiconductor elements 1 do not overlap within the operation period Tz.

[0100] Therefore, the power conversion device 100 of the modified example of FIG. 6 can obtain substantially the same effects as the power conversion device 100 of the above-described embodiment.

[0101] (4) Other The power conversion device 100 of the embodiment can be applied to, for example, railway vehicles, automobiles, ships, aircraft, power generation devices, etc. The power conversion device 100 of the embodiment may be provided in the same system as another power conversion device such as an AC inverter circuit.

[0102] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0103] 1a, 1b, 1c...semiconductor elements, 2a, 2b, 2c...gate drivers, 3...brake resistor section, 4, 4a, 4b, 4c...control section, 5, 5a, 5b, 5c...voltage detection section, 6, 6a, 6b, 6c...current detection section, 7a, 7b, 7c...power conversion unit, 9...DC power supply, 100...power conversion device, 200...external device

Claims

1. A brake resistor portion provided between a first node and a second node; a plurality of semiconductor elements provided between the brake resistor unit and the second node, each connected in series to the brake resistor unit and connected in parallel to each other between the brake resistor unit and the second node; a plurality of gate drivers corresponding to the plurality of semiconductor elements, respectively, and supplying drive voltages to the corresponding semiconductor elements; a control unit that supplies gate commands corresponding to the drive voltages to each of the plurality of gate drivers based on one carrier wave; Equipped with the plurality of semiconductor elements are set to a conductive state at mutually different timings in synchronization with a periodic waveform of the carrier wave during an operation period of the brake resistor unit, During each of the plurality of portions of the operation period, only one semiconductor element among the plurality of semiconductor elements that is set to a conductive state passes a current output from the brake resistor unit. Power conversion device.

2. When the number of the plurality of semiconductor elements is represented by N (where N is a natural number equal to or greater than 2), and the operation period is represented by T, The operating period is divided into N portions; The length of each of the N divided portions of the operating period is denoted by T / N. The power conversion device according to claim 1 .

3. The brake resistor unit receives regenerative power from a motor and outputs the current corresponding to the regenerative power. The power conversion device according to claim 1 or 2.

4. the plurality of semiconductor elements include a first semiconductor element, a second semiconductor element, and a third semiconductor element; the carrier wave includes a first period, a second period, and a third period in the operating period; In the first period, the first semiconductor element is set to a conductive state, the second and third semiconductor elements are set to a non-conductive state, and the first semiconductor element passes the current; In the second period, the second semiconductor element is set to a conductive state, the first and third semiconductor elements are set to a non-conductive state, and the second semiconductor element passes the current; In the third period, the third semiconductor element is set to a conductive state, the first and second semiconductor elements are set to a non-conductive state, and the third semiconductor element passes the current; a magnitude of a load on the first semiconductor element caused by the current, a magnitude of a load on the second semiconductor element caused by the current, and a magnitude of a load on the third semiconductor element caused by the current are equal; The power conversion device according to any one of claims 1 to 3.

5. A brake resistor portion provided between the first node and the second node; a plurality of power conversion units provided between the brake resistor unit and the second node, each connected in series to the brake resistor unit and connected in parallel to each other between the brake resistor unit and the second node; Equipped with Each of the plurality of power conversion units A semiconductor element; a gate driver that supplies a drive voltage to the semiconductor element; a control unit that supplies a gate command corresponding to the drive voltage to the gate driver based on a carrier wave; Including, the semiconductor elements are set to a conductive state at mutually different timings in synchronization with a periodic waveform of the carrier wave during an operation period of the brake resistor unit, During each of the plurality of portions of the operation period, only one of the semiconductor elements set to a conductive state passes a current output from the brake resistor unit. Power conversion device.

6. When the number of the plurality of power conversion units is represented by N (where N is a natural number equal to or greater than 2), and the operation period is represented by T, The operating period is divided into N portions; The length of each of the N divided portions of the operating period is denoted by T / N. The power conversion device according to claim 5 .

7. the control unit of one of the plurality of power conversion units generates a synchronization signal; the synchronization signal is supplied to each of the control units of the remaining power conversion units of the plurality of power conversion units; each of the control units of the remaining power conversion units aligns a phase of the carrier wave of the control unit of the remaining power conversion unit with a phase of the carrier wave of the control unit of the one power conversion unit based on the synchronization signal; The power conversion device according to claim 5 or 6.

8. the synchronization signal is a pulse wave having a rising edge and a falling edge, the phase of the carrier wave of each of the plurality of power conversion units is synchronized with either the rising edge or the falling edge; The power conversion device according to claim 7.

9. The brake resistor unit receives regenerative power from a motor and outputs the current corresponding to the regenerative power. The power conversion device according to any one of claims 5 to 8.

10. the plurality of power conversion units include a first power conversion unit, a second power conversion unit, and a third power conversion unit; During a first portion of the operating period, the semiconductor device of the first power conversion unit is set to a conductive state, and the semiconductor devices of the second power conversion unit and the third power conversion unit are set to a non-conductive state, and the semiconductor device of the first power conversion unit passes the current; During a second portion of the operating period, the semiconductor device of the second power conversion unit is set to a conductive state, and the semiconductor device of the first power conversion unit and the semiconductor device of the third power conversion unit are set to a non-conductive state, and the semiconductor device of the second power conversion unit passes the current; During a third portion of the operating period, the semiconductor device of the third power conversion unit is set to a conductive state, and the semiconductor devices of the first power conversion unit and the second power conversion unit are set to a non-conductive state, and the semiconductor devices of the third power conversion unit pass the current; a magnitude of a load on the semiconductor device of the first power conversion unit caused by the current, a magnitude of a load on the semiconductor device of the second power conversion unit caused by the current, and a magnitude of a load on the semiconductor device of the third power conversion unit caused by the current are equal; The power conversion device according to any one of claims 5 to 9.

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