Circuit board, semiconductor device, and method for manufacturing the semiconductor device

Abstract

To provide a circuit board configured to detect poor connection between a capacitor and a circuit board, a semiconductor device, and a method for manufacturing the semiconductor device.SOLUTION: In a wiring board frame 4, a plurality of wiring boards 40 are arranged side by side, each wiring board having lands 41a, 41b formed on a first surface 40s and electrically connected to a capacitor. The wiring board frame includes inspection wiring 42 formed on the first surface 40s of the wiring board 40, extended between the lands 41a, 41b in a direction that intersects with a line connecting the lands 41a, 41b, and having an inspection terminal at both ends. The inspection wiring 42 is formed so that the capacitors are arranged in series in a path where the capacitors are mounted on the lands 41a, 41b. The inspection wiring 42 has a cut CR between the lands 41a, 41b.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present embodiment relates to a circuit board, a semiconductor device, and a method for manufacturing a semiconductor device. [Background technology]

[0002] As a countermeasure against noise during high-speed operation, semiconductor devices have been proposed in which capacitors are mounted on wiring substrates together with semiconductor chips. However, there are problems with the physical connection between the capacitor and the wiring substrate, such as tombstoning and disconnection. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2020 / 0373306 [Patent Document 2] US Patent Application Publication No. 2005 / 0090041 [Patent Document 3] U.S. Patent No. 10,593,480 [Patent Document 4] U.S. Patent No. 8,912,802 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present embodiment is to provide a circuit board, a semiconductor device, and a method for manufacturing a semiconductor device that can efficiently detect poor connections between a capacitor and a circuit board. [Means for solving the problem]

[0005] The circuit board of this embodiment has a first surface and a second surface opposite to the first surface, and includes a plurality of wiring boards, each of which has a pair of electrodes formed on the first surface and electrically connected to a capacitor. The plurality of wiring boards are arranged with their respective first surfaces aligned on the same plane, and a plurality of wiring layers are stacked between the first surface and the second surface. An inspection wiring is formed between the pair of electrodes formed on the first surface of each of the wiring boards, extending in a direction intersecting a line connecting the pair of electrodes and having inspection terminals at both ends. The inspection wiring is formed so that the capacitor is arranged in series in the path of the inspection wiring when the capacitor is mounted on the pair of electrodes. The inspection wiring has a break between the pair of electrodes. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment; [Figure 2A] FIG. 1 is a schematic diagram illustrating an example of the arrangement of semiconductor chips and capacitors mounted on a wiring board, and is a top view of the wiring board on which the semiconductor chips and capacitors are arranged, viewed from above the first surface (positive side in the Z direction). [Figure 2B] 1 is a schematic diagram illustrating an example of the arrangement of semiconductor chips and capacitors mounted on a wiring board, and is a side view of the wiring board on which the semiconductor chips and capacitors are arranged, viewed from the positive side in the X direction. FIG. [Figure 3] FIG. 10 is a plan view illustrating an example of the arrangement of test wires on a wiring board. [Figure 4] 4 is an enlarged plan view of a rectangular area B enclosed by a dotted line in FIG. 3. FIG. [Figure 5] 10 is a plan view illustrating an example of a layout of inspection wiring in a wiring board frame. FIG. [Figure 6] 6 is a cross-sectional view taken along line CC' of the wiring board frame shown in FIG. 5. [Figure 7] 1A and 1B are diagrams illustrating an example of the configuration of a capacitor mounted on a semiconductor device according to an embodiment. [Figure 8]8A to 8C are diagrams illustrating a manufacturing process for the capacitor of FIG. 7. [Figure 9] FIG. 2 is a plan view illustrating the positional relationship between a capacitor and a wiring board. [Figure 10] 4 is a cross-sectional view illustrating the configuration of a joint between a capacitor and a wiring board. FIG. [Figure 11A] 1 is a flowchart illustrating an example of a manufacturing process of a semiconductor device according to an embodiment. [Figure 11B] 10 is a flowchart illustrating an example of a process for inspecting the physical connection state of a capacitor mounted on a wiring board frame. [Figure 12] 10 is a cross-sectional view illustrating another arrangement of the inspection wires in the wiring board frame. FIG. [Figure 13] 10 is a cross-sectional view illustrating another arrangement of the inspection wires and the inspection terminals in the wiring board frame. FIG. [Figure 14A] FIG. 10 is a schematic diagram illustrating another example of the arrangement of semiconductor chips and capacitors mounted on a wiring board, and is a top view of the wiring board on which the semiconductor chips and capacitors are arranged, viewed from above the first surface (positive side in the Z direction). [Figure 14B] FIG. 10 is a schematic diagram illustrating another example of the arrangement of semiconductor chips and capacitors mounted on a wiring board, and is a side view of the wiring board on which the semiconductor chips and capacitors are arranged, viewed from the positive side in the X direction. [Figure 15] FIG. 10 is a plan view illustrating another example of the arrangement of test wires on a wiring board. [Figure 16] FIG. 10 is a plan view illustrating another example of the layout of the inspection wires in the wiring board frame. [Figure 17] 10 is a cross-sectional view illustrating another configuration of the joint portion between the capacitor and the wiring board. FIG. [Figure 18] FIG. 10 is a cross-sectional view illustrating yet another configuration of the joint portion between the capacitor and the wiring board. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment will be described with reference to the drawings.

[0008] In the following description, an XYZ coordinate system, which is an example of a Cartesian coordinate system, is used. That is, a plane parallel to the surface of wiring substrate 40 constituting semiconductor device 100 is defined as the XY plane, and a direction perpendicular to the XY plane is defined as the Z axis. The X axis and Y axis are defined as two perpendicular directions within the XY plane. Note that, for convenience of explanation, the up-down direction of the wiring substrate will be described below using a relative up-down relationship in which the positive Z axis side (the surface on which the semiconductor chip is provided) is the upper side, but this does not represent an up-down relationship according to the vertical direction.

[0009] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment. Note that FIG. 1 is a schematic diagram illustrating the cross-sectional structure of the semiconductor device according to the embodiment, and the ratios between components are different from the actual ratios. The semiconductor device 100 according to the embodiment is a semiconductor package formed by, for example, sealing components such as a semiconductor chip and a capacitor mounted on a wiring substrate with a molding resin. The semiconductor device 100 includes a controller chip 20 as a semiconductor chip, a capacitor 30, a wiring substrate 40, solder balls 50, and a molding resin 60. The molding resin 60 is an example of a sealing resin. The semiconductor device 100 also includes a NAND flash memory chip (hereinafter referred to as a memory chip) as a semiconductor chip on the positive side of the controller chip 20 in the Y direction (the back side of the paper).

[0010] The wiring substrate 40 is, for example, an insulating resin wiring substrate or a ceramic wiring substrate having a wiring layer provided on or inside thereof. The wiring substrate 40 has a first surface 40s and a second surface 40b. The controller chip 20, the capacitor 30, and the memory chip 10 are provided on the first surface 40s. The second surface 40b has solder balls 50 formed as external terminals for a BGA package. The solder balls 50 are an example of terminals for connecting to external devices. The wiring substrate 40 has multiple stacked wiring layers, and an inspection wiring 42 is formed on the topmost wiring layer. The inspection wiring 42 is used to inspect the physical connection state between the capacitor 30 and the wiring substrate 40, and is formed to cross under the capacitor 30.

[0011] 2A and 2B are diagrams illustrating an example of the arrangement of semiconductor chips and capacitors mounted on a wiring substrate. Fig. 2A is a top view of the wiring substrate on which the semiconductor chips and capacitors are arranged, viewed from above the first surface (positive side in the Z direction). Fig. 2B is a side view of the wiring substrate on which the semiconductor chips and capacitors are arranged, viewed from the positive side in the X direction. Note that Fig. 1 shows a cross section of the semiconductor device 100 taken at the position indicated by A-A' in Fig. 2A.

[0012] As shown in FIG. 2A , a memory chip 10, a controller chip 20, and a capacitor 30 are mounted on a wiring substrate 40. The memory chips 10 are thin plates having a rectangular planar shape. The memory chips 10 are arranged on a first surface 40s of the wiring substrate 40 so that the thickness direction of the thin plate is parallel to the Z direction and the long sides are parallel to the X direction. More specifically, the memory chips 10 are arranged so that the distance between one side of the memory chip 10 on the positive side in the X direction and one side of the wiring substrate 40 on the positive side in the X direction is approximately equal to the distance between one side of the memory chip 10 on the negative side in the X direction and one side of the wiring substrate 40 on the negative side in the X direction, and the distance between one side of the memory chip 10 on the negative side in the Y direction and one side of the wiring substrate 40 on the negative side in the Y direction is greater than the distance between one side of the memory chip 10 on the positive side in the Y direction and one side of the wiring substrate 40 on the positive side in the Y direction. The memory chips 10 are arranged stacked in the Z direction. For example, as shown in Figure 2B, two memory chips 10 arranged adjacent to each other in the Z direction are arranged offset by a predetermined distance in the Y direction. That is, each memory chip 10 is arranged so that a portion of the top surface thereof is not covered by the other memory chips 10. Note that although four memory chips 10 are stacked in Figures 2A and 2B, the number of stacked memory chips 10 is not particularly limited.

[0013] The controller chip 20 is a thin plate having a rectangular planar shape. The controller chip 20 is disposed on the first surface 40s of the wiring substrate 40 so that the thickness direction of the thin plate is parallel to the Z direction and the long sides are parallel to the X direction. More specifically, the controller chip 20 is disposed on the negative side of the Y direction relative to the memory chip 10 so as not to overlap with the memory chip 10 in the Z direction. That is, the controller chip 20 is disposed so that one side of the controller chip 20 on the positive side in the Y direction is located a predetermined distance away from one side of the memory chip 10 on the negative side in the Y direction. The controller chip 20 is disposed approximately in the center of the wiring substrate 40 in the X direction. The length of the short sides of the controller chip 20 is shorter than the length of the short sides of the memory chip 10.

[0014] The multiple capacitors 30 have a rectangular parallelepiped shape. The multiple capacitors 30 are arranged on the first surface 40s of the wiring substrate 40 so that the bottom surfaces of the individual capacitors 30 face the first surface 40s. In the example shown in FIG. 2A , the multiple capacitors 30 are arranged in the spaces on the negative and positive X-direction sides of the controller chip 20. Each capacitor 30 is arranged at a predetermined distance from adjacent components so as not to overlap with other capacitors 30, the controller chip 20, or the memory chip 10 in the Z direction. The capacitors 30 arranged on the negative X-direction side of the controller chip 20 are arranged so that the long sides of their bottom surfaces are parallel to the Y-direction, while the capacitors 30 arranged on the positive X-direction side of the controller chip 20 are arranged so that the long sides of their bottom surfaces are parallel to the X-direction. As shown in FIGS. 2A and 2B , the multiple capacitors 30 arranged on the positive X-direction side of the controller chip 20 are arranged at the same position in the X-direction and at a predetermined interval in the Y-direction. Note that FIG. 2A shows an example in which three capacitors 30 are arranged, but the number of capacitors 30 is not particularly limited. External electrodes 32 are formed on a pair of surfaces (hereinafter referred to as end surfaces) of the capacitor 30 that are perpendicular to the bottom surface and face each other in the long side direction of the bottom surface. The external electrodes 32 extend from the end surfaces and are also formed on parts of the bottom surface and top surface.

[0015] The wiring layer of the wiring board 40 is provided with inspection wiring 42 for inspecting the physical connection state between the capacitor 30 and the wiring board 40. FIG. 3 is a plan view illustrating an example of the arrangement of inspection wiring on a wiring board. FIG. 3 shows the arrangement of inspection wiring on a wiring board in which semiconductor chips and capacitors are arranged as shown in FIGS. 2A and 2B. Note that terminals for electrically connecting the memory chip 10 and the controller chip 20 to the wiring board 40 are also provided on the first surface 40s of the wiring board 40, but FIG. 3 only shows the terminals 41 for electrically connecting the capacitor 30 to the wiring board 40 and the inspection wiring 42, and does not show other wiring and terminals.

[0016] Terminals 41_1, 41_2, and 41_3 for connecting the capacitor 30 to the wiring substrate 40 are formed on the first surface 40s of the wiring substrate 40. Hereinafter, when there is no need to distinguish between the terminals 41_1, 41_2, and 41_3, they will simply be referred to as terminals 41. Since one capacitor 30 has two external electrodes 32, a positive terminal and a negative terminal, the terminal 41 has two rectangular lands 41a and 41b corresponding to the respective external electrodes 32. The lands 41a and 41b are an example of a pair of electrodes electrically connected to the capacitor 30. The lands 41a and 41b are formed on the first surface 40s at positions where the external electrodes 32 of the capacitor 30 will be located. The lands 41a and 41b are spaced apart along the long side of the bottom surface of the capacitor 30 located above. In other words, the lands 41a and 41b are electrically and physically disconnected before the capacitor 30 is mounted. When the capacitor 30 is mounted on the wiring board 40 and the two external electrodes 32 are connected to the lands 41a and 41b, respectively, the lands 41a and 41b are electrically connected via the capacitor 30.

[0017] An inspection wiring 42 is also formed on the first surface 40s of the wiring board 40. The inspection wiring 42 is provided to inspect the physical connection state between the capacitor 30 and the wiring board 40 and detect any connection defects. The inspection wiring 42 is formed by extending between the land 41a and the land 41b in a direction perpendicular to the direction in which the lands 41a and 41b are arranged (a direction parallel to the long side of the bottom surface of the capacitor 30 installed above the lands 41a and 41b). For example, in FIG. 3, the lands 41a and 41b constituting the terminal 41_1 at the lower left corner of the first surface 40s are arranged side by side in the Y direction. Therefore, the inspection wiring 42 is formed by extending in the X direction between these lands 41a and 41b. Also, for example, in FIG. 3, two terminals 41_2 and 41_3 are arranged at the lower right corner of the first surface 40s. The lands 41a and 41b of the terminal 41_2 are arranged side by side in the X direction, and the inspection wiring 42 is formed between the lands 41a and 41b and extends in the Y direction. The lands 41a and 41b of the terminal 41_3 are also arranged side by side in the X direction, and the inspection wiring 42 is formed between the lands 41a and 41b and extends in the Y direction.

[0018] FIG. 4 is an enlarged plan view of a rectangular region B surrounded by a dotted line in FIG. 3. The rectangular region B is a diagram illustrating the positional relationship between the lands 41a and 41b and the inspection wiring 42. The inspection wiring 42 is physically disconnected in the region between the lands 41a and 41b. The inspection wiring 42 has terminal portions 42a and 42b and an inter-terminal connection portion 42c. The terminal portions 42a and 42b are partial wirings of the inspection wiring 42 formed in the region between the lands 41a and 41b. The widths of the terminal portions 42a and 42b are narrower than the separation distance between the lands 41a and 41b, and the inspection wiring 42 is disposed at a distance from the lands 41a and 41b. In FIG. 4, the inspection wiring 42 is formed at a distance D2 from each of the lands 41a and 41b. One end of terminal portion 42a faces one end of terminal portion 42b across a cut portion CR. Cut portion CR is an example of a disconnection portion. The length of cut portion CR, i.e., the distance between the end of terminal portion 42a and the end of terminal portion 42b, is set to distance D1. How distances D1 and D2 are determined will be explained in detail later. The other end of terminal portion 42a is connected to one end of inter-terminal connection portion 42c. The other end of terminal portion 42b is connected to one end of another inter-terminal connection portion 42c.

[0019] The inter-terminal connection portions 42c are classified into the following two groups: The first group has one end connected to the terminal portion 42a (or terminal portion 42b) and the other end located on the periphery of the wiring board 40. The second group has one end connected to the terminal portion 42a (or terminal portion 42b) and the other end connected to a terminal portion 42b (or terminal portion 42a) that is different from the terminal portion 42b (or terminal portion 42a) that faces the terminal portion 42a (or terminal portion 42b) across the cut portion CR.

[0020] For example, in FIG. 3, an inspection wiring 42 is formed extending in the X direction between lands 41a and 41b constituting terminal 41_1 located at the lower left of first surface 40s. This inspection wiring 42 is cut in the region between land 41a and land 41b. A terminal portion 42a is formed on the negative side of cut portion CR in the X direction, and a terminal portion 42b is formed on the positive side of cut portion CR in the X direction. One end of terminal portion 42a faces one end of terminal portion 42b across cut portion CR. The other end of terminal portion 42a is connected to one end of inter-terminal connection portion 42c. This inter-terminal connection portion 42c extends in the negative side of the X direction and is formed linearly to the periphery of wiring substrate 40 (one side parallel to the Y direction that is located on the negative side of the X direction). In other words, this inter-terminal connection portion 42c belongs to the first group.

[0021] One end of the terminal portion 42b faces one end of the terminal portion 42a across the cut portion CR. The other end of the terminal portion 42b is connected to one end of a terminal connection portion 42c that is different from the terminal connection portion 42c described above. This terminal connection portion 42c extends to the positive side of the X direction and has a bent portion along the way. This terminal connection portion 42c changes its extending direction at the bent portion and extends toward the negative side of the Y direction beyond the bent portion, extending to the periphery of the wiring substrate 40 (one side parallel to the X direction that is located on the negative side of the Y direction). In other words, this terminal connection portion 42c also belongs to the first group. In this way, the terminal connection portion 42c may be formed linearly or may have a bent portion along the way.

[0022] 3, for example, an inspection wire 42 is formed extending in the Y direction between lands 41a and 41b constituting terminal 41_2 located at the lower right of first surface 40s. This inspection wire 42 is cut in the region between land 41a and land 41b. A terminal portion 42a is formed on the negative side of cut portion CR in the Y direction, and a terminal portion 42b is formed on the positive side of cut portion CR in the Y direction.

[0023] One end of the above-mentioned terminal portion 42b faces one end of the terminal portion 42a across the cut portion CR. The other end of the terminal portion 42b is connected to one end of an inter-terminal connection portion 42c that is different from the above-mentioned inter-terminal connection portion 42c. This inter-terminal connection portion 42c extends in the positive Y direction and is connected to one end of the terminal portion 42a formed between the lands 41a and 41b that constitute the terminal 41_3. In other words, this inter-terminal connection portion 42c belongs to the second group. Note that the inter-terminal connection portion 42c that belongs to the second group may also be formed linearly, like the inter-terminal connection portion 42c that belongs to the first group, or may have a bent portion along the way.

[0024] The number and positions of the inter-terminal connections 42c to be arranged vary depending on the number and positions of the capacitors 30 mounted on the wiring board 40. However, regardless of the number and positions of the capacitors 30, two or more inter-terminal connections 42c belonging to the first group are arranged on the wiring board 40.

[0025] The semiconductor device of the embodiment is manufactured using a multi-cavity wiring board (hereinafter referred to as a wiring board frame 4) in which a plurality of wiring boards 40 are arranged in a matrix. FIG. 5 is a plan view illustrating an example of a layout of test wiring in the wiring board frame. The wiring board frame 4 is an example of a circuit board. A plurality of wiring boards 40 are arranged in a matrix on one wiring board frame 4. For example, a total of 100 wiring boards 40 are arranged in five rows in the Y direction and twenty columns in the X direction. In the wiring board frame 4, each wiring board 40 is surrounded by a gap region 70. The gap region 70 is a region that is discarded when the semiconductor device is separated by dicing. Each wiring board 40 has terminals 41 connected to external electrodes 32 of capacitors 30 and test wiring 42 formed on a first surface 40s, excluding a region 410 where a memory chip is mounted and a region 420 where a controller chip is mounted. In gap region 70, inspection terminals 43 and inspection wiring 42 are formed on a surface (hereinafter referred to as first surface 70s) located on the same side as first surface 40s of wiring board 40. In the following description, in gap region 70, a surface located on the same side as second surface 40b of wiring board 40 will be referred to as second surface 70b. Furthermore, the surface of wiring board frame 4 that includes first surface 40s and first surface 70s will be referred to as first surface 4s, and the surface of wiring board frame 4 that includes second surface 40b and second surface 70b will be referred to as second surface 4b.

[0026] Inspection wiring 42 is formed on first surface 4s of wiring board frame 4 so as to form a single wiring without branches when terminal portions 42a, 42b facing each other across cut portion CR are electrically connected. Inspection wiring 42 is also formed so that terminals 41 mounted on each wiring board 40 are arranged in series along its path. Inspection wiring 42 is also formed so that all wiring boards 40 are arranged in series along its path. Inspection terminals 43 include inspection terminals 43a and inspection terminals 43b. Inspection terminals 43a are formed at both ends of inspection wiring 42 formed in series. Inspection terminals 43b are also formed midway along inspection wiring 42. Specifically, they are formed midway along the wiring connecting two inter-terminal connection portions 42c arranged on different wiring boards 40.

[0027] After mounting the capacitors 30 on each wiring board 40 of the wiring board frame 4, inspection is performed to check for physical connection defects between the wiring boards 40 and the capacitors 30. Specifically, the DC resistance value between the inspection terminals 43a formed on both ends of the inspection wires 42 is measured. An inspection electrode 33 is formed on the bottom surface of the capacitor 30 (the surface facing the first surface 40s of the wiring board 40). (The configuration of the capacitor 30 will be described in detail later.) When the capacitors 30 are connected to all of the terminals 41 formed on the first surface 40s of the wiring board 40, one end of the terminal portion 42a and one end of the terminal portion 42b formed between the lands 41a and 41b of the terminal 41 are electrically connected via the inspection electrode 33. If a physical connection defect occurs between the capacitor 30 and the terminal 41 due to tombstones, detachment, or the like, one end of the terminal portion 42a and one end of the terminal portion 42b are not electrically connected.

[0028] After mounting capacitors 30 on each wiring board 40 of the wiring board frame 4, the DC resistance value between the inspection terminals 43a formed on both ends of the inspection wiring 42 is measured, and if the DC resistance value is lower than a set threshold, it is determined that all of the capacitors 30 mounted on the wiring board frame 4 are physically connected to the wiring boards 40 (terminals 41 thereof). If the DC resistance value is equal to or greater than the set threshold, it is determined that a physical connection failure has occurred in one of the capacitors 30. Subsequently, by measuring the DC resistance value between any terminals using the inspection terminals 43b formed midway along the inspection wiring 42, it is possible to identify the wiring board 40 on which the capacitor 30 with the connection failure is mounted. Once the wiring board 40 has been identified, the capacitor 30 with the physical connection failure is detected, for example, by image inspection or the like.

[0029] A common method involves capturing an image of the first surface 4s of the wiring board frame 4 from above (or a transmission image using X-rays or the like) and detecting connection defects in the capacitors 30 using an image recognition program or visual inspection. However, image-based inspection methods, particularly visual inspection methods, have the problem of variations in results depending on the inspector. Furthermore, as the number of capacitors 30 mounted on the wiring board frame 4 increases, the inspection time increases, reducing inspection efficiency. Furthermore, when sampling inspection is performed, connection defects in uninspected locations cannot be detected. In contrast, the semiconductor device 100 of the embodiment can efficiently detect the presence or absence of physical connection defects in all of the capacitors 30 in a short time, regardless of the number of capacitors 30 mounted on the wiring board frame 4.

[0030] Next, the structure of the wiring board frame 4 will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view of the wiring board frame taken along line CC' shown in Fig. 5. The wiring board frame 4 has surface wiring layers L1 and L3 and an intermediate wiring layer L2.

[0031] The surface wiring layer L1 is a wiring layer formed on the first surface 4s, and has formed thereon terminals and wirings electrically connected to components mounted on the wiring board 40, such as terminals electrically connected to terminals (not shown) of the memory chip 10 and the controller chip 20, and terminals 41 electrically connected to the capacitor 30. The surface wiring layer L1 also has formed thereon inspection wirings 42 and inspection terminals 43. The inspection terminals 43 are formed only on the first surface 70s of the gap region 70. The inspection wirings 42 are formed on both the first surface 40s of the wiring board 40 and the first surface 70s of the gap region 70. Note that the inspection wirings 42 and the inspection terminals 43 are not electrically connected to other wirings and terminals in the surface wiring layer L1 (for example, wirings and terminals electrically connected to components mounted on the wiring board 40, such as terminals of the memory chip 10 and the controller chip 20, and terminals 41 of the capacitor 30). An intermediate wiring layer L2 is formed below the surface wiring layer L1 via a solder resist layer 46.

[0032] The intermediate wiring layer L2 is a multilayer wiring layer formed by laminating multiple wiring layers. Terminals and wiring (terminals and wiring electrically connected to components mounted on the wiring board 40) formed on the surface wiring layer L1 are electrically connected to wiring formed on the intermediate wiring layer L2 through vias 48. An insulating layer 45 or a core layer 44 is formed between the wirings (between adjacent wirings above and below) formed by lamination on the intermediate wiring layer L2. The core layer 44 is, for example, a hard plate-like member made of glass fiber and epoxy resin. Wiring formed on the upper and lower surfaces of the core layer 44 is electrically connected via one of multiple through-hole wirings 47. The through-hole wiring 47 is wiring embedded in a through-hole (through-hole) provided penetrating the core layer 44. Wiring formed on the upper and lower surfaces of the insulating layer 45 are electrically connected via vias 48. A surface wiring layer L3 is formed below the intermediate wiring layer L2 with a solder resist layer 46 interposed therebetween. 5 shows the wiring board frame 4 having the core layer 44, it is also possible to use a so-called coreless board frame that does not have the core layer 44. In this case, multiple wirings formed in the intermediate wiring layer L2 are stacked with an insulating layer 45 sandwiched between them, and the wirings are electrically connected to each other through vias 48.

[0033] The surface wiring layer L3 is a wiring layer formed on the second surface 4b, and has lands 49 formed thereon for connecting solder balls 50 as external terminals. The wires formed on the intermediate wiring layer L2 and the lands 49 are electrically connected through vias 48. With this configuration, the memory chip 10 and the controller chip 20 are electrically connected to the solder balls 50 through each portion of the wiring board 40. The inspection wires 42 and the inspection terminals 43 formed on the surface wiring layer L1 are not electrically connected to other wires and terminals (terminals and wires electrically connected to components mounted on the wiring board 40) formed on the surface wiring layer L1 through the intermediate wiring layer L2 and the surface wiring layer L3. They are also not electrically connected to the solder balls 50.

[0034] Components such as memory chip 10, controller chip 20, and capacitor 30 are mounted on each wiring board 40 of wiring board frame 4 configured in this manner, and these components are electrically connected to surface wiring layer L1 of wiring board 40. After each wiring board 40 is molded and solder balls 50 are connected to lands 49, the periphery of wiring board 40 is cut by dicing to separate semiconductor devices 100. Dicing separates wiring board 40 and gap region 70 along the thick line in FIG. 6 , and thereby separates portions of inspection wiring 42 formed in gap region 70 and inspection terminals 43 from semiconductor device 100. That is, one end of inter-terminal connection portion 42c located on the periphery of wiring board 40 shown in FIG. 3 is a cut end of inspection wiring 42 on the wiring board 40 side, generated by dicing. The cut end is an example of a termination portion.

[0035] Next, the structure of the capacitor 30 will be described. FIG. 7 is a diagram illustrating an example of the configuration of a capacitor mounted on the semiconductor device of the embodiment. The capacitor 30 of the embodiment is a so-called multilayer ceramic capacitor having a structure in which dielectric layers and internal electrodes are laminated in multiple layers. FIG. 7 shows a side view (upper view) and a bottom view (lower view) of the capacitor 30. The capacitor 30 includes a laminate 31, an external electrode 32, and an inspection electrode 33. The laminate 31 is a fired body having a laminate structure in which ceramic dielectric layers and internal electrode layers are alternately laminated. The laminate 31 has a rectangular parallelepiped shape and a rectangular bottom surface. The external electrode 32 is an external terminal that electrically connects the internal electrode layers of the laminate 31 to lands 41a and 41b formed on the wiring substrate 40. The external electrode 32 is formed on an end surface of the laminate 31. The external electrode 32 also extends from the end surface and is formed on a part of the bottom surface and top surface. For example, a copper (Cu) electrode is used as the external electrode 32. A nickel (Ni) / tin (Sn) plating layer is formed on the surface of the Cu electrode. The inspection electrode 33 is an electrode formed in the center of the bottom surface of the laminate 31, and has a rectangular surface. The inspection electrode 33 is formed between and spaced apart from two external electrodes 32 formed including opposing short sides of the bottom surface of the laminate 31. A length E1 of the inspection electrode 33 in a direction parallel to the short sides of the bottom surface of the laminate 31 is longer than a distance D1 (the distance between the opposing terminal portions 42a, 42b). Furthermore, a length E2 of the inspection electrode 33 in a direction parallel to the long sides of the bottom surface of the laminate 31 is longer than the width of the terminal portions 42a, 42b. As will be described later, the inspection electrode 33 is connected to the wiring board 40 via solder 61. When the capacitor 30 and the wiring board 40 are pressure-bonded, the solder 61 may protrude from the inspection electrode 33. Even in such a case, the length E2 of the inspection electrode 33 is sufficiently shorter than the distance between the lands 41a and 41b so that the lands 41a and 41b are not electrically connected via the solder 61. The inspection electrode 33 is formed of, for example, the same material as the external electrode 32.

[0036] Figure 8 is a diagram explaining the manufacturing process for the capacitor shown in Figure 7. First, fine powder of dielectric ceramic is mixed with a solvent, dispersant, binder, etc. to form a mud-like slurry, which is then thinly spread on a carrier film to form a dielectric green sheet. Next, these green sheets are screen-printed with internal electrode patterns, which are then stacked and pressure-bonded, and then cut into a large number of individual chip pieces, which are fired to form a ceramic laminate 31 (see FIG. 8(a)). Next, Cu electrodes 32a are applied and baked in areas on both end surfaces of the laminate 31 where external electrodes 32 will be formed, and in an area in the center of the bottom surface where an inspection electrode 33 will be formed (see FIG. 8(b)). Finally, Ni and Sn are layered in this order on the surface of the Cu electrode 32a by electrolytic plating to form the external electrodes 32 and the inspection electrode 33, completing the capacitor 30 to be mounted on the semiconductor device 100 of this embodiment (see FIG. 8(c)).

[0037] The bonding region between the capacitor 30 having the above-described structure and the wiring board 40 will be described with reference to FIGS. 9 and 10. FIG. 9 is a plan view illustrating the positional relationship between the capacitor and the wiring board. FIG. 9 shows an example of the positional relationship between components formed on the first surface 40s of the wiring board 40 and components formed on the bottom surface of the capacitor 30, and is a plan view of a rectangular region B on the first surface 40s of the wiring board 40, surrounded by a dotted line in FIG. 3. FIG. 10 is a cross-sectional view illustrating the configuration of the bonding portion between the capacitor and the wiring board. FIG. 10 is an example of a cross-section after the capacitor 30 has been bonded to the wiring board 40 with solder 61, and is a cross-sectional view taken along line D-D' in FIG. 9.

[0038] 9, when bonding to the wiring board 40, the position of the capacitor 30 is determined so that, in a direction parallel to the long sides of the bottom surface of the capacitor 30 (X direction in FIG. 9), the lower surfaces of the two external electrodes 32 are included in the surfaces of the lands 41a and 41b, one side of the inspection electrode 33 facing the land 41a is located on the first surface 40s between the land 41a and the inspection wiring 42, and one side of the inspection electrode 33 facing the land 41b is located on the first surface 40s between the inspection wiring 42 and the land 41b. Furthermore, when bonding to the wiring board 40, the position of the capacitor 30 is determined so that, in a direction parallel to the short sides of the bottom surface of the capacitor 30 (Y direction in FIG. 9), the lower surfaces of the two external electrodes 32 are included in the surfaces of the lands 41a and 41b, one side of the inspection electrode 33 crosses the terminal portion 42a, and the opposing side of the inspection electrode 33 crosses the terminal portion 42b.

[0039] That is, the two external electrodes 32 are arranged so as to be physically and electrically connected to the lands 41a and 41b, but not physically or electrically connected to the terminal portions 42a and 42b, respectively. The testing electrode 33 is arranged so as to be physically and electrically connected to the terminal portions 42a and 42b, but not physically or electrically connected to the lands 41a and 41b.

[0040] When mounting the capacitor 30 on the wiring board 40, misalignment may occur within the plane of the first surface 40s. The distance D1 between the terminals 42a and 42b is set so that the testing electrode 33 is positioned across both the terminals 42a and 42b even if the capacitor 30 is misaligned in a direction parallel to the short side of the bottom surface. For example, the distance D1 is set to less than half the width of the lands 41a and 41b in a direction parallel to the short side of the bottom surface of the capacitor 30. Furthermore, the terminals 42a and 42b may be formed with errors due to processing accuracy relative to their designed shapes. The distance D1 is set so that even if the terminals 42a and 42b are formed longer than their designed shapes, one end of the terminal 42a and one end of the terminal 42b do not come into contact with each other, preventing unintended electrical connection. For example, the distance D1 is set to 50 μm or more.

[0041] Furthermore, the distance D2 between the inspection wiring 42 and the lands 41a and 41b is set so that the inspection electrode 33 does not come into contact with the lands 41a and 41b even if the capacitor 30 is misaligned in a direction perpendicular to the short side of the bottom surface (the X direction in Figure 9).

[0042] As shown in Figure 9, once the positions of the external electrodes 32 on the bottom surface of the capacitor 30 and the testing electrodes 33 are determined on the first surface 40s of the wiring board 40, a mask material (e.g., a screen printing plate) with openings at the determined bonding positions is placed over the first surface 40s of the wiring board 40, and paste-like cream solder is applied onto the mask material. Next, pressure is applied using a squeegee or similar device to push the cream solder out of the openings and print (apply) it onto the first surface 40s exposed through the openings in the mask material. The mask material is then removed, and the capacitor 30 is placed on the cream solder and mounted using a reflow method. Because the cream solder is conductive, the external electrodes 32 of the capacitor 30 are electrically connected to the lands 41a and 41b of the wiring board 40.

[0043] As shown in FIG. 10 , the external electrodes 32 of the capacitor 30 are connected to the surfaces of the lands 41a and 41b formed on the first surface 40s of the wiring board 40 via solder 61 (cream solder melted and solidified by reflow processing). The solder 61 is formed in a fillet shape between the bottom surface of the external electrode 32 and the lands 41a and 41b, and from the surfaces of the lands 41a and 41b along the end surfaces of the capacitor 30 to a predetermined height. This physically and electrically connects one external electrode 32 to the land 41a, and physically and electrically connects the other external electrode 32 to the land 41b. The solder 61 is also formed between the testing electrode 33 formed on the bottom surface of the capacitor 30 and the terminal portion 42a, physically and electrically connecting the testing electrode 33 to the terminal portion 42a. Furthermore, the solder 61 formed on the surface of the testing electrode 33 physically and electrically connects the terminal portion 42b, which is disposed in the depth direction of the drawing, to the testing electrode 33.

[0044] That is, when the capacitor 30 is connected to the terminal 41 via the solder 61, the terminals 42a and 42b, which are arranged opposite each other in a direction perpendicular to the long side of the bottom surface of the capacitor 30, are electrically connected via the solder 61 and the testing electrode 33. On the other hand, if tombstoning or falling off occurs due to heating or stress during the manufacturing process of the semiconductor device 100, causing a physical connection failure between the capacitor 30 and the terminal 41, the testing electrode 33 and the terminal 42a and / or the testing electrode 33 and the terminal 42b will no longer be physically connected. Therefore, if a physical connection failure occurs between the capacitor 30 and the terminal 41, one end of the terminal 42a and one end of the terminal 42b will no longer be electrically connected.

[0045] As described above, according to this embodiment, the inspection electrodes 33 are provided between the external electrodes 32 on the bottom surfaces of the capacitors 30. Furthermore, the inspection wiring 42 is provided on the first surface 4s of the wiring board frame 4. The inspection wiring 42 is arranged so that, when all of the capacitors 30 mounted on each wiring board 40 are physically connected to the wiring board 40, the inspection electrodes 33 formed on each capacitor 30 are connected in series in a daisy chain manner. With this configuration, by measuring the resistance value between the inspection terminals 43a provided at both ends of the inspection wiring 42, it is possible to collectively detect the presence or absence of connection defects (failures in physical connection to the wiring board 40) for the capacitors 30 mounted on all of the wiring boards 40 provided on the wiring board frame 4. Therefore, connection defects between the capacitors and the wiring boards can be efficiently detected.

[0046] Furthermore, not only the external electrodes 32 and the lands 41a, 41b but also the testing electrodes 33 and the testing wiring 42 are physically connected by the solder 61, which increases the connection strength between the capacitors 30 and the wiring board 40 and prevents the capacitors 30 from falling off the wiring board 40. This also has the effect of improving the yield of the semiconductor device.

[0047] Next, a method for manufacturing the semiconductor device 100 of the embodiment will be described. Fig. 11A is a flowchart illustrating an example of a manufacturing process of the semiconductor device of the embodiment. First, capacitors 30 are soldered to all terminals 41 of a wiring board 40 formed on a wiring board frame 4 to physically connect the wiring board 40 and the capacitors 30, and external electrodes 32 of the capacitors 30 are electrically connected to the surface wiring layer L1 of the wiring board 40 (S1). When a semiconductor device is manufactured using a wiring board frame 4 on which capacitors 30 are mounted, S1 is omitted.

[0048] Next, for all of the wiring boards 40 formed on the wiring board frame 4, the backsides of the memory chips 10 are bonded to the region 410 on the first surface 40s, and the backsides of the controller chips 20 are bonded to the region 420 on the first surface 40s (S2). S2 is a process known as die bonding. The region 410 on the first surface 40s of the wiring board 40 and the backsides of the memory chips 10, and the region 420 and the backsides of the controller chips 20 are bonded using a non-conductive adhesive such as a die attach film (DAF). Furthermore, when multiple memory chips 10 are stacked as shown in FIG. 1A, the DAF is also used to bond adjacent memory chips 10 vertically.

[0049] Next, the wiring board frame 4 is heated in an oven to harden the adhesive (S3). Furthermore, the terminals of the memory chip 10 and the controller chip 20 are connected to the terminals of the surface wiring layer L1 of the wiring board 40 using metal wires such as gold (Au) (S4). S4 is a process known as wire bonding.

[0050] Next, the wiring board frame 4 is sealed with resin (S5). S5 is a process known as molding. In S5, the resin sealing of the multiple wiring boards 40 formed on the wiring board frame 4 is performed all at once. Next, solder balls 50, which are external terminals, are bonded to lands 49 formed on the surface wiring layer L3 of the wiring board frame 4 using a conductive adhesive such as solder paste (S6). Next, the wiring board frame 4 is heated by a reflow process to firmly bond the lands 49 and the solder balls 50 to each other (S7). Finally, the wiring board 40 is cut between the gap regions 70 and the gap regions 70 to separate the semiconductor devices 100 (S8). S8 is a process known as dicing. By performing the above steps, the semiconductor device 100 of the embodiment is manufactured. After the capacitors 30 are mounted on the wiring board frame 4, DC resistance can be measured using the inspection terminals 43 formed in the gap regions 70 of the wiring board frame 4 until the wiring board frame 4 is diced.

[0051] 11B is a flowchart illustrating an example of a process for inspecting the physical connection state of capacitors 30 mounted on wiring board frame 4. First, the DC resistance value between inspection terminals 43a formed on both ends of inspection wire 42 is measured (S11). If the DC resistance value is lower than a set threshold value (S12, YES), it is determined that all capacitors 30 mounted on wiring board frame 4 are physically connected to wiring board 40 (S13), and the inspection ends.

[0052] On the other hand, if the DC resistance value is equal to or greater than the set threshold value (S12, NO), it is determined that a physical connection failure has occurred in one of the capacitors 30 (S14). In addition to inspection terminal 43a, inspection terminal 43b formed midway along inspection wiring 42 is also used to measure the DC resistance value between any of the terminals (S15). If the DC resistance value is lower than the set threshold value (S16, YES), it is determined that capacitors 30 on wiring board 40 located between the terminals used in the measurement of S15 are physically connected to wiring board 40 (S18). In order to detect a capacitor with a connection failure, inspection terminals 43a and 43b to be measured are changed (S19), and the process returns to S15 to measure the DC resistance value between the terminals. On the other hand, if the DC resistance value is equal to or greater than the set threshold value (S16, NO), it is determined that a physical connection failure has occurred among capacitors 30 on wiring board 40 located between the terminals used in the measurement of S15 (S17), and the inspection ends. If it is desired to further narrow down the wiring boards 40 on which the capacitors 30 having the physical connection failure are mounted, the process returns to S19, changes the test terminals 43a and 43b to be measured, and continues the test.

[0053] Thus, according to the semiconductor device of the embodiment, in the above-mentioned manufacturing process, it is possible to efficiently detect a physical connection failure between the capacitor 30 and the wiring board 40 at any timing between the execution of S1 and the execution of S8.

[0054] For example, an inspection is performed between S1 and S2. If a capacitor 30 is found to have a connection defect, its location (on which wiring board 40 it is mounted) is identified. In the steps after S2, components such as memory chips 10 and controller chips 20 are not mounted on wiring boards 40 with connection defects with capacitors 30. This reduces the number of memory chips 10 and controller chips 20 used, leading to cost savings. Furthermore, for example, an inspection is performed between S7 and S8. This allows detection of connection defects (tombstoning, detachment, etc.) in capacitors 30 caused by stress due to thermal history applied to the product in the steps up to S7. If a connection defect occurs, it is possible to identify which wiring board 40 the connection defect occurs on. After the semiconductor devices are singulated in S8, semiconductor devices with connection defects can be eliminated. This allows the number of semiconductor devices to be tested to be narrowed down, resulting in cost reduction and test time reduction.

[0055] In the semiconductor device described above, the inspection wiring 42 is formed only on the surface wiring layer L1 of the wiring board frame 4. However, the terminals 42a and 42b may be formed on the intermediate wiring layer L2. FIG. 12 is a cross-sectional view illustrating another arrangement of the inspection wiring in the wiring board frame. As shown in FIG. 12, for example, the inter-terminal connection portion 42c may be formed on the uppermost layer of the intermediate wiring layer L2 and electrically connected to the terminals 42a and 42b and the inspection terminals 43 formed on the surface wiring layer L1 through vias 48. As shown in FIG. 12, the inter-terminal connection portion 42c may be formed across the surface wiring layer L1 and the intermediate wiring layer L2, or may be formed only on the intermediate wiring layer L2. Furthermore, the inter-terminal connection portion 42c may be formed on a layer other than the uppermost layer of the intermediate wiring layer L2 or across multiple layers. In this way, forming at least a portion of the inter-terminal connection portion 42c on the intermediate wiring layer L2 increases the flexibility of the wiring design. Therefore, even when the space for forming the inspection wiring 42 on the first surface 40s of the wiring board 40 is limited, the inspection wiring 42 can be reliably arranged.

[0056] Furthermore, in the semiconductor device described above, inspection terminals 43 are formed on surface wiring layer L1 of wiring board frame 4, but they may also be formed on surface wiring layer L3. FIG. 13 is a cross-sectional view illustrating another arrangement of inspection wiring and inspection terminals in the wiring board frame. As shown in FIG. 13, inspection terminals 43 may be formed on surface wiring layer L3 and electrically connected to inter-terminal connection portions 42c formed on surface wiring layer L1 via through-hole wiring 471. In this manner, by forming inspection terminals 43 on surface wiring layer L3 and exposing them from second surface 4b of wiring board frame 4, it is possible to reliably inspect for poor connections between capacitors 30 and wiring board 40 even after first surface 40s of wiring board 40 is covered with mold resin 60. Note that even when inspection terminals 43 are formed on surface wiring layer L3, some or all of inter-terminal connection portions 42c may be formed on intermediate wiring layer L2, as described above.

[0057] Furthermore, the number of memory chips 10 and capacitors 30 mounted on the wiring substrate 40 and the arrangement of the memory chips 10, controller chip 20, and capacitor 30 on the first surface 40s are not limited to the numbers and arrangements shown in FIGS. 2A and 2B. FIGS. 14A and 14B are diagrams illustrating another example of the arrangement of semiconductor chips and capacitors mounted on a wiring substrate. FIG. 14A is a top view of the wiring substrate on which the semiconductor chips and capacitors are arranged, viewed from above the first surface (positive side in the Z direction). FIG. 14B is a side view of the wiring substrate on which the semiconductor chips and capacitors are arranged, viewed from the positive side in the X direction. In FIGS. 2A and 2B, a memory chip group in which four memory chips 10 are stacked while being slightly shifted from each other is arranged on the positive side in the Y direction of the controller chip 20, and two capacitors 30 are arranged on the positive side in the X direction of the controller chip 20, and one capacitor 30 is arranged on the negative side in the X direction. 14A and 14B, a group of memory chips, each of which is formed by stacking four memory chips 10 while slightly shifting each other, is disposed on the positive side and negative side of the Y direction of the controller chip 20, and one capacitor 30 is disposed on each of the positive side and negative side of the X direction of the controller chip 20. In this manner, the capacitors 30 may be disposed in any free space not occupied by the memory chips 10 or the controller chip 20, and their positions on the wiring board 40 can be freely designed. Furthermore, any number of capacitors 30 can be mounted depending on the area of ​​the free space available for installation on the first surface 40s of the wiring board 40 and the capacitance required for operation of the semiconductor device 100.

[0058] FIG. 15 is a plan view illustrating another example of the arrangement of test wiring on a wiring board. FIG. 15 shows the arrangement of test wiring on a wiring board on which semiconductor chips and capacitors are arranged as shown in FIGS. 14A and 14B. As shown in FIG. 15, two pairs of lands 41a and 41b for connecting capacitor 30 to wiring board 40 are formed on first surface 40s of wiring board 40. Lands 41a and 41b are formed on first surface 40s at positions where external electrodes 32 of capacitor 30 are to be placed. Lands 41a and 41b are spaced apart and arranged along the long side of the bottom surface of capacitor 30 placed above. Test wiring 42 is formed by extending between land 41a and land 41b in a direction perpendicular to the direction in which lands 41a and 41b are arranged (a direction parallel to the long side of the bottom surface of capacitor 30 placed above lands 41a and 41b). The inspection wiring 42 is physically cut in the region between the land 41a and the land 41b, forming a cut portion CR.

[0059] Fig. 16 is a plan view illustrating another example of the layout of the test wiring in the wiring board frame. Fig. 16 shows a multi-cavity wiring board frame 4 in which the wiring boards 40 shown in Fig. 15 are arranged in a matrix. Even if the positions and number of capacitors 30 mounted on the wiring board 40 are different, the test wiring 42 can be formed so that it becomes a single wire without branches when the opposing terminal portions 42a, 42b are electrically connected via the cut portion CR on the first surface 4s of the wiring board frame 4.

[0060] Furthermore, in the semiconductor device 100 described above, the inspection electrode 33 is formed on the bottom surface of the capacitor 30 using the same material as the external electrode 32 as a component for electrically connecting the terminal portion 42a and the terminal portion 42b, and the terminal portions 42a, 42b and the first surface 40s are connected using solder 61. However, any adhesive other than the solder 61 may be used as long as it is a conductive material. FIG. 17 is a cross-sectional view illustrating another configuration of the joint between the capacitor and the wiring board. In the configuration shown in FIG. 17, the inspection electrode 33 formed on the bottom surface of the capacitor 30 is connected to the terminal portions 42a, 42b and the first surface 40s using an anisotropic conductive film (ACF) 62. The anisotropic conductive film 62 is less likely to deform when heat or pressure is applied than the solder 61. Therefore, even if pressure or heat is applied after the capacitor 30 is bonded to the wiring board 40, the anisotropic conductive film 62 and the land 41a, and the anisotropic conductive film 62 and the land 41b can be kept separated from each other, and the lands 41a and 41b can be more reliably prevented from being electrically connected to each other. The testing electrode 33 and the anisotropic conductive film 62 are examples of testing conductors.

[0061] Fig. 18 is a cross-sectional view illustrating yet another configuration of the joint between a capacitor and a wiring board. In the configuration shown in Fig. 18, capacitor 30 does not have testing electrode 33 formed on its bottom surface, and capacitor 30 is connected to terminals 42a, 42b and first surface 40s via anisotropic conductive film 62. In this manner, when capacitor 30 is physically connected to wiring board 40, the member provided on the bottom surface of capacitor 30 so as to electrically connect terminals 42a, 42b can be replaced with another conductive material.

[0062] Although the embodiments of the present invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. This novel embodiment can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0063] 4...wiring board frame, 4s...first surface, 4b...second surface, 10...memory chip, 20...controller chip, 30...Capacitor, 31...Laminate, 32...external electrode, 33...Inspection electrode, 40...wiring board, 41...Terminal, 41a, 41b, 49… Land, 42...Inspection wiring, 42a, 42b...Terminal section, 42c...Terminal connection part, 43, 43a, 43b...inspection terminals, 50...solder ball, 60...Molding resin, 61...Solder, 70...interstitial area, 100...Semiconductor device

Claims

1. A circuit board having a plurality of wiring boards each having a first surface and a second surface opposite to the first surface, and a pair of electrodes electrically connected to a capacitor formed on the first surface, the plurality of wiring substrates are arranged with their first surfaces on the same plane, a plurality of wiring layers are stacked between the first surface and the second surface; an inspection wiring is formed between the pair of electrodes formed on the first surface of each of the wiring boards, extending in a direction intersecting a line connecting the pair of electrodes and having inspection terminals at both ends; the test wiring is formed so that the capacitors are arranged in series in the path of the test wiring when the capacitors are mounted on the pair of electrodes, The inspection wiring has a broken portion between the pair of electrodes.

2. A plurality of pairs of electrodes are formed on the wiring substrate, 2. The circuit board according to claim 1, wherein the inspection wiring is formed for each of the wiring boards such that, when the capacitor is mounted on the pair of electrodes, the capacitor is disposed in series in the path of the inspection wiring.

3. The capacitor is connected to the pair of electrodes, 2. The circuit board according to claim 1, wherein the capacitor includes a laminate formed by laminating dielectric layers and internal electrodes, and a pair of external electrodes electrically connected to the pair of electrodes provided on the wiring board at both ends of the laminate, and a thin-film testing conductor is formed between the pair of external electrodes on a surface of the laminate facing the first surface of the wiring board, the testing conductor having a planar shape capable of covering the entire disconnection portion.

4. 2. The circuit board according to claim 1, wherein the terminal for inspection is formed in a path of the wiring for inspection that connects the cut portions of two different wiring boards.

5. 2. The circuit board according to claim 1, wherein a top layer of the plurality of wiring layers is formed so as to be exposed from the first surface, and at least a portion of the inspection wiring formed between the pair of electrodes is formed on the top layer.

6. 2. The circuit board according to claim 1, wherein a gap region is formed around the wiring board in a plane parallel to the first plane, and the inspection terminals are formed in the gap region.

7. 7. The circuit board according to claim 6, wherein a lowest layer of said plurality of wiring layers is formed so as to be exposed from said second surface, and said terminals for inspection are formed on said lowest layer.

8. a wiring board having a first surface and a second surface opposite to the first surface; a semiconductor chip provided on the first surface of the wiring board; a capacitor connected to a pair of electrodes provided on the first surface of the wiring board; a sealing resin covering the first surface of the wiring board and surfaces of the semiconductor chip and the capacitor; and an external device connection terminal provided on the second surface of the wiring board; A semiconductor device having a plurality of wiring layers are stacked between the first surface and the second surface of the wiring substrate; a semiconductor device, wherein a test wiring is formed on the first surface of the wiring board, the test wiring having an end portion on a side surface perpendicular to the first surface and the second surface, and including a portion extending between the pair of electrodes in a direction intersecting a line connecting the pair of electrodes.

9. 9. The semiconductor device according to claim 8, wherein the inspection wiring has a break between the pair of electrodes.

10. 9. The semiconductor device according to claim 8, wherein an uppermost layer of said plurality of wiring layers is formed so as to be exposed from said first surface, and at least a portion of said inspection wiring formed between said pair of electrodes is formed on said uppermost layer.

11. 10. The semiconductor device according to claim 9, wherein the capacitor includes a laminate formed by laminating dielectric layers and internal electrodes, and a pair of external electrodes electrically connected to the pair of electrodes provided on the wiring board at both ends of the laminate, and a thin-film testing conductor is formed between the pair of external electrodes on a surface of the laminate facing the first surface of the wiring board, the testing conductor having a planar shape capable of covering the entire disconnection portion.

12. 12. The semiconductor device according to claim 11, wherein the inspection wiring is electrically connected only to the inspection conductor of the capacitor.

13. a circuit board including a plurality of wiring boards each having a first surface and a second surface opposite to the first surface, the plurality of wiring boards each having a pair of electrodes formed on the first surface and a capacitor electrically connected to the pair of electrodes, the plurality of wiring boards being arranged side by side with the first surfaces of the wiring boards being flush with each other, the plurality of wiring boards having inspection wiring extending between the pair of electrodes in a direction intersecting a line connecting the pair of electrodes and having inspection terminals at both ends thereof, the plurality of wiring boards being arranged side by side with the first surfaces of the wiring boards being flush with each other ... thermally curing the adhesive; electrically connecting terminals of the semiconductor chip and terminals of the circuit board; covering the first surface of the wiring substrate and surfaces of the semiconductor chip and the capacitor with a sealing resin; physically and electrically connecting an external device connection terminal to the second surface of the circuit board using a conductive adhesive; thermally curing the conductive adhesive; cutting the circuit board into individual wiring boards; measuring a DC resistance between the terminals for inspection until the circuit board is cut off, and inspecting a physical connection state between the capacitor and the wiring board; A method for manufacturing a semiconductor device, comprising:

Images