Rectifier circuit and power supply using the same

Abstract

To provide a rectification circuit having large effect on loss reduction and a power supply using the same.SOLUTION: A rectification circuit comprises a first switching element QL1 of an enhancement type, a second switching element QH1 of a depletion type which is connected with a drain side of the first switching element in series and has a breakdown voltage higher than the first switching element, a third switching element QL2 of an enhancement type, and a fourth switching element QH2 of a depletion type which is connected with a drain side of the third switching element in series and has a breakdown voltage higher than the third switching element. A source of the first switching element is connected with a source of the third switching element. A gate of the first switching element is connected with a node between the third switching element and the fourth switching element. A gate of the third switching element is connected with a node between the first switching element and the second switching element.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a rectifier circuit and a power supply using the same. [Background technology]

[0002] Rectifier circuits for rectifying AC to DC generally use diodes or MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Rectification using diodes has the problem of large losses due to the voltage drop caused by the built-in potential of the diode. On the other hand, synchronous rectification using MOSFETs has the advantage of low losses because there is no built-in potential in the MOSFET and the forward current rises from 0V, so using MOSFETs allows for even lower-loss rectification.

[0003] An example of a rectifier circuit using a MOSFET is the technology described in Patent Document 1. Patent Document 1 discloses a rectifier circuit that achieves synchronous rectification without using a voltage detection circuit to determine the turn-on / off timing of the MOSFET. In this rectifier circuit, the drain-source voltage of a rectifier MOSFET (233) is divided by resistors (171, 172) and input to the gate-source voltage of another rectifier MOSFET (183) that shares a common source (Figure 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-295627 Summary of the Invention [Problem to be solved by the invention]

[0005] In the rectifier circuit of Patent Document 1, the waveform of the gate-source voltage of the rectifier MOSFET (183) is a waveform obtained by resistively dividing the waveform of the drain-source voltage of the rectifier MOSFET (233). For example, when rectifying a sine wave voltage, the gate-source voltage of the rectifier MOSFET (183) also becomes sinusoidal, and the rise and fall of the gate-source voltage becomes slow, which causes a problem of reducing the loss reduction effect achieved by synchronous rectification.

[0006] Therefore, an object of the present invention is to provide a rectifier circuit that performs synchronous rectification using a rectifying MOSFET, and that is capable of achieving a greater loss reduction effect than conventional rectifier circuits, and a power supply using the same. [Means for solving the problem]

[0007] One embodiment of the present invention for solving the above problem is a rectifier circuit including a first enhancement-type switching element, a second depletion-type switching element connected in series to the drain side of the first switching element and having a higher withstand voltage than the first switching element, a third enhancement-type switching element, and a fourth depletion-type switching element connected in series to the drain side of the third switching element and having a higher withstand voltage than the third switching element, wherein the source of the first switching element and the source of the third switching element are connected, the gate of the first switching element is connected to a node between the third switching element and the fourth switching element, and the gate of the third switching element is connected to a node between the first switching element and the second switching element. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a rectifier circuit that performs synchronous rectification using a rectifying MOSFET, and a power supply using the same that can achieve a greater loss reduction effect than conventional rectifier circuits, thereby enabling high-density packaging of the rectifier circuit and the power supply using the same.

[0009] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing the configuration of a rectifier circuit according to a first embodiment of the present invention; [Figure 2] Graph showing the rectified waveform by the rectifier circuit of Figure 1 [Figure 3] A diagram showing the configuration of a rectifier bridge using the rectifier circuit of Figure 1. [Figure 4] FIG. 10 is a diagram showing the configuration of a rectifier circuit according to a second embodiment of the present invention; [Figure 5] FIG. 10 is a diagram showing the configuration of a rectifier circuit according to a third embodiment of the present invention. [Figure 6] FIG. 10 is a diagram showing the configuration of a rectifier circuit according to a fourth embodiment of the present invention. [Figure 7] FIG. 10 is a diagram showing the configuration of a semiconductor package according to a fifth embodiment of the present invention. [Figure 8] FIG. 10 is a diagram showing the configuration of a front-end power supply according to a sixth embodiment of the present invention. [Figure 9] FIG. 1 shows the configuration of a rectifier circuit according to a first conventional example. [Figure 10] Graph showing the rectified waveform by the rectifier circuit of Figure 9 [Figure 11] FIG. 1 is a diagram showing the configuration of a rectifier circuit of a comparative example; [Figure 12] Graph showing the rectified waveform by the rectifier circuit of Figure 11 DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and detailed description of overlapping components will be omitted. [Example]

[0012] The configuration of a rectifier circuit according to a first embodiment of the present invention and a method for controlling the same will be described with reference to Figures 1 to 3 and Figures 9 to 12. Figure 1 is a diagram showing the configuration of the rectifier circuit according to the first embodiment, Figure 2 is a graph showing rectified waveforms produced by the rectifier circuit of Figure 1, and Figure 3 is a diagram showing the configuration of a rectifier bridge to which the rectifier circuit of Figure 1 is applied. Figures 9 to 12 are diagrams showing the configuration and rectified waveforms of a conventional rectifier circuit shown as a comparative example to make the configuration of the present invention easier to understand.

[0013] First, the configuration of the rectifier circuit of this embodiment will be described using Fig. 1. As shown in Fig. 1, the rectifier circuit of this embodiment includes enhancement-type switching elements QL1 (first switching element) and QL2 (third switching element), depletion-type switching elements QH1 (second switching element) and QH2 (fourth switching element), a control circuit 1 connected to the gate of QH1, and a control circuit 2 connected to the gate of QH2.

[0014] 1, QH1 and QH2 are depletion-type N-channel MOSFETs, and QL1 and QL2 are enhancement-type N-channel MOSFETs, as an example of application to the two rectifier MOSFETs LQ on the low side of the rectifier bridge in Fig. 3. The operation of the rectifier circuit of this embodiment will be explained in the case where QH1 and QH2 are depletion-type N-channel MOSFETs, and QL1 and QL2 are enhancement-type N-channel MOSFETs.

[0015] However, QH1 and QH2 may use SiC-JFET (Junction-gate Field-Effect Transistor) or GaN-HEMT (High Electron Mobility Transistor).

[0016] Next, the operation of the rectifier circuit of this embodiment will be described using Figure 2. Figure 2 shows the voltage waveform when the rectifier circuit of Figure 1 is applied to two rectifier MOSFETs LQ on the low side of the rectifier bridge of Figure 3 and a sinusoidal voltage is applied to the input voltage Vin. Period T1 is the rectification period for QH1 and QL1 and the non-rectification period for QH2 and QL2. Period T2 is the non-rectification period for QH1 and QL1 and the rectification period for QH2 and QL2.

[0017] Immediately after the start of the rectification period T1 for QH1 and QL1, QL1 is off, so the rectified current flows through the body diode of QL1. At this time, the voltage Vds1 between the drain of QH1 and the source of QL1 is less than the threshold voltage Vref2, so control circuit 1 turns on QH1 by controlling the gate voltage of QH1 to be equal to or greater than the gate threshold voltage of QH1. Therefore, the rectified current flows through the source-drain path of QH1. Control circuit 2 also controls the gate voltage of QH2, turning QH2 on. As a result, charge flows from the source of QH2 into the drain-source capacitance of QL2 and the gate-source capacitance of QL1, increasing the drain-source voltage of QL2 and the gate-source voltage of QL1. At this time, the drain-source capacitance of QL2 and the gate-source capacitance of QL1 are charged in parallel, so the drain-source voltage of QL2 and the gate-source voltage of QL1 are equal. Also, since QH2 is on at this time, the drain-source voltage of QH2 is equal to the voltage drop caused by the drain-source capacitance of QL2, the current charging the gate-source capacitance of QL1, and the drain-source resistance of QH2.

[0018] Thereafter, as the input voltage increases, that is, as the voltage Vds2 between the drain of QH2 and the source of QL2 increases, the gate-source voltage of QL1 also increases. Thereafter, when the gate-source voltage of QL1 becomes greater than the gate threshold voltage of QL1, QL1 turns on and the rectified current is commutated from the body diode of QL1 to the source-drain path of QL1.

[0019] As described above, QH1 and QL1 are in the ON state during the rectification period, making it possible to reduce loss due to the rectification current.

[0020] Subsequently, when the voltage Vds2 between the drain of QH2 and the source of QL2 exceeds a certain threshold voltage Vref1, the control circuit 2 controls the gate voltage of QH2 to be less than the gate threshold voltage of QH2, thereby turning QH2 off. However, the threshold voltage Vref1 is sufficiently greater than the gate threshold voltage Vlth1 of QL1 and less than the gate-source breakdown voltage of QL1.

[0021] After that, the drain-source capacitance of QH2 begins to charge, and as the input voltage increases, the drain-source voltage of QH2, the drain-source voltage of QL2, and the gate-source voltage of QL1 increase. However, the drain-source capacitance of QL2 and the gate-source capacitance of QL1 are connected in parallel, while the drain-source capacitance of QH2 is connected in series with these capacitances. In addition, the gate-source capacitance of a MOSFET is generally larger than its drain-source capacitance. Therefore, the increase in the drain-source voltage Vds2 of QH2 is dominated by the increase in the drain-source voltage of QH2. As a result, despite the increase in the drain-source voltage Vds2 of QH2 and the drain-source voltage of QH2, the drain-source voltage of QL2 and the gate-source voltage of QL1 remain roughly constant at the threshold voltage Vref1.

[0022] When the input voltage changes from increasing to decreasing, the voltage Vds2 between the drain of QH2 and the source of QL2 also decreases. For the same reason that the increase in the voltage Vds2 between the drain of QH2 and the source of QL2 was dominated by the increase in the drain-source voltage of QH2, the decrease in the voltage Vds2 between the drain of QH2 and the source of QL2 is dominated by the decrease in the drain-source voltage of QH2. As a result, despite the decrease in the voltage Vds2 between the drain of QL2 and the drain-source voltage of QH2, the drain-source voltage of QL2 and the gate-source voltage of QL1 remain roughly constant at the threshold voltage Vref1.

[0023] Thereafter, when the voltage Vds2 between the drain of QH2 and the source of QL2 becomes equal to the threshold voltage Vref1, the control circuit 2 controls the gate voltage of QH2 to be equal to or higher than the gate threshold voltage of QH2, thereby turning QH2 on.

[0024] As a result, the gate-source capacitance of QL1 and the drain-source capacitance of QL2 are discharged in parallel, and the gate-source voltage Vlgs1 of QL1 decreases. When the gate-source voltage of QL1 becomes less than the gate threshold voltage Qlth1 of QL1, QL1 turns off.

[0025] When the polarity of the input voltage subsequently changes, rectification period T2 of QH2 and QL2 begins. Just as control circuit 2 turns off QH2 during rectification period T1 of QH1 and QL1 described above, control circuit 1 turns off QH1 during rectification period T2.

[0026] This is how QH1 and QL1 are turned on and off. QH2 and QL2 are turned on and off in the same way. However, the threshold voltage Vref2 used for control is sufficiently larger than the gate threshold voltage Vlth2 of QL2, and smaller than the gate-source breakdown voltage of QL2. The above operation achieves synchronous rectification.

[0027] <Conventional Example 1> Here, the configuration of another conventional rectifier circuit will be described with reference to Fig. 9. Fig. 9 is a diagram showing the configuration of a rectifier circuit of Conventional Example 1, which corresponds to the rectifier circuit of Patent Document 1. The rectifier circuit of Fig. 9 is composed of rectifying MOSFETs QR1 and QR2 and voltage dividing resistors Rp11, Rp12, Rp21, and Rp22.

[0028] The operation of the rectifier circuit of Fig. 9 will be explained using Fig. 10. Fig. 10 is a graph showing rectified waveforms by the rectifier circuit of Fig. 9, and shows the voltage waveforms when the rectifier circuit of Fig. 9 is applied to two rectifier MOSFETs LQ on the low side of the rectifier bridge of Fig. 3 and a sinusoidal voltage is applied to the input voltage Vin. Period T1 is the rectification period of rectifier MOSFET QR1 and the non-rectification period of rectifier MOSFET QR2. Period T2 is the non-rectification period of rectifier MOSFET QR1 and the rectification period of rectifier MOSFET QR2.

[0029] As an example, let's look at the operation of QR1. During period T1, the drain-source voltage Vds2 of QR2 is divided by voltage-dividing resistors Rp21 and Rp22, and the voltage generated across Rp22 is applied between the gate and source of QR1. In Figure 10, the waveform of the gate-source voltage Vgs1 of QR1 during period T1, which is the rectification period of QR1, is a sine wave that has been reduced by the resistive voltage divider.

[0030] As described above, in the rectifier circuit shown in Figure 9, the gate-source voltages of the rectifier MOSFETs generated during the rectification period are sinusoidal waves reduced by the resistive voltage division. This lengthens the period from the start of the rectification period until the gate-source voltages Vgs1 and Vgs2 exceed the gate threshold voltages Vth1 and Vth2 of the rectifier MOSFETs QR1 and QR2, as well as the period from when the gate-source voltages Vgs1 and Vgs2 fall below the gate threshold voltages Vth1 and Vth2 of the rectifier MOSFETs QR1 and QR2 until the end of the rectification period. In other words, the rise and fall of the gate-source voltages Vgs1 and Vgs2 are slowed. As a result, the proportion of the rectification period during which the rectifier MOSFETs are on decreases, reducing the loss reduction effect achieved by synchronous rectification.

[0031] On the other hand, in the rectifier circuit of this embodiment shown in FIG. 1, when the input voltage is lower than the threshold voltages Vref1 and Vref2, the input voltage is applied as is between the gate and source of QL1 and between the gate and source of QL2 without being reduced by resistive voltage division (here, voltage drops caused by the resistance components of the switches in the ON state in the control circuit and the resistance components of the wiring are not considered to be part of the resistive voltage division). In other words, the rise and fall of the gate-source voltage in the rectifier circuit of FIG. 1 is faster than in the rectifier circuit of FIG. 9. As a result, the proportion of the period during which the rectifying MOSFET is on relative to the rectification period is larger, and the loss reduction effect of synchronous rectification is greater.

[0032] Comparative Example The configuration of another conventional rectifier circuit will be described using Fig. 11. Fig. 11 is a diagram showing the configuration of a rectifier circuit of a comparative example. The rectifier circuit of Fig. 11 is composed of rectifying MOSFETs QR1 and QR2, and QS1 and QS2.

[0033] The operation of the rectifier circuit of Figure 11 will be explained using Figure 12. Figure 12 shows the voltage waveforms when the rectifier circuit of Figure 11 is applied to the two rectifier MOSFETs LQ on the low side of the rectifier bridge of Figure 3 and a sinusoidal voltage is applied to the input voltage Vin. Period T1 is the rectification period of rectifier MOSFET QR1 and the non-rectification period of rectifier MOSFET QR2. Period T2 is the non-rectification period of rectifier MOSFET QR1 and the rectification period of rectifier MOSFET QR2.

[0034] In the rectifier circuit of FIG. 11, the rise and fall of the gate-source voltage are the same as those of the rectifier circuit of FIG.

[0035] However, in the rectifier circuit of Figure 11, QS1 and QS2 are required to have the same withstand voltage as QR1 and QR2. For example, when used in a commercial rectifier circuit, switching elements with a withstand voltage of 600V are used for QS1, QS2, QR1, and QR2. As a result, when mounting the rectifier circuit of Figure 11, it is necessary to ensure creepage distance to ensure insulation, and QS1 and QS2 become an obstacle to high-density mounting.

[0036] On the other hand, in the rectifier circuit of this embodiment shown in Figure 1, QH1 and QH2 are required to have a high withstand voltage, but QL1 and QL2 can have a low withstand voltage. For example, when used in a commercial rectifier circuit, QH1 and QH2 can be switching elements with a withstand voltage of 600V, and QL1 and QL2 can be switching elements with a withstand voltage of 20V. As a result, while the rectifier circuit of Figure 11 requires four high-voltage switching elements (QR1, QR2, QS1, QS2), the rectifier circuit of this embodiment only requires two high-voltage switching elements (QH1, QH2).

[0037] As described above, the rectifier circuit of this embodiment makes it possible to reduce the number of high-voltage switching elements while maintaining the loss reduction effect achieved by synchronous rectification. [Example]

[0038] 4 is a diagram showing the configuration of a rectifier circuit according to a second embodiment of the present invention. The configuration of the rectifier circuit according to the second embodiment of the present invention and a control method therefor will be described with reference to FIG. 4. This embodiment is a specific example of the circuit configuration of the first embodiment.

[0039] As shown in FIG. 4, in the rectifier circuit of this embodiment, in control circuit 1, the gate of QH1 is connected to the source of QL1, and in control circuit 2, the gate of QH2 is connected to the source of QL2.

[0040] With this configuration, the threshold voltage Vref1 is the absolute value of the gate threshold voltage Vhth2 of QH2, and the threshold voltage Vref2 is the absolute value of the gate threshold voltage Vhth1 of QH1. Therefore, synchronous rectification can be achieved by selecting the gate threshold voltage Vhth2 of QH2 and the gate threshold voltage Vhth1 of QH1 so that Vref1 and Vref2 are sufficiently larger than the gate threshold voltage Vlth1 of QL1 and the gate threshold voltage Vlth2 of QL2, respectively, and smaller than the gate-source breakdown voltage of QL1 and the gate-source breakdown voltage of QL2, respectively. The effect of this configuration is that the control circuits 1 and 2 can be realized with simple configurations. [Example]

[0041] Fig. 5 is a diagram showing the configuration of a rectifier circuit according to a third embodiment of the present invention. The configuration of a rectifier circuit according to a second embodiment of the present invention and a control method therefor will be described with reference to Fig. 5. This embodiment is a more specific example of the circuit configuration of the first embodiment.

[0042] 5, the rectifier circuit of this embodiment includes a Zener diode whose cathode and anode are connected to the drain and source of QL1, and a Zener diode whose cathode and anode are connected to the drain and source of QL2, respectively. The Zener voltages of these Zener diodes are smaller than the drain-source breakdown voltages of QL1 and QL2. This configuration makes it possible to prevent the drain-source voltage Vlds1 of QL1 and the drain-source voltage Vlds2 of QL2 from becoming larger than the withstand voltages of QL1 and QL2, causing breakdowns in QL1 and QL2. [Example]

[0043] FIG. 6 is a diagram showing the configuration of a rectifier circuit according to a fourth embodiment of the present invention. The configuration of the rectifier circuit according to the fourth embodiment of the present invention and a method of controlling it will be described with reference to FIG. 6. As shown in FIG. 6, the rectifier circuit of this embodiment includes, in control circuit 1, voltage-dividing resistors Rp11 connected between the gate and source of QH1 and Rp12 connected between the gate of QH1 and the source of QL1, and in control circuit 2, voltage-dividing resistors Rp21 connected between the gate and source of QH2 and Rp22 connected between the gate of QH2 and the source of QL2.

[0044] In the rectifier circuit of this embodiment, the threshold voltage Vref1 can be approximately calculated as Vref1=|Vhth2|(Rp21+Rp22) / Rp21, and the threshold voltage Vref2 can be approximately calculated as Vref2=|Vhth1|(Rp11+Rp12) / Rp11.

[0045] Therefore, synchronous rectification can be achieved by selecting the values ​​of the gate threshold voltage Vhth1 of QH1, the gate threshold voltage Vhth2 of QH2, and the voltage-dividing resistors Rp11, Rp12, Rp21, and Rp22 so that Vref1 and Vref2 are sufficiently larger than the gate threshold voltage Vlth1 of QL1 and the gate threshold voltage Vlth2 of QL2, respectively, and smaller than the gate-source breakdown voltage of QL1 and the gate-source breakdown voltage of QL2, respectively.

[0046] The effect of this embodiment is that the constraints on the gate threshold voltage when selecting QH1 and QH2 are reduced. [Example]

[0047] FIG. 7 is a diagram showing the configuration of a semiconductor package according to a fifth embodiment of the present invention. The semiconductor package according to the fifth embodiment of the present invention will be described with reference to FIG. 7. FIG. 7 shows a configuration in which the rectifier circuits described in the first to fourth embodiments are built into a semiconductor package 3. The semiconductor package 3 has three external terminals: a first terminal Td1, a second terminal Td2, and a third terminal Ts. FIG. 7 shows the rectifier circuit described in the second embodiment (FIG. 4) as an example, and the rectifier circuits described in the other embodiments may also be used.

[0048] An advantage of this embodiment is that when designing and manufacturing a product that uses a rectifier circuit, by purchasing and incorporating a rectifier circuit with a built-in control circuit like this embodiment, it becomes unnecessary to incorporate the control circuit into the design and manufacturing process yourself, thereby reducing the number of steps required for design and implementation. [Example]

[0049] Fig. 8 is a diagram showing the configuration of a front-end power supply according to a sixth embodiment of the present invention. A front-end power supply according to the sixth embodiment of the present invention will be described with reference to Fig. 8. Fig. 8 shows an example of a power supply to which the rectifier circuits of the present invention described in the first to fifth embodiments can be applied.

[0050] The scope of application of the present invention is general rectifier circuits used in power converters. For example, in a front-end power supply as shown in Fig. 8, the present invention can be applied by replacing commercial rectifier diodes CRD1 to CRD4, freewheeling diodes FWD1 and FWD2, and secondary-side rectifier diodes SSD1 and SSD2 as rectifier circuits used in respective places where they are used.

[0051] For example, in a configuration where N-channel MOSFETs are used for CRD3 and CRD4 and the source is common, the rectifier circuit of the present invention using N-channel MOSFETs for QH1, QL1, QH2, and QL2 can be applied.

[0052] Furthermore, in a configuration where the drain is common when an N-channel MOSFET is applied, such as CRD1 and CRD2, the source is common when a P-channel MOSFET is applied, so the rectifier circuit of the present invention using P-channel MOSFETs for QH1, QL1, QH2, and QL2 can be applied.

[0053] 8, the rectifier circuit of the present invention, which uses P-channel MOSFETs for QH1, QL1, QH2, and QL2, can be applied to SSD1 and SSD2. However, there is also a power converter circuit configuration in which the rectifier circuit of the present invention, which uses N-channel MOSFETs for QH1, QL1, QH2, and QL2, can be applied to SSD1 and SSD2. Also, a configuration is possible in which the commercial rectifier diodes CRD3 and CRD4 are replaced with the rectifier circuit of any one of the first to fourth embodiments, and diodes or synchronous rectifier circuits are used for the commercial rectifier diodes CRD1 and CRD2.

[0054] By applying the rectifier circuit of the present invention to a power supply such as a front-end power supply, it is possible to contribute to reducing loss and improving reliability of the power supply.

[0055] As described above, according to the present invention, it is possible to provide a rectifier circuit that performs synchronous rectification using a rectifying MOSFET, and that is capable of achieving a greater loss reduction effect than conventional rectifier circuits, and a power supply using the same.

[0056] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0057] 1, 2...Control circuit, 3...Semiconductor package, Td1, Td2, Ts...Terminal, Rp11, Rp12, Rp21, Rp22...Voltage dividing resistor, LQ...Two switching elements on the low side of the rectifier bridge, CRD1 to CRD4...Commercial rectifier diodes, FWD1, FWD2...Freewheeling diodes, SSD1, SSD2...Secondary side rectifier diodes, QH1, QH2...Depletion type switching elements, QL1, QL2...Enhancement type switching elements, Vhds1, Vhds2...Drain-source voltages of depletion type switching elements QH1, QH2, Vhgs1, Vhgs2...Gate-source voltages of depletion type switching elements QL1, QL2, Vhth1, Vhth2...Gate threshold voltages of depletion type switching elements QL1, QL2, Vlds1, Vlds2...Enhancement type switching elements Vth11, Vth22...gate threshold voltages of depletion-type MOSFETs QS1, QS2; CC1, CC2...control circuit of conventional rectifier circuit; Rp1 to Rp4...voltage dividing resistors of conventional rectifier circuit; T1, T2...rectification periods of QH1 and QL1, QH2 and QH1, or rectification MOSFETs Rectification period of QR1 and QR2, Vds1, Vds2...voltage between the drain of QH1 and the source of QL1, voltage between the drain of QH2 and the source of QL2, or drain-source voltage of rectifying MOSFET QR1, drain-source voltage of rectifying MOSFET QR2, Vgs1, Vgs2...gate-source voltage of rectifying MOSFET QR1, QR2.

Claims

1. an enhancement-type first switching element; a depletion-type second switching element connected in series to a drain side of the first switching element and having a higher withstand voltage than the first switching element; an enhancement-type third switching element; a depletion-type fourth switching element connected in series to a drain side of the third switching element and having a higher withstand voltage than the third switching element, the source of the first switching element and the source of the third switching element are connected together; a gate of the first switching element is connected to a node between the third switching element and the fourth switching element; a gate of the third switching element connected to a node between the first switching element and the second switching element;

2. 2. The rectifier circuit according to claim 1, a first control circuit is connected to a gate of the second switching element, and a second control circuit is connected to a gate of the fourth switching element; When N-channel switching elements are applied to the first switching element, the second switching element, the third switching element, and the fourth switching element, when a voltage applied between a drain of the fourth switching element and a source of the third switching element is equal to or lower than a first threshold voltage, the second control circuit controls the fourth switching element to be on, when a voltage applied between a drain of the fourth switching element and a source of the third switching element is higher than the first threshold voltage, the second control circuit controls the fourth switching element to be off, when a voltage applied between a drain of the second switching element and a source of the first switching element is equal to or lower than a second threshold voltage, the first control circuit controls the second switching element to be on, and when a voltage applied between a drain of the second switching element and a source of the first switching element is higher than the second threshold voltage, the first control circuit controls the second switching element to be off, the first threshold voltage is equal to or greater than a gate threshold voltage of the first switching element and smaller than a positive gate-source breakdown voltage of the first switching element, the second threshold voltage is equal to or greater than a gate threshold voltage of the third switching element and smaller than a positive gate-source breakdown voltage of the third switching element, and when P-channel switching elements are used as the first switching element, the second switching element, the third switching element, and the fourth switching element, when a voltage applied between the drain of the fourth switching element and the source of the third switching element is equal to or greater than the third threshold voltage, the second control circuit controls the fourth switching element to be on, and when a voltage applied between the drain of the fourth switching element and the source of the third switching element is smaller than the first threshold voltage, the second control circuit controls the fourth switching element to be off; when a voltage applied between the drain of the second switching element and the source of the first switching element is equal to or greater than a fourth threshold voltage, the first control circuit controls the second switching element to be turned on, and when a voltage applied between the drain of the second switching element and the source of the first switching element is smaller than the fourth threshold voltage, the first control circuit controls the second switching element to be turned off; The third threshold voltage is equal to or lower than a gate threshold voltage of the first switching element and is higher than a negative gate-source breakdown voltage of the first switching element, and the fourth threshold voltage is equal to or lower than a gate threshold voltage of the third switching element and is higher than a negative gate-source breakdown voltage of the third switching element.

3. 2. The rectifier circuit according to claim 1, The rectifier circuit is characterized in that the second switching element and the fourth switching element are SiC-JFETs.

4. 2. The rectifier circuit according to claim 1, The rectifier circuit is characterized in that the second switching element and the fourth switching element are GaN-HEMTs.

5. 2. The rectifier circuit according to claim 1, a first Zener diode having a cathode and an anode connected to the drain terminal and the source terminal of the first switching element, respectively; a second Zener diode having a cathode and an anode connected to the drain terminal and the source terminal of the third switching element, respectively;

6. 3. The rectifier circuit according to claim 2, a first resistor having a first terminal connected to the source of the second switching element and a second terminal connected to the gate of the second switching element; a second resistor having a first terminal connected to the gate of the second switching element and a second terminal connected to the source of the first switching element; a third resistor having a first terminal connected to the source of the fourth switching element and a second terminal connected to the gate of the fourth switching element; and a first resistor having a first terminal connected to the gate of the fourth switching element and a second terminal connected to the source of the third switching element.

7. 3. The rectifier circuit according to claim 2, In the first control circuit, the gate of the second switching element is connected to the source of the first switching element, and in the second control circuit, the gate of the fourth switching element is connected to the source of the third switching element.

8. 2. The rectifier circuit according to claim 1, A rectifier circuit characterized in that the rectifier circuit is built into a single semiconductor package.

9. A power supply using the rectifier circuit according to any one of claims 1 to 8.

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