Semiconductor switching element drive circuit

Abstract

To provide a highly reliable and inexpensive drive circuit.SOLUTION: A drive circuit (10) for driving a semiconductor switching element (Q3) having a grounded source and a gate comprises a pulse transformer (T1) having at least one primary winding, a first secondary winding and a second secondary winding, a switching element (Q1) which is connected in series with the primary winding and drives the pulse transformer (T1) in response to a pulse duration modulation (PWM) control signal, a first transmission circuit (11) which is connected between the first secondary winding and the gate of the semiconductor switching element (Q3) and transmits a positive ON drive voltage to the gate of the semiconductor switching element (Q3), and a second transmission circuit (12) which is connected between the second secondary winding and the gate of the semiconductor switching element (Q3) and transmits a negative OFF drive voltage to the gate of the semiconductor switching element (Q3).SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a drive circuit for a semiconductor switching element. [Background technology]

[0002] Semiconductor switching elements include field-effect transistors (Si-FETs) made of Si and FETs (SiC-FETs) made of SiC. In the case of Si-FETs, a drive voltage of 10V or more is sufficient to reduce the ON resistance. However, in the case of SiC-FETs, a drive voltage of 18V or more must be applied between the gate and source; this is an issue in that the ON resistance does not decrease to the same level as that of Si-FETs. Also, in the case of SiC-FETs, the gate threshold voltage is low, at 1.6V to 4V. Therefore, when turning off a SiC-FET, it is desirable to apply a negative drive voltage between the gate and source.

[0003] Various drive circuits for driving such semiconductor switching elements have been proposed.

[0004] For example, Patent Document 1 discloses a drive circuit using SiC-FETs as each of two power switches connected in a half-bridge. In Patent Document 1, the SiC-FET is limited to a maximum load drive voltage of -10 V (negative voltage) and a maximum threshold voltage V of 3 V. th and requires a maximum of +20V to fully enter the ohmic region. Patent Document 1 describes that the DC gate supply voltage is defined to be close to the maximum load supply voltage, e.g., −8V for a −10V device limit.

[0005] In a possible embodiment, the applied input signal is a pulse-width modulated (PMW) signal. In a possible embodiment, the drive circuit includes a differentiation circuit, a magnetic trigger circuit, two trigger circuits, two ramp generating circuits, a magnetic coupling circuit, and two resistors. The magnetic trigger circuit includes a transformer with one primary winding and four secondary windings.

[0006] Patent Document 2 provides a technology that contributes to improving the response speed of the switching operation of a semiconductor switching element and suppressing ringing. The gate drive circuit for a semiconductor switching element disclosed in Patent Document 2 includes a pulse transformer whose primary winding is connected to a pulse voltage source, and a discharge transistor and a Zener diode connected in parallel between one end of a secondary winding of the pulse transformer and the other end of the secondary winding. One end of the secondary winding of the pulse transformer is connected to the gate of the semiconductor switching element, and the other end is connected to the source of the semiconductor switching element. The discharge transistor is used to sufficiently discharge any charge remaining in the gate capacitance of the semiconductor switching element when the semiconductor switching element is turned off.

[0007] The first and second diodes are connected in series to the center of one end of the secondary winding, with the first and second diodes connected in that order in the forward direction toward the gate of the semiconductor switching element. The discharge transistor has an emitter connected to the cathode of the second diode at one end of the secondary winding, a collector connected to the other end of the secondary winding, and a base connected to the series connection point of the first and second diodes and to the other end of the secondary winding via a resistor. The Zener diode has a cathode connected to the anode of the first diode at one end of the secondary winding and an anode connected to the other end of the secondary winding. The semiconductor switching element has a structure with a capacitive gate and converts DC power energy supplied from a DC power source to a load into pulsed energy.

[0008] Patent Document 2 describes that a specific example of a power switching element is an element (so-called SiC element) with a MOSFET (metal oxide semiconductor field effect transistor) structure made of SiC (silicon carbide) and having a capacitive gate. Patent Document 2 also describes that when multiple switch products SW are to be switched simultaneously, a configuration including a pulse transformer having a primary winding connected to a pulse voltage source and multiple secondary windings arranged opposite to the primary winding can be used. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Special Publication No. 2015-509333 [Patent Document 2] Japanese Patent Publication No. 2020-014032 Summary of the Invention [Problem to be solved by the invention]

[0010] As mentioned above, when the semiconductor switching element is made of SiC-FET, the gate threshold voltage is low, at 1.6 V to 4 V. Therefore, when turning off the SiC-FET, it is desirable to apply a negative drive voltage between the gate and source. This poses a problem of complicating the drive circuit, as will be described in detail later with reference to the drawings.

[0011] Patent Document 1 only discloses a drive circuit that drives two power switches connected in a half-bridge configuration, that is, Patent Document 1 does not disclose a drive circuit that drives one power switch.

[0012] In Patent Document 2, the pulse transformer has only one secondary winding. Therefore, in the gate drive circuit disclosed in Patent Document 2, only a positive voltage can be applied as a drive voltage between the gate and source of the semiconductor switching element. Therefore, if the semiconductor switching element is made of a SiC-FET, a negative voltage cannot be applied to the gate as a drive voltage when the SiC-FET is turned off.

[0013] An object of the present invention is to provide a drive circuit for a semiconductor switch element that solves the above-mentioned problems. [Means for solving the problem]

[0014] In one embodiment of the present invention, a drive circuit (10) for driving a semiconductor switching element (Q3) having a grounded source and gate includes a pulse transformer (T1) having at least one primary winding, a first secondary winding, and a second secondary winding; a switching element (Q1) connected in series with the primary winding and driving the pulse transformer (T1) in response to a pulse width modulation (PWM) control signal; and a resistor between the first secondary winding and the gate-source of the semiconductor switching element (Q3). a first transmission circuit (11) connected between the second secondary winding and the gate-source of the semiconductor switching element (Q3) and transmitting a first induced voltage induced in the first secondary winding as an ON drive voltage, which is a positive voltage, between the gate and source of the semiconductor switching element (Q3); and a second transmission circuit (12) connected between the second secondary winding and the gate-source of the semiconductor switching element (Q3) and transmitting a second induced voltage induced in the second secondary winding as an OFF drive voltage, which is a negative voltage, between the gate and source of the semiconductor switching element (Q3). [Effects of the Invention]

[0015] According to the present invention, a highly reliable and inexpensive driving circuit can be provided. [Brief explanation of the drawings]

[0016] [Figure 1]FIG. 1 is a circuit diagram showing a configuration of a drive circuit according to a related art. [Figure 2] 2 is a waveform diagram showing a drive waveform supplied between the gate and source of a semiconductor switching element driven by the drive circuit shown in FIG. 1. FIG. [Figure 3] 1 is a circuit diagram showing a configuration of a drive circuit according to an embodiment of the present invention. [Figure 4] 4 is a waveform diagram showing a drive waveform supplied between the gate and source of a semiconductor switching element driven by the drive circuit shown in FIG. 3. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0017] [Related Technology] To facilitate understanding of the present invention, the related art relating to the present invention will be described.

[0018] FIG. 1 is a circuit diagram showing the configuration of a drive circuit 20 according to the related art.

[0019] The illustrated drive circuit 20 is a circuit for driving a semiconductor switching element Q11. The illustrated semiconductor switching element Q11 is made of a SiC-MOSFET and has a gate, a source, and a drain. The source of the semiconductor switching element Q11 is connected to the ground terminal PGND and is thus grounded. The drain of the semiconductor switching element Q11 is connected to a switching (SW) transformer (not shown). The gate of the semiconductor switching element Q11 is connected to the output terminal of the drive circuit 20 via a resistor R11 and is also connected to the ground terminal PGND via a resistor R12 and is thus grounded.

[0020] The illustrated drive circuit 20 includes a first DC / DC converter 21, a second DC / DC converter 22, a control circuit 23, and an integrated circuit (IC) 24 for driving a FET.

[0021] First DC / DC converter 21 is a +20V power supply that generates an ON drive voltage of +20V to drive semiconductor switching element Q11 ON. Second DC / DC converter 22 is a ±5V power supply that supplies an OFF drive voltage of -5V between the gate and source of semiconductor switching element Q11 when turning semiconductor switching element Q11 OFF. Control circuit 23 is a circuit that generates a +5V control signal for PWM control.

[0022] The FET driver IC 24 is connected to the gate of the semiconductor switching element Q11 via a resistor R11. The FET driver IC 24 is also connected to the first DC / DC converter 21, the second DC / DC converter 22, and the control circuit 23. In response to a control signal supplied from the control circuit 23, the FET driver IC 24 selects either the ON drive voltage supplied from the first DC / DC converter 21 or the OFF drive voltage supplied from the second DC / DC converter 22, and supplies the selected drive voltage between the gate and source of the semiconductor switching element Q11 via the resistor R11.

[0023] FIG. 2 is a waveform diagram showing the drive waveform supplied between the gate and source of semiconductor switching element Q11.

[0024] When semiconductor switching element Q11 is turned on, an ON drive voltage of +20V is supplied between the gate and source of semiconductor switching element Q11. When semiconductor switching element Q11 is turned off, an OFF drive voltage of -5V is supplied between the gate and source of semiconductor switching element Q11.

[0025] 1, it can be seen that the drive circuit 20 of the related art has a complex circuit configuration and a large number of components, which causes a decrease in mean time between failures (MTBF).

[0026] [Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The configurations described in the following embodiments are merely examples, and the technical scope of the present invention is not limited thereto.

[0027] A driver circuit 10 according to one embodiment of the present invention will be described with reference to FIG.

[0028] The illustrated drive circuit 10 is a circuit for driving semiconductor switching element Q3. The illustrated semiconductor switching element Q3 is made of a SiC MOSFET and has a gate, a source, and a drain. The illustrated SiC MOSFET is made of an N-channel MOSFET. The source of semiconductor switching element Q3 is connected to a ground terminal PGND and is grounded. The drain of semiconductor switching element Q3 is connected to a SW transformer (not shown). The gate of semiconductor switching element Q3 is connected to drive circuit 10, as will be described later.

[0029] The illustrated drive circuit 10 is characterized in that it does not use DC / DC converters 21 and 22 as in the drive circuit 20 shown in FIG. 1, but instead obtains an ON drive voltage and an OFF drive voltage using a pulse transformer T1, which will be described later.

[0030] The drive circuit 10 includes the above-mentioned pulse transformer T1, a switching element Q1, a first transmission circuit 11, a second transmission circuit 12, and a control signal generator 14.

[0031] The pulse transformer T1 has an auxiliary winding (1-2) and a primary winding (3-4) on the primary side, and a first secondary winding (5-6) and a second secondary winding (7-8) on the secondary side. The auxiliary winding (1-2) has Nr turns. The primary winding (3-4) has N1 turns. The first secondary winding (5-6) has N2 turns. The second secondary winding (7-8) has N3 turns.

[0032] Next, the circuit configuration provided on the primary side of the pulse transformer T1 will be described.

[0033] One end (1) of the auxiliary winding (1-2) is connected to the ground terminal SGND via a diode CR1, and is thus grounded. That is, the anode of the diode CR1 is connected to the ground terminal SGND, and the cathode of the diode CR1 is connected to one end (1) of the auxiliary winding (1-2). A DC voltage of Vcc is supplied to the other end (2) of the auxiliary winding (1-2).

[0034] A DC voltage Vcc is also supplied to one end (3) of the primary winding (3-4), and the other end (4) of the primary winding (3-4) is connected to the drain of a switching element Q1, which will be described later.

[0035] The illustrated switching element Q1 is made of a SiC MOSFET and has a gate, a source, and a drain. The illustrated SiC MOSFET is made of an N-channel MOSFET. The switching element Q1 is connected in series with the primary winding (3-4).

[0036] More specifically, the source of the switching element Q1 is connected to the ground terminal SGND and is grounded, and the drain of the semiconductor switching element Q1 is connected to the other end (4) of the primary winding (3-4), as described above.

[0037] The control signal generator 14 is a circuit for generating a PWM control signal. One end of the control signal generator 14 is connected to the gate of the switching element Q1 via a resistor R1. The other end of the control signal generator 14 is connected to a ground terminal SGND and is thus grounded. The gate of the switching element Q1 is also connected to the ground terminal SGND via a resistor R2.

[0038] Therefore, the PWM control signal generated by the control signal generator 14 is supplied to the gate of the switching element Q1 via the resistor R1. In response to this PWM control signal, the switching element Q1 drives the pulse transformer T1.

[0039] More specifically, the PWM control signal is a signal that alternates between an ON signal (High) during an ON period and an OFF signal (Low) during an OFF period. In response to the ON signal (High), the switching element Q1 passes current through the primary winding (3-4) of the pulse transformer T1. Therefore, when the ON signal (High) of the PWM control signal is transmitted to the gate of the switching element Q1, the pulse transformer T1 is driven.

[0040] Next, the circuit configuration provided on the secondary side of the pulse transformer T1 will be described.

[0041] The first transmission circuit 11 is connected between the first secondary winding (5-6) and the gate-source of the semiconductor switching element Q3. The first transmission circuit 11 is a circuit for transmitting the first induced voltage induced in the first secondary winding (5-6) of the pulse transformer T1 between the gate and source of the semiconductor switching element Q3 as an ON drive voltage, which is a positive voltage.

[0042] As mentioned above, the number of turns of the primary winding (3-4) is N1, and the number of turns of the first secondary winding (5-6) is N2. A DC voltage of Vcc is supplied to the primary winding (3-4). Therefore, the first induced voltage (ON drive voltage) is expressed as N2 × Vcc / N1. In this example, the peak value of the first induced voltage (ON drive voltage) is equal to +20V. In other words, the ratio N2:N1 (transformation ratio) is determined from the DC voltage Vcc so that the peak value of the first induced voltage (ON drive voltage) is +20V.

[0043] More specifically, during the ON period, the first transmission circuit 11 transmits the first induced voltage as an ON drive voltage between the gate and source of the semiconductor switching element Q3. The illustrated first transmission circuit 11 includes a first diode CR2, a second diode CR3, and a first resistor R4 connected in series in this order between one end (5) of the first secondary winding (5-6) and the gate of the semiconductor switching element Q3.

[0044] The anode of the first diode CR2 is connected to one end (5) of the first secondary winding (5-6). The cathode of the first diode CR2 is connected to the anode of the second diode CR3. The cathode of the second diode CR3 is connected to the gate of the semiconductor switching element Q3 via the first resistor R4.

[0045] The other end (6) of the first secondary winding (5-6) is connected to the ground terminal PGND and is grounded.

[0046] One end (7) of the second secondary winding (7-8) is also connected to the ground terminal PGND and is thus grounded.

[0047] The second transmission circuit 12 is connected between the second secondary winding (7-8) and the gate-source of the semiconductor switching element Q3. The second transmission circuit 12 is a circuit for transmitting a second induced voltage induced in the second secondary winding (7-8) of the pulse transformer T1 between the gate and source of the semiconductor switching element Q3 as an OFF drive voltage, which is a negative voltage. In this example, the OFF drive voltage is equal to -5V.

[0048] More specifically, the illustrated second transmission circuit 12 includes a holding circuit 122 that holds the second induced voltage as a holding voltage during the ON interval, and a release circuit 124 that releases the held voltage as an OFF drive voltage between the gate and source of the semiconductor switching element Q3 during the OFF interval.

[0049] The holding circuit 122 includes a Zener diode CR5, a second resistor R6, and a third diode CR4 connected in series in this order between one end (7) of the second secondary winding (7-8) and the other end (8) of the second secondary winding (7-8), and a capacitor C1 connected in parallel with the Zener diode CR5.

[0050] The cathode of the Zener diode CR5 is connected to one end (7) of the second secondary winding (7-8). The anode of the Zener diode CR5 is connected to the anode of the third diode CR4 via a second resistor R6. The cathode of the third diode CR4 is connected to the other end (8) of the second secondary winding (7-8).

[0051] In this example, the Zener voltage of the Zener diode CR5 is set to 5.1 V. The capacitor C1 holds the second induced voltage as a holding voltage during the ON period.

[0052] On the other hand, the discharge circuit 124 includes a control transistor Q2, a third resistor R3, a fourth resistor R7, and the first resistor R4. In the illustrated example, the control transistor Q2 is a PNP transistor.

[0053] The emitter of the control transistor Q2 is connected to the cathode of the second diode CR3. The collector of the control transistor Q2 is connected to the anode of the Zener diode CR5. A third resistor R3 is connected between the base of the control transistor Q2 and the cathode of the first diode CR2. A fourth resistor R7 is connected between the cathode of the first diode CR2 and the anode of the Zener diode CR5.

[0054] Therefore, the control transistor Q2 is turned on during the OFF period, and the voltage held in the capacitor C1 is discharged as an OFF driving voltage between the gate and source of the semiconductor switching element Q3.

[0055] The illustrated drive circuit 10 further includes a fifth resistor R5 and a sixth resistor R8. The fifth resistor R5 is connected between the gate and source of the semiconductor switching element Q3. The sixth resistor R8 is connected in parallel with the capacitor C1.

[0056] FIG. 4 is a waveform diagram showing a drive waveform supplied between the gate and source of the semiconductor switching element Q3.

[0057] [Explanation of the operation of the embodiment] Next, the operation of the drive circuit 10 shown in FIG. 3 will be described with reference to FIG.

[0058] An ON signal (High) of the PWM control signal generator 14 is transmitted to the gate of the switching element Q1 via resistor R1. In response to this ON signal, the switching element Q1 drives the pulse transformer T1 (i.e., causes current to flow through the primary winding (3-4) of the pulse transformer T1). A first induced voltage of N2 × Vcc / N1 (equivalent to +20 V in this example) is induced in the first secondary winding (5-6) of the driven pulse transformer T1. This induced first induced voltage is supplied as an ON drive voltage between the gate and source of the semiconductor switching element Q3 via first transmission circuit 11 (see the ON section in FIG. 4).

[0059] In parallel with this operation, a second induced voltage of N3 × Vcc / N1 is induced in the second secondary winding (7-8) of the driven pulse transformer T1. This induced second induced voltage is stored as a holding voltage in capacitor C1 of holding circuit 122 of second transfer circuit 12. This stored holding voltage is equal to −5 V. However, at this time, control transistor Q2 of release circuit 124 is in the OFF state, so the stored holding voltage is not supplied between the gate and source of semiconductor switching element Q3.

[0060] After that, the control signal generator 14 transmits an OFF signal (Low) of the PWM control signal to the gate of the switching element Q1 via the resistor R1. In response to this OFF signal, the switching element Q1 stops driving the pulse transformer T1. As a result, the first and second induced voltages are not induced in the first secondary winding (5-6) and the second secondary winding (7-8).

[0061] At the same time, the control transistor Q2 of the discharge circuit 124 turns on (i.e., transitions to the ON state). In response to this transition of the control transistor Q2 to the ON state, the holding voltage (-5V) stored in the capacitor C1 of the holding circuit 122 is supplied as an OFF drive voltage between the gate and source of the semiconductor switching element Q3 via the control transistor Q2 and the first resistor R4 (see the OFF section in FIG. 4).

[0062] [Explanation of Effects of the Embodiments] Next, the effects of this embodiment will be described.

[0063] The above-described embodiment of the present invention provides the following advantages.

[0064] The effect of the embodiment is that it is possible to provide an optimal drive waveform required to drive a semiconductor switching element such as a SiC-FET at low cost, with a small number of parts, and with high reliability.

[0065] The present invention is not limited to the above-described embodiment, and various modifications of the components can be made without departing from the spirit of the invention. Furthermore, various inventions can be created by appropriately combining multiple components.

[0066] For example, in the above embodiment, the control transistor constituting the discharge circuit 124 of the second transmission circuit 12 is a PNP transistor Q2, but the present invention is not limited to this. That is, the control transistor according to the present invention may be any type that turns off when driving the semiconductor switching element Q3 to ON and turns on when driving the semiconductor switching element Q3 to OFF. Also, in the above embodiment, the switching element for driving the pulse transformer T1 is an N-channel SiC-FET Q1, but the present invention is not limited to this. That is, the switching element according to the present invention may be any type that can drive the pulse transformer T1. Furthermore, in the above embodiment, the semiconductor switching element driven by the drive circuit 10 is an N-channel SiC-FET Q3, but the present invention is not limited to this. That is, the semiconductor switching element to which the present invention is applied may be any type that requires a negative voltage to be applied between the gate and source when turning it OFF.

[0067] Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the above-described embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. [Industrial Applicability]

[0068] A drive circuit according to the present invention can be used in the technical fields of AC / DC converters, DC / DC converters, inverters, motor control, uninterruptible power systems (UPS), and power conversion of renewable energy. [Explanation of symbols]

[0069] 10. Drive circuit 11 First transmission circuit 12 Second transmission circuit 122 Holding circuit 124 Emission circuit 14 Control Signal Generator Q1 switching element Q2 control transistor Q3 Semiconductor switching element T1 pulse transformer

Claims

1. A drive circuit (10) for driving a semiconductor switching element (Q3) having a grounded source and gate, a pulse transformer (T1) having at least one primary winding, a first secondary winding, and a second secondary winding; a switching element (Q1) connected in series with the primary winding and driving the pulse transformer (T1) in response to a PWM control signal; a first transmission circuit (11) connected between the first secondary winding and the gate-source of the semiconductor switching element (Q3), for transmitting a first induced voltage induced in the first secondary winding to the gate-source of the semiconductor switching element (Q3) as an ON drive voltage which is a positive voltage; a second transmission circuit (12) connected between the second secondary winding and the gate-source of the semiconductor switching element (Q3), for transmitting a second induced voltage induced in the second secondary winding between the gate and source of the semiconductor switching element (Q3) as an OFF drive voltage, which is a negative voltage; and The semiconductor switching element (Q3) is made of a silicon carbide voltage-effect transistor (SiC-FET), A DC voltage of Vcc is supplied to the primary winding, If the number of turns of the primary winding is N1 and the number of turns of the first secondary winding is N2, then: The first induced voltage is expressed as N2×Vcc / N1, The peak value of the ON driving voltage is +20 V, the OFF drive voltage is −5 V; The PWM control signal is a signal that alternates between an ON signal in an ON period and an OFF signal in an OFF period, The switching element (Q1) flows a current through the primary winding in response to the ON signal, The first transmission circuit (11) transmits the first induced voltage as the ON drive voltage between the gate and source of the semiconductor switching element (Q3) during the ON section; The second transmission circuit (12) a holding circuit (122) that holds the second induced voltage as a holding voltage during the ON period; a discharge circuit (124) that discharges the holding voltage as the OFF drive voltage between the gate and source of the semiconductor switching element (Q3) during the OFF period; Including, the first transmission circuit (11) includes a first diode (CR2), a second diode (CR3), and a first resistor (R4) connected in series in this order between one end of the first secondary winding and the gate of the semiconductor switching element (Q3); The other end of the first secondary winding is grounded, One end of the second secondary winding is grounded, The holding circuit (122) a Zener diode (CR5), a second resistor (R6), and a third diode (CR4) connected in series in this order between one end of the second secondary winding and the other end of the second secondary winding; a capacitor (C1) connected in parallel to the Zener diode (CR5); Including, The capacitor (C1) holds the second induced voltage as the holding voltage during the ON period. Drive circuit.

2. The discharge circuit (124) a control transistor (Q2) whose emitter is connected to the cathode of the second diode (CR3) and whose collector is connected to the anode of the Zener diode (CR5); a third resistor (R3) connected between the base of the control transistor (Q2) and the cathode of the first diode (CR2); a fourth resistor (R7) connected between the cathode of the first diode (CR2) and the anode of the Zener diode (CR5); the first resistor (R4); Including, The control transistor (Q2) is turned on during the OFF period to discharge the voltage held in the capacitor (C1) as the OFF driving voltage between the gate and source of the semiconductor switching element (Q3). The drive circuit of claim 1 .

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