Totem pole PFC circuit control method and device based on improved SOGI-PLL

Abstract

The invention discloses a totem-pole PFC circuit control method and device based on an improved SOGI-PLL, and belongs to the technical field of totem-pole PFC circuits, and the method comprises the steps: collecting the input voltage, input current and bus voltage of a totem-pole PFC circuit; synchronous phase information of the power grid voltage is obtained through an improved second-order generalized integral phase-locked loop; generating a current amplitude reference signal, and combining the current amplitude reference signal with the synchronous phase information to synthesize a current reference signal; generating a pulse width modulation signal for controlling a high-frequency switching tube; and a switching signal of the power frequency switching tube is generated based on the synchronous phase information, and the power frequency switching tube and the high-frequency switching tube are driven in combination with the pulse width modulation signal, so that the action time sequence is synchronous with the phase of the power grid voltage, and therefore, waveform tracking of the input current is realized, and current distortion at the zero crossing point is suppressed. Precise phase synchronization is realized based on the improved SOGI-PLL, totem pole PFC zero-crossing current distortion is effectively suppressed, and the power factor and waveform quality are improved.

Description

A totem pole PFC circuit control method and device based on an improved SOGI-PLL Technical Field

[0001] This invention belongs to the field of totem pole PFC circuit technology, and more specifically, relates to a totem pole PFC circuit control method and device based on an improved SOGI-PLL. Background Technology

[0002] With the rapid development of power electronics technology, high-efficiency, high-power-factor, and low-harmonic-pollution power conversion systems have become a core requirement in industrial power supplies, new energy, and electric vehicles. Totem-pole PFC circuits, due to their high efficiency and high power density, are gradually replacing traditional bridge PFCs and becoming the mainstream front-end rectifier topology. This circuit adopts a bridgeless design, utilizing high-speed switching devices to achieve a bidirectional current path, and can achieve a power factor close to 1 in boost mode, making it widely used in medium- and high-power AC-DC converters.

[0003] However, a long-standing key technical challenge in the actual operation of totem-pole PFC is the significant distortion and abrupt change in the input current near the zero-crossing point of the grid voltage, known as "zero-crossing distortion." This phenomenon not only increases the total harmonic distortion rate of the input current, reducing the system power factor, but may also lead to excessive electromagnetic interference and decreased system efficiency, severely restricting the application of totem-pole PFC in high-power-quality applications. Traditional solutions based on zero-crossing detection or simple software phase-locked loops are highly susceptible to noise, harmonics, and voltage distortion near the zero-crossing point of the grid voltage because the signal amplitude approaches zero, leading to phase detection deviations or even loss of lock-in. This phase error is directly transmitted to the reference signal generation stage of the current loop, causing the inductor current reference to be out of sync with the actual voltage, exacerbating the zero-crossing distortion.

[0004] In existing technologies, to address the performance optimization problem of totem-pole PFCs, some solutions reduce switching losses by adjusting the pulse width of the switching unit when the input current is low. However, this method cannot maintain the operation of high-frequency switching transistors near the zero-crossing point of the grid voltage, leading to current tracking delay and easily causing bus voltage fluctuations and current distortion. Another phase-locked loop (PLL) scheme uses an improved second-order generalized integrator to extract the grid fundamental component and employs a low-pass filter to suppress DC offset. However, its dynamic response is slow, and DC suppression takes a long time to converge when the grid voltage changes abruptly, making it difficult to adapt to rapidly changing operating conditions. These shortcomings limit the performance and overall robustness of totem-pole PFCs near the zero-crossing point. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a totem pole PFC circuit control method and device based on an improved SOGI-PLL.

[0006] The present invention adopts the following technical solution.

[0007] The first aspect of this invention provides a totem-pole PFC circuit control method based on an improved SOGI-PLL. The totem-pole PFC circuit includes an upper arm and a lower arm, each arm including a power frequency switch and a high-frequency switch. The method includes: acquiring the input voltage, input current, and bus voltage of the totem-pole PFC circuit; obtaining the synchronization phase information of the grid voltage through an improved second-order generalized integral phase-locked loop based on the input voltage; generating a current amplitude reference signal based on the bus voltage and its target value, and synthesizing a current reference signal by combining the synchronization phase information; generating a pulse width modulation signal for controlling the high-frequency switch based on the current reference signal and the input current; generating a switching signal for the power frequency switch based on the synchronization phase information, and driving the power frequency switch and the high-frequency switch by combining the pulse width modulation signal, so that the operating timing of the power frequency switch and the high-frequency switch is synchronized with the phase of the grid voltage, thereby realizing waveform tracking of the input current and suppressing current distortion at zero crossings.

[0008] Optionally, obtaining the synchronization phase information of the grid voltage through the improved second-order generalized integral phase-locked loop includes: performing cascaded notch filtering on the input voltage to filter out harmonics of a preset number; performing second-order generalized integral resonance processing on the filtered voltage signal to separate the in-phase and quadrature components of the fundamental voltage and suppress DC offset in the signal; and calculating and outputting the fundamental phase and its sine value of the grid voltage through the phase-locked loop based on the in-phase and quadrature components as the synchronization phase information.

[0009] Optionally, the suppression of DC offset in the signal includes: extracting the DC component contained in the filtered voltage signal by performing an integral operation on the voltage error signal during the second-order generalized integral resonance processing; and feeding the extracted DC component as a compensation amount back to the operation loop of the resonance processing to compensate for the DC offset in the filtered voltage signal.

[0010] Optionally, generating the pulse width modulation signal for controlling the high-frequency switching transistor includes: receiving a duty cycle command based on the current reference signal and the input current; generating a carrier signal synchronized with the synchronization phase information; comparing the duty cycle command with the carrier signal to generate a pulse width modulation pulse; and allocating the pulse width modulation pulse as a drive signal for controlling the high-frequency switching transistors in the upper and lower bridge arms according to the synchronization phase information.

[0011] Optionally, generating the switching signal of the power frequency switch based on the synchronization phase information includes: determining the half-cycle interval of the grid voltage according to the synchronization phase information; when it is determined to be in the positive half-cycle interval, generating a drive signal to control the power frequency switch of the lower bridge arm to turn on and the power frequency switch of the upper bridge arm to turn off; when it is determined to be in the negative half-cycle interval, generating a drive signal to control the power frequency switch of the upper bridge arm to turn on and the power frequency switch of the lower bridge arm to turn off.

[0012] A second aspect of this invention provides a totem pole PFC circuit control device based on an improved SOGI-PLL, used to implement the totem pole PFC circuit control method based on an improved SOGI-PLL described in the first aspect of this invention. The device includes: an input voltage detection unit, an input current detection unit, a bus voltage detection unit, a control unit, and a drive unit. The input voltage detection unit is used to acquire the input voltage of the totem pole PFC circuit; the input current detection unit is used to acquire the input current of the totem pole PFC circuit; the bus voltage detection unit is used to acquire the bus voltage of the totem pole PFC circuit; and the control unit is connected to the input voltage detection unit and the bus voltage detection unit. The control unit is connected to the measurement unit, the input current detection unit, and the bus voltage detection unit. The control unit is used to perform the following: based on the input voltage, obtain the synchronous phase information of the grid voltage through an improved second-order generalized integral phase-locked loop; generate a current amplitude reference signal based on the bus voltage and its target value, and synthesize a current reference signal by combining the synchronous phase information; generate a pulse width modulation command based on the current reference signal and the input current; generate a power frequency switch switching command based on the synchronous phase information; the drive unit is connected to the control unit and is used to generate and output drive signals to the corresponding power frequency switch and high frequency switch according to the pulse width modulation command and the power frequency switch switching command.

[0013] Optionally, the control unit includes an improved second-order generalized integral phase-locked loop module, a voltage loop controller, a current loop controller, and a PWM generation module, wherein: the improved second-order generalized integral phase-locked loop module is used to obtain the synchronization phase information based on the input voltage; the voltage loop controller is used to generate the current amplitude reference signal based on the bus voltage and its target value; the current loop controller is used to generate the pulse width modulation command based on the current reference signal and the input current; and the PWM generation module is used to generate the power frequency switching command based on the synchronization phase information and process the pulse width modulation command.

[0014] A third aspect of the present invention provides a totem pole PFC circuit, comprising a totem pole PFC circuit control device based on an improved SOGI-PLL as described in the second aspect of the present invention.

[0015] A fourth aspect of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded onto the processor, it implements a totem pole PFC circuit control method based on an improved SOGI-PLL according to a first aspect of the present invention.

[0016] A fifth aspect of this invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements a totem-pole PFC circuit control method based on an improved SOGI-PLL, as described in the first aspect of this invention. Compared with the prior art, the beneficial effects of this invention include at least the following: 1. This invention accurately obtains the grid synchronization phase through an improved SOGI-PLL, ensuring that the switching action is strictly synchronized with the grid zero-crossing point, thus suppressing current distortion of the totem-pole PFC circuit at the zero-crossing point.

[0017] 2. This invention effectively filters out specific harmonics and separates the fundamental component by performing cascaded notch filtering and resonance processing on the input voltage, thereby improving the phase-locked loop accuracy and anti-interference capability under harmonic pollution conditions.

[0018] 3. This invention suppresses DC offset in the signal through an integral compensation loop, thereby enhancing the system's robustness to DC components and avoiding phase detection errors caused by DC interference.

[0019] 4. This invention achieves precise control of high-frequency switching transistors by generating a carrier wave synchronized with the phase and comparing it to generate PWM, thereby optimizing the dynamic performance and stability of current tracking.

[0020] 5. This invention controls the switching of the power frequency switch tube in the half-cycle interval based on the synchronous phase information, which reduces the switching loss of the power frequency tube and improves the overall system efficiency.

[0021] 6. This invention constructs a complete closed-loop control system through integrated detection, control and drive units, which improves the control accuracy and reliability of the totem pole PFC.

[0022] 7. This invention clearly divides the control unit into a phase-locked loop, voltage loop, current loop and PWM generation module through modular design, which optimizes the system architecture and facilitates debugging and functional expansion.

[0023] 8. By integrating the control device into the totem pole PFC main circuit, the present invention achieves a high degree of synergy between control and power topology, thereby improving the power density and performance consistency of the product.

[0024] 9. The present invention implements the control method in an electronic device through a computer program, giving the control strategy the advantages of being digital, programmable, and easy to upgrade.

[0025] 10. By storing the control method in a computer-readable storage medium, the present invention achieves standardized preservation and cross-platform portability of the technical solution. Attached Figure Description

[0026] Figure 1 is an overall system block diagram of the present invention according to an embodiment of the present invention; Figure 2 is a structural block diagram of the improved SOGI-PLL according to an embodiment of the present invention; Figure 3 is a structural block diagram of the improved SOGI-QSG according to an embodiment of the present invention; Figure 4 is a flowchart of the method according to an embodiment of the present invention; Figure 5 is an implementation effect diagram according to an embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this invention.

[0028] In Embodiment 1, the present invention provides a totem pole PFC circuit control method based on an improved SOGI-PLL. The totem pole PFC circuit includes an upper bridge arm and a lower bridge arm. Each bridge arm includes a power frequency switch and a high frequency switch, as shown in Figure 4. The method includes: Step 1, acquiring the input voltage, input current and bus voltage of the totem pole PFC circuit.

[0029] Step 2: Based on the input voltage, obtain the synchronization phase information of the grid voltage through an improved second-order generalized integral phase-locked loop.

[0030] Preferably, the method of obtaining the synchronization phase information of the grid voltage through the improved second-order generalized integral phase-locked loop includes: performing cascaded notch filtering on the input voltage to filter out harmonics of a preset number; performing second-order generalized integral resonance processing on the filtered voltage signal to separate the in-phase component and quadrature component of the fundamental voltage and suppress DC offset in the signal; and calculating and outputting the fundamental phase and its sine value of the grid voltage through the phase-locked loop based on the in-phase component and the quadrature component as the synchronization phase information.

[0031] More preferably, the suppression of DC offset in the signal includes: extracting the DC component contained in the filtered voltage signal by performing an integral operation on the voltage error signal during the second-order generalized integral resonance processing; and feeding the extracted DC component as a compensation amount back to the operation loop of the resonance processing to compensate for the DC offset in the filtered voltage signal.

[0032] It should be noted that this invention, through the cascaded notch filtering, resonance separation, and DC suppression mechanism of the improved SOGI-PLL, can still accurately extract the fundamental phase near the zero-crossing point of the grid voltage. This solves the problem that traditional solutions are susceptible to harmonic and noise interference and lose lock-up under low-amplitude signals, and provides a reliable reference for the subsequent synchronous control of the switching transistors.

[0033] Step 3: Based on the bus voltage and its target value, generate a current amplitude reference signal, and combine it with the synchronization phase information to synthesize a current reference signal.

[0034] Step 4: Based on the current reference signal and the input current, generate a pulse width modulation signal for controlling the high-frequency switching transistor.

[0035] Preferably, generating the pulse width modulation signal for controlling the high-frequency switching transistor includes: receiving a duty cycle command based on the current reference signal and the input current; generating a carrier signal synchronized with the synchronization phase information; comparing the duty cycle command with the carrier signal to generate a pulse width modulation pulse; and allocating the pulse width modulation pulse as a drive signal for controlling the high-frequency switching transistors in the upper and lower bridge arms according to the synchronization phase information.

[0036] Step 5: Generate the switching signal of the power frequency switch based on the synchronization phase information, and drive the power frequency switch and the high frequency switch in combination with the pulse width modulation signal, so that the operation timing of the power frequency switch and the high frequency switch is synchronized with the phase of the grid voltage, thereby realizing waveform tracking of the input current and suppressing current distortion at the zero crossing point.

[0037] Preferably, generating the switching signal of the power frequency switch based on the synchronization phase information includes: determining the half-cycle interval of the grid voltage according to the synchronization phase information; when it is determined to be in the positive half-cycle interval, generating a drive signal to control the power frequency switch of the lower bridge arm to turn on and the power frequency switch of the upper bridge arm to turn off; when it is determined to be in the negative half-cycle interval, generating a drive signal to control the power frequency switch of the upper bridge arm to turn on and the power frequency switch of the lower bridge arm to turn off.

[0038] It should be noted that the method provided in this embodiment achieves high-precision phase synchronization near the zero-crossing point of the grid voltage by employing an improved SOGI-PLL with cascaded notch filtering and DC suppression functions. This solves the phase detection deviation problem caused by interference in traditional phase-locked loop methods under low-amplitude signals. Furthermore, this method utilizes this precise phase information to synchronously coordinate the PWM signal of the high-frequency switching transistor and the switching signal of the power frequency switching transistor, ensuring strict synchronization between the switching action and the zero-crossing point of the grid voltage. This eliminates current distortion caused by commutation asynchrony from the control timing perspective, ultimately achieving a smooth transition of the input current near the zero-crossing point, significantly improving the power factor and current waveform quality of the totem-pole PFC circuit.

[0039] This invention provides a totem pole PFC circuit control device based on an improved SOGI-PLL in Embodiment 2, used to implement the totem pole PFC circuit control method based on an improved SOGI-PLL described in Embodiment 1. The device includes: an input voltage detection unit, an input current detection unit, a bus voltage detection unit, a control unit, and a drive unit. The input voltage detection unit is used to acquire the input voltage of the totem pole PFC circuit; the input current detection unit is used to acquire the input current of the totem pole PFC circuit; the bus voltage detection unit is used to acquire the bus voltage of the totem pole PFC circuit; and the control unit is connected to the input voltage detection unit. The control unit is connected to the input current detection unit and the bus voltage detection unit. The control unit is used to perform the following: based on the input voltage, obtain the synchronous phase information of the grid voltage through an improved second-order generalized integral phase-locked loop; generate a current amplitude reference signal based on the bus voltage and its target value, and synthesize a current reference signal by combining the synchronous phase information; generate a pulse width modulation command based on the current reference signal and the input current; generate a power frequency switch switching command based on the synchronous phase information; the drive unit is connected to the control unit and is used to generate and output drive signals to the corresponding power frequency switch and high frequency switch according to the pulse width modulation command and the power frequency switch switching command.

[0040] Preferably, the control unit includes an improved second-order generalized integral phase-locked loop module, a voltage loop controller, a current loop controller, and a PWM generation module, wherein: the improved second-order generalized integral phase-locked loop module is used to obtain the synchronization phase information based on the input voltage; the voltage loop controller is used to generate the current amplitude reference signal based on the bus voltage and its target value; the current loop controller is used to generate the pulse width modulation command based on the current reference signal and the input current; and the PWM generation module is used to generate the power frequency switching command based on the synchronization phase information and process the pulse width modulation command.

[0041] It should be noted that the device provided in this embodiment integrates input voltage, current, and bus voltage detection units, and works in conjunction with a control unit including an improved SOGI-PLL module, a dual-loop controller, and a PWM generation module to construct a complete closed-loop control system. This device achieves real-time and accurate extraction of grid phase, stable regulation of bus voltage, and rapid tracking of input current. Its modular design not only hardware-encapsulates the process described in claims 1-5, solving the problems of low reliability and poor consistency in purely software or discrete control schemes, but also achieves safe isolation and power amplification of control signals through the drive unit, ensuring reliable driving of the power switching transistors by control commands. This results in stable and reliable suppression of zero-crossing distortion and improved overall efficiency at the system level.

[0042] In Embodiment 3, the present invention provides a totem pole PFC circuit, which includes the totem pole PFC circuit control device based on the improved SOGI-PLL described in Embodiment 2.

[0043] Embodiment 4 of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded onto the processor, it implements a totem pole PFC circuit control method based on an improved SOGI-PLL as described in Embodiment 1.

[0044] Embodiment 5 of the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements a totem pole PFC circuit control method based on an improved SOGI-PLL as described in Embodiment 1.

[0045] In Embodiment 6, the present invention provides an application example of a totem pole PFC circuit control device based on an improved SOGI-PLL, as shown in Figure 1. In this embodiment, the grid input unit is used to provide AC input voltage to provide energy input for the entire totem pole PFC circuit, and the output terminal is connected to one end of the power inductor L.

[0046] The totem pole PFC main circuit is a core power topology, including: upper bridge arm: composed of upper high-frequency transistor Q1 and upper power frequency transistor Q3.

[0047] Lower bridge arm: Composed of the lower high-frequency transistor Q2 and the lower power frequency transistor Q4.

[0048] The high-frequency transistor functions as high-frequency PWM modulation to achieve current ripple suppression and precise energy transfer to the bus; the power frequency transistor functions as continuous power frequency conduction to provide a freewheeling path for the inductor and reduce half-cycle energy transfer loss.

[0049] Power inductor L: Connected in series between the output of the mains input unit and the midpoint between the upper high-frequency transistor Q1 and the lower high-frequency transistor Q2, it is used for energy storage and current filtering.

[0050] Bus capacitor C: connected in parallel to the positive terminal of the bus (+U) bus ) and the negative terminal of the busbar (-U bus Between ) is used to stabilize bus voltage and filter out bus ripple.

[0051] The control device includes a detection unit group, a control unit, and a drive unit. The detection unit group contains three independent detection units responsible for acquiring key electrical signals, including: an input voltage detection unit connected in parallel between the positive and negative terminals of the power grid input unit.

[0052] Input current detection unit: connected in series between the positive output terminal of the mains input unit and the input terminal of the power inductor L.

[0053] Bus voltage detection unit: connected in parallel to the positive terminal of the bus (+U) bus ) and bus negative terminal (-U bus )between.

[0054] The control unit is the core of the control system and has the following built-in functional modules: An improved second-order generalized integral phase-locked loop module: its input terminal is connected to the acquisition signal u from the input voltage detection unit. in The output terminal outputs the fundamental phase signal θ of the power grid and the fundamental phase sine value (sinθ).

[0055] Voltage loop controller: The input terminals are connected to the preset target bus voltage u. ref The acquisition signal u of the bus voltage detection unit bus The output terminal outputs a reference signal i for the current amplitude. ref_amp .

[0056] Current loop controller: The input terminals are connected to the current reference signal i. ref (Current amplitude reference signal i) ref_amp The product signal of the fundamental phase sine sinθ and the acquisition signal i from the input current detection unit. in The output terminal outputs the duty cycle instruction D of the high-frequency transistor PWM control signal.

[0057] PWM generation module: The input terminal is connected to the duty cycle command D of the current loop controller and the phase signal θ of the improved second-order generalized integral phase-locked loop module, and the output terminal is connected to the drive unit, which can dynamically switch the drive logic of the switching transistor according to the phase signal.

[0058] The drive unit contains four independent isolated drive circuits. The input terminal is connected to the PWM generation module of the control unit, and the output terminal is connected to the gate of four switching transistors respectively, realizing high and low voltage isolation and power amplification of the control signal.

[0059] Furthermore, the improved SOGI-PLL module is the core sub-module of the control unit. Its core function is to accurately extract the fundamental phase at the zero-crossing point of the grid voltage (low amplitude, strong noise scenario) through a combination design of cascaded notch filter + SOGI resonance separation + phase-locked loop phase calculation, providing a reference for synchronous triggering of the switching transistor. Its internal structure corresponds to Figure 2: Internal block diagram of the improved SOGI-PLL, which includes: (1) Cascaded notch filter unit: near the resonant frequency, the SOGI-QSG's ability to attenuate harmonics in the right frequency band is much weaker than that in the left frequency band. The actual power frequency voltage will carry low-frequency odd harmonics such as 3rd, 5th, and 7th. These signals are all in the right frequency band, which can easily cause voltage waveform distortion and affect the extraction accuracy of information such as fundamental frequency and amplitude.

[0060] Therefore, a cascaded notch filter unit is connected in series at the front end of the phase-locked loop, and the input terminal is connected to the original voltage signal u collected by the input voltage detection unit. in It has three built-in second-order three-parameter notch filters for filtering u in The 3rd, 5th, and 7th odd harmonics in the loop are removed to avoid their impact on the phase-locked loop.

[0061] Its transfer function is shown in the following equation:

[0062] in, , Notch factor, The center frequency of the notch filter; The fundamental frequency of the grid voltage is 50Hz, which is taken here.

[0063] Determine the performance parameters of a second-order, three-parameter notch filter, including the notch center frequency. The notch depth (Depth, attenuation factor at the center frequency) and the notch bandwidth (Wb, the difference in cutoff frequencies when attenuated to -3dB) can be used to define the notch factor:

[0064]

[0065] (2) Improved second-order generalized integrator signal generator (SOGI-QSG): The input terminal is connected to the output signal of the cascaded notch filter unit (voltage u after harmonic filtering). in_filter The core component is a second-order generalized integrator with a preset resonant frequency of the power grid standard frequency (50Hz). Two cascaded integrators phase-shift the input signal, and the gain is adjusted using a proportional coefficient k to separate the fundamental component, outputting the fundamental in-phase component u. α (In phase with the grid fundamental voltage) and quadrature component u β(Lags the fundamental voltage by 90°). Based on the traditional structure, an improvement is made to extract the voltage error signal after gain. The DC component is estimated by an integrator. A signal with the same magnitude but opposite polarity as the DC component of the main signal is injected into the main circuit adder, thereby effectively enhancing its ability to suppress the DC component.

[0066] Its structure is shown in Figure 3, and its recursive function is shown in the following equation:

[0067] in, This is the gain coefficient. This is the DC suppression coefficient. (3) Phase-locked loop phase calculation unit: The core is a digital phase-locked loop (PLL), and the input terminal is connected to the improved SOGI-QSG u α u β Perform a Park transformation to convert it to u in the dq coordinate system. d u q Then, the fundamental phase is accurately tracked through the closed-loop logic of the phase detector, loop filter, and voltage-controlled oscillator.

[0068] The phase detector compares the input reference voltage with the phase angle of the sinusoidal waveform generated by the voltage-controlled oscillator to generate an error signal proportional to the phase angle error. The loop filter uses a PI controller to establish the dynamic response characteristics of the input and output, which can control the phase-locked error to zero in steady state. The voltage-controlled oscillator outputs a phase signal θ that is in phase with the fundamental wave of the power grid according to the control voltage, and at the same time generates the fundamental wave phase sine value sinθ through a multiplier.

[0069] Furthermore, the core of the synchronous triggering of the switching transistors is based on the precise phase signal of the improved SOGI-PLL module to realize the synchronous operation of the high-frequency transistors (Q1, Q2), the power frequency transistors (Q3, Q4) and the zero-crossing point of the power grid, so as to avoid the distortion of the current at the zero-crossing point. The specific implementation is as follows (the drive unit is only responsible for signal amplification, and the core control logic is in the PWM generation module of the control unit): (1) The power frequency switching transistors (Q3, Q4) synchronously trigger the PWM generation module to receive the phase signal θ in real time, and control the on and off of the power frequency switching transistors according to the positive and negative half-cycle intervals of the power grid voltage: when θ∈[0,π) (positive half-cycle of the power grid voltage), the PWM generation module outputs a high-level drive signal S4 to drive the lower power frequency transistor Q4 to turn on, and at the same time outputs a low-level drive signal S3 to turn off the upper power frequency transistor Q3.

[0070] When θ∈[π,2π) (negative half-cycle of grid voltage), the PWM generation module outputs a high-level drive signal S3 to drive the upper power frequency transistor Q3 to turn on, and at the same time outputs a low-level drive signal S4 to turn off the lower power frequency transistor Q4.

[0071] The power frequency switch remains continuously on during its half-cycle of conduction (without high-frequency switching), and only switches on and off at the zero-crossing point, thereby effectively reducing its switching losses.

[0072] (2) Synchronous triggering of high-frequency switching transistors (Q1, Q2) In order to achieve accurate tracking of the input current to the reference signal, the control of high-frequency switching transistors must ensure that the current reference is synchronized with the phase of the power grid, and the switching action sequence is also coordinated with the phase.

[0073] The PWM generation module generates a high-frequency triangular carrier signal, the initial phase of which is synchronized with the phase signal θ. The duty cycle command D output by the current loop controller is compared with the instantaneous value of the triangular carrier to generate a drive signal. The specific logic is as follows: During the positive half-cycle (θ∈[0,π)): If the duty cycle command D is greater than the instantaneous value of the triangular carrier, a high-level drive signal S2 is output to drive the lower high-frequency transistor Q2 to turn on, and a low-level drive signal S1 is output to turn off the upper high-frequency transistor Q1.

[0074] If the duty cycle instruction D is less than the instantaneous value of the triangular carrier, a low-level drive signal S2 is output to turn off the lower high-frequency transistor Q2, and a high-level drive signal S1 is output to turn on the upper high-frequency transistor Q1.

[0075] During the negative half-cycle (θ∈[π,2π)): If the duty cycle instruction D is greater than the instantaneous value of the triangular carrier, a high-level drive signal S1 is output to drive the upper high-frequency transistor Q1 to turn on, and a low-level drive signal S2 is output to turn off the lower high-frequency transistor Q2.

[0076] If the duty cycle instruction D is less than the instantaneous value of the triangular carrier, a low-level drive signal S1 is output to turn off the upper high-frequency transistor Q1, and a high-level drive signal S2 is output to turn on the lower high-frequency transistor Q2.

[0077] By using the above-mentioned synchronous triggering mechanism, combined with the smoothing of the duty cycle command near the zero crossing point, the current can be ensured to transition smoothly near the zero crossing point, effectively suppressing current distortion.

[0078] In Embodiment 7, this invention provides an application example of a totem pole PFC circuit control method based on an improved SOGI-PLL. Relying on the collaborative work of the detection unit, control unit, and drive unit described in Embodiment 6, the implementation effect is shown in Figure 5, including the following steps: Step 1, system initialization and signal acquisition start-up.

[0079] After the controller is powered on, the control unit performs initialization: configuring the parameters of the improved SOGI-PLL module, phase-locked loop, voltage loop, and current loop, etc.; starting the detection unit group: the input voltage detection unit, input current detection unit, and bus voltage detection unit start to continuously collect signals, and the collected signals are uploaded to the control unit in real time.

[0080] Step 2, Improved SOGI-PLL Phase-Locked Loop Operation. The control unit will input the voltage u collected by the input voltage detection unit. in The input is fed into the improved SOGI-PLL module, which follows the process of cascaded notch filtering → SOGI resonance separation of the fundamental wave → phase-locked loop phase calculation, and outputs the fundamental wave phase θ and the fundamental wave sine value sinθ.

[0081] Step 3, voltage loop control calculation. This is not limited to PI controllers or sliding mode controllers. The input is the target bus voltage reference signal u. ref and the current bus voltage u bus Output limiting is implemented to prevent overload caused by excessive current reference.

[0082] Step 4, current loop control calculation. This is not limited to PI controllers or sliding mode controllers. The input is the target current reference signal i. ref and the current input current i in Limit the output of the duty cycle instruction D to prevent the high-frequency tube from malfunctioning due to an excessively small or large duty cycle.

[0083] Step 5: Generation and output of high-frequency transistor drive signals. The PWM generation module of the control unit generates a triangular carrier wave; the duty cycle command D is compared with the triangular carrier wave to generate high-frequency transistor drive signals S1 and S2; drive signals S1 and S2 are input to the drive unit, and after isolation and amplification, they are output to the gates of the upper high-frequency transistor Q1 and the lower high-frequency transistor Q2 to control the on and off of the high-frequency transistors.

[0084] Step 6: Generation and output of power frequency transistor drive signals. The PWM generation module generates S3 and S4 drive signals based on phase θ to achieve half-cycle control of the upper power frequency transistor Q3 and the lower power frequency transistor Q4.

[0085] Step 7, cyclic execution and real-time adjustment. The control unit repeats steps two through six, updating the outputs of the phase-locked loop, voltage loop, and current loop, as well as the switching transistor drive signals, based on the latest acquired signals; it responds in real-time to grid voltage fluctuations and load changes, dynamically adjusting iref and duty cycle D.

[0086] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A control method for a totem-pole PFC circuit based on an improved SOGI-PLL, wherein the totem-pole PFC circuit comprises an upper bridge arm and a lower bridge arm, each bridge arm comprising a power frequency switch and a high-frequency switch, characterized in that, include: The input voltage, input current, and bus voltage of the totem pole PFC circuit are collected; based on the input voltage, the synchronization phase information of the grid voltage is obtained through an improved second-order generalized integral phase-locked loop; based on the bus voltage and its target value, a current amplitude reference signal is generated, and a current reference signal is synthesized by combining the synchronization phase information. Based on the current reference signal and the input current, a pulse width modulation signal for controlling the high-frequency switching transistor is generated; based on the synchronization phase information, a switching signal for the power frequency switching transistor is generated, and the power frequency switching transistor and the high-frequency switching transistor are driven in combination with the pulse width modulation signal, so that the operating timing of the power frequency switching transistor and the high-frequency switching transistor is synchronized with the phase of the grid voltage, thereby realizing waveform tracking of the input current and suppressing current distortion at zero crossings.

2. The totem pole PFC circuit control method based on the improved SOGI-PLL according to claim 1, characterized in that: The method of obtaining the synchronization phase information of the grid voltage through the improved second-order generalized integral phase-locked loop includes: performing cascaded notch filtering on the input voltage to filter out harmonics of a preset number; performing second-order generalized integral resonance processing on the filtered voltage signal to separate the in-phase and quadrature components of the fundamental voltage and suppress DC offset in the signal; and calculating and outputting the fundamental phase and its sine value of the grid voltage through the phase-locked loop based on the in-phase and quadrature components as the synchronization phase information.

3. The totem pole PFC circuit control method based on the improved SOGI-PLL according to claim 2, characterized in that: The suppression of DC offset in the signal includes: extracting the DC component contained in the filtered voltage signal by performing an integral operation on the voltage error signal during the second-order generalized integral resonance processing; and feeding the extracted DC component as a compensation amount back to the operation loop of the resonance processing to compensate for the DC offset in the filtered voltage signal.

4. The totem pole PFC circuit control method based on the improved SOGI-PLL according to claim 1, characterized in that: The step of generating a pulse width modulation signal for controlling the high-frequency switching transistor includes: receiving a duty cycle command based on the current reference signal and the input current; generating a carrier signal synchronized with the synchronization phase information; comparing the duty cycle command with the carrier signal to generate a pulse width modulation pulse; and allocating the pulse width modulation pulse as a drive signal for controlling the high-frequency switching transistors in the upper and lower bridge arms according to the synchronization phase information.

5. The totem pole PFC circuit control method based on the improved SOGI-PLL according to claim 1, characterized in that: The step of generating the switching signal for the power frequency switch based on the synchronization phase information includes: determining the half-cycle interval of the grid voltage according to the synchronization phase information; when it is determined to be in the positive half-cycle interval, generating a drive signal to control the power frequency switch of the lower bridge arm to turn on and the power frequency switch of the upper bridge arm to turn off; when it is determined to be in the negative half-cycle interval, generating a drive signal to control the power frequency switch of the upper bridge arm to turn on and the power frequency switch of the lower bridge arm to turn off.

6. A totem pole PFC circuit control device based on an improved SOGI-PLL, used to implement the totem pole PFC circuit control method based on an improved SOGI-PLL as described in any one of claims 1-5, characterized in that, include: The system comprises an input voltage detection unit, an input current detection unit, a bus voltage detection unit, a control unit, and a drive unit, wherein: the input voltage detection unit is used to acquire the input voltage of the totem-pole PFC circuit; the input current detection unit is used to acquire the input current of the totem-pole PFC circuit; the bus voltage detection unit is used to acquire the bus voltage of the totem-pole PFC circuit; the control unit is connected to the input voltage detection unit, the input current detection unit, and the bus voltage detection unit respectively, and the control unit is used to perform: based on the input voltage, obtaining the synchronization phase information of the grid voltage through an improved second-order generalized integral phase-locked loop; generating a current amplitude reference signal based on the bus voltage and its target value, and synthesizing a current reference signal by combining the synchronization phase information; A pulse width modulation command is generated based on the current reference signal and the input current; a power frequency switch switching command is generated based on the synchronization phase information; the driving unit is connected to the control unit and is used to generate and output driving signals to the corresponding power frequency switch and high frequency switch according to the pulse width modulation command and the power frequency switch switching command.

7. A totem pole PFC circuit control device based on an improved SOGI-PLL according to claim 6, characterized in that: The control unit includes an improved second-order generalized integral phase-locked loop module, a voltage loop controller, a current loop controller, and a PWM generation module, wherein: the improved second-order generalized integral phase-locked loop module is used to obtain the synchronization phase information based on the input voltage; the voltage loop controller is used to generate the current amplitude reference signal based on the bus voltage and its target value; the current loop controller is used to generate the pulse width modulation command based on the current reference signal and the input current; and the PWM generation module is used to generate the power frequency switching command based on the synchronization phase information and process the pulse width modulation command.

8. A totem-pole PFC circuit, characterized in that, The device includes a totem pole PFC circuit control device based on an improved SOGI-PLL as described in claim 6 or 7.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the computer program is loaded into the processor, it implements a totem pole PFC circuit control method based on an improved SOGI-PLL according to any one of claims 1-5.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements a totem pole PFC circuit control method based on an improved SOGI-PLL according to any one of claims 1-5.

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