Terminating and resuming prefetching in instruction cache

Abstract

To provide a method for efficiently performing cache control relating to prefetch.SOLUTION: In a processor (100) including a hierarchical cache subsystem, a memory controller subsystem (101) speculatively determines a hit or miss condition of a virtual address in a first memory cache (130) and speculatively translates a virtual address to a physical address; associated with the hit or miss condition and the physical address, configures a status to a valid state; responsive to receipt of a first indication from a CPU core (102) that no program instructions associated with the virtual address are needed, reconfigures the status to an invalid state; and responsive to receipt of a second indication from the CPU core (102) that a program instruction associated with the virtual address is needed, reconfigures the status back to a valid state.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Some memory systems include multi-level cache systems. When a request for a particular memory address is received from a processor core by the memory controller, the memory controller determines whether the data associated with that memory address resides in the first level cache (L1). If the data resides in the L1 cache, the data is returned from the L1 cache. If the data associated with the memory address does not reside in the L1 cache, the memory controller accesses the second level cache (L2). The L2 is larger than the L1 cache and can therefore hold more data. If the data resides in the L2 cache, the data is returned from the L2 cache to the processor core, and a copy is also stored in the L1 cache in case the same data is requested again. Additional memory level hierarchies are possible. Summary of the Invention

[0002] In one example, a system includes a processor, the processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss status of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. In association with the hit or miss status and the physical address, the memory controller subsystem configures a status to a valid state. In response to receiving a first indication from the CPU core that a program instruction associated with the virtual address is not needed, the memory controller subsystem reconfigures the status to an invalid state, and in response to receiving a second indication from the CPU core that a program instruction associated with the first virtual address is needed, the memory controller subsystem reconfigures the status to a valid state without additional accesses to a TAGRAM or address translation logic. [Brief explanation of the drawings]

[0003] [Figure 1] 1 illustrates a processor according to an example.

[0004] [Figure 2] 1 illustrates the promotion of an L1 memory cache access to a full L2 cache line access, according to an example.

[0005] [Figure 3] 1 is a flowchart illustrating performance improvement according to an example.

[0006] [Figure 4] 10 is another flowchart illustrating another performance improvement according to an example.

[0007] [Figure 5] 2 illustrates a system including the processor of FIG. 1. DETAILED DESCRIPTION OF THE INVENTION

[0008] 1 illustrates an example of a processor 100 including a hierarchical cache subsystem. The processor 100 in this example includes a central processing unit (CPU) core 102, a memory controller subsystem 101, an L1 data cache (L1D) 115, an L1 program cache (L1P) 130, and an L2 memory cache 155. In this example, the memory controller subsystem 101 includes a data memory controller (DMC) 110, a program memory controller (PMC) 120, and a unified memory controller (UMC) 150. In this example, at the L1 cache level, data and program instructions are divided into separate caches. Instructions to be executed by the CPU core 102 are stored in the L1P 130 and then provided to the CPU core 102 for execution. Meanwhile, data is stored in the L1D 115. CPU core 102 can read data from and write data to L1D 115 and has read access to L1P 130 (but no write access to L1P 130). L2 memory cache 155 can store both data and program instructions.

[0009] While the sizes of L1D 115, L1P 130, and L2 memory cache 155 may vary depending on the implementation, in one example, the size of L2 memory cache 155 is larger than the size of either L1D 115 or L1P 130. For example, L1D 115 may be 32 kilobytes in size and L1P may also be 32 kilobytes in size, while the size of the L2 memory cache may be 64 kilobytes to 4 megabytes in size. Also, the cache line size of L1D 115 may be the same as the cache line size of L2 memory cache 155 (e.g., 128 bytes), while the cache line size of L1P 130 may be smaller (e.g., 64 bytes).

[0010] When data is needed by the CPU core 102, the DMC 110 receives an access request for the target data from the CPU core 102. The access request may include an address (e.g., a virtual address) from the CPU core 102. The DMC 110 determines whether the target data resides in the L1D 115. If the data resides in the L1D 115, the data is returned to the CPU core 102. However, if the data requested by the CPU core 102 does not reside in the L1D 115, the DMC 110 provides an access request to the UMC 150. This access request may include a physical address generated by the DMC 110 based on a virtual address (VA) provided by the CPU core 102. The UMC 150 determines whether the physical address provided by the DMC 110 resides in the L2 memory cache 155. If the data resides in the L2 memory cache 155, the data is returned from the L2 memory cache 155 to the CPU core 102, and a copy is stored in the L1D 115. Additional layers of cache subsystems may also exist. For example, the L3 memory cache or system memory may be available to be accessed, so if data requested by CPU core 102 is not present in either L1D 115 or L2 memory cache 155, the data may be accessed in an additional cache level.

[0011] When the CPU core 102 needs additional instructions to execute relative to a program instruction, the CPU core 102 provides a VA 103 to the PMC 120. The PMC responds to the VA 103 provided by the CPU core 102 by initiating a workflow to return a prefetch packet 105 of program instructions to the CPU 102 for execution. The prefetch size of the packet varies depending on the implementation, but in one example, the size of the prefetch packet is equal to the size of a cache line of the L1P 130. If the L1P cache line size is, for example, 64 bytes, the prefetch packet returned to the CPU core 102 may also contain 64-byte program instructions.

[0012] The CPU core 102 also provides a prefetch count 104 to the PMC 120. In some implementations, the prefetch count 104 is provided to the PMC 120 after the CPU core 102 provides the VA 103. The prefetch count 104 indicates the number of prefetch units of program instructions following the prefetch unit starting with the VA 103. For example, the CPU core 102 may provide a VA of 200h. This VA is associated with a 64-byte prefetch unit starting with virtual address 200h. If the CPU core 102 wants the memory controller subsystem 101 to send additional instructions for execution following the prefetch unit associated with virtual address 200h, the CPU core 102 submits a prefetch count having a value greater than 0. A prefetch count of 0 means that the CPU core 102 does not need any more prefetch units. For example, a prefetch count of 6 requests that CPU core 102 retrieve and return 6 additional prefetch units' worth of instructions to CPU core 102 for execution. The returned prefetch units are shown in FIG. 1 as prefetch packets 105.

[0013] Continuing with the example of FIG. 1, PMC 120 includes TAGRAM 121, address translator 122, and registers 123. TAGRAM 121 contains a list of virtual addresses whose contents (program instructions) are cached in L1P 130. Address translator 122 translates the virtual addresses into physical addresses (PAs). In one example, address translator 122 generates a physical address directly from the virtual address. For example, the lower 12 bits of the VA may be used as the least significant 12 bits of the PA, and the most significant bits of the PA (above the lower 12 bits) are generated based on a set of tables configured in main memory prior to program execution. In this example, L2 memory cache 155 is addressable using physical addresses rather than virtual addresses. Register 123 stores a hit / miss indicator 124 from the TAGRAM 121 lookup, a physical address 125 generated by address translator 122, and a valid bit 126 (also referred to herein as a status bit) that indicates whether the corresponding hit / miss indicator 124 and physical address 125 are valid or invalid.

[0014] Upon receiving a VA 103 from the CPU 102, the PMC 120 performs a TAGRAM 121 lookup to determine whether the L1P 130 contains the program instruction associated with that virtual address. The result of the TAGRAM lookup is a hit or miss indicator 124. A hit means the VA is present in the L1P 130, and a miss means the VA is not present in the L1P 130. In the case of an L1P 130 hit, the target prefetch unit is retrieved from the L1P 130 by the PMC 120 and returned to the CPU core 102 as a prefetch packet 105.

[0015] In the event of an L1P 130 miss, the PA (generated based on the VA) is provided by the PMC 120 to the UMC 150, as indicated at 142. A byte count 140 is also provided from the PMC 120 to the UMC 150. The byte count indicates the number of bytes from the L2 memory cache 155 to be retrieved (if present), beginning with the PA 142. In one example, the byte count 140 is a multi-bit signal that encodes the number of bytes desired from the L2 memory cache 155. In one example, the line size of the L2 memory cache is 128 bytes, with each line divided into an upper half (64 bytes) and a lower half (64 bytes). Thus, the byte count 140 may encode the number 64 (if only the upper or lower 64 bytes from a given L2 memory cache line are needed) or 128 (if the entire L2 memory cache line is needed). In another example, the byte count may be a single bit signal where one state (e.g., 1) implicitly encodes an entire L2 memory cache line and another state (e.g., 0) implicitly encodes half an L2 memory cache line.

[0016] UMC 150 also includes TAGRAM 152. PA 142 received by UMC 150 from PMC 120 is used to perform a lookup into TAGRAM 152 to determine whether the target PA is a hit or a miss in L2 memory cache 155. If there is a hit in L2 memory cache 155, the target information, which may be half a cache line or an entire cache line depending on byte count 140, is returned to CPU core 102 and a copy is stored in L1P 130, from which the same program instruction is provided to CPU 102 the next time CPU core 102 attempts to fetch the same program instruction.

[0017] 1 , CPU core 102 provides VA 103 and prefetch count 104 to PMC 120. PMC 120 initiates the workflow for retrieving prefetch packets from L1P 130 or L2 memory cache 155, as described above. Using prefetch count 104 and the original VA 103, PMC 120 calculates additional virtual addresses and begins retrieving prefetch packets corresponding to those calculated VAs from L1P 130 or L2 memory cache 155. For example, if the prefetch count is 2 and VA 103 from CPU core 102 is 200h, PMC 120 calculates the next two VAs as 240h and 280h, rather than CPU core 102 providing each such VA to PMC 120.

[0018] 2 illustrates a specific example where optimizations result in improved performance of processor 100. As previously discussed, the line width of L2 memory cache 155 is greater than the line width of L1P. In one example, as shown in FIG. 2, L1P is 64 bytes wide and L2 memory cache 155 has a line width of 128 bytes. L2 memory cache 155 is organized as an upper half 220 and a lower half 225. UMC 150 may read an entire 128-byte cache line from L2 memory cache 155 or only one half of the L2 memory cache (either upper half 220 or lower half 225).

[0019] A given VA, when present in L2 memory cache 155, may translate to a particular PA that maps to either the lower half 225 or the upper half 220 of a given line of the L2 memory cache. Based on the addressing scheme used to represent the VA and PA, PMC 120 may determine whether a given VA maps to the lower half 225 or the upper half 220. For example, a particular bit (e.g., bit 6) in the VA may be used to determine whether the corresponding PA maps to the upper half or the lower half of a line of the L2 memory cache. For example, bit 6 being 0 may indicate the lower half, and bit 6 being 1 may indicate the upper half.

[0020] Reference numeral 202 illustrates an example of a VA of 200h provided by CPU core 102 to PMC 120, with a corresponding prefetch count of 6. Reference numeral 210 illustrates that the list of VAs running through the cache pipeline described above includes 200h (received from CPU core 102) and the next six consecutive virtual addresses 240h, 280h, 2c0h, 300h, 340h, and 380h (calculated by PMC 120).

[0021] Each address from 200h through 380h is processed as described above. Any or all of the VAs may be misses in L1P 130. PMC 120 may combine two consecutive VAs that miss in L1P 130 into a single L2 cache line access attempt. Thus, if 200h and 240h both miss in L1P 130, and the physical address corresponding to 200h corresponds to the lower half 225 of a particular cache line in L2 memory cache 155, and the physical address corresponding to 240h corresponds to the upper half 225 of the same cache line in L2 memory cache, PMC 120 may issue a single PA 142 to UMC 150 with a byte count 140 that specifies the entire cache line from the L2 memory cache. Thus, two consecutive VA misses in L1P 130 may be promoted to one full-line L2 memory cache lookup.

[0022] If the last VA in a series of VAs initiated by the CPU core 102 (e.g., VA380h in the VA series 210) maps to the lower half 225 of a cache line in the L2 memory cache 155, then, according to the described example, the entire cache line in the L2 memory cache 155 is retrieved, even if only the lower half 225 was needed. The same reaction occurs if the CPU provides the VA 103 to the PMC 120 with a prefetch count of 0, meaning that the CPU 102 needed only a single prefetch unit. The additional overhead, time, or power consumption expended to retrieve the entire cache line and provide the entire cache line to the L1P 130 is very small, if any. Because program instructions are often executed in linear order, it is generally highly likely that the program instructions in the upper half 220 will be executed following the execution of the instructions in the lower half 225 anyway. Therefore, the next set of instructions is received at very little cost, and such instructions are likely to be needed anyway.

[0023] 2 illustrates, via arrow 213, that VA380h maps to the lower half 225 of cache line 260 in L2 memory cache 155. PMC 120 determines this mapping, for example, via examination of one or more bits of the VA or its corresponding physical address following translation by address translator 122. PMC 120 promotes the lookup process to the full cache line with UMC 150 by presenting the PA associated with VA380h along with a byte count 104 that identifies the entire cache line. The entire 128-byte cache line (if present in L2 memory cache 155) is then retrieved and written to L1P 130 in two separate 64-byte cache lines, as shown at 265.

[0024] However, if the last VA in the series of VAs (or if there is only one VA for a prefetch count of 0) maps to the top half 220 of a cache line in L2 memory cache 155, PMC 120 requests UMC 150 to look up in its TAGRAM 152 and return only the top half of the cache line to CPU core 102 and L1P 130. The next PA may be in the bottom half 225 of the next cache line in L2 memory cache 155, and additional time, overhead, and power may be consumed to speculatively retrieve the next cache line, without certainty that CPU core 102 will need to execute these instructions.

[0025] 3 shows an example of a flowchart 300 for the above-described method. The operations may be performed in the order shown or in another order. Also, the operations may be performed sequentially, or two or more operations may be performed simultaneously.

[0026] At 302, the method includes receiving, by memory controller subsystem 101, a request to access N prefetch units of program instructions. In one implementation, this operation is performed by CPU core 102, which provides an address and a count value to PMC 120. The address may be a virtual address or a physical address, and the count value may indicate the number of additional prefetch units required by CPU core 102.

[0027] At 304, an index value I is initialized to a value of 1. This index value is used to determine when the last virtual address in a series of consecutive virtual addresses should be processed by PMC 120. At 306, the method determines whether prefetch unit I is a hit or a miss to L1P 130. This determination is made, in some instances, by determining whether the virtual address is present in the PMC's TAGRAM 121. There are two possible outcomes from determination 306: a hit or a miss.

[0028] If the virtual address is a hit in L1P 130, then at 308, the corresponding line in L1P 130 containing the desired prefetch unit is returned from L1P 130 and provided to CPU core 102 as a prefetch packet 105. Next, at 310, the index is incremented (I=I+1). If I has not yet reached N+1 (as determined in determination operation 312), the VA of the last one of the prefetch units has not yet been evaluated for a hit / miss determination, and control loops back to 306 to evaluate the next I prefetch unit for a hit or miss in L1P 130. When I reaches N+1, all N prefetch units have been evaluated, the corresponding program instructions have been provided to CPU core 102, and the process stops.

[0029] For a given Ith prefetch unit, if PMC 120 determines at 306 that there is a miss in L1P 130, then at 314 a determination is made as to whether I has reached a value of N. If I is not equal to N (indicating that the last VA in the series of VAs has not been reached), then at 316 the method includes memory controller subsystem 101 obtaining the program instruction from L2 memory cache 155 (if present therein, or, if not, from a third level cache or system memory). Index value I is then incremented at 318, and control loops back to decision 306.

[0030] If I reaches N at 314 (indicating that the last VA in the series of VAs has been reached), the method includes determining, at 320, whether the VA of the Ith prefetch unit maps to the lower half or the upper half of a cache line in the L2 memory cache 155. Examples of how this determination may be made are described above. If the VA of the Ith prefetch unit maps to the upper half, the method includes, at 322, retrieving program instructions from only the upper half of a cache line in the L2 memory cache.

[0031] However, if the VA of the I-th prefetch unit maps to the lower half, the method includes, at 324, promoting the L2 memory cache access to a full cache line access and, at 326, obtaining the program instructions from the full cache line of the L2 memory cache.

[0032] 1, as described above, following presentation of VA 103 from CPU core 102 to PMC 120, CPU core 102 may also provide PMC 120 with prefetch count 104. The prefetch count may be 0, meaning that CPU core 102 no longer requires instructions other than those contained in the prefetch unit beginning with VA 103. However, between receipt of VA 103 and the subsequent prefetch count, PMC 120 may be performing some work, as described below.

[0033] Upon receiving VA 103, PMC 120 performs a lookup in TAGRAM 121 to determine whether the first VA (provided by CPU core 102) is a hit or miss in L1P and then performs a VA-to-PA translation using address translator 122. PMC 120 also calculates a second VA (the next consecutive VA following the VA provided by the CPU core) before receiving prefetch count 104. PMC 120 speculatively accesses TAGRAM 121, determines the hit / miss status of the second VA using address translator 122, and populates register 123 with hit / miss indication 124 and PA 125. Valid bit 126 in register 123 is set to a valid state, thereby enabling further processing of the second VA as described above (e.g., retrieving the corresponding cache line from L1P 130, if present, or from L2 memory cache 155, if necessary).

[0034] However, before further processing of the second VA occurs, the CPU core 102 can send a prefetch count of 0 to the PMC 120, meaning that the CPU core does not need any prefetch units other than the prefetch unit beginning with the original VA 103. At this point, the PMC 120 is provided with a prefetch count of 0, and therefore, no prefetch unit associated with the second VA is needed. However, the PMC has also already determined the hit / miss status of the second VA and generated a corresponding PA. Both the hit / miss indicator 124 and the PA 125 are stored in register 123 by the time the 0 prefetch count is received by the PMC 120. The PMC 120 then changes the status of the valid bit 126 to indicate an invalid state, thereby eliminating further processing of the second VA. This situation (the valid bit set to an invalid state) is called a "kill," and therefore, the PMC 120 kills the processing of the second VA.

[0035] However, in some cases, CPU core 102 may determine that, despite the previous abort, the prefetch unit associated with the second VA should actually be retrieved from L1P 130 or L2 memory cache 155, as described above. For example, if CPU core 102 does not have further internal prediction information to inform it of the next requested instruction address, CPU core 102 informs PMC 120 that it should continue prefetching linearly starting from the last requested address. This situation may arise, for example, due to a misprediction of branch prediction logic in CPU core 102. CPU core 102 then issues resume signal 106 to PMC 120. PMC 120 responds to the resume signal by returning valid bit 126 to a valid state, thereby enabling continued processing of the second VA through the memory subsystem pipeline, as described above. In this manner, CPU 102 need not directly present the second VA to PMC 120. Instead, the PMC 120 may, for example, maintain the second VA in a register 123 and also maintain its hit / miss indicator 124, thereby avoiding the power consumption and time spent again determining the hit / miss status of the second VA and converting it to a PA.

[0036] 4 shows an example flowchart 400 for initiating, terminating, and resuming a memory address lookup. The operations may be performed in the order shown or in another order. Also, the operations may be performed sequentially, or two or more operations may be performed simultaneously.

[0037] At 402, the method includes receiving, by memory controller subsystem 101, an access request at a first VA. In one implementation, this operation is performed by CPU core 102, which provides the first VA to PMC 120. The method includes, at 404, determining whether the first VA is a hit or a miss in L1P 30. In one example, this operation is performed by accessing TAGRAM 121 of the PMC to determine the hit / miss status of the first VA. The first VA is translated to a first PA at 406, for example, by using address translator 122.

[0038] At 408, the method includes calculating a second VA based on the first VA. The second VA may be calculated by incrementing the first VA by a value to generate an address of a byte that is 64 bytes following the byte associated with the first VA. The method includes determining at 410 whether the second VA is a hit or a miss in L1P 30. In one example, this operation is accomplished by accessing TAGRAM 121 of the PMC to determine the hit / miss status of the second VA. The second VA is translated at 412 to a second PA by using address translator 122 as described above. At 414, the method includes updating a register (e.g., register 123) with hit / miss indicator 124 and the second PA. Also, valid bit 126 is configured to be valid.

[0039] PMC 120 then receives the prefetch count at 416. Next, if the prefetch count is greater than zero at 418, then at 420, program instructions from L1P 130 or L2 memory cache 155 (or additional levels) are retrieved as described above. However, if the prefetch count is zero, then at 422, valid bit 126 is changed to an invalid state. Thus, despite providing PMC 120 with a prefetch count of zero, CPU core 102 may provide a resume indication to PMC 120 (424). At 426, PMC 120 returns valid bit 126 to a valid state, and memory controller subsystem 101 then obtains (428) program instructions associated with the second PA from L1P, L2 memory cache, etc., as appropriate.

[0040] 5 illustrates an exemplary use of the processor 100 described herein. In this example, the processor 100 is part of a system-on-chip (SoC) 500 that includes the processor 100 and one or more peripheral ports or devices. In this example, the peripherals include a universal asynchronous transmitter (UART) 502, a universal serial bus (USB) port 504, and an Ethernet controller 506. The SoC 500 may perform any of a variety of functions implemented by program instructions executed by the processor 100, for example. Multiple processors 100 may be provided, and multiple CPU cores 102 may be included within a given processor 100.

[0041] As used herein, the term "couple" means either an indirect or direct wired or wireless connection. Thus, when a first device couples to a second device, the connection may be through a direct connection or through an indirect connection via other devices and connections. Also, as used herein, "based on" means "based at least in part on." Thus, if X is based on Y, X may be a function of Y and any number of other factors.

[0042] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the claims of the invention.

Claims

1. A device, a processor; a memory configured to store a set of instructions; a memory controller coupled to the processor and the memory, receiving an indication of a first address from the processor; performing an address translation on the first address to determine a second address; Retrieving from the memory a first subset of the set of memories associated with the second address; providing the processor with a first subset of the set of instructions; determining a third address based on the first address, the third address being contiguous with the first address; performing an address translation on the third address to determine a fourth address; receiving a count associated with the first address from the processor; determining whether to fetch from the memory a second subset of the set of instructions associated with the fourth address based on the count; the memory controller configured as follows: Including, the device.

2. 10. The device of claim 1, the memory controller includes a register; The memory controller: storing the fourth address and an indication that the fourth address is valid in the register; determining whether to fetch a second subset of the set of instructions from the memory to indicate that the fourth address is not valid when the count is zero; The device further configured as follows.

3. 3. The device of claim 2, the memory controller is further configured to determine whether to retrieve a second subset of the set of instructions from the memory by changing the indicator in the register to indicate that the fourth address is valid upon receiving a resume instruction.

4. 4. The device of claim 3, 10. A device, wherein the processor is configured to provide the restart indication based on a branch misprediction.

5. 3. The device of claim 2, the memory includes a level 1 (L1) cache and a level 2 (L2) cache; The device, wherein the memory controller is further configured to store in the register an indication of whether a second subset of the set of instructions is in the L1 cache.

6. 6. The device of claim 5, the memory controller includes a tag RAM; The device, wherein the memory controller is further configured to determine whether a second subset of the set of instructions is in the L1 cache based on the tag RAM.

7. 10. The device of claim 1, The device, wherein the memory controller is further configured to retrieve a second subset of the set of memories from the memory when the count is greater than zero.

8. 10. The device of claim 1, The device, wherein the first address and the third address are virtual addresses, and the second address and the fourth address are physical addresses.

9. 10. The device of claim 1, The device, wherein the memory controller is further configured to determine the third address without regard to the count and to perform address translation on the third address.

10. 10. The device of claim 1, The device, wherein the memory controller is further configured to retrieve the count after performing an address translation on the third address to determine a fourth address.

11. 1. A method comprising: receiving, by a memory controller, an indication of a first address and a count associated with the first address; performing, by the memory controller, an address translation on the first address to determine a second address; providing a first set of instructions stored at the second address by the memory controller to a processor; determining, by the memory controller, a third address that is contiguous with the first address based on the first address; performing, by the memory controller, an address translation on the third address to determine a fourth address; determining, by the memory controller, whether to provide the processor with a second set of instructions stored at the fourth address based on the count; A method comprising:

12. 12. The method of claim 11, storing the fourth address and an indication that the fourth address is valid in the register in a register; modifying an index in the register to indicate that the fourth address is not valid based on the count; The method further comprises:

13. 13. The method of claim 12, The method further comprising determining whether to change an indicator in the register to indicate that the fourth address is valid based on whether a resume indication is received.

14. 14. The method of claim 13, The method, wherein the restart indication is based on a branch misprediction.

15. 13. The method of claim 12, The method further comprising storing in the register an indication of whether the second set of instructions is in an L1 cache.

16. 12. The method of claim 11, The method, wherein determining whether to provide the second set of instructions provides the second set of instructions to the processor when the count is greater than zero.

17. 12. The method of claim 11, The method, wherein the first address and the third address are virtual addresses, and the second address and the fourth address are physical addresses.

18. 12. The method of claim 11, The method, wherein determining the third address and performing address translation on the third address are performed without regard to the count.

19. 12. The method of claim 11, The method, wherein the count is received after performing address translation on the third address.

20. The method of claim 15, the memory controller includes a tag RAM; The method further includes determining whether the second set of instructions is in the L1 cache based on the tag RAM.

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