Decoding method and decoding circuit for single channel communication

Abstract

To reduce circuit complexity and reduce chip packaging and wiring.SOLUTION: A method of decoding a single-channel communication includes the steps of: generating a low level of a clock signal based on a high level of a long- and short-code signal; generating a delay pulse signal based on the long- and short-code signal, a delay time length of the delay pulse signal being a half of a clock period; generating a high level of the clock signal based on the delay pulse signal; and generating a digital signal based on the clock signal and the long- and short-code signal. The decoding method simultaneously decodes a clock signal and a data signal.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] (Related Applications) This application claims priority to a Chinese patent application filed on October 15, 2021, with application number 202111200511.4, entitled "Single-channel communication encoding method, decoding method, encoding circuit and decoding circuit," the entire contents of which are incorporated herein by reference.

[0002] The present invention belongs to the field of analog-digital hybrid circuits, and specifically relates to a decoding method and a decoding circuit for single-channel communication. [Background technology]

[0003] A digital isolator is used for communication and consists of a source side and a secondary side that receives the signal transmitted from the source side.

[0004] Figure 1 shows a common method for isolated data and clock transmission, where the source side uses an isolated channel to transmit the data and clock signals to the isolated secondary side. This method requires two isolated channels, operates with high power consumption, and requires high wafer costs. It also requires more routing during chip packaging, resulting in high packaging costs.

[0005] Figure 2 shows a single-channel isolated communication system based on clock data recovery technology. The source side synchronizes with the clock data signal and transmits it serially to the isolated secondary side via a transmitter. The secondary side extracts the clock from the received data signal through a clock data recovery circuit, then uses the extracted clock to resample the data, ultimately obtaining the recovered clock and data signal.

[0006] Figure 3 shows the clock data recovery circuit and timing of a typical phase locked loop circuit.

[0007] The circuits shown in Figures 2 and 3 both have the following technical drawbacks: (1) They cannot communicate long strings of "0" or "1" signals. (2) The data code rate and phase of the transmitted signal are deviated from the frequency and phase of the voltage-controlled oscillator in the clock data recovery circuit at the receiving end, so it takes a long time to lock the frequency and phase, which makes it take a long time to establish communication. (3) The clock data recovery circuit must first lock the frequency and then lock the phase, which increases the number of control loops, making the design more complex and costly. Summary of the Invention

[0008] SUMMARY OF THE INVENTION An object of the present invention is to provide an efficient communication method that can simultaneously encode clock and data signals, reduce circuit complexity, and reduce chip packaging routing.

[0009] In order to achieve one of the above objects, one embodiment of the present invention provides an encoding method for single-channel communication, comprising: combining a clock signal and a data signal to generate a long-short code signal; the long-short code signal comprises a long code signal and a short code signal; a pulse width of the long code signal coincides with that of the clock signal; a pulse width of the short code signal coincides with that of the clock signal; and the long code signal has a duty cycle different from that of the short code signal.

[0010] As a further refinement of an embodiment of the present invention, the duty ratios of the long and short code signals satisfy the relation Tclk=TS+TL, where Tclk is the clock period, TS is the high level time of the short code signal, TL is the high level time of the long code signal, and TS is not equal to TL.

[0011] As a further improvement of one embodiment of the present invention, the step of combining the clock signal and the data signal to generate a long and short code signal includes: generating a first delayed clock signal based on a clock signal; generating a pulse signal based on the first delayed clock signal; generating a high level of a long code signal and a high level of a short code signal based on the pulse signal; generating a second delayed clock signal based on the first delayed clock signal; generating a low level of a short code signal based on the second delayed clock signal; generating a low level of the long code signal based on a clock signal; generating a data delayed signal based on the first delayed clock signal and a data signal; and selecting the long code signal or the short code signal based on the data signal to generate the long and short code signal.

[0012] In a further refinement of an embodiment of the present invention, the first delayed clock signal has a delay time TS relative to the clock signal, the second delayed clock signal has a delay time TS relative to the first delayed clock signal, and the data delayed signal has a delay time TS relative to the data signal.

[0013] As a further improvement of one embodiment of the present invention, the step of combining the clock signal and the data signal to generate the long and short code signal includes: generating a first pulse signal based on the clock signal, generating a first delayed clock signal based on the clock signal, generating a second delayed clock signal based on the first delayed clock signal, generating a second pulse signal based on the second delayed clock signal, generating a third pulse signal based on the first delayed clock signal, generating a high level of the long code signal or a high level of the short code signal based on the third pulse signal, generating a data delayed signal based on the data signal and the first delayed clock signal, selecting the first pulse signal or the second pulse signal based on the data delayed signal, generating a low level of the short code signal based on the selected second pulse signal, and generating a low level of the long code signal based on the selected first pulse signal.

[0014] In order to achieve one of the above objects of the present invention, one embodiment of the present invention comprises a first delay circuit used to generate a first delayed clock signal based on a clock signal; a pulse generator used to generate a pulse signal based on the first delayed clock signal; a reset terminal receiving the pulse signal and outputting a high level long code signal; a clock terminal receiving the clock signal and using the clock signal to trigger the output of a low level long code signal; a reset terminal receiving the pulse signal and using the short code trigger to output a high level short code signal; and a pulse generator used to generate a second delayed clock signal based on the first delayed clock signal. and a second delay circuit connected to the long code trigger, the short code trigger receiving the second delayed clock signal at a clock end and outputting a low level short code signal, the short code trigger having a clock end receiving the first delayed clock signal and a data end coupled to a data signal, and an output end used for outputting a data delayed signal; and a data selector having a first input end coupled to the output end of the long code trigger, a second input end coupled to the output end of the short code trigger, and a selection end coupled to the output end of the selection trigger, the data selector being used to select and output the long code signal or the short code signal according to the data delayed signal to form a long-short code signal.

[0015] In order to achieve one of the above objects of the invention, one embodiment of the present invention includes a first delay circuit used to generate a first delayed clock signal according to a clock signal, a second delay circuit used to generate a second delayed clock signal according to the first delayed signal, a first pulse generator used to generate a first pulse signal according to the first delayed clock signal, a second pulse generator used to generate a second pulse signal according to the second delayed clock signal, a third pulse generator used to generate a third pulse signal according to the first delayed clock signal, a selection trigger having a clock terminal receiving the first delayed clock signal, a data terminal coupled to a data signal, and an output terminal used to output a data delayed signal; a data selector having a first input terminal coupled to the first pulse generator, a second input terminal coupled to the second pulse generator, a selection terminal coupled to a data delay signal, and used to select a first pulse signal or a second pulse signal according to the data delay signal; and an output trigger having a reset terminal coupled to the third pulse generator and a clock terminal coupled to the output terminal of the data selector, and used to generate a high level of a long code signal or a high level of a short code signal according to the third pulse signal, the clock terminal receiving the first pulse signal and generating a low level of a long code signal, and the clock terminal receiving the second pulse signal and generating a low level of a short code signal.

[0016] In order to achieve one of the above objects of the invention, one embodiment of the present invention provides a decoding method for single-channel communication, including the steps of: generating a low level of a clock signal according to a high level of a long and short code signal; generating a delayed pulse signal according to the long and short code signal, where the delay time of the delayed pulse signal is half a clock period; generating a high level of a clock signal according to the delayed pulse signal; and generating a digital signal according to the clock signal and the long and short code signal.

[0017] As a further improvement to an embodiment of the present invention, the step of generating a delayed pulse signal according to the long and short code signal further includes: generating a long and short code delay signal according to the long and short code signal; and controlling a delay time of the long and short code signal according to a phase difference between the long and short code delay signal and the long and short code signal.

[0018] As a further improvement of one embodiment of the present invention, controlling the delay times of the long and short code signals according to a phase difference between the long and short code delay signals and the long and short code signals further includes converting the phase difference signal into a voltage signal, and controlling the delay times of the long and short code delay signals according to the voltage signal.

[0019] In order to achieve one of the above objects of the invention, one embodiment of the present invention provides a decoding circuit for single-channel communication, including: a delay pulse circuit used to delay a long and short code signal by half a clock period to generate a long and short code delayed signal; a pulse generator used to generate a delayed pulse signal according to the long and short code delay signal; a clock trigger having a clock terminal to which the long and short code signal is coupled and which generates a low level clock signal according to the long and short code signal, and a reset terminal coupled to the output terminal of the pulse generator, the clock trigger being used to generate a high level clock signal according to the delayed pulse signal; and a digital signal trigger having a clock terminal coupled to the output terminal of the clock trigger and a data terminal to which the long and short code signal is coupled, the digital signal being used to generate a digital high level or a digital low level according to a trigger clock signal.

[0020] As a further improvement of an embodiment of the present invention, the delay pulse circuit comprises a delay circuit and a pulse circuit, the delay circuit comprising: a delay circuit intermediate stage used for converting the long / short code signal into a long / short code delayed signal; a frequency / phase discriminator used for detecting a phase difference between the long / short code delayed signal and the long / short code signal; a charge pump used for converting the phase difference into a current signal; and a low pass filter used for converting the current signal into a voltage signal, the delay circuit intermediate stage being coupled to the low pass filter, and the delay circuit intermediate stage being used for receiving the voltage signal to control a delay time of the long / short code delayed signal.

[0021] As a further improvement of one embodiment of the present invention, the decoding circuit further comprises a flip-flop detector, an oscillator and a data selector, wherein during non-communication, the flip-flop detector outputs a low level and the data selector couples the output of the oscillator to a delay locked loop to establish a voltage signal, and during communication, the flip-flop detector outputs a high level and the data selector couples the long / short code signal to the delay pulse circuit. [Effects of the Invention]

[0022] The present invention has at least the following beneficial technical effects compared with the prior art. (1) The long and short code encoding method is used to combine the data signal and the clock signal for communication, which results in higher efficiency and lower power consumption. (2) Supporting single-channel communication reduces chip packaging and routing, thereby reducing chip manufacturing costs. (3) The structure of the encoding circuit and the decoding circuit is simple, which can reduce the complexity of the circuit design. (4) The communication establishment time is short. [Brief explanation of the drawings]

[0023] [Figure 1] FIG. 1 is a schematic diagram showing a communication circuit of the prior art. [Figure 2]FIG. 1 is a schematic diagram illustrating another prior art communication circuit. [Figure 3] FIG. 1 is a schematic diagram illustrating yet another prior art communication circuit. [Figure 4] 1 is a schematic diagram showing a communication circuit structure of the present invention; [Figure 5] FIG. 2 is a schematic diagram showing encoding timing according to the present invention. [Figure 6] FIG. 2 is a schematic diagram showing the flow of the encoding method of the present invention. [Figure 7] 1 is a schematic diagram showing an encoding circuit structure of the present invention; [Figure 8] FIG. 2 is a schematic diagram showing the timing of the encoding circuit of the present invention. [Figure 9] FIG. 10 is a schematic diagram showing the flow of another encoding method of the present invention. [Figure 10] FIG. 2 is a schematic diagram showing another circuit structure of the present invention. [Figure 11] FIG. 10 is a schematic diagram showing another circuit timing of the present invention. [Figure 12] FIG. 2 is a schematic diagram showing the flow of the decoding method of the present invention. [Figure 13] 1 is a schematic diagram showing a decoding circuit structure of the present invention; [Figure 14] FIG. 2 is a schematic diagram illustrating the decoding circuit timing of the present invention. [Figure 15] 1 is a schematic diagram showing the structure of a delay circuit included in a decoding circuit of the present invention; [Figure 16] 1 is a schematic diagram showing the structure of a circuit for pre-establishing a control voltage included in a decoding circuit of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0024] In order to help those skilled in the art understand the technical solution of the present invention, the technical solution of the present invention will be described in more detail below with reference to the drawings. The technical solution of the present invention will be described in the order of encoding and decoding.

[0025] <Encoding method> 4 is a schematic diagram showing a communication circuit structure of a digital isolation chip or an isolation amplifier chip. The communication circuit includes a source side 401 and a secondary side 403. The source side 401 transmits communication data, and the secondary side 403 receives communication data. The source side 401 includes an encoder 402 and a transmitter 404, and the secondary side 403 includes a receiver 406 and a decoder 408.

[0026] The transmitter 404 and the receiver 406 are coupled to each other via an isolation capacitor 410. The input of the encoder 402 is used to receive a data signal TD and a clock signal TCLK, and the output of the decoder 408 outputs a digital signal RD and a clock signal RCLK.

[0027] FIG. 5 is a schematic diagram showing the encoding timing of the data signal TD, the clock signal TCLK and the long and short code signal WNP of the present invention, in which the clock signal TCLK and the data signal TD are combined using an encoding method to generate the long and short code signal WNP.

[0028] The long-short code signal WNP includes a long code signal WP and a short code signal NP, the pulse width of the long code signal WP is the same as the clock signal TCLK, the pulse width of the short code signal NP is the same as the clock signal TCLK, and the duty of the long code signal WP is different from that of the short code signal NP.

[0029] The duty ratio of the long code signal WP between high and low levels is greater than that of the short code signal NP. The long code signal WP indicates that the data signal TD is "1," and the short code signal NP indicates that the data signal TD is "0."

[0030] The pulse width of the long code signal WP or the short code signal NP is one clock period Tclk, and the duty ratio of the long / short code signal WNP satisfies the relation Tclk=TS+TL, where Tclk is the clock period, TS is the high level time of the short code signal NP, and TL is the high level time of the long code signal WP, but TS is not equal to TL. As shown in the drawing, the low level of the long code signal WP is equal to the pulse width of the high level of the short code signal NP.

[0031] The above-mentioned long-short code encoding method combines the data signal TD and the clock signal TCLK for communication, resulting in higher efficiency and lower power consumption. At the same time, it supports single-channel communication, reducing chip packaging and routing, and thus chip manufacturing costs. Furthermore, the structure of the encoding circuit and decoding circuit is simple, reducing the complexity of circuit design.

[0032] The present invention is fundamentally different from the conventional OOK method, which uses an oscillation signal (ON) indicating 1 and an oscillation signal (OFF) indicating 0. In the present invention, long and short code signals WNP with different duty ratios are transmitted using the OOK method. That is, ON transmits a high level in the long and short code signal WNP, and OFF transmits a low level in the long and short code signal WNP. In other words, ON or OFF indicates a high or low level, but the content of the data signal TD is indicated by the different duty ratios of the long and short code signal WNP.

[0033] <Encoding method 1> Figure 6 is a schematic diagram showing the flow of the long and short code encoding method. This method involves obtaining a "clock signal" and then: 602: Generating a first delayed clock signal based on a clock signal; 604: Generating a pulse signal based on the first delayed clock signal; 606: generating a high level of a long code signal and a high level of a short code signal according to the pulse signal; 608: generating a second delayed clock signal according to the first delayed clock signal; 610: generating a low level of a short code signal according to a second delayed clock signal; 612: generating a low level of a long code signal based on a clock signal; 614: generating a data delay signal according to the first delay clock signal and the data signal; 616: Selecting a long code signal or a short code signal according to the data signal to generate a long / short code signal.

[0034] Steps 602-616 are now explained in more detail using the circuit structure shown in FIG. 7 and the timing shown in FIG.

[0035] The delay circuits, pulse generators, triggers, data selectors, and other circuits included in FIG. 7 and other drawings are all standard devices, and the present invention can be implemented by those skilled in the art according to their acquired knowledge without describing these standard devices.

[0036] The clock signal TCLK is coupled to a first delay circuit (Delay) 702, and the output terminal of the first delay circuit 702 is coupled to a pulse generator (One-shot) 706. The pulse generator 706 operates according to the timing shown in the lower right of Figure 7, and its output terminal is coupled to the reset terminal S of a long code trigger 708 and a short code trigger 710, the data terminal D of the long code trigger 708 and the short code trigger 710 is grounded, and the output terminal Q of the long code trigger 708 and the short code trigger 710 is coupled to the first input terminal (the first terminal of the MUX (MUX stands for Multiplexer, and is called a data selector in Japanese)) and the second input terminal (the zeroth terminal of the MUX) of a data selector 712, respectively. The input terminal of the second delay circuit (Delay) 704 is coupled to the output terminal of the first delay circuit 702, the output terminal of the second delay circuit 704 is coupled to the clock terminal of the short code trigger 710, the output terminal of the first delay circuit 702 is coupled to the clock terminal of the selection trigger 716, the data signal TD is coupled to the data terminal D of the selection trigger 716, and the output terminal Q of the selection trigger 716 is coupled to the selection terminal Sel of the data selector 712. The data selector 712 further includes an output terminal for outputting the long / short code signal WNP.

[0037] 6 to 8, in step 602, a first delayed clock signal TD1 is generated based on the clock signal TCLK. A first delay circuit 702 generates the first delayed clock signal TD1 based on the clock signal TCLK. The delay time of the first delayed clock signal TD1 relative to the clock signal TCLK is TS.

[0038] In step 604, a pulse signal is generated according to the first delayed clock signal TD1. The rising edge of the first delayed clock signal TD1 triggers the pulse generator 706, which generates a pulse signal according to the first delayed clock signal TD1. This pulse signal is sent to the reset ends S of the long code trigger 708 and the short code trigger 710.

[0039] In step 606, the long code trigger 708 and the short code trigger 710 generate a high level 8022 of the long code signal WP and a high level 8024 of the short code signal NP according to the pulse signal. After the pulse signal disappears, the long code signal WP and the short code signal NP can maintain a high level state.

[0040] In steps 608 and 610, a second delay clock signal TD2 is generated according to the first delay clock signal TD1. The second delay circuit 704 generates the second delay clock signal TD2 according to the first delay clock signal TD1. The delay time of the second delay clock signal TD2 relative to the first delay clock signal TD1 is TS.

[0041] When the rising edge of the second delayed clock signal TD2 occurs, the clock edge of the short code trigger 710 is at high level, the short code trigger 710 outputs low level, and the data edge D is grounded, thereby generating a low level 804 of the short code signal NP.

[0042] In step 612, the long code signal WP is generated at a low level 808 based on the clock signal. When the rising edge 806 of the next clock cycle arrives, the clock edge of the long code trigger 708 receives the clock signal and triggers it to output a level of the data edge D, which is grounded. At this time, the output signal forms the long code signal WP at a low level 808.

[0043] In step 614, a data delay signal TDD1 is generated according to the first delay clock signal TD1 and the data signal TD. The first delay clock signal TD1 is delayed by TS from the clock signal TCLK or the data signal TD, and the data signal TD is synchronized with the clock signal TCLK. Therefore, the data signal TD is coupled to the data end of the selection trigger 716 using the first delay clock signal TD1 as a clock source, and the data delay signal TDD1 is generated synchronously. That is, the delay time of the data delay signal TDD1 relative to the data signal TD is TS.

[0044] In step 616, the long code signal WP or the short code signal NP is selected according to the data signal TD to generate the long / short code signal WNP. The data delay signal TDD1 is coupled to the selection terminal Sel of the data selector 712, which selects and outputs the long code signal WP, i.e., the input signal at the first input terminal in the figure, when the data delay signal TDD1 is at a high level, and selects and outputs the short code signal NP, i.e., the input signal at the second input terminal in the figure, when the data delay signal TDD1 is at a low level. The data delay signal TDD1 is synchronized with the long / short code signal WNP, and selects and outputs the long code signal WP or the short code signal NP according to the data delay signal TDD1 to form the encoding of the long / short code signal WNP.

[0045] <Encoding method 2> Referring to Figure 9, another single-channel communication encoding method provided by the present invention is shown. This method involves obtaining a "clock signal" and then: 902: Generating a first pulse signal based on a clock signal; 904: Generating a first delayed clock signal based on the clock signal; 906: generating a second delayed clock signal based on the first delayed clock signal; 908: Generating a second pulse signal based on the second delayed clock signal; 910: Generating a third pulse signal based on the first delayed clock signal; 912: generating a high level of a long code signal or a high level of a short code signal according to the third pulse signal; 914: generating a data delay signal based on the data signal and the first delay clock signal; 916: Selecting the first pulse signal or the second pulse signal according to the data delay signal; 918: generating a low level of the short code signal according to the selected second pulse signal; 920: Generating a low level of a long code signal according to the selected first pulse signal.

[0046] Steps 902 to 920 will be explained in more detail below using the circuit structure shown in FIG. 10 and the timing chart shown in FIG.

[0047] Referring to FIG. 10, the encoding circuit includes a first delay circuit (Delay) 1002, a second delay circuit (Delay) 1004, a first pulse generator (One-shot 1) 1006, a second pulse generator (One-shot 2) 1008, a third pulse generator (One-shot 3) 1014, a data selector (MUX) 1010, a selection trigger 1012, and an output trigger 1016.

[0048] The clock signal TCLK is coupled to a first delay circuit 1002 and a first pulse generator 1006. The output terminal of the first delay circuit 1002 is coupled to an input terminal of a second delay circuit 1004, the output terminal of the second delay circuit 1004 is coupled to an input terminal of a second pulse generator 1008, and the output terminal of the second pulse generator 1008 is coupled to a second input terminal of a data selector 1010 (the 0th terminal of the MUX).

[0049] The output terminal of the first pulse generator 1006 is coupled to a first input terminal (first terminal of MUX) of a data selector 1010, the data signal TD is coupled to a data input terminal D of a selection trigger 1012, the output terminal Q of the selection trigger 1012 is coupled to a selection terminal Sel of the data selector 1010 (i.e., the selection terminal Sel of the data selector 1010 is coupled to the data delay signal TDD1), the output terminal of the third pulse generator 1014 is coupled to a reset terminal S of an output trigger 1016, and the clock terminal of the output trigger 1016 is coupled to the output terminal of the data selector 1010 to form node A. The output trigger 1016 further includes a grounded data terminal D and an output terminal Q for outputting a long / short code signal WNP.

[0050] 9 to 11, in step 902, a first pulse signal P1 is generated at node A based on the clock signal TCLK, and the rising edge 1102 of the clock signal triggers the first pulse generator 1006, which generates the first pulse signal P1 based on the first delayed clock signal (i.e., the rising edge 1102). The first pulse signal P1 is input to a first input terminal of a data selector 1010.

[0051] In step 904, a first delayed clock signal TD1 is generated based on the clock signal TCLK. A first delay circuit 1002 generates the first delayed clock signal TD1 based on the clock signal TCLK, and the first delayed clock signal TD1 serves as the basis for a second delayed clock signal TD2. The delay time of the first delayed clock signal TD1 relative to the clock signal is TS.

[0052] In step 906, a second delay clock signal TD2 is generated based on the first delay clock signal TD1. The second delay circuit 1004 generates the second delay clock signal TD2 according to the first delay signal TD1, and the delay time of the second delay clock signal TD2 relative to the first delay clock signal TD1 is TS.

[0053] In step 908, a second pulse signal P2 is generated based on the second delayed clock signal TD2. The second pulse generator 1008 generates the second pulse signal P2 based on the second delayed clock signal TD2. The second pulse signal P2 is used to cause the output trigger 1016 to output a low level.

[0054] In step 910, a third pulse signal (not shown in timing diagram) is generated based on the first delayed clock signal TD1. The third pulse generator 1014 generates the third pulse signal based on the first delayed clock signal TD1.

[0055] In step 912, this third pulse signal resets the output trigger 1016 to generate a high level 1104 of the long code signal WP or a high level 1106 of the short code signal NP (the long code signal WP and the short code signal NP are recorded in the long / short code signal WNP).

[0056] In step 914, a data delay signal TDD1 is generated according to the data signal TD and the first delayed clock signal TD1. The clock terminal of the selection trigger 1012 receives the first delayed clock signal TD1, the data terminal D couples the data signal TD, and the output terminal Q outputs the data delay signal TDD1, which is synchronized with the first delayed clock signal TD1.

[0057] In step 916, the data selector 1012 selects either the first pulse signal P1 or the second pulse signal P2 according to the data delay signal TDD1. When the data delay signal TDD1 is at a high level, the data selector 1012 outputs the first pulse signal P1, and when the data delay signal TDD1 is at a low level, the data selector 1012 outputs the second pulse signal P2.

[0058] In step 920, the long code signal WP is generated to a low level 1108 according to the selected first pulse signal P1. Since the rising edge of the first pulse signal P1 coincides with the rising edge of the clock signal TCLK, the first pulse signal P1 causes the output trigger 1016 to generate the long code signal WP to a low level 1108. After that, the third pulse generator 1014 generates a pulse signal to pull up the output level of the output trigger 1016 again, forming the long code signal WP to a high level 1104, thereby completing one long code encoding.

[0059] In step 918, the low level 1110 of the short code signal NP is generated according to the selected second pulse signal P2. The delay time of the rising edge of the second pulse signal P2 relative to the first delayed clock signal TD1 is TS. After the high level of the output trigger 1016 is maintained for the delay time TS, the output level of the output trigger 1016 is pulled down by the second pulse signal P2 to form the low level 1110 of the short code signal NP. Then, when the rising edge of the first delayed clock signal TD1 occurs, the third pulse generator 1014 generates a pulse signal to pull up the output level of the output trigger 1016 again to form the high level 1106 of the short code signal NP, thereby completing one short code encoding.

[0060] <Decryption method> Referring to Figure 12, a decoding method for single channel communication is shown. After obtaining the "long and short code signal", 1202: generating a low level of a clock signal according to a high level of a long and short code signal; 1204: generating a delay pulse signal according to the long and short code signal, and the delay time of the delay pulse signal is half a clock period; 1206: generating a high level of a clock signal according to the delayed pulse signal; 1208: Generating a digital signal based on the clock signal and the long and short code signal.

[0061] Steps 1202 to 1208 will be explained in more detail below using the circuit structure shown in FIG. 13 and the timing chart shown in FIG.

[0062] Referring to FIG. 13, the circuit structure includes a delay pulse circuit (Delay 0.5Tclk) 1302, a pulse generator (One-shot) 1304, a clock trigger 1306, and a digital signal trigger 1308.

[0063] The long and short code signal WNP is coupled to the delay pulse circuit 1302, the output of which is coupled to the pulse generator 1304, the long and short code signal WNP is coupled to a data end D of a digital signal trigger 1308, the clock end of a clock trigger 1306 is coupled to the long and short code signal WNP, the reset end S of the clock trigger 1306 is coupled to the output end of the pulse generator 1304 for receiving the delayed pulse signal SET, and the output end Q of the clock trigger 1306 is coupled to the clock end of the digital signal trigger 1308 for outputting the clock signal RCLK. The clock trigger 1306 further includes a data end D which is grounded, and the digital signal trigger 1308 further includes an output end Q for outputting the digital signal RD.

[0064] 12 to 14, in step 1202, a low level 1402 of the clock signal RCLK is generated in accordance with the high level of the long / short code signal WNP. After the rising edge 1404 of the long / short code signal WNP is input to the clock trigger 1306, the output terminal Q of the clock trigger 1306 outputs the low level 1402 (contained in the clock signal RCLK) of the data terminal D. That is, the clock trigger 1306 generates the low level of the clock signal RCLK in accordance with the long / short code signal WNP.

[0065] In step 1204, a delayed pulse signal SET is generated according to the long and short code signal WNP. The delay time of the delayed pulse signal SET is half a clock period (0.5 Tclk). The delay pulse circuit 1302 delays the long and short code signal WNP by half a clock period to generate a long and short code delayed signal, and the pulse generator 1304 generates the delayed pulse signal SET according to this long and short code delayed signal. In other words, the length from the rising edge 1408 of the delayed pulse signal SET to the rising edge 1404 of the long and short code signal WNP is half a clock period.

[0066] In step 1206, the delayed pulse signal SET resets the output Q of the clock trigger 1306 to output a high level, thereby forming a high level of the clock signal RCLK.

[0067] Steps 1202 to 1206 can be repeated to generate multiple clock signals RCLK.

[0068] In step 1208, a digital signal RD is generated based on the clock signal RCLK and the long and short code signal WNP.

[0069] The digital signal trigger 1308 generates a digital high level or a digital low level 1406 contained in the digital signal RD based on the clock signal RCLK.

[0070] Since the rising edge 1410 of the clock signal RCLK is exactly at the middle position (half cycle) of the data signal, the output signal of the digital signal trigger 1308 is either a high level of the long code signal WP or a low level of the short code signal NP, so that the output decoded high-low level signal exactly corresponds to the encoding of the long and short code signal WNP.

[0071] The above method can be further improved, in which generating a delay pulse signal SET according to the long and short code signal WNP further includes: generating a long and short code delay signal SET according to the long and short code signal WNP; and controlling a delay time of the long and short code signal WNP according to a phase difference between the long and short code delay signal and the long and short code signal WNP.

[0072] The above method can be further improved so that controlling the delay time of the long / short code signal WNP according to the phase difference between the long / short code delay signal and the long / short code signal WNP further includes converting the phase difference signal corresponding to the phase difference into a voltage signal, and controlling the delay time of the long / short code delay signal according to the voltage signal.

[0073] 15, the decoding circuit for single-channel communication has the same internal structure as the delay pulse circuit 1302 in FIG. 13, but the delay pulse circuit 1302 may further include a pulse circuit. Specifically, the delay circuit includes a delay circuit intermediate stage 1502 for converting the long / short code signal WNP into a long / short code delayed signal WNPD, a frequency / phase discriminator 1504 for detecting a phase difference between the long / short code delayed signal WNPD and the long / short code signal WNP, a charge pump 1506 for converting the phase difference into a current signal, and a low-pass filter 1508 for converting the current signal into a voltage signal Vctrl. The delay circuit intermediate stage 1502 is coupled to the output end of the low-pass filter 1508 and receives the voltage signal Vctrl to control the delay time of the long / short code delayed signal WNPD.

[0074] The feedback circuit from the phase signal to the voltage signal, formed by the above frequency / phase discriminator 1504 to low-pass filter 1508, precisely controls the time of the delay circuit, allowing for more fine control of the delay time, and by combining it with other parts of the decoding circuit, an accurate clock signal RCLK can be restored.

[0075] The other part includes a pulse generator One-shot, a clock trigger, and a digital signal trigger, similar to the circuit in Figure 13. Here, the long / short code delay signal WNPD is coupled to the input terminal of the pulse generator One-shot, and its output terminal is coupled to the reset terminal S of the clock trigger to output a delayed pulse signal Set. The data terminal D of the clock trigger is grounded, and the long / short code signal WNP is coupled to its clock terminal, outputting a clock signal RCLK from its output terminal Q. The clock terminal of the digital signal trigger is coupled to the output terminal Q of the clock trigger, and the long / short code signal WNP is coupled to its data terminal D, outputting a digital signal RD from the output terminal Q.

[0076] Referring to FIG. 16, based on FIG. 15, a circuit for pre-establishing a control voltage is added, and a flip-flop detector 602, an oscillator 604 (with a period T osc15 ), and a data selector (MUX) 608. The oscillator 604 is coupled to the second input terminal (0th terminal of MUX) of the data selector 608, the long / short code signal WNP is coupled to the first input terminal (1st terminal of MUX) of the data selector 608 and the input terminal of the flip-flop detector 602, the output terminal of the flip-flop detector 602 is coupled to the selection terminal Sel of the data selector 608, and the output terminal of the data selector 608 replaces the WNP input of the circuit in FIG.

[0077] When not communicating, the flip-flop detector 602 outputs a low level, and the data selector 608 couples the output of the oscillator 604 to the delay-locked loop (a circuit formed by the rear delay circuit intermediate stage 1502, frequency and phase discriminator, charge pump, and low-pass filter) to establish a voltage signal Vctrl.

[0078] During communication, the flip-flop detector 602 outputs a high level, and the data selector 608 couples the long / short code signal WNP to the delay pulse circuit.

[0079] Other parts of the circuit are similar to those in Figure 15, including a pulse generator one-shot, a clock trigger, and a digital signal trigger. Here, the input terminal of the pulse generator one-shot is coupled to the long / short code delay signal WNPD, its output terminal is coupled to the reset terminal S of the clock trigger to output a delayed pulse signal Set, its data terminal D of the clock trigger is grounded, its clock terminal is coupled to the long / short code signal WNP and its output terminal Q outputs a clock signal RCLK, and its clock terminal is coupled to the output terminal Q of the clock trigger, its data terminal D is coupled to the long / short code signal WNP and its output terminal Q outputs a digital signal RD. At the same time, the frequency / phase discriminator is coupled to the charge pump via two output terminals to output control signals UP and DOWN.

[0080] When not communicating, the delay locked loop has already established the voltage signal Vctrl of the voltage controlled delay line (including the delay circuit intermediate stage 1502), and this voltage signal Vctrl is close to the final voltage signal during communication, so there is no establishment time required by a normal clock data recovery circuit, and accurate communication can be achieved when the long and short code signal WNP arrives, thereby achieving high-speed communication establishment.

[0081] Although the technical content and technical features of the present invention have been described above, those skilled in the art can still make various substitutions and modifications based on the teachings and disclosure of the present invention without departing from the spirit of the present invention, so the protection scope of the present invention is not limited to the disclosure of the embodiments, and all substitutions and modifications that do not depart from the present invention shall be included in the scope of the claims of the present invention.

Claims

1. generating a low level of a clock signal according to a high level of the long and short code signal; generating a delay pulse signal according to the long and short code signal, the delay time of the delay pulse signal being half a clock period; generating a high level of a clock signal according to the delayed pulse signal; generating a digital signal according to the clock signal and the long and short code signal; a long code signal having a duty ratio different from that of the short code signal, the ...

2. 2. The decoding method for single-channel communication according to claim 1, wherein the step of generating a delay pulse signal according to the long and short code signal further comprises: generating a long and short code delay signal according to the long and short code signal; and controlling a delay time of the long and short code signal according to a phase difference between the long and short code delay signal and the long and short code signal.

3. A decoding method for single-channel communication as described in claim 2, characterized in that controlling the delay time of the long and short code signal according to the phase difference between the long and short code delay signal and the long and short code signal further includes converting the phase difference signal into a voltage signal and controlling the delay time of the long and short code delay signal according to the voltage signal.

4. a delay pulse circuit used to delay the long and short code signal by half a clock period to generate a long and short code delayed signal; a pulse generator used to generate a delayed pulse signal according to the long and short code delay signal; a clock trigger used to generate a high level of a clock signal according to the delayed pulse signal; a digital signal trigger used to generate a digital high level or a digital low level based on a clock signal; a long code signal having a duty ratio different from that of the short code signal, the ...

5. The clock trigger has a clock end coupled to the long and short code signal, and generates a low level clock signal based on the long and short code signal, and a reset end coupled to the output end of the pulse generator; 5. The decoding circuit for single-channel communication according to claim 4, wherein the clock edge of the digital signal trigger is coupled to the output end of the clock trigger, and the long / short code signal is coupled to the data end.

6. The data end of the clock trigger is grounded; the clock trigger is configured such that after the rising edge of the long / short code signal is input to the clock trigger, the output terminal of the clock trigger outputs a low level of the data edge; 5. The decoding circuit for single-channel communication according to claim 4, wherein said low level is included in said clock signal.

7. the output terminal of the digital signal trigger is used to output a digital signal; 5. The decoding circuit for single-channel communication according to claim 4, wherein the output signal of said digital signal trigger is a high level of said long code signal or a low level of said short code signal.

8. The delay pulse circuit includes a delay circuit, a delay circuit intermediate stage used to convert said long and short code signal to said long and short code delayed signal; a frequency and phase discriminator used to detect a phase difference between the long and short code delay signal and the long and short code signal; a charge pump used to convert the phase difference into a current signal; a low pass filter used to convert the current signal into a voltage signal; 5. The decoding circuit for single-channel communication according to claim 4, wherein the delay circuit intermediate stage is coupled to the low-pass filter, and the delay circuit intermediate stage receives the voltage signal and is used to control the delay time of the long and short code delay signal.

9. 9. The decoding circuit for single-channel communication according to claim 8, wherein the delay pulse circuit further comprises a pulse circuit.

10. the decoding circuit further comprises a flip-flop detector, an oscillator, and a data selector; When there is no communication, the flip-flop detector outputs a low level, and the data selector couples the output of the oscillator to the delay-locked loop to establish a voltage signal; 9. The decoding circuit for single-channel communication according to claim 8, wherein during communication, the flip-flop detector outputs a high level, and the data selector couples the long and short code signal to the delay pulse circuit.

11. 11. The decoding circuit for single-channel communication according to claim 10, wherein the oscillator is coupled to a second input terminal of the data selector, the long / short code signal is coupled to a first input terminal of the data selector and an input terminal of the flip-flop detector, and the output terminal of the flip-flop detector is coupled to a selection terminal of the data selector.

12. 12. The decoding circuit for single-channel communication according to claim 11, wherein the second input terminal is a 0th terminal of the data selector, and the first input terminal is a 1st terminal of the data selector.

13. 11. The decoding circuit for single-channel communication according to claim 10, wherein the delay-locked loop includes a post-delay circuit intermediate stage, the frequency / phase discriminator, the charge pump, and the low-pass filter.

14. the delay locked loop is used to establish a voltage signal for a voltage controlled delay line; the voltage signal is close to the final voltage signal during communication; 11. The decoding circuit for single-channel communication according to claim 10, wherein the voltage-controlled delay line includes the delay circuit intermediate stage.

15. 11. The decoding circuit for single-channel communication according to claim 10, wherein the frequency and phase discriminator is coupled to the charge pump via two outputs to output control signals UP and DOWN.

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