High frequency package and method of manufacturing the same

Abstract

A high frequency package (1) comprises: a first wiring substrate (2); a semiconductor chip (3) that is disposed on the first wiring substrate (2) with first solder bumps (6) therebetween and that is electrically connected to the first wiring substrate (2); a second wiring substrate (4) that is disposed on the first wiring substrate (2) with second solder bumps (7) therebetween and that is electrically connected to the first wiring substrate (2), said second solder bumps (7) being disposed around the semiconductor chip (3) on the first wiring substrate (2); and a reinforcing material (5) that is filled between the first solder bumps (6) and the second solder bumps (7) and that is filled from above the first wiring substrate (2) to the second wiring substrate (4) and the semiconductor chip (3). Formed in the second wiring substrate (4) is a through hole (4c) that passes through the second wiring substrate (4) in a plate thickness direction. In a view along the plate thickness direction, at least part of the semiconductor chip (3) and at least part of the reinforcing material (5) are at a position overlapping with the through hole (4c).

Description

[Technical Field]

[0001] The present disclosure relates to a high frequency package including a semiconductor chip and a method for manufacturing the high frequency package. [Background technology]

[0002] Conventionally, high-frequency packages have been known that include a first wiring substrate, a semiconductor chip, and a second wiring substrate. In such high-frequency packages, the semiconductor chip is mounted on the first wiring substrate via solder bumps, and the first wiring substrate is mounted on the second wiring substrate via solder bumps arranged around the semiconductor chip. Hereinafter, when distinguishing between the solder bumps connecting the first wiring substrate and the semiconductor chip and the solder bumps connecting the first wiring substrate and the second wiring substrate, the former will be referred to as the first solder bumps and the latter will be referred to as the second solder bumps.

[0003] In a high-frequency package, the semiconductor chip is disposed between the second wiring board and the first solder bumps, so it is necessary to avoid interference between the semiconductor chip and the second wiring board. Therefore, in a high-frequency package, as disclosed in Patent Document 1, a counterbore recessed in a direction away from the semiconductor chip is provided on the surface of the second wiring board facing the semiconductor chip. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2012 / 140934 Summary of the Invention [Problem to be solved by the invention]

[0005] In the high-frequency package disclosed in Patent Document 1, the temperature of the high-frequency package rises and falls due to heat generated by electronic components such as semiconductor chips and changes in the ambient temperature. When the temperature of the high-frequency package changes, strain occurs in the first solder bumps arranged on the periphery of the semiconductor chip and the second solder bumps arranged around the recesses due to the difference in the linear expansion coefficients between the first wiring board and the semiconductor chip, the difference in the linear expansion coefficients between the first wiring board and the second wiring board, and the recesses in the second wiring board. When this strain occurs repeatedly, there is a problem that the first solder bumps and the second solder bumps break.

[0006] In particular, when a waveguide plate is attached to the surface of the second wiring board facing away from the semiconductor chip and the first wiring board, the difference in the linear expansion coefficient between the second wiring board and the waveguide plate is also added, increasing the amount of strain in the first solder bumps and the second solder bumps, which creates the problem of making the breakage of the first solder bumps and the second solder bumps more likely to progress.

[0007] A common approach to reducing distortion of the first solder bumps is to infiltrate an insulating underfill material into the gap between the first wiring substrate and the semiconductor chip, or to apply an insulating sidefill material between the first wiring substrate and the outer periphery of the semiconductor chip.

[0008] However, when the underfill material is applied, it comes into contact with all of the first solder bumps, which can degrade the electrical characteristics of the high-frequency package. On the other hand, when the side fill material is applied after the semiconductor chip is mounted on the first wiring board via the first solder bumps, the area to which the side fill material is applied is small, so the side fill material may come into contact with both the first and second solder bumps. If the side fill material adheres to the first or second solder bumps, the first or second solder bumps may fly off during the secondary reflow process in which the first wiring board is mounted on the second wiring board, causing problems with the connection between the semiconductor chip and the first wiring board and the connection between the first wiring board and the second wiring board.

[0009] The present disclosure has been made in consideration of the above, and aims to obtain a high-frequency package that can reduce distortion of the solder bumps while preventing deterioration of the electrical characteristics of the high-frequency package and scattering of the solder bumps during the secondary reflow process. [Means for solving the problem]

[0010] To solve the above-mentioned problems and achieve the object, the high-frequency package according to the present disclosure includes a first wiring substrate, a semiconductor chip disposed on the first wiring substrate via first solder bumps and electrically connected to the first wiring substrate, a second wiring substrate disposed on the first wiring substrate via second solder bumps disposed around the semiconductor chip on the first wiring substrate and electrically connected to the first wiring substrate, and a reinforcing material filled between the first solder bumps and the second solder bumps and filling from the first wiring substrate to the second wiring substrate and the semiconductor chip. The second wiring substrate has a through hole formed therein that penetrates in the thickness direction of the second wiring substrate. When viewed in the thickness direction, at least a portion of the semiconductor chip and at least a portion of the reinforcing material are positioned to overlap the through hole. [Effects of the Invention]

[0011] According to the present disclosure, it is possible to prevent deterioration of the electrical characteristics of the high frequency package and scattering of the solder bumps in the secondary reflow process, while reducing distortion of the solder bumps. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a cross-sectional view showing a high-frequency package according to a first embodiment; [Figure 2] FIG. 1 is a plan view showing a high-frequency package according to a first embodiment; [Figure 3] 1 is a cross-sectional view showing a method for manufacturing a high-frequency package according to a first embodiment, illustrating a first reflow process; [Figure 4] 1 is a cross-sectional view showing a method for manufacturing a high-frequency package according to a first embodiment, illustrating a second reflow process; [Figure 5] 1 is a cross-sectional view showing a coating step in a method for manufacturing a high-frequency package according to a first embodiment; FIG. [Figure 6] 1 is a cross-sectional view showing a hardening step in the method for manufacturing a high-frequency package according to a first embodiment; FIG. [Figure 7] 1 is a cross-sectional view showing a high-frequency package according to a conventional technique; [Figure 8] 1 is a cross-sectional view showing a state of a conventional high-frequency package at high temperatures; [Figure 9] FIG. 1 is a cross-sectional view showing a state in which a waveguide plate is attached to a conventional high-frequency package, and shows the state of the conventional high-frequency package and the waveguide plate at high temperatures. [Figure 10] 10 is a cross-sectional view showing a high-frequency package according to a second embodiment of the present invention; [Figure 11] 10 is a cross-sectional view showing a high-frequency package according to a third embodiment. [Figure 12] 10 is a cross-sectional view showing a high-frequency package according to a fourth embodiment. [Figure 13] FIG. 10 is a plan view showing a high-frequency package according to a fourth embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, a high-frequency package and a method for manufacturing the high-frequency package according to an embodiment will be described in detail with reference to the drawings.

[0014] Embodiment 1 FIG. 1 is a cross-sectional view of a high-frequency package 1 according to a first embodiment. FIG. 2 is a plan view of the high-frequency package 1 according to the first embodiment. As shown in FIG. 1, the high-frequency package 1 includes a first wiring board 2, a semiconductor chip 3, a second wiring board 4, and a reinforcing member 5. Hereinafter, when describing the directions of the components of the high-frequency package 1, the thickness direction of the first wiring board 2 and the second wiring board 4 is referred to as a first direction, and a direction perpendicular to the first direction is referred to as a second direction. In the following description, the direction from the outer periphery of the first wiring board 2 and the second wiring board 4 in the second direction to the center of the first wiring board 2 and the second wiring board 4 in the second direction is referred to as an inward direction, and the side opposite the inward direction is referred to as an outward direction. In FIG. 2, the reinforcing member 5 is hatched with dots to clearly indicate the extent of the reinforcing member 5.

[0015] The shape of first wiring board 2 in a plan view is quadrangular. First wiring board 2 has first front surface 2a and first back surface 2b facing away from first front surface 2a.

[0016] The semiconductor chip 3 is disposed on the first surface 2a of the first wiring substrate 2 via the first solder bumps 6. The semiconductor chip 3 is electrically connected to the first wiring substrate 2 via the first solder bumps 6. The semiconductor chip 3 is disposed between the second wiring substrate 4 and the first solder bumps 6. A portion of the semiconductor chip 3 is disposed in a through hole 4c (described later) of the second wiring substrate 4. The semiconductor chip 3 is an integrated circuit that processes high frequencies in the microwave and millimeter wave bands. A plurality of first solder bumps 6 are disposed at intervals from one another in the second direction. The outermost first solder bumps 6 are disposed on the periphery of the semiconductor chip 3. Hereinafter, the first solder bumps 6 disposed on the periphery of the semiconductor chip 3 will be referred to as first solder bumps 6a. As shown in FIG. 2, the semiconductor chip 3 has a rectangular shape in a plan view.

[0017] As shown in FIG. 1, the second wiring board 4 is disposed on the first surface 2a of the first wiring board 2 via the second solder bumps 7. The second wiring board 4 is electrically connected to the first wiring board 2 via the second solder bumps 7. The second wiring board 4 has a second surface 4a and a second back surface 4b facing away from the second surface 4a. The second back surface 4b and the first surface 2a are disposed with a gap in the first direction. The second wiring board 4 has a through hole 4c formed therein, which penetrates in the first direction. The through hole 4c penetrates from the second surface 4a to the second back surface 4b.

[0018] The second solder bumps 7 are arranged around the semiconductor chip 3 and the first solder bumps 6 on the first surface 2a of the first wiring substrate 2. The innermost second solder bump 7 is arranged around the portion of the through hole 4c that opens to the second back surface 4b. Hereinafter, the second solder bump 7 arranged around the portion of the through hole 4c that opens to the second back surface 4b will be referred to as the second solder bump 7a. The first solder bump 6a and the second solder bump 7a are arranged with a gap between them in the second direction. The outermost second solder bump 7 is arranged on the outer periphery of the first wiring substrate 2. Hereinafter, the second solder bump 7 arranged on the outer periphery of the first wiring substrate 2 will be referred to as the second solder bump 7b. As shown in FIG. 2, the planar shape of the second wiring substrate 4 and the planar shape of the through hole 4c are rectangular.

[0019] As shown in FIG. 1 , the reinforcing material 5 is filled between the first solder bumps 6 a and the second solder bumps 7 a, and also fills from the first surface 2 a of the first wiring substrate 2 to the second wiring substrate 4 and the semiconductor chip 3. This reduces distortion of the first solder bumps 6 a arranged on the periphery of the semiconductor chip 3. It also reduces distortion of the second solder bumps 7 a arranged around the portions of the through holes 4 c that open to the second back surface 4 b. The reinforcing material 5 contacts the first solder bumps 6 a and the second solder bumps 7 a, but does not contact the remaining first solder bumps 6 and second solder bumps 7. In this embodiment, the reinforcing material 5 fills a portion of the through holes 4 c, but does not necessarily fill the through holes 4 c. It is sufficient for the reinforcing material 5 to reach from the first surface 2 a of the first wiring substrate 2 to the second back surface 4 b of the second wiring substrate 4. In this embodiment, the reinforcing material 5 extends from the first surface 2a of the first wiring substrate 2 to the outer periphery of the semiconductor chip 3, but it is sufficient if the reinforcing material 5 extends from the first surface 2a of the first wiring substrate 2 to the surface of the semiconductor chip 3 that faces the first wiring substrate 2. The reinforcing material 5 is, for example, a thermosetting resin.

[0020] 2, when viewed in a first direction, which is the plate thickness direction, at least a portion of the semiconductor chip 3 and at least a portion of the reinforcing material 5 are positioned to overlap with the through hole 4c. In other words, when viewed in the first direction, at least a portion of the semiconductor chip 3 and at least a portion of the reinforcing material 5 are exposed through the through hole 4c. In this embodiment, when viewed in the first direction, the entire semiconductor chip 3 is positioned to overlap with the through hole 4c.

[0021] Next, a manufacturing method of the high-frequency package 1 according to the present embodiment will be described with reference to Figs. 3 to 6. The manufacturing method of the high-frequency package 1 includes a first reflow step, a second reflow step, a coating step, and a curing step. Fig. 3 is a cross-sectional view showing the manufacturing method of the high-frequency package 1 according to the first embodiment, illustrating the first reflow step. Fig. 4 is a cross-sectional view showing the manufacturing method of the high-frequency package 1 according to the first embodiment, illustrating the second reflow step. Fig. 5 is a cross-sectional view showing the manufacturing method of the high-frequency package 1 according to the first embodiment, illustrating the coating step. Fig. 6 is a cross-sectional view showing the manufacturing method of the high-frequency package 1 according to the first embodiment, illustrating the curing step.

[0022] As shown in FIG. 3, the first reflow process is a process of mounting the semiconductor chip 3 on the first wiring board 2 via the first solder bumps 6. Prior to the first reflow process, the first solder bumps 6 and the second solder bumps 7 are formed in advance on the first wiring board 2. In the first reflow process, the semiconductor chip 3 is first placed on the first wiring board 2 via the first solder bumps 6. Next, the first solder bumps 6 are heated to their melting temperature for a reflow process, melting the first solder bumps 6. When the melted first solder bumps 6 harden, a structure is obtained in which the semiconductor chip 3 is mounted on the first wiring board 2 via the first solder bumps 6.

[0023] The second reflow process is a process of mounting the first wiring board 2 on the second wiring board 4 via the second solder bumps 7 so that at least a portion of the semiconductor chip 3 overlaps with the through-holes 4c when viewed in the first direction. In the second reflow process, the first wiring board 2 on which the semiconductor chip 3 is mounted is first placed on the second wiring board 4 via the second solder bumps 7. Next, the second solder bumps 7 are heated to their melting temperature for a reflow process, melting the second solder bumps 7. In the second reflow process, the first solder bumps 6 are remelted. The melted first solder bumps 6 and second solder bumps 7 harden, resulting in a structure in which the semiconductor chip 3 is mounted on the first wiring board 2 via the first solder bumps 6 and the first wiring board 2 is mounted on the second wiring board 4 via the second solder bumps 7.

[0024] The coating process is a process of coating the material that will become the reinforcing material 5 between the first solder bump 6a and the second solder bump 7a through the through hole 4c. In the coating process, a nozzle 8 is inserted into the through hole 4c, and the material is coated between the first solder bump 6a and the second solder bump 7a. In the coating process, the material is coated from the first surface 2a of the first wiring board 2 to the second wiring board 4 and the semiconductor chip 3.

[0025] The curing step is a step of curing the applied material. In the curing step, the applied material is heated to harden it. By performing the above steps, the high frequency package 1 is manufactured.

[0026] Next, the effects of the high-frequency package 1 and the method for manufacturing the high-frequency package 1 according to this embodiment will be described.

[0027] First, referring to FIGS. 7 to 9, a high-frequency package 1D according to a conventional technique will be described, in which through holes 4c are not formed in the second wiring board 4, and a counterbore 9 is formed in the second wiring board 4. FIG. 7 is a cross-sectional view showing the high-frequency package 1D according to the conventional technique. FIG. 8 is a cross-sectional view showing the state of the high-frequency package 1D according to the conventional technique at high temperature. FIG. 9 is a cross-sectional view showing a state in which a waveguide plate 10 is attached to the high-frequency package 1D according to the conventional technique, and is a cross-sectional view showing the state of the high-frequency package 1D and the waveguide plate 10 according to the conventional technique at high temperature.

[0028] As shown in FIG. 7, in the high-frequency package 1D according to the conventional technique, in order to avoid interference between the semiconductor chip 3 and the second wiring board 4, a counterbore 9 recessed in a direction away from the semiconductor chip 3 is provided on the second back surface 4b of the second wiring board 4.

[0029] When the linear expansion coefficient of the first wiring board 2 shown in FIG. 8 is A, the linear expansion coefficient of the semiconductor chip 3 is B, and the linear expansion coefficient of the second wiring board 4 is C, the relationship of B < C < A generally holds. When the temperature of the high-frequency package 1D changes, due to the difference in the linear expansion coefficients between the first wiring board 2 and the semiconductor chip 3, the difference in the linear expansion coefficients between the first wiring board 2 and the second wiring board 4, and the counterbore 9 of the second wiring board 4, strain occurs in the first solder bump 6 and the second solder bump 7. In particular, the strain generated in the first solder bump 6a becomes larger compared to the strain of the other first solder bumps 6. Also, the strain generated in the second solder bumps 7a, 7b becomes larger compared to the strain of the other second solder bumps 7. When such strain of the first solder bump 6a and the second solder bumps 7a, 7b is repeated, there is a problem that breakage of the first solder bump 6a and breakage of the second solder bumps 7a, 7b occur.

[0030] As shown in FIG. 9, in the conventional high-frequency package 1D according to the prior art, from the viewpoint of electrical characteristics, a structure in which a waveguide plate 10 is attached to a second wiring board 4 with screws 11 is used. The waveguide plate 10 is attached to the second surface 4a of the second wiring board 4. When the linear expansion coefficient of the waveguide plate 10 is D, it is generally in the relationship of B < C < A ≤ D. When the waveguide plate 10 is attached to the second surface 4a of the second wiring board 4, when the temperature of the high-frequency package 1D changes, in addition to the difference in the linear expansion coefficients between the members described above, the difference in the linear expansion coefficients between the second wiring board 4 and the waveguide plate 10 is also added, and the strain amounts of the first solder bumps 6a and the second solder bumps 7a, 7b increase. As a result, there is a problem that the breakage of the first solder bump 6a and the breakage of the second solder bumps 7a, 7b tend to progress.

[0031] As means for reducing the strain of the first solder bump 6a, there are means such as infiltrating an insulating underfill material into the gap between the first wiring board 2 and the semiconductor chip 3, or applying an insulating side fill material between the outer peripheral portions of the first wiring board 2 and the semiconductor chip 3. However, when infiltrating the underfill material, since the underfill material comes into contact with all of the first solder bumps 6, there is a problem that the electrical characteristics of the high-frequency package 1D deteriorate. On the other hand, when applying the side fill material after mounting the semiconductor chip 3 on the first wiring board 2 via the first solder bumps 6, since the area where the side fill material is applied is narrow, the side fill material may come into contact with both the first solder bumps 6 and the second solder bumps 7. When the side fill material adheres to the first solder bumps 6 or the second solder bumps 7, the first solder bumps 6 or the second solder bumps 7 scatter in the secondary reflow process of mounting the first wiring board 2 on the second wiring board 4, and there is a problem that problems occur in the connection between the semiconductor chip 3 and the first wiring board 2 and the connection between the first wiring board 2 and the second wiring board 4.

[0032] 1 and 2, second wiring board 4 has through-holes 4c formed therein, which penetrate through second wiring board 4 in the thickness direction, and when viewed along the thickness direction, at least a portion of semiconductor chip 3 and at least a portion of reinforcing material 5 are positioned to overlap through-holes 4c. With this configuration, after completing the second reflow step of mounting first wiring board 2 to second wiring board 4 via second solder bumps 7, a material to become reinforcing material 5 can be applied through through-holes 4c of second wiring board 4, thereby preventing scattering of first solder bumps 6 and second solder bumps 7 during the second reflow step.

[0033] 1, in this embodiment, the reinforcing material 5 is filled between the first solder bumps 6a and the second solder bumps 7a, and also fills from the first surface 2a of the first wiring board 2 to the second wiring board 4 and the semiconductor chip 3. This configuration reduces distortion of the first solder bumps 6a arranged on the periphery of the semiconductor chip 3, and also reduces distortion of the second solder bumps 7a arranged around the portions of the through holes 4c that open to the second back surface 4b. This makes it possible to prevent breakage of the first solder bumps 6a and the second solder bumps 7a.

[0034] 1, the reinforcing material 5 does not contact all of the first solder bumps 6. That is, the reinforcing material 5 contacts only the first solder bumps 6a. This configuration can prevent the electrical characteristics of the high-frequency package 1 from deteriorating.

[0035] As described above, in this embodiment, it is possible to reduce the distortion of the first solder bump 6a and the second solder bump 7a while preventing the deterioration of the electrical characteristics of the high-frequency package 1 and the scattering of the second solder bump 7 in the secondary reflow process.

[0036] Embodiment 2 Next, a high-frequency package 1A according to a second embodiment will be described with reference to Fig. 10. Fig. 10 is a cross-sectional view showing the high-frequency package 1A according to the second embodiment. In this embodiment, the filling range of the reinforcing material 5 differs from that of the first embodiment. In the second embodiment, parts that overlap with those of the first embodiment are given the same reference numerals and descriptions thereof will be omitted.

[0037] The reinforcing material 5 fills the entire through hole 4c. The reinforcing material 5 also contacts the surface of the semiconductor chip 3 that faces away from the first wiring board 2.

[0038] In this embodiment, since the reinforcing material 5 fills the entire through hole 4c, the distortion of the second solder bump 7a can be further reduced, and therefore, the breakage of the second solder bump 7a can be further suppressed.

[0039] Embodiment 3 Next, a high-frequency package 1B according to a third embodiment will be described with reference to Fig. 11. Fig. 11 is a cross-sectional view showing a high-frequency package 1B according to the third embodiment. This embodiment differs from the first embodiment in that the reinforcing material 5 includes a first reinforcing material 5a and a second reinforcing material 5b. In the third embodiment, parts that overlap with those in the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0040] The reinforcing material 5 includes a first reinforcing material 5a and a second reinforcing material 5b. The first reinforcing material 5a is filled between the first solder bumps 6a and the second solder bumps 7a. The first reinforcing material 5a is filled from the first surface 2a of the first wiring board 2 to the second wiring board 4 and the semiconductor chip 3. The first reinforcing material 5a is in contact with the first solder bumps 6a and the second solder bumps 7a, but is not in contact with the other first solder bumps 6 and the second solder bumps 7. In this embodiment, the first reinforcing material 5a is filled in a portion of the through hole 4c, but it does not have to be filled in the through hole 4c. It is sufficient that the first reinforcing material 5a reaches from the first surface 2a of the first wiring board 2 to the second back surface 4b of the second wiring board 4. In this embodiment, the first reinforcing material 5a extends from the first surface 2a of the first wiring substrate 2 to the outer periphery of the semiconductor chip 3, but it is sufficient if the first reinforcing material 5a extends from the first surface 2a of the first wiring substrate 2 to the surface of the semiconductor chip 3 that faces the first wiring substrate 2. The first reinforcing material 5a is, for example, a thermosetting resin.

[0041] The second reinforcing material 5b is layered on the first reinforcing material 5a and fills the through hole 4c. The second reinforcing material 5b is disposed on the surface of the first reinforcing material 5a facing away from the first wiring board 2. In this embodiment, the second reinforcing material 5b fills a portion of the through hole 4c, but it may fill the entire through hole 4c. In this embodiment, the second reinforcing material 5b extends from above the first reinforcing material 5a to the same position as the second surface 4a of the second wiring board 4, but it may also extend from above the first reinforcing material 5a to near the second surface 4a. The second reinforcing material 5b contacts the outer periphery of the semiconductor chip 3 and the surface of the semiconductor chip 3 facing away from the first wiring board 2. The second reinforcing material 5b is, for example, a thermosetting resin. The difference in linear expansion coefficient between the second reinforcing material 5b and the second wiring board 4 is smaller than the difference in linear expansion coefficient between the first reinforcing material 5a and the second wiring board 4. The difference in linear expansion coefficient between second reinforcing material 5b and second wiring board 4 is smaller than the difference in linear expansion coefficient between second wiring board 4 and each component of high-frequency package 1C other than second reinforcing material 5b.

[0042] In this embodiment, the reinforcing material 5 includes a first reinforcing material 5a that fills the gap between the first solder bump 6a and the second solder bump 7a, and a second reinforcing material 5b that is layered on the first reinforcing material 5a and fills the through-hole 4c. In this embodiment, the difference in the linear expansion coefficient between the second reinforcing material 5b and the second wiring board 4 is smaller than the difference in the linear expansion coefficient between the first reinforcing material 5a and the second wiring board 4. This configuration allows the first reinforcing material 5a to reduce distortion of the first solder bump 6a caused by the difference in the linear expansion coefficient between the first wiring board 2 and the semiconductor chip 3, and distortion of the second solder bump 7a caused by the difference in the linear expansion coefficient between the first wiring board 2 and the second wiring board 4. This configuration also allows the second reinforcing material 5b to reduce distortion of the second solder bump 7a caused by the provision of the through-hole 4c in the second wiring board 4. This makes it possible to further prevent the first solder bumps 6a and the second solder bumps 7a from breaking.

[0043] Although second reinforcing material 5b is a thermosetting resin, it may be a conductive adhesive. This improves the heat dissipation effect of second wiring board 4. Furthermore, by electrically connecting second reinforcing material 5b, which is a conductive adhesive, to the ground layer of second wiring board 4, an electromagnetic shielding effect can be obtained.

[0044] Embodiment 4 Next, a high-frequency package 1C according to a fourth embodiment will be described with reference to FIGS. 12 and 13. FIG. 12 is a cross-sectional view showing the high-frequency package 1C according to the fourth embodiment. FIG. 13 is a plan view showing the high-frequency package 1C according to the fourth embodiment. This embodiment differs from the first embodiment in that a portion of the semiconductor chip 3 overlaps with the through-hole 4c. In the fourth embodiment, portions that overlap with those in the first embodiment are denoted by the same reference numerals and will not be described again. In FIG. 13, in order to clearly show the scope of the semiconductor chip 3 and the reinforcing material 5, the semiconductor chip 3 is hatched with diagonal lines and the reinforcing material 5 is hatched with dots.

[0045] As shown in FIG. 13 , the semiconductor chip 3 has multiple corners 3a and multiple sides 3b connecting adjacent corners 3a. When viewed in the first direction, the second wiring board 4 has multiple through holes 4c formed therein, each overlapping with one of the multiple corners 3a. In this embodiment, the number of corners 3a and the number of through holes 4c are four. One through hole 4c is provided for each corner 3a. When viewed in the first direction, each corner 3a and the ends of the two sides 3b adjacent to each corner 3a are positioned to overlap one of the multiple through holes 4c. In other words, when viewed in the first direction, which is the plate thickness direction, a portion of the semiconductor chip 3 overlaps with the through hole 4c. When viewed in the first direction, a portion of the reinforcing member 5 also overlaps with the through hole 4c.

[0046] When viewed in the first direction, the through-hole 4c may be located at a position overlapping with a portion other than the corner 3a and the end of the side 3b of the semiconductor chip 3. For example, when viewed in the first direction, the through-hole 4c may be located at a position overlapping with only the center of the side 3b of the semiconductor chip 3.

[0047] In this embodiment, when viewed in the first direction, which is the plate thickness direction, a part of the semiconductor chip 3 is located in a position overlapping with the through hole 4c. This configuration can achieve the following four effects. (1) The effect of being able to reduce the processing time in the step of forming the through holes 4c in the second wiring board 4. (2) The opening area of ​​the through-hole 4c is reduced, so that distortion of the second wiring board 4 can be reduced. (3) An effect that a wiring pattern can be provided in an area of ​​the second wiring board 4 where there are no through holes 4c. (4) The effect of being able to reduce the amount of reinforcing material 5 used.

[0048] The configurations shown in the above embodiments are merely examples, and may be combined with other known technologies, or different embodiments may be combined with each other. It is also possible to omit or modify parts of the configurations as long as they do not deviate from the gist of the invention. [Explanation of symbols]

[0049] 1, 1A, 1B, 1C, 1D high frequency package, 2 first wiring board, 2a first front surface, 2b first rear surface, 3 semiconductor chip, 3a corner portion, 3b side, 4 second wiring board, 4a second front surface, 4b second rear surface, 4c through hole, 5 reinforcement material, 5a first reinforcement material, 5b second reinforcement material, 6, 6a first solder bump, 7, 7a, 7b second solder bump, 8 nozzle, 9 counterbore, 10 waveguide plate, 11 screw.

Claims

1. a first wiring substrate; a semiconductor chip disposed on the first wiring substrate and electrically connected to the first wiring substrate via first solder bumps; a second wiring substrate disposed on the first wiring substrate and electrically connected to the first wiring substrate via second solder bumps disposed around the semiconductor chip on the first wiring substrate; a reinforcing material that is filled between the first solder bumps and the second solder bumps and that is filled from the first wiring substrate to the second wiring substrate and the semiconductor chip; Equipped with a through hole penetrating the second wiring substrate in a thickness direction of the second wiring substrate is formed; A high-frequency package, characterized in that, when viewed along the thickness direction, at least a portion of the semiconductor chip and at least a portion of the reinforcing material are positioned so as to overlap the through hole.

2. 2. The high frequency package according to claim 1, wherein the semiconductor chip is entirely positioned so as to overlap the through hole when viewed along the thickness direction.

3. 2. The high-frequency package according to claim 1, wherein the reinforcing material fills the entire through-hole.

4. The reinforcing material is a first reinforcing material filled between the first solder bump and the second solder bump; a second reinforcing material that is laminated on the first reinforcing material and filled in the through holes; Including, 4. The high-frequency package according to claim 1, wherein the difference in the linear expansion coefficient between the second reinforcing material and the second wiring board is smaller than the difference in the linear expansion coefficient between the first reinforcing material and the second wiring board.

5. 5. The high frequency package according to claim 4, wherein the second reinforcing material is a conductive adhesive.

6. 1. A method for manufacturing a high-frequency package comprising: a first wiring substrate; a semiconductor chip disposed on the first wiring substrate via first solder bumps and electrically connected to the first wiring substrate; a second wiring substrate disposed on the first wiring substrate via second solder bumps disposed around the semiconductor chip on the first wiring substrate and electrically connected to the first wiring substrate; and a reinforcing material filled between the first solder bumps and the second solder bumps and also filled from above the first wiring substrate to the second wiring substrate and the semiconductor chip, wherein a through hole penetrating through the second wiring substrate in a plate thickness direction is formed in the second wiring substrate, a first reflow process of mounting the semiconductor chip on the first wiring board using the first solder bumps; a secondary reflow process of mounting the first wiring substrate to the second wiring substrate by the second solder bumps so that at least a portion of the semiconductor chip overlaps with the through hole when viewed along the board thickness direction; a coating step of coating the reinforcing material between the first solder bump and the second solder bump through the through hole; a curing step of curing the applied material to form the reinforcement member; A method for manufacturing a high-frequency package, comprising:

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