Semiconductor device and data storage system including the same

Abstract

To provide a semiconductor device which may increase integration density and reliability, and a data storage system including the semiconductor device.SOLUTION: A semiconductor device includes: a stack structure 23', 35' extending into a staircase region SA from a memory cell array region MCA on a pattern structure 17', and including interlayer insulating layers 25, 38 and gate layers 27g, 40g alternately stacked in a vertical direction; a separation structure including a portion penetrating through the stack structure and in contact with the pattern structure; a memory vertical structure 47 including a portion penetrating through the stack structure in the memory cell array region and in contact with the pattern structure, where an upper surface of the memory vertical structure is positioned at a first height level; gate contact plugs 75 disposed on the gate pads; and a first peripheral contact plug 61a separated from the gate layers, where an upper surface of the first peripheral contact plug is positioned at a second height level higher than the first height level. The separation structure extends in the memory cell array region in a first horizontal direction X toward the staircase region.SELECTED DRAWING: Figure 2a

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a data system including the same. [Background technology]

[0002] In electronic systems requiring data storage, semiconductor devices capable of storing large amounts of data are required. Accordingly, methods for increasing the data storage capacity of semiconductor devices have been studied. For example, as one method for increasing the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally has been proposed. Summary of the Invention [Problem to be solved by the invention]

[0003] One of the technical problems to be solved by the technical concept of the present invention is to provide a semiconductor device capable of improving the integration density and reliability.

[0004] One of the technical problems to be solved by the technical concept of the present invention is to provide a data storage system including a semiconductor device. [Means for solving the problem]

[0005] According to an embodiment of the present invention, there is provided a semiconductor device, comprising: a memory cell array region and a staircase region on a pattern structure; a stack structure disposed in the memory cell array region and extending from the memory cell array region into the staircase region, the stack structure including interlayer insulating layers and gate layers alternately stacked in a vertical direction, the gate layers including gate pads arranged in a staircase region; an isolation structure contacting the pattern structure and including a portion penetrating the stack structure; a memory vertical structure contacting the pattern structure and including a portion penetrating the stack structure in the memory cell array region; a support vertical structure contacting the pattern structure and including a portion penetrating the stack structure in the staircase region; a gate contact plug disposed on the gate pad; and a first peripheral contact plug spaced apart from the gate layer. The isolation structure includes a line portion extending in a first horizontal direction toward the staircase region in the memory cell array region, an upper surface of the memory vertical structure is located at a first height level, an upper surface of the first peripheral contact plug is located at a second height level higher than the first height level, an upper surface of the isolation structure is located at a third height level higher than the second height level, and an upper surface of the gate contact plug is located at a fourth height level higher than the third height level.

[0006] According to one embodiment of the present invention, there is provided a semiconductor device including a first structure, a second structure vertically overlapping the first structure, a memory vertical structure, a support vertical structure, a peripheral contact plug, an isolation structure, and a gate contact plug, wherein the first structure includes a pattern structure including a silicon layer, the second structure is stacked in a memory cell array region at a distance from the first structure in the vertical direction and includes a gate layer extending from the memory cell array region into a staircase region adjacent to the memory cell array region, the gate layer including gate pads arranged in a staircase region, the memory vertical structure including a portion that contacts the pattern structure and penetrates the gate layer in the memory cell array region, and the support vertical structure is in contact with the pattern structure to support the stacked structure in the staircase region. the peripheral contact plug is spaced apart from the gate layer; the isolation structure includes a portion that contacts the pattern structure and penetrates the second structure; the gate contact plug is disposed on the gate pad; an upper surface of the memory vertical structure is located at a first height level, an upper surface of the first peripheral contact plug is located at a second height level, an upper surface of the isolation structure is located at a third height level, and an upper surface of the gate contact plug is located at a fourth height level, and the first to fourth height levels are located at different heights.

[0007] According to an embodiment of the present invention, there is provided a data storage system including a main substrate, a semiconductor device on the main substrate, and a controller electrically connected to the semiconductor device and controlling the semiconductor device. The semiconductor device includes a memory cell array region and a staircase region on a pattern structure, a stack structure disposed in the memory cell array region and extending from the memory cell array region into the staircase region, the stack structure including interlayer insulating layers and gate layers alternately stacked in a vertical direction, the gate layer including gate pads arranged in a staircase region, an isolation structure contacting the pattern structure and including a portion penetrating the stack structure, a memory vertical structure contacting the pattern structure and including a portion penetrating the stack structure in the memory cell array region, and a support vertical structure contacting the pattern structure and including a portion penetrating the stack structure in the staircase region. the isolation structure includes a line portion extending in a first horizontal direction toward the staircase region in the memory cell array region; an upper surface of the memory vertical structure is located at a first height level, an upper surface of the first peripheral contact plug is located at a second height level higher than the first height level, an upper surface of the isolation structure is located at a third height level higher than the second height level, and an upper surface of the gate contact plug is located at a fourth height level higher than the third height level; the memory vertical structure includes a channel layer, and the support vertical structure does not include material of the channel layer. [Effects of the Invention]

[0008] According to an embodiment of the technical concept of the present invention, a semiconductor device including a memory vertical structure, a peripheral contact plug, a support vertical structure, an isolation structure, and a gate contact plug, and a data storage system including the same can be provided. The support vertical structure can prevent deformation or distortion of gate layers stacked at a vertical distance. The memory vertical structure, the peripheral contact plug, the isolation structure, and the gate contact plug can have upper surfaces located at different height levels. By providing a method for forming the isolation structure after forming the peripheral contact plug and the support vertical structure, and a semiconductor device formed by this method, it is possible to provide a semiconductor device and a data storage system that can improve integration density and reliability.

[0009] The various yet significant advantages and effects of the present invention are not limited to the above, but can be more easily understood in the course of describing specific embodiments of the present invention. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic plan view showing an illustrative example of a semiconductor device according to an embodiment of the present invention; [Figure 2a] 1 is a schematic cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention; [Figure 2b] 1 is a schematic cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention; [Figure 2c] 1 is a schematic cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention; [Figure 3] 1 is a schematic, partially enlarged cross-sectional view showing a part of a semiconductor device according to an embodiment of the present invention; [Figure 4] 1 is a schematic, partially enlarged cross-sectional view showing a part of a semiconductor device according to an embodiment of the present invention; [Figure 5] 1 is a schematic, partially enlarged cross-sectional view showing a part of a semiconductor device according to an embodiment of the present invention; [Figure 6] FIG. 10 is a schematic cross-sectional view showing a modified example of a semiconductor device according to an embodiment of the present invention. [Figure 7] FIG. 10 is a schematic cross-sectional view showing a modified example of a semiconductor device according to an embodiment of the present invention. [Figure 8a] 1A-1D are schematic cross-sectional views illustrating an illustrative example of a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 8b] 1A-1D are schematic cross-sectional views illustrating an illustrative example of a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 8c] 1A-1D are schematic cross-sectional views illustrating an illustrative example of a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 9a] 1A-1D are schematic cross-sectional views illustrating an illustrative example of a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 9b] 1A-1D are schematic cross-sectional views illustrating an illustrative example of a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 10a] 1A-1D are schematic cross-sectional views illustrating an illustrative example of a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 10b] 1A-1D are schematic cross-sectional views illustrating an illustrative example of a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 10c] 1A-1D are schematic cross-sectional views illustrating an illustrative example of a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 11] 1 is a diagram illustrating a data storage system including a semiconductor device according to an exemplary embodiment of the present invention; [Figure 12] 1 is a perspective view schematically illustrating a data storage system including a semiconductor device according to an exemplary embodiment of the present invention; [Figure 13] 1 is a cross-sectional view schematically illustrating a data storage system including a semiconductor device according to an exemplary embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, terms such as "top," "upper," "upper surface," "lower," "lower," "bottom," "side," etc., may be understood to refer to the drawings unless otherwise indicated by a drawing reference number. Terms such as "upper," "middle," and "lower" may be used in place of other terms, such as "first," "second," and "third," to describe elements in the specification. While terms such as "first" and "second" may be used to describe various elements, the elements are not limited by these terms, and a "first element" may be named a "second element."

[0012] First, an illustrative example of a semiconductor device according to an embodiment of the present invention will be described with reference to Figures 1 to 2c. Figure 1 is a schematic plan view showing an illustrative example of a semiconductor device according to an embodiment of the present invention, Figure 2a is a schematic cross-sectional view showing a region taken along line I-I' in Figure 1, Figure 2b is a schematic cross-sectional view showing a region taken along line II-II' in Figure 1, and Figure 2c is a schematic cross-sectional view showing a region taken along line III-III' in Figure 1.

[0013] 1 to 2c, a semiconductor device 1 according to an embodiment may include a first structure 3 and a second structure 21 overlapping the first structure 3 in the vertical direction Z.

[0014] In an illustrative example, the first structure 3 may include a pattern structure 17. The pattern structure 17 may include at least one silicon layer.

[0015] In an illustrative example, the pattern structure 17 may include a first pattern layer 17a, a second pattern layer 17b', a third pattern layer 17c, and a fourth pattern layer 17d. The second pattern layer 17b' and the fourth pattern layer 17d may be spaced apart from each other on the first pattern layer 17a. The second pattern layer 17b' and the fourth pattern layer 17d may be distinguished by different hatching in FIGS. 2a and 2b. The third pattern layer 17c may cover the second pattern layer 17b and the fourth pattern layer 17d on the first pattern layer 17a. The first pattern layer 17a may have a thickness greater than that of the second pattern layer 17b, the third pattern layer 17c, and the fourth pattern layer 17d. The first pattern layer 17a may be disposed below the second, third, and fourth pattern layers 17b', 17c, and 17d. At least one of the first pattern layer 17a, the second pattern layer 17b, the third pattern layer 17c, and the fourth pattern layer 17d may include a silicon layer. For example, the first pattern layer 17a, the second pattern layer 17b, and the third pattern layer 17c may include a silicon layer, for example, a silicon layer having an N-type conductivity, and the fourth pattern layer 17d may include a silicon layer and other materials. For example, the fourth pattern layer 17d may include a plurality of layers stacked in sequence, for example, a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence.

[0016] In an illustrative example, the first structure 3 may further include a semiconductor substrate 4, a peripheral circuit 8 on the semiconductor substrate 4, and a lower insulating layer 13 covering the peripheral circuit 8 on the semiconductor substrate 4. The peripheral circuit 8 may include circuit elements 9, such as transistors, each including a peripheral gate 9a and a peripheral source / drain 9b, and circuit wiring 11 electrically connected to the circuit elements 9. A portion of the circuit wiring 11 may be peripheral circuit pads 11p1, 11p2. The pattern structure 17 may be disposed on the lower insulating layer 13.

[0017] In an illustrative example, the pattern structure 17 may be disposed on the lower insulating layer 13 .

[0018] In an illustrative example, the pattern structure 17 may further include a ground pattern 18. For example, the ground pattern 18 may be disposed under the first pattern layer 17a and may be grounded to the semiconductor substrate 4 via a portion of the circuit wiring 11. The ground pattern 18 may be extended from the first pattern layer 17a. For example, if the first pattern layer 17a is formed of a silicon layer, the ground pattern 18 may be formed of a silicon layer extending from the silicon layer.

[0019] In an illustrative example, the pattern structure 17 may have gaps 17g, where each of the gaps 17g may be a slit or an opening penetrating the pattern structure 17.

[0020] In an illustrative example, the first structure 3 may further include an inner intermediate insulating layer 19 a filling the gap 17 g and an outer intermediate insulating layer 19 disposed on the outside of the pattern structure 17 .

[0021] In an illustrative example, the second structure 21 may include a memory cell array region MCA and a staircase region SA. The second structure 21 may include stacked structures 23′ and 35′ disposed in the memory cell array region MCA and extending from the memory cell array region MCA into the staircase region SA.

[0022] In an illustrative example, the stacked structures 23′ and 35′ may include a first stacked structure 23′ and a second stacked structure 35′ on the first stacked structure 23′. The first stacked structure 23′ may include first interlayer insulating layers 25 and first gate layers 27g that are alternately stacked in a vertical direction Z. The vertical direction Z may be a direction perpendicular to an upper surface of the pattern structure 17. The first gate layer 27g may have first gate pads 27p arranged in a stepped pattern in the stepped region SA.

[0023] In an illustrative example, the second stacked structure 35′ may include second interlayer insulating layers 38 and second gate layers 40g that are alternately stacked in the vertical direction Z. The second gate layers 40g may have second gate pads 40P that are arranged in a stepped pattern within the stepped region SA.

[0024] The first interlayer insulating layer 25 and the second interlayer insulating layer 38 may constitute interlayer insulating layers 25 and 38, and the first gate layer 27g and the second gate layer 40g may constitute gate layers 27g and 40g. Therefore, the stacked structures 23' and 35' may include the interlayer insulating layers 25 and 38 and the gate layers 27g and 40g that are alternately stacked in the vertical direction Z. The gate layers 27g and 40g may have the first and second gate pads 27P and 40P that are arranged in a stepped pattern in the stepped region SA.

[0025] In the embodiment, a "gate pad" can be defined as a region of the gate layer that is not covered by other gate layers within the staircase region SA.

[0026] In the embodiment, the first and second gate pads 27P and 40P may be arranged in various stepped shapes in addition to the stepped shape shown in the drawings.

[0027] In an illustrative example, the first and second gate pads 27P and 40P may have a thickness greater than that of the first and second gate layers 27g and 40g located in the memory cell array region MCA. For example, the first gate pad 27P may be a thickened portion at an end of the first gate layer 27g.

[0028] In an illustrative example, each of the first and second gate layers 27g and 40g may include a conductive material. For example, the first and second gate layers 27g and 40g may be formed of one or more of doped polysilicon, a metal-semiconductor compound (e.g., TiSi, TaSi, CoSi, NiSi, or WSi), a metal nitride (e.g., TiN, TaN, or WN), or a metal (e.g., Ti or W). The interlayer insulating layers 25 and 38 may be formed of an insulating material such as silicon oxide.

[0029] In an illustrative example, the stacked structures 23′, 35′ may further include one or more through regions TA. Each of the through regions TA may further include an insulating horizontal layer 27i, 40i located at the same level as the first and second gate layers 27g, 40g adjacent to the through region TA. For example, a portion of the through region TA adjacent to the first gate layer 27g may include a first insulating horizontal layer 27i located at the same level as the first gate layer 27g, and a portion of the through region TA adjacent to the second gate layer 40g may include a second insulating horizontal layer 40i located at the same level as the second gate layer 40g.

[0030] In an illustrative example, each of the through regions TA may further include a reinforcing horizontal layer 28, 41 on the uppermost insulating horizontal layer of the insulating horizontal layers 27i, 40i and in contact with the uppermost insulating horizontal layer. For example, the through region TA spaced apart from the second laminate structure 35′ may include a first reinforcing horizontal layer 28 in contact with the uppermost first insulating horizontal layer of the first insulating horizontal layers 27i, and the through region TA located within the first and second laminate structures 23′, 35′ may include a second reinforcing horizontal layer 41 in contact with the uppermost second insulating horizontal layer of the second insulating horizontal layers 40i.

[0031] In an illustrative example, the first and second insulating horizontal layers 27i and 40i may be formed of a different insulating material from the first and second interlayer insulating layers 25 and 38. For example, the first and second insulating horizontal layers 27i and 40i may be formed of a first silicon nitride, and the first and second interlayer insulating layers 25 and 38 may be formed of a silicon oxide.

[0032] In an illustrative example, the first and second reinforcing horizontal layers 28 and 41 may be formed of a second silicon nitride having an etching rate different from that of the first silicon nitride of the first and second insulating horizontal layers 27i and 40i. The second silicon nitride may be a material having a faster etching rate than the first silicon nitride.

[0033] 1, in the stacked structures 23' and 35', each of the through regions TA may be surrounded by a gate region (GA in FIG. 1). Here, the gate region GA may be a region where the first and second gate layers 27g and 40g are disposed. Therefore, each of the through regions TA may be surrounded by the adjacent first and second gate layers 27g and 40g.

[0034] In an illustrative example, the second structure 21 may further include capping insulating layers 32 and 14. The capping insulating layers 32 and 44 may include a first capping insulating layer 32 and a second capping insulating layer 44. The first capping insulating layer 32 may cover the first gate pad 27P, a portion of the pattern structure 17 not covered by the first stacked structure 23′, and the outer intermediate insulating layer 19b. The second capping insulating layer 44 may cover the second gate pad 40P and the first capping insulating layer 32. The first and second capping insulating layers 32 and 14 may be formed of an insulating material such as silicon oxide.

[0035] The semiconductor device 1 according to the embodiment may further include a memory vertical structure 47 penetrating the second structure 21′. The memory vertical structure 47 may include a portion penetrating the stacked structures 23′ and 35′ in the memory cell array region MCA. The memory vertical structure 47 may extend from the portion penetrating the second structure 21′ into the pattern structure 17 to contact the pattern structure 17. For example, the memory vertical structure 47 may sequentially penetrate the third pattern layer 17c and the second pattern layer 17b′ and extend into the first pattern layer 17a. The memory vertical structure 47 may contact at least one of the first to third pattern layers 17a, 17b′, and 17c, which may be formed of silicon layers. Therefore, the memory vertical structure 47 may contact at least one silicon layer of the pattern structure 17.

[0036] The semiconductor device 1 according to the embodiment may further include a string isolation pattern 45 penetrating one or more upper gate layers located on the upper side of the second gate layer 40g. The string isolation pattern 45 may be made of silicon oxide.

[0037] The semiconductor device 1 according to the embodiment may further include a dummy vertical structure 47d that penetrates the string isolation pattern 45, penetrates the second structure 21′, and contacts the pattern structure 17. The dummy vertical structure 47d may have the same cross-sectional structure as the memory vertical structure 47 and may be formed of the same material.

[0038] The semiconductor device 1 according to the embodiment may further include a first upper insulating layer 58 on the second structure 21'. The first upper insulating layer 58 may include silicon oxide.

[0039] The semiconductor device 1 according to the embodiment may further include support vertical structures 62 that penetrate the first upper insulating layer 58 and the second structure 21′ and contact the pattern structure 17. At least a plurality of the support vertical structures 62 may sequentially penetrate the third pattern layer 17c and the fourth pattern layer 17d of the pattern structure 17 and extend into the first pattern layer 17a. Any one of the support vertical structures 62 may be spaced apart from the fourth pattern layer 17d and extend into the first pattern layer 17a through the third pattern layer 17c.

[0040] Although a plurality of support vertical structures 62 may be arranged, for convenience of explanation, only one support vertical structure will be described.

[0041] The upper surface of the support platform vertical structure 62 may be disposed at a higher level than the upper surface of the memory vertical structure 47 .

[0042] In the embodiment, the term "level" may refer to the height level when viewed from the top surface of the pattern structure 17.

[0043] In an illustrative example, the support vertical structure 62 may comprise silicon dioxide or silicon dioxide with voids formed therein.

[0044] The semiconductor device 1 according to the embodiment may further include peripheral contact plugs 61 a, 61 b, and 61 c. The peripheral contact plugs 61 a, 61 b, and 61 c may include a first peripheral contact plug 61 a, a second peripheral contact plug 61 b, and a third peripheral contact plug 61 c.

[0045] In an illustrative example, the first peripheral contact plug 61a may penetrate the first upper insulating layer 58 and the second structure 21′ and contact the pattern structure 17. The first peripheral contact plug 61a may penetrate the first and second capping insulating layers 32 and 44 of the second structure 21′ and be spaced apart from the stack structures 23′ and 35′ of the second structure 21′.

[0046] In an illustrative example, the first pattern layer 17a formed of a polysilicon layer having N-type conductivity in the pattern structure 17 may be a common source region, and the first peripheral contact plug 61a may be a common source contact plug electrically connected to the common source region. The first peripheral contact plug 61 may be in contact with the first pattern layer 17a.

[0047] In an illustrative example, the second peripheral contact plug 61b may penetrate the first upper insulating layer 58, the second structure 21′, and the inner intermediate insulating layer 19a and extend downward to contact the first peripheral circuit pad 11p1. The second peripheral contact plug 61b may penetrate at least one of the first and second capping insulating layers 32 and 44 of the second structure 21′ and the through region TA of the stack structures 23′ and 35′ of the second structure 21′. Therefore, the second peripheral contact plug 61b may include a portion that penetrates the insulating horizontal layers 27i and 40i in the through region TA.

[0048] In an illustrative example, the third peripheral contact plug 61c may penetrate the first upper insulating layer 58, the first and second capping insulating layers 32, 44 of the second structure 21′, and the outer intermediate insulating layer 19b, and extend downward to contact the second peripheral circuit pad 11p2.

[0049] The first to third peripheral contact plugs 61a, 61b, and 61c may be separated from the first and second gate layers 27g and 40g of the stacked structures 23' and 35' and may not contact the first and second gate layers 27g and 40g.

[0050] The top surfaces of the first to third peripheral contact plugs 61a, 61b, and 61c may be disposed at substantially the same level as the top surface of the support vertical structure 62. The top surfaces of the first to third peripheral contact plugs 61a, 61b, and 61c and the support vertical structure 62 may be disposed at a higher level than the top surface of the memory vertical structure 47.

[0051] A second upper insulating layer 64 may be disposed on the first upper insulating layer 58. The second upper insulating layer 64 may include silicon oxide.

[0052] The semiconductor device 1 according to the embodiment may further include an isolation structure 68 penetrating the second upper insulating layer 64, the first upper insulating layer 58, and the second structure 21′. Each of the isolation structures 68 may be formed of silicon oxide or silicon oxide having voids formed therein. The isolation structure 68 may include a plurality of main isolation structures 68M parallel to each other and auxiliary isolation structures 68S disposed between the main isolation structures 68M. Each of the isolation structures 68 may include a line portion extending in a first horizontal direction X. The first horizontal direction X may be parallel to an upper surface of the pattern structure 17. The first horizontal direction X may be a direction toward the staircase region SA in the memory cell array region MCA. Each of the auxiliary isolation structures 68S may have a length shorter than that of each of the main isolation structures 68M. The main separation structure 68M may penetrate the second structure 21′ to separate the stacked structures 23′ and 35′ in a second horizontal direction Y. The second horizontal direction Y may be parallel to the top surface of the pattern structure 17 and may be perpendicular to the first horizontal direction X.

[0053] An upper surface of the isolation structure 68 may be disposed at a higher level than an upper surface of the first to third peripheral contact plugs 61 a , 61 b ​​, and 61 c and the support vertical structure 62 .

[0054] Each of the isolation structures 68 may contact the gate layer 27g, 40g adjacent to the isolation structure 68.

[0055] In an illustrative example, the isolation structure 68 may include an isolation protrusion 68p protruding in a direction toward the gate layers 27g and 40g adjacent to the isolation structure 68. The width of the portion of the isolation structure 68 where the isolation protrusion 68p is located may be greater than the width of the portion adjacent to the isolation protrusion 68p in the vertical direction Z.

[0056] In an illustrative example, the isolation structures 68 may extend downward from the portions penetrating the second structures 21′ to contact the pattern structures 17′. At least one of the isolation structures 68 may contact the first pattern layer 17a. At least one of the isolation structures 68 may penetrate the third and fourth pattern layers 17c and 17d and a portion of the first pattern layer 17a.

[0057] The semiconductor device 1 according to the embodiment may further include a dielectric layer 67. The dielectric layer 67 may include a high-k dielectric having a dielectric constant greater than that of silicon oxide. For example, the dielectric layer 67 may be formed of a high-k dielectric such as aluminum oxide, lanthanum oxide, or hafnium oxide.

[0058] The dielectric layer 67 may include a first dielectric layer portion (67a in FIG. 2c) and a second dielectric layer portion (67b in FIG. 2c). The first dielectric layer portion 67a may cover upper and lower surfaces of the gate layers 27g and 40g, be disposed between the gate layers 27g and 40g and the memory vertical structure 47, and be disposed between the gate layers 27g and 40g and the support vertical structure 62. The second dielectric layer portion 67b may extend from the first dielectric layer portion 67a and cover a side surface of the isolation structure 68 that is not in contact with the gate layers 27g and 40g.

[0059] In an illustrative example, the lower end of the support vertical structure 62 may be disposed at a different level from the lower end of the isolation structure 68 adjacent to the support vertical structure 62. For example, the lower end of the support vertical structure 62 may be disposed at a lower level than the lower end of the isolation structure 68. The lower end of the support vertical structure 62 may contact the first pattern layer 17a. The lower end of the isolation structure 68 may be separated from the first pattern layer 17a by the second dielectric layer portion 67b.

[0060] The semiconductor device 1 according to the embodiment may further include a third upper insulating layer 72 disposed on the second upper insulating layer 64. The third upper insulating layer 72 may include silicon oxide.

[0061] The semiconductor device 1 according to the embodiment may further include a gate contact plug 75 that penetrates the first to third upper insulating layers 58, 64, and 72 and extends downward to contact the gate pad 40p. An upper surface of the gate contact plug 75 may be disposed at a higher level than an upper surface of the isolation structure 68.

[0062] The semiconductor device 1 according to the embodiment may further include a fourth upper insulating layer 78 disposed on the third upper insulating layer 72. The fourth upper insulating layer 78 may include silicon oxide.

[0063] The semiconductor device 1 according to the embodiment may further include a bit line contact plug 81b that penetrates the first to fourth upper insulating layers 58, 64, 72, and 78 and is electrically connected to the memory vertical structure 47.

[0064] In an illustrative example, the bit line contact plug 81 b may include sides that are not vertically aligned with the sides of the memory vertical structure 47 .

[0065] The semiconductor device 1 according to the embodiment may further include peripheral upper plugs 81s, 81p1, and 81p2 penetrating the second to fourth upper insulating layers 64, 72, and 78. The peripheral upper plugs 81s, 81p1, and 81p2 may further include a first peripheral upper plug 81s electrically connected to the first peripheral contact plug 61a, a second peripheral upper plug 81p1 electrically connected to the second peripheral contact plug 61b, and a third peripheral upper plug 81p2 electrically connected to the third peripheral contact plug 61c.

[0066] In an illustrative example, the first peripheral upper plug 81s may include a side surface that is not vertically aligned with a side surface of the first peripheral contact plug 61a.

[0067] In an illustrative example, the second peripheral upper plug 81p1 may include a side surface that is not vertically aligned with a side surface of the second peripheral contact plug 61b.

[0068] In an illustrative example, the third peripheral upper plug 81p2 may include a side surface that is not vertically aligned with a side surface of the third peripheral contact plug 61c.

[0069] The semiconductor device 1 according to the embodiment may further include an upper gate plug 81 g that penetrates the fourth upper insulating layer 78 and is electrically connected to the gate contact plug 75 .

[0070] In an illustrative example, the gate contact plug 75 and the gate upper plug 81g may include a first gate contact plug and a first gate upper plug that contact each other, and the first gate contact plug may include a side that is not vertically aligned with a side of the first gate upper plug.

[0071] The semiconductor device 1 according to the embodiment may further include wirings 84b, 84g, and 84p disposed on the fourth upper insulating layer 78. The wirings 84b, 84g, and 84p may include a bit line 84b electrically connected to the bit line contact plug 81b, gate connecting wirings 84g electrically connecting each of the gate upper plugs 81g to the plurality of second peripheral upper plugs 81p1, a first peripheral wiring 84s electrically connected to the first peripheral upper plug 81s, and a second peripheral wiring 84p electrically connected to the third peripheral upper plug 81p2.

[0072] In the above-described embodiment, each of the isolation structures 68 may include a line portion extending in the first horizontal direction X from the memory cell array region MCA toward the staircase region SA.

[0073] In the above-described embodiment, the top surface of the memory vertical structure 47 may be located at a first height level, the top surface of the first peripheral contact plug 61a may be located at a second height level, the top surface of the isolation structure 68 may be located at a third height level, and the top surface of the gate contact plug 75 may be located at a fourth height level. The top surface of the support vertical structure 62 may be located at the second height level. The first to fourth height levels may be different heights from each other. In an illustrative example, the second height level may be higher than the first height level, the third height level may be higher than the second height level, and the fourth height level may be higher than the third height level.

[0074] Next, an illustrative example of the gate contact plug 75 will be described with reference to Figure 3. Figure 3 is a partially enlarged view of the portion indicated by "A" in Figure 2a.

[0075] 3, each of the gate contact plugs 75 may include a plug pattern 75b and a liner layer 75a covering the side and bottom surfaces of the plug pattern 75b. The liner layer 75a may include at least one of a metal material such as Ti and a metal nitride such as TiN. The plug pattern 75b may include a metal material such as tungsten.

[0076] Next, an illustrative example of the second and third peripheral contact plugs 61b and 61c will be described with reference to Figure 4. Figure 4 is a partial enlarged view of the portions indicated by "B1" and "B2" in Figure 2a.

[0077] 4, each of the second and third peripheral contact plugs 61b and 61c may include a plug pattern 60b and a liner layer 60a covering the side and bottom surfaces of the plug pattern 60b. The liner layer 60a may include at least one of a metal material, such as Ti, and a metal nitride, such as TiN. The plug pattern 60b may include a metal material, such as tungsten. The first peripheral contact plug 61a may include the same material as the second and third peripheral contact plugs 61b and 61c, for example, the liner layer 60a and the plug pattern 60b.

[0078] An illustrative example of the gate layers 27g, 40g and the memory vertical structure 47 will now be described with reference to Figure 5. Figure 5 is a partial enlarged view of the portion marked "C" in Figure 2a.

[0079] 5, the gate layers 27g, 40g may include one or more lower gate layers GL1, GL2, the one or more upper gate layers GU1, GU2, and a plurality of intermediate gate layers GM disposed between the one or more lower gate layers GL1, GL2 and the one or more upper gate layers GU1, GU2. In an illustrative example, the one or more upper gate layers GU1, GU2 may be spaced apart from each other in the vertical direction Z. For example, the plurality of upper gate layers GU1, GU2 may include a first upper gate layer GU1 and a second upper gate layer GU2 disposed below the first upper gate layer GU1.

[0080] In an illustrative example, the one or more lower gate layers GL1 and GL2 may be a plurality of lower gate layers spaced apart from each other in the vertical direction Z. For example, the plurality of lower gate layers GL1 and GL2 may include a first lower gate layer GL1 and a second lower gate layer GL2 disposed on the first lower gate layer GL1.

[0081] In an illustrative example, a plurality of the intermediate gate layers GM may be word lines.

[0082] In an illustrative example, the first lower gate layer GL1 may be a ground select gate line of a ground select transistor, and the second lower gate layer GL2 may be a dummy gate line. In another example, the first lower gate layer GL1 may be an erase control gate line of an erase control transistor that can be used in an erase operation to erase data stored in a memory cell using a gate induced drain leakage (GIDL) phenomenon, and the second lower gate layer GL2 may be a ground select gate line of a ground select transistor.

[0083] In an illustrative example, the plurality of upper gate layers GU1 and GU2 may be string select gate lines of string select transistors. In another example, the first upper gate layer 30U1 of the plurality of upper gate layers GU1 and GU2 may be an erase control gate line of an erase control transistor, and the second upper gate layer GU2 may be a string select gate line of a string select transistor.

[0084] The memory vertical structure 47 may include a lower vertical portion 47L that penetrates the first stacked structure 23' and an upper vertical portion 47U that penetrates the second stacked structure 35'.

[0085] In an illustrative example, the width of the upper region of the lower vertical portion 47L can be different from the width of the lower region of the upper vertical portion 47U. For example, the width of the upper region of the lower vertical portion 47L can be greater than the width of the lower region of the upper vertical portion 47U.

[0086] In an illustrative example, the side surfaces of the lower vertical portion 47L and the upper vertical portion 47U that are adjacent to each other may not be aligned in the vertical direction Z.

[0087] In an illustrative example, the middle side of the memory vertical structure 47 located at a height level between the uppermost first gate layer of the first gate layers 27g of the first stacked structure 23′ and the lowermost second gate layer of the second gate layers 40g of the second stacked structure 35′ may include a curved portion 47V.

[0088] At the same height level as the curved portion 47V of the middle side of the memory vertical structure 47, each side of the above-mentioned isolation structure 68 can be substantially straight, and each side of the peripheral contact plugs 61a, 61b, 61c can be substantially straight.

[0089] The memory vertical structure 47 may include an insulating gap fill layer 53, a channel layer 51 covering the outer and bottom surfaces of the insulating gap fill layer 53, an information storage structure 49 covering the outer and bottom surfaces of the channel layer 51, and a pad material layer 55 on the insulating gap fill layer 53.

[0090] The information storage structure 49 may include a first dielectric layer 49c covering the outer surface and bottom of the channel layer 51, an information storage material layer 49b covering the outer surface and bottom of the first dielectric layer 49c, and a second dielectric layer 49a covering the outer surface and bottom of the information storage material layer 49b. The second dielectric layer 49c may be in contact with the channel layer 51, and the information storage material layer 49b may be spaced apart from the channel layer 51. The insulating gap fill layer 53 may include silicon oxide, for example, silicon oxide formed by atomic layer deposition, or silicon oxide having voids formed therein. The first dielectric layer 49a may include silicon oxide or silicon oxide doped with impurities. The second dielectric layer 49c may include at least one of silicon oxide and a high-dielectric material. The information storage material layer 49b may include a material capable of trapping charge and storing information, for example, silicon nitride.

[0091] The information storage material layer 49b of the information storage structure 49 of the memory vertical structure 47 may include a region capable of storing information in a semiconductor device such as a flash memory device. The channel layer 51 may include polysilicon. The pad material layer 55 may include at least one of doped polysilicon, a metal nitride (e.g., TiN), a metal (e.g., W), and a metal-semiconductor compound (e.g., TiSi).

[0092] The memory vertical structure 47 may penetrate the third pattern layer 17c and the second pattern layer 17b' of the pattern structure 17' in this order and extend into the first pattern layer 17a. In the pattern structure 17', the second pattern layer 17b' may penetrate the information storage structure 49 and contact the channel layer 51.

[0093] In an embodiment, the support vertical structure (62 in FIGS. 2b and 2c) may not include the material of the channel layer 51 of the memory resin structure 47. In an embodiment, the support vertical structure (62 in FIGS. 2b and 2c) may be formed of an insulating material, for example, silicon oxide.

[0094] Next, a modified example of the support platform vertical structure 62 will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view showing a modified example of the support platform vertical structure 62 in the cross-sectional structure of Fig. 2c.

[0095] In a modified example, referring to FIG. 6, the support vertical structure 62′ in the modified example may include a support protrusion 62p extending in a direction toward the gate layer 27g, 40g adjacent to the support vertical structure 62′ among the gate layers 27g, 40g.

[0096] In the support vertical structure 62', the width of the portion where the support protrusion 62p is located may be greater than the width of the portion adjacent to the support protrusion 62p in the vertical direction Z.

[0097] The gate layers 27g and 40g may be disposed between any one of the support structures 62' and any one of the isolation structures 68 adjacent to each other.

[0098] In the support vertical structure 62′, the support protrusion 62p may protrude a first distance when viewed from a side of a portion of the support vertical structure 62′ that contacts the first and second interlayer insulating layers 25 and 38. In the isolation structure 68, the isolation protrusion 68p may protrude a second distance greater than the first distance when viewed from a side of a portion of the isolation structure 68 that faces the first and second interlayer insulating layers 25 and 38. Therefore, the width of any one of the isolation protrusions 68p may be greater than the width of any one of the support protrusions 62p.

[0099] Next, an illustrative example of a semiconductor device according to a modified embodiment of the present invention will be described with reference to Fig. 7. In Fig. 7, region Ia-Ia' may be a cross-sectional region schematically showing a region cut along a first horizontal direction, and region IIIa-IIIa' may be a cross-sectional region schematically showing a region cut along a second horizontal direction perpendicular to the first horizontal direction.

[0100] 7, a semiconductor device 100 according to a modified embodiment may include a vertically stacked lower structure 103 and upper structure 203. The lower structure 103 may be a memory semiconductor chip, and the upper structure 203 may be a logic semiconductor chip.

[0101] The lower structure 103 may include a pattern structure 117 and a structure 121 on the pattern structure 117. The pattern structure 117 may include first to fourth pattern layers 117a to 117d corresponding to the first to fourth pattern layers 17a to 17d, respectively, with reference to FIGS.

[0102] The structure 121 may have substantially the same structure as the second structure 21' described with reference to FIGS. 1 to 2c, except for the through region TA. For example, the structure 121 may include a stacked structure including gate layers 27g and 40g and interlayer insulating layers 25 and 38 that are alternately stacked. The gate layers 27g and 40g may include gate pads 27p and 40p that are substantially the same as those described with reference to FIGS. 1 to 2c. The structure 121 may include the first and second capping insulating layers 32 and 44 described with reference to FIGS. 1 to 2c.

[0103] The lower structure 103 may further include the first to fourth upper insulating layers 58, 64, 72, and 78, which are substantially the same as those described with reference to FIGS. 1 to 2c.

[0104] The lower structure 103 may include the isolation structure 68, the memory vertical structure 47, the support vertical structure 62, the first peripheral contact plug 61a, the gate contact plug 75, the bit line contact plug 81b, the gate upper plug 81g, the first peripheral upper plug 81s, and the wirings 84b, 84g, and 84s, which are substantially the same as those described in Figures 1 to 2c.

[0105] The lower structure 103 may include a capping insulating structure 115 on the fourth upper insulating layer 78 and a lower junction wiring structure 110 electrically connected to the wirings 84b, 84g, and 84s within the capping insulating structure 115. The lower junction wiring structure 110 may include a lower bonding pad 110p.

[0106] The upper structure 203 may include a semiconductor substrate 204, a peripheral circuit 209 disposed between the semiconductor substrate 204 and the lower structure 103, and an upper bonding wiring structure 210 disposed between the peripheral circuit 209 and the lower structure 103. The upper bonding wiring structure 210 may include upper bonding pads 210p. The peripheral circuit 209 may include peripheral elements such as transistors including peripheral gates 209a and peripheral source / drains 209b.

[0107] The lower bonding pads 110p of the lower bonding wiring structure 110 may contact the upper bonding pads 210p of the upper bonding wiring structure 210. The lower bonding pads 110p and the upper bonding pads 110p may include a copper material.

[0108] Next, an illustrative example of a method for forming a semiconductor device according to an embodiment of the present invention will be described with reference to Figures 8a to 10c. In Figures 8a to 10c, Figures 8a and 10a are cross-sectional views schematically showing an area taken along line I-I' in Figure 1, Figures 8b, 9a, and 10b are cross-sectional views schematically showing an area taken along line II-II' in Figure 1, and Figures 8c and 10c are cross-sectional views schematically showing an area taken along line III-III' in Figure 1.

[0109] 8a, 8b, and 8c, a first structure 3 may be formed. The formation of the first structure 3 may include forming a peripheral circuit 8 on a semiconductor substrate 4 and a lower insulating layer 13 covering the peripheral circuit 8, forming a preliminary pattern structure 17 having a gap 17g on the lower insulating layer 13, and forming intermediate insulating layers 19a and 19b that fill the gap 17g and are disposed on outer surfaces of the preliminary pattern structure 17. The peripheral circuit 8 may include circuit elements 9, such as transistors, each including a peripheral gate 9a and a peripheral source / drain 9b, and circuit wiring 11 electrically connected to the circuit element 9. Some of the circuit wiring 11 may be peripheral circuit pads 11p1 and 11p2.

[0110] The preliminary pattern structure 17 may be formed by forming a first pattern layer 17a, forming intermediate pattern layers 17b and 17d spaced apart from each other on the first pattern layer 17a, and forming a third pattern layer 17c covering the intermediate pattern layers 17b and 17d on the first pattern layer 17a. The first and third pattern layers 17a and 17c may be formed of silicon layers. The intermediate pattern layers 17b and 17d may include a plurality of layers stacked in sequence, for example, a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence.

[0111] The intermediate insulating layers 19 a and 19 b may include an inner intermediate insulating layer 19 a filling the gap 17 g and an outer intermediate insulating layer 19 b formed on the outer surface of the preliminary pattern structure 17 .

[0112] A second structure 21 may be formed on the first structure 3. The second structure 21 may include pre-laminate structures 23, 35 including alternately stacked interlayer insulating layers 25, 38 and horizontal layers 27, 40, and capping insulating layers 32, 44 covering at least a portion of the pre-laminate structures 23, 35. The horizontal layers 27, 40 may include pad regions arranged in a stepped pattern. For example, forming the second structure 21 may include forming a first pre-laminate structure 23 on the preliminary pattern structure 17, forming a first capping insulating layer 32 covering a portion of the first pre-laminate structure 23 and the outer intermediate insulating layer 19b, forming a second pre-laminate structure 35 on the first pre-laminate structure 23, and forming a second capping insulating layer 44 covering a portion of the second pre-laminate structure 35 and the first capping insulating layer 32.

[0113] The first pre-laminate structure 23 may include a first interlayer insulating layer 25 and a first horizontal layer 27 that are alternately stacked. The second pre-laminate structure 35 may include a second interlayer insulating layer 40 and a second horizontal layer 40 that are alternately stacked. The first and second interlayer insulating layers 25 and 38 may be made of silicon oxide, and the first and second horizontal layers 27 and 40 may be made of silicon nitride.

[0114] In an illustrative example, the first horizontal layer 27 on at least one side of the first preliminary laminate structure 23 may include pad regions arranged in a stepped pattern. The second horizontal layer 40 on at least one side of the second preliminary laminate structure 35 may include pad regions arranged in a stepped pattern. In the second preliminary structure 21, a region where the stepped pad regions of the first and second horizontal layers 27 and 40 are located may be defined as a stepped region SA, and a region adjacent to the stepped region SA where the first and second horizontal layers 27 and 40 are located may be defined as a memory cell array region MCA.

[0115] In an illustrative example, a first reinforcing horizontal layer 28 may be formed on the stepped region of the first horizontal layer 27 before forming the first capping insulating layer 32. A second reinforcing horizontal layer 41 may be formed on the stepped pad region of the second horizontal layer 40 before forming the second capping insulating layer 44. The first and second reinforcing horizontal layers 41 may be formed of silicon nitride.

[0116] A memory vertical structure 47 may be formed through the memory cell array region MCA of the second preliminary structure 21 and in contact with the preliminary pattern structure 17. Forming the memory vertical structure 47 may include forming a sacrificial vertical portion through the first preliminary laminate structure 23 before forming the second preliminary laminate structure 35, forming an upper channel hole through the second preliminary laminate structure 35 to expose the sacrificial vertical portion after forming the second preliminary laminate structure 35, removing the sacrificial vertical portion exposed by the channel hole to form a lower channel hole, and forming the memory vertical structure 47 in the lower and upper channel holes. The memory vertical structure 47 may include the information storage structure (49 in FIG. 6), the channel layer (51 in FIG. 6), the gap fill material layer (53 in FIG. 6), and the pad material layer (55 in FIG. 6), as described in FIG. 6.

[0117] A first upper insulating layer 58 may be formed on the second preliminary structure 21 .

[0118] The peripheral contact plugs 61a, 61b, 61c and the dummy plug 61d may be formed simultaneously. The peripheral contact plugs 61a, 61b, 61c may include a first peripheral contact plug 61a, a second peripheral contact plug 61b, and a third peripheral contact plug 61c. The first peripheral contact plug 61a may penetrate the first upper insulating layer 58 and the second preliminary structure 21 and contact the preliminary pattern structure 17. The first peripheral contact plug 61a may penetrate the first and second capping insulating layers 32 and 44 of the second preliminary structure 21 and be spaced apart from the preliminary stack structures 23 and 35 of the second preliminary structure 21. The second peripheral contact plug 61b may penetrate the first upper insulating layer 58, the second preliminary structure 21, and the inner intermediate insulating layer 19a and extend downward to contact the first peripheral circuit pad 11p1. The third peripheral contact plug 61c may penetrate the first upper insulating layer 58, the first and second capping insulating layers 32 and 44 of the second preliminary structure 21, and the outer intermediate insulating layer 19b, and extend downward to contact the second peripheral circuit pad 11p2. The dummy plug 61d may penetrate the first upper insulating layer 58 and the preliminary stack structures 23 and 35 of the second preliminary structure 21, and contact the pattern structure 17.

[0119] The peripheral contact plugs 61a, 61b, 61c and the dummy plug 61d may include the plug pattern (60b in FIG. 4) identical to that described in FIG. 4 and the liner layer (60a in FIG. 4) covering the side and bottom surfaces of the plug pattern 60b.

[0120] 9a and 9b, the dummy plugs 61d in FIGS. 8b and 8c may be replaced with the support vertical structures 62. For example, the dummy plugs 61d in FIGS. 8b and 8c may be removed to form support holes, and the support vertical structures 62 may be formed in the support holes. The support vertical structures 62 may be formed of an insulating material such as silicon oxide. Thus, the support vertical structures 62 described in FIGS. 2b and 2c may be formed.

[0121] In another example, to form the support base vertical structure 62' in the modified example described in Figure 6, while forming the support hole, the first and second horizontal layers 27, 40 exposed by the support hole can be partially etched to increase the width of the support hole.

[0122] 10a, 10b, and 10c, a second upper insulating layer 64 may be formed on the first upper insulating layer 58. An isolation trench 68t may be formed to sequentially penetrate the second upper insulating layer 64, the first upper insulating layer 58, and the second preliminary structure 21 and extend into the preliminary pattern structure 17. The isolation trench 68t may expose the first intermediate pattern layer (17b in FIG. 9a) under the memory cell array region MCA and may be separated from the second intermediate pattern layer 17d. After removing the first intermediate pattern layer (17b in FIG. 9a) exposed by the isolation trench 68t, a third pattern layer 17b' may be formed in the space where the first intermediate pattern layer (17b in FIG. 9a) was removed. The third pattern layer 17b' may be formed of a polysilicon layer having N-type conductivity. The remaining second intermediate pattern layer 17d can be referred to as a fourth pattern layer 17d.

[0123] The first and second horizontal layers 27 and 40 of the second preliminary structure 21 exposed by the isolation trench 68t may be partially etched to form an empty space, and first and second gate layers 27g and 40g may be formed in the empty space. The first preliminary stack structure 23 may be formed of a first stack structure 23' including the first interlayer insulating layer 25 and the first gate layer 27g, and the second preliminary stack structure 35 may be formed of a second stack structure 35' including the second interlayer insulating layer 38 and the second gate layer 40g. Therefore, the second preliminary structure 21 may be formed of a second structure 21' including the first and second stack structures 23' and 35'.

[0124] The first and second horizontal layers 27 and 40 may remain and be formed as the first and second insulating horizontal layers 27i and 40i described with reference to Figures 1 to 2c. A region in the second structure 21' where the first and second insulating horizontal layers 27i and 40i are formed may be defined as a through region TA.

[0125] In an illustrative example, prior to forming the first and second gate layers 27g, 40g in the open spaces, a dielectric layer 57 as described in FIG. 2c may be conformally formed.

[0126] Forming the first and second gate layers 27g and 40g in the vacant spaces may include forming a conductive material layer in the vacant spaces and etching the conductive material layer.

[0127] An isolation structure 68 may be formed in the isolation trench 68t. The isolation structure 68 may be formed of silicon oxide.

[0128] 2a, 2b, and 2c, a third upper insulating layer 72 may be formed on the second upper insulating layer 64. A gate contact plug 75 may be formed by penetrating the first to third upper insulating layers 58, 64, and 72 and extending downward to contact the gate pad 40p. A fourth upper insulating layer 78 may be formed on the third upper insulating layer 72. A bit line contact plug 81b may be formed by penetrating the first to fourth upper insulating layers 58, 64, 72, and 78 and electrically connected to the memory vertical structure 47, peripheral upper plugs 81s, 81p1, and 81p2 may be formed by penetrating the second to fourth upper insulating layers 64, 72, and 78, and a gate upper plug 81g may be formed by penetrating the fourth upper insulating layer 78 and electrically connected to the gate contact plug 75. Wirings 84b, 84g, and 84p may be formed on the fourth upper insulating layer 78. The wirings 84b, 84g, and 84p may include a bit line 84b electrically connected to the bit line contact plug 81b, a gate connecting wiring 84g electrically connecting each of the gate upper plugs 81g to the plurality of second peripheral upper plugs 81p1, a first peripheral wiring 84s electrically connected to the first peripheral upper plug 81s, and a second peripheral wiring 84p electrically connected to the third peripheral upper plug 81p2.

[0129] Next, a data storage system including a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 11, 12 and 13, respectively.

[0130] FIG. 11 is a diagram illustrating a data storage system including a semiconductor device according to an exemplary embodiment of the present invention.

[0131] 11 , a data storage system 1000 according to an exemplary embodiment of the present invention may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be a storage device including the semiconductor device 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be a solid state drive (SSD) device, a Universal Serial Bus (USB), a computing system, a medical device, or a communication device including the semiconductor device 1100.

[0132] In an embodiment, the data storage system 1000 can be an electronic system that stores data.

[0133] The semiconductor device 1100 may be a semiconductor device according to any one of the embodiments described above with reference to Figures 1 to 10c. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0134] The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. For example, the first structure 1100F may include the peripheral circuit (8 in FIG. 2a) described above.

[0135] The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines UL1, UL2, first and second gate lower lines LL1, LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0136] The above-mentioned pattern structure (17' in Figures 2a to 2c) may include a silicon layer having N-type conductivity, and the silicon layer having N-type conductivity may be the common source line CSL.

[0137] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The numbers of the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2 may be variously modified according to embodiments.

[0138] In an exemplary embodiment, the upper transistors UT1 and UT2 may comprise string select transistors, and the lower transistors LT1 and LT2 may comprise ground select transistors. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of a memory cell transistor MCT, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0139] Of the first and second gate layers 27g and 40g described above with reference to FIG. 5, the lower gate layers GL1 and GL2 may be the gate lower lines LL1 and LL2, at least a plurality of the middle gate layers GM may be the word lines WL, and the upper gate layers GU1 and GU2 may be the gate upper lines UL1 and UL2.

[0140] In an exemplary embodiment, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 may be used in an erase operation that erases data stored in the memory cell transistor MCT using a gate induced drain leakage (GIDL) phenomenon.

[0141] The common source line CSL, the first and second gate lower lines LL1, LL2, the word line WL, and the first and second gate upper lines UL1, UL2 can be electrically connected to the decoder circuit 1110 via a first connecting wiring 1115 extending to the second structure 1100S within the first structure 1100F.

[0142] In an exemplary embodiment, the lower gate layers (30L1 and 30L2 in FIG. 2a) may be the lower gate lines LL1 and LL2, and the upper gate layers (30U1 and 30U2 in FIG. 2a) may be the upper gate lines UL1 and UL2. A plurality of the middle gate layers (30M in FIG. 2a) may be the word lines WL.

[0143] The bit line BL may be electrically connected to the page buffer 1120 through a second connecting wire 1125 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be the bit line 84b of FIGS. 2a and 2b.

[0144] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor of the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by a logic circuit 1130. The semiconductor device 1000 may communicate with the controller 1200 through the I / O pad 1101 electrically connected to the logic circuit 1130. The I / O pad 1101 may be electrically connected to the logic circuit 1130 through an I / O connecting line 1135 extending to the second structure 1100S in the first structure 1100F.

[0145] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. According to an embodiment, the data storage system 1000 may include a plurality of semiconductor devices 1100, in which case the controller 1200 may control the plurality of semiconductor devices 1000.

[0146] The processor 1210 may control the overall operation of the data storage system 1000, including the controller 1200. The processor 1210 may operate according to predetermined firmware and control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor device 1100. Control commands for controlling the semiconductor device 1100, data to be written to the memory cell transistors MCT of the semiconductor device 1100, data to be read from the memory cell transistors MCT of the semiconductor device 1100, etc. may be transferred via the NAND interface 1221. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When a control command is received from an external host via the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0147] FIG. 12 is a perspective view schematically illustrating a data storage system including a semiconductor device according to an exemplary embodiment of the present invention.

[0148] 12, a data storage system 2000 according to an exemplary embodiment of the present invention may include a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 may be connected to the controller 2002 by a wiring pattern 2005 formed on the main board 2001.

[0149] The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In an exemplary embodiment, the data storage system 2000 may communicate with the external host via any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In an exemplary embodiment, the data storage system 2000 may operate using power supplied from the external host via the connector 2006. The data storage system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0150] The controller 2002 can write data to the semiconductor package 2003 and read data from the semiconductor package 2003, thereby improving the operating speed of the data storage system 2000.

[0151] The DRAM 2004 may be a buffer memory for reducing the speed difference between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 may also operate as a kind of cache memory and provide space for temporarily storing data in a control operation for the semiconductor package 2003. When the data storage system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0152] The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b spaced apart from each other. Each of the first and second semiconductor packages 2003a and 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the semiconductor chips 2200 may include a semiconductor device according to any one of the embodiments described above with reference to FIGS. 1 to 10c.

[0153] Each of the first and second semiconductor packages 2003a and 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of each of the semiconductor chips 2200, a connecting structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chip 2200 and the connecting structure 2400 on the package substrate 2100.

[0154] The package substrate 2100 may be a printed circuit board including package top pads 2130. Each of the semiconductor chips 2200 may include input / output pads 2210.

[0155] In an exemplary embodiment, the connecting structure 2400 may be a bonding wire electrically connecting the I / O pad 2210 and the package upper pad 2130. Therefore, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pad 2130 of the package substrate 2100. According to an embodiment, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other by a connecting structure including a through silicon via (TSV), instead of the connecting structure 2400 by a bonding wire method.

[0156] In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be included in one package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on an interposer substrate separate from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other by wiring formed on the interposer substrate.

[0157] Fig. 13 is a cross-sectional view schematically illustrating a semiconductor package according to an exemplary embodiment of the present invention. Fig. 13 illustrates an exemplary embodiment of the semiconductor package 2003 of Fig. 12, and conceptually illustrates a region obtained by cutting the semiconductor package 2003 of Fig. 12 along cutting line IV-IV'.

[0158] 12 and 13, a package substrate 2100 in a semiconductor package 2003 may be a printed circuit board. The package substrate 2100 may include a package substrate body 2120, package upper pads 2130 disposed on an upper surface of the package substrate body 2120, lower pads 2125 disposed on a lower surface of the package substrate body 2120 or exposed through the lower surface, and internal wiring 2135 electrically connecting the upper pads 2130 and the lower pads 2125 inside the package substrate body 2120. The upper pads 2130 may be electrically connected to a connecting structure 2400. The lower pads 2125 may be connected to a wiring pattern 2005 of a main substrate 2010 of the data storage system 2000 via a conductive connecting portion 2800.

[0159] Each of the semiconductor chips 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including a peripheral wiring 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a memory channel structure 3220 and an isolation structure (3230 in FIG. 12) penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the memory channel structure 3220, and a gate connecting wiring (93b in FIG. 2a) electrically connected to a word line WL of the gate stack structure 3210. The first structure 3100 may include the first structure 1100F in FIG. 11, and the second structure 3200 may include the second structure 1100S in FIG. 11.

[0160] Each of the semiconductor chips 2200 may include a through wiring 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The through wiring 3245 may penetrate the gate stack structure 3210 and may be further disposed outside the gate stack structure 3210.

[0161] Each of the semiconductor chips 2200 may further include input / output connection wiring electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200, and input / output pads 2210 electrically connected to the input / output connection wiring.

[0162] 13, the enlarged portion indicated by reference numeral 1 is intended to illustrate that the semiconductor chip 2200 of FIG. 13 can be modified to include the cross-sectional structure shown in FIG. 2a. Therefore, each of the semiconductor chips 2200 may include the semiconductor device 1 according to any one of the embodiments described above with reference to FIGS. 1 to 6.

[0163] In another example, each of the semiconductor chips 2200 may include the semiconductor device 100 according to the embodiment described with reference to FIG.

[0164] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential characteristics thereof. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not limiting. [Explanation of symbols]

[0165] 1 semiconductor device 3 first structure 8 Peripheral circuit 17' Pattern structure 19a Inner intermediate insulating layer 19b Outer intermediate insulating layer 21' Second structure 23' First laminated structure 25 First interlayer insulating layer 27g First gate layer 27i First insulating horizontal layer 32 First capping insulating layer 35' Second laminated structure 38 Second interlayer insulating layer 40g Second gate layer 40i Second insulating horizontal layer 44 second capping insulating layer 47 memory vertical structure 58 First upper insulating layer 61a First peripheral contact plug 61b Second peripheral contact plug 61c Third peripheral contact plug 61d Auxiliary support vertical structure 62 Support vertical structure 62p Support protrusion 65 Second upper insulating layer 67 Dielectric layer 67a First dielectric portion 67b second dielectric portion 68 isolation structure 68p Separation protrusion 72 Third upper insulating layer 75 gate contact plug 78 fourth upper insulating layer 81b Bit line contact plug 81g Gate upper plug 81p Periphery top plug 84b Bit line 84g Gate connection wiring 84s First peripheral wiring 84p Second peripheral wiring

Claims

1. a memory cell array region and a staircase region on the pattern structure; a stacked structure disposed in the memory cell array region and extending from the memory cell array region into the staircase region, the stacked structure including interlayer insulating layers and gate layers alternately stacked in a vertical direction, the gate layers including gate pads arranged in a staircase pattern within the staircase region; an isolation structure including a portion that contacts the pattern structure and penetrates the laminate structure; a memory vertical structure including a portion that contacts the pattern structure and penetrates the stack structure in the memory cell array region; a support vertical structure including a portion that contacts the pattern structure and penetrates the laminate structure in the staircase region; a gate contact plug disposed on the gate pad; a first peripheral contact plug spaced apart from the gate layer; the isolation structure extends in the memory cell array region in a first horizontal direction toward the staircase region; an upper surface of the memory vertical structure at a first elevation level; an upper surface of the first peripheral contact plug is located at a second height level higher than the first height level; an upper surface of the isolation structure is located at a third height level higher than the second height level; The semiconductor device, wherein an upper surface of the gate contact plug is located at a fourth height level that is higher than the third height level.

2. a bit line contact plug on the memory vertical structure and in contact with the memory vertical structure; a peripheral upper plug on the first peripheral contact plug and in contact with the first peripheral contact plug; a gate upper plug that is above and in contact with the gate contact plug; a bit line on the bit line contact plug, the bit line being electrically connected to the bit line contact plug; a peripheral wiring on the peripheral upper plug and electrically connected to the peripheral upper plug; 2. The semiconductor device of claim 1, further comprising a gate connecting wire on the gate upper plug and electrically connected to the gate upper plug.

3. the bit line contact plug includes a side that is not vertically aligned with a side of the memory vertical structure; the peripheral upper plug includes a side surface that is not vertically aligned with a side surface of the first peripheral contact plug; a first gate upper plug of the gate upper plugs contacts a first gate contact plug of the gate contact plugs; The semiconductor device of claim 2 , wherein the first gate upper plug includes a side surface that is not vertically aligned with a side surface of the first gate contact plug.

4. the memory vertical structure includes a channel layer; The semiconductor device according to claim 1 , wherein the support vertical structure does not contain material of the channel layer.

5. The semiconductor device of claim 4 , wherein an upper surface of the support vertical structure is located at the second height level.

6. The semiconductor device of claim 4 , wherein a lower end of the support vertical structure is disposed at a different level from a lower end of the isolation structure adjacent to the support vertical structure.

7. The semiconductor device according to claim 6 , wherein the lower end of the support base vertical structure is disposed at a lower level than the lower end of the isolation structure.

8. the pattern structure includes a silicon layer; The semiconductor device according to claim 1 , wherein the first peripheral contact plug has a lower surface in contact with the silicon layer.

9. a semiconductor substrate; a peripheral circuit including a first peripheral circuit pad on the semiconductor substrate; The laminated structure further includes a through region; the through region includes an insulating horizontal layer located at the same level as a gate layer adjacent to the through region among the gate layers, the pattern structure is disposed on the peripheral circuit; the pattern structure includes a gap; The semiconductor device according to claim 1 , wherein the first peripheral contact plug contacts the first peripheral circuit pad and extends upward to penetrate the gap and the insulating horizontal layer in the through region.

10. a semiconductor substrate; a peripheral circuit including a first peripheral circuit pad on the semiconductor substrate; further including a second peripheral contact plug; The laminated structure further includes a through region; the through region includes an insulating horizontal layer located at the same level as the gate layer adjacent to the through region; the pattern structure is disposed on the peripheral circuit; the pattern structure includes a gap; the second peripheral contact plug contacts the first peripheral circuit pad and extends upward to penetrate the gap and the insulating horizontal layer in the through region; The semiconductor device according to claim 1 , wherein an upper surface of the second peripheral contact plug is located at the second height level.

11. further including a third peripheral contact plug; the peripheral circuit further includes a second peripheral circuit pad; the third peripheral contact plug contacts the second peripheral circuit pad outside the pattern structure and extends upward; The semiconductor device of claim 10 , wherein an upper surface of the third peripheral contact plug is located at the second height level.

12. further comprising a dielectric layer; the isolation structure includes an isolation protruding portion that protrudes toward a gate layer adjacent to the isolation structure among the gate layers, the isolation structure contacts a gate layer adjacent to the isolation structure among the gate layers; the dielectric layer includes a first dielectric layer portion and a second dielectric layer portion; the first dielectric layer portions cover upper and lower surfaces of each of the gate layers, are disposed between each of the gate layers and the memory vertical structure, and are disposed between each of the gate layers and the support vertical structure; The semiconductor device according to claim 1 , wherein the second dielectric layer portion extends from the first dielectric layer portion and covers a side of the isolation structure that is not in contact with the gate layer.

13. the isolation structure comprises silicon oxide; 13. The semiconductor device of claim 12, wherein the dielectric layer includes a high-k dielectric having a dielectric constant greater than that of the silicon oxide.

14. the laminated structure includes a first laminated structure and a second laminated structure on the first laminated structure; the first stacked structure includes first interlayer insulating layers and first gate layers alternately stacked in the vertical direction, the second stacked structure includes second interlayer insulating layers and second gate layers alternately stacked in the vertical direction, the first and second interlayer insulating layers constitute the interlayer insulating layer; the first and second gate layers constitute the gate layer; 14. The semiconductor device of claim 1, wherein a side of the memory vertical structure located at a height level between a top first gate layer of the first gate layers and a bottom second gate layer of the second gate layers includes a curved portion.

15. At the same height level as the curved portion of the side of the memory vertical structure, the side of the isolation structure is substantially straight; The semiconductor device according to claim 14 , wherein the side surface of the first peripheral contact plug is substantially straight at the same height level as the curved portion of the side surface of the memory vertical structure.

16. the support vertical structure includes a support protrusion protruding toward one of the gate layers adjacent to the support vertical structure, the isolation structure includes an isolation protrusion protruding toward the gate layer adjacent to the isolation structure among the gate layers, The semiconductor device according to claim 1 , wherein a width of a first separation protrusion of any one of the separation protrusions is greater than a width of a first support base protrusion of any one of the support base protrusions.

17. a semiconductor substrate; a peripheral circuit below the semiconductor substrate; an upper bond pad below the peripheral circuit; a lower interface pad attached to and in contact with the upper interface pad from below the upper interface pad; The semiconductor device of claim 1 , wherein the lower bond pad is disposed on the stack structure.

18. a first structure; and a second structure vertically overlapping the first structure; a memory vertical structure; a support base vertical structure; a peripheral contact plug; an isolation structure; a gate contact plug; the first structure includes a pattern structure including a silicon layer; the second structure includes a gate layer stacked in the memory cell array region and spaced apart in the vertical direction, the gate layer extending from the memory cell array region into a staircase region adjacent to the memory cell array region; the gate layer includes gate pads arranged in a stepped pattern within the stepped region; the memory vertical structure includes a portion that contacts the pattern structure and penetrates the gate layer in the memory cell array region; the support vertical structure includes a portion that contacts the pattern structure and penetrates the gate layer in the staircase region; the peripheral contact plug is spaced apart from the gate layer; the isolation structure includes a portion that contacts the pattern structure and penetrates the second structure; the gate contact plug is disposed on the gate pad; an upper surface of the memory vertical structure at a first elevation level; an upper surface of the peripheral contact plug located at a second elevation level; an upper surface of the isolation structure is located at a third elevation level; an upper surface of the gate contact plug is located at a fourth elevation level; The first to fourth height levels are located at different heights from one another.

19. the second height level is higher than the first height level; the third height level is higher than the second height level; 20. The semiconductor device of claim 18, wherein the fourth height level is higher than the third height level.

20. The main board and a semiconductor device on the main substrate; a controller electrically connected to the semiconductor device and controlling the semiconductor device; The semiconductor device includes: a memory cell array region and a staircase region on the pattern structure; a stacked structure disposed in the memory cell array region and extending from the memory cell array region into the staircase region, the stacked structure including interlayer insulating layers and gate layers alternately stacked in a vertical direction, the gate layers including gate pads arranged in a staircase pattern within the staircase region; an isolation structure including a portion that contacts the pattern structure and penetrates the laminate structure; a memory vertical structure including a portion that contacts the pattern structure and penetrates the stack structure in the memory cell array region; a support vertical structure including a portion that contacts the pattern structure and penetrates the laminate structure in the staircase region; a gate contact plug disposed on the gate pad; a first peripheral contact plug spaced apart from the gate layer; the isolation structure extends in the memory cell array region in a first horizontal direction toward the staircase region; an upper surface of the memory vertical structure at a first elevation level; an upper surface of the first peripheral contact plug is located at a second height level higher than the first height level; an upper surface of the isolation structure is located at a third height level higher than the second height level; an upper surface of the gate contact plug is located at a fourth height level that is higher than the third height level; the memory vertical structure includes a channel layer; The data storage system, wherein the support vertical structure does not include material from the channel layer.

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