Multilayer ceramic capacitor and method of manufacturing the same

Abstract

To suppress an increase in equivalent series resistance in a direction from an internal electrode layer of a multilayer ceramic capacitor to an external electrode.SOLUTION: A multilayer ceramic capacitor according to an embodiment includes: an element body including a first surface, a second surface facing the first surface, a first internal electrode layer in which an end is exposed on the first surface side, and that has anisotropy such that a current path in a direction toward the first surface is shorter than a direction orthogonal to the direction toward the first surface in the same plane, a second internal electrode layer in which an end is exposed on the second surface side, and that has anisotropy such that a current path in a direction toward the second surface is shorter than a direction orthogonal to the direction toward the second surface in the same plane, and a dielectric layer provided between the first internal electrode layer and the second internal electrode layer; a first external electrode formed on the first surface of the element body and connected to the first internal electrode; and a second external electrode formed on the second surface of the element body and connected to the second internal electrode.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor and a method for manufacturing a multilayer ceramic capacitor. [Background technology]

[0002] As electronic devices become smaller and more functional, there is a demand for multilayer ceramic capacitors with a lower profile and increased capacitance. To meet this demand, one method is to reduce the thickness of the internal electrodes of the multilayer ceramic capacitor while increasing the number of layers of the internal electrodes.

[0003] Patent Document 1 discloses a method for forming an internal electrode layer to have a composite structure having a base metal internal electrode main layer and ceramic particles embedded in this internal electrode main layer, in order to prevent the internal electrode layer from being broken due to spheroidization during formation of the internal electrode layer. Patent Document 2 discloses a configuration in which, in order to improve the mechanical strength of a laminated electronic component, internal electrode layers and dielectric layers are alternately stacked, and needle-like crystals penetrate the electrode discontinuities of the internal electrode layers and are arranged so as to bridge the dielectric layers. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-311985 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-258190 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in a structure in which internal electrode layers and dielectric layers are alternately stacked, the internal electrode layers may fracture due to differences in the materials between the internal electrode layers and the dielectric layers, which may result in an increase in equivalent series resistance (hereinafter sometimes referred to as ESR) in the direction from the internal electrode layers to the external electrode. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a multilayer ceramic capacitor capable of suppressing an increase in equivalent series resistance in the direction from the internal electrode layers toward the external electrodes, and a method for manufacturing the multilayer ceramic capacitor. [Means for solving the problem]

[0006] In order to solve the above problem, a multilayer ceramic capacitor according to one aspect of the present invention comprises: an element body having a first surface, a second surface opposite to the first surface; a first internal electrode layer having an end exposed on the first surface side and anisotropy such that the current path in the direction toward the first surface is shorter than in a direction perpendicular to the direction toward the first surface in the same plane; a second internal electrode layer having an end exposed on the second surface side and anisotropy such that the current path in the direction toward the second surface is shorter than in a direction perpendicular to the direction toward the second surface in the same plane; and a dielectric layer provided between the first internal electrode layer and the second internal electrode layer; a first external electrode formed on the first surface of the element body and connected to the first internal electrode; and a second external electrode formed on the second surface of the element body and connected to the second internal electrode.

[0007] Furthermore, a multilayer ceramic capacitor according to one aspect of the present invention comprises an element body having a first surface, a second surface opposite to the first surface, a first internal electrode layer whose end is exposed on the first surface side and whose continuity rate in a direction toward the first surface is greater than the continuity rate in a direction perpendicular to the direction toward the first surface in the same plane, a second internal electrode layer whose end is exposed on the second surface side and whose continuity rate in a direction toward the second surface is greater than the continuity rate in a direction perpendicular to the direction toward the second surface in the same plane, and a dielectric layer provided between the first internal electrode layer and the second internal electrode layer; a first external electrode formed on the first surface of the element body and connected to the first internal electrode; and a second external electrode formed on the second surface of the element body and connected to the second internal electrode.

[0008] Furthermore, in a multilayer ceramic capacitor according to one embodiment of the present invention, the continuity ratio of the first internal electrode layer in the direction toward the first surface and the continuity ratio of the second internal electrode layer in the direction toward the second surface are 80% or more and less than 100%, and the continuity ratio of the first internal electrode layer in the direction perpendicular to the direction toward the first surface in the same plane and the continuity ratio of the second internal electrode layer in the direction perpendicular to the direction toward the second surface in the same plane are 70% or more and 90% or less.

[0009] Furthermore, in a multilayer ceramic capacitor according to one aspect of the present invention, the continuity ratio of the first internal electrode layer in a direction toward the first surface is 1.1 to 1.4 times the continuity ratio of the first internal electrode layer in a direction perpendicular to the direction toward the first surface in the same plane, and the continuity ratio of the second internal electrode layer in a direction perpendicular to the direction toward the second surface in the same plane is 1.1 to 1.4 times the continuity ratio of the second internal electrode layer in a direction perpendicular to the direction toward the second surface in the same plane.

[0010] In addition, in the multilayer ceramic capacitor according to one aspect of the present invention, the continuity ratio is an average value at different cut positions when the capacitor is cut in the same direction at different positions on the same plane.

[0011] Furthermore, in a multilayer ceramic capacitor according to one aspect of the present invention, the first internal electrode layer has a first fracture portion fractured in a direction toward the first surface, and the second internal electrode layer has a second fracture portion fractured in a direction toward the second surface.

[0012] Furthermore, in a multilayer ceramic capacitor according to one aspect of the present invention, the number of gaps in the first internal electrode layer in a region of a predetermined length toward the first surface is smaller than the number of gaps in the first internal electrode layer in a region of the predetermined length in a direction perpendicular to the direction toward the first surface in the same plane, and the number of gaps in the second internal electrode layer in the region of the predetermined length toward the second surface is smaller than the number of gaps in the second internal electrode layer in a region of the predetermined length in a direction perpendicular to the direction toward the second surface in the same plane.

[0013] In addition, in the multilayer ceramic capacitor according to one aspect of the present invention, the first internal electrode layers and the second internal electrode layers do not contain a ceramic component.

[0014] In addition, in the multilayer ceramic capacitor according to one aspect of the present invention, the first internal electrode layers and the second internal electrode layers are made of a single metal or an alloy.

[0015] In addition, in the multilayer ceramic capacitor according to one aspect of the present invention, the first internal electrode layer and the second internal electrode layer are sputtered films.

[0016] In addition, in the multilayer ceramic capacitor according to one aspect of the present invention, the film thickness of each of the first internal electrode layers and the second internal electrode layers is within a range of 0.05 μm to 0.5 μm.

[0017] In addition, in the multilayer ceramic capacitor according to one aspect of the present invention, the dielectric material is mainly composed of an oxide ceramic.

[0018] In addition, in the multilayer ceramic capacitor according to one aspect of the present invention, the dielectric is a sintered body of a coating film.

[0019] Furthermore, a method for manufacturing a multilayer ceramic capacitor according to one aspect of the present invention includes the steps of: applying a dielectric slurry film onto a carrier film; forming an electrode pattern on the dielectric slurry film; stacking the dielectric slurry films on which the electrode patterns have been formed to form a laminated block; compressing the laminated block in the stacking direction so that the expansion rate in the planar direction of the laminated block is anisotropic; singulating the compressed laminated block to form an element body in which ends of the electrode patterns are exposed from the dielectric slurry film; applying a conductive paste for a base layer to the element body, the conductive paste for a base layer contacting the ends of the electrode patterns; firing the element body on which the conductive paste for the base layer has been applied to form a fired body in which an underlayer is integrated with the element body; and forming a plating layer on the underlayer.

[0020] In addition, in a method for manufacturing a multilayer ceramic capacitor according to one aspect of the present invention, the electrode patterns are formed by sputtering.

[0021] Furthermore, in accordance with a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present invention, the laminated block includes a first region in which the dielectric slurry films and the electrode patterns are alternately laminated, a second region in which the electrode patterns are laminated with the dielectric slurry films interposed therebetween, and a third region in which the electrode patterns are absent in the lamination direction of the dielectric slurry films.

[0022] Furthermore, in accordance with the method for manufacturing a multilayer ceramic capacitor according to one aspect of the present invention, when the laminated block is compressed in the lamination direction by a hydrostatic press, the pressure applied to the second region is greater than the pressure applied to the third region.

[0023] Furthermore, according to a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present invention, the elongation rate of the dielectric slurry film from the first region toward the third region is greater than the elongation rate of the dielectric slurry film from the first region toward the second region, and the electrode pattern breaks due to the elongation of the dielectric slurry film.

[0024] Furthermore, in the method for manufacturing a multilayer ceramic capacitor according to one aspect of the present invention, the ends of the internal electrode layers are exposed from the dielectric layer in the second region and connected to the base layer.

[0025] Furthermore, according to a method for manufacturing a multilayer ceramic capacitor according to one aspect of the present invention, the continuity ratio of the internal electrode layer from the first region toward the second region is greater than the continuity ratio of the internal electrode layer from the first region toward the third region. [Effects of the Invention]

[0026] According to the present invention, it is possible to suppress an increase in equivalent series resistance in the direction from the internal electrode layers to the external electrodes of the multilayer ceramic capacitor. [Brief explanation of the drawings]

[0027] [Figure 1A] 1 is a perspective view showing an example of the configuration of a multilayer ceramic capacitor in accordance with a first embodiment. [Figure 1B] 1B is a cross-sectional view showing an example of the configuration of an internal electrode in region ML of FIG. 1A. [Figure 1C] 1B is a cross-sectional view showing an example of the configuration of an internal electrode in region MW of FIG. 1A. [Figure 2A] 10 is a plan view showing an example of a current path when the continuity ratio of the internal electrode in the length direction is greater than the continuity ratio in the width direction. FIG. [Figure 2B] 10 is a plan view showing an example of a current path when the continuity ratio of the internal electrode in the length direction is equal to the continuity ratio in the width direction. FIG. [Figure 2C] 10 is a plan view showing an example of a current path when the continuity ratio of the internal electrode in the length direction is smaller than the continuity ratio in the width direction. FIG. [Figure 3A] 10A and 10B are plan views showing examples in which the cutting positions are changed when calculating the continuity rate of the internal electrodes. [Figure 3B] FIG. 10 is a diagram showing an example of the relationship between the cutting position of the internal electrode and the continuity rate. [Figure 4] 3 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5A] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5B] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5C] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5D] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5E] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5F] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5G] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5H] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 6A] 5D is a cross-sectional view showing an example of the configuration of one element region of the laminate block of FIG. 5C in the length direction and width direction before isostatic pressing. FIG. [Figure 6B] FIG. 1 is a cross-sectional view showing the pressure distribution applied to one element region of a laminated block by isostatic pressing. [Figure 7A] FIG. 2 is a plan view showing the positional relationship between a charge accumulation portion, an electrode lead portion, and a side margin portion in the element body region. [Figure 7B] 7B is a plan view showing the state of the internal electrode pattern before isostatic pressing of the charge accumulation section and the electrode lead section of FIG. 7A. FIG. [Figure 7C] 7B is a plan view showing the state of the internal electrode pattern after the charge accumulation section and the electrode lead section of FIG. 7A have been isostatically pressed. FIG. [Figure 8] FIG. 10 is a perspective view showing a method for compressing a laminated block according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the present invention, and not all combinations of features described in the embodiments are necessarily essential to the configuration of the present invention. The configuration of the embodiments may be modified or changed as appropriate depending on the specifications of the device to which the present invention is applied and various conditions (such as usage conditions and usage environment). The technical scope of the present invention is determined by the claims and is not limited by the individual embodiments described below. Furthermore, the drawings used in the following description may differ in scale and shape from the actual structure to make each configuration easier to understand.

[0029] (First embodiment) FIG. 1A is a perspective view showing an example of the configuration of the multilayer ceramic capacitor according to the first embodiment, FIG. 1B is a cross-sectional view showing an example of the configuration of the internal electrodes in region ML of FIG. 1A, and FIG. 1C is a cross-sectional view showing an example of the configuration of the internal electrodes in region MW of FIG. 1A.

[0030] 1A to 1C, multilayer ceramic capacitor 1 includes an element body 2 and external electrodes 6A, 6B. Element body 2 includes a laminate 2A, a lower cover layer 5A, and an upper cover layer 5B. Laminate 2A includes internal electrode layers 3A, 3B, and a dielectric layer 4.

[0031] A lower cover layer 5A is provided on the lower layer of the laminate 2A, and an upper cover layer 5B is provided on the upper layer of the laminate 2A. The internal electrode layers 3A, 3B are alternately stacked with dielectric layers 4 interposed therebetween. Note that while FIG. 1A shows an example in which a total of 11 internal electrode layers 3A, 3B are stacked, the number of stacked internal electrode layers 3A, 3B is not particularly limited. In this case, the shape of the element body 2 and the laminate 2A can be a substantially rectangular parallelepiped shape. The element body 2 may be chamfered along its ridges. Note that in the following description, the direction in which the side surfaces of the element body 2 face each other may be referred to as the length direction DL, the direction in which the front and rear surfaces of the element body 2 face each other may be referred to as the width direction DW, and the direction in which the top and bottom surfaces of the element body 2 face each other may be referred to as the stacking direction (height direction) DS.

[0032] The external electrodes 6A, 6B are formed on the element body 2 so as to face each other while being separated from each other in the longitudinal direction DL. In this case, each of the external electrodes 6A, 6B is formed continuously from the mounting surface side of the element body 2 to the side surfaces, front surface, and rear surface. Furthermore, each of the external electrodes 6A, 6B is formed continuously from the mounting surface side of the element body 2 through the side surfaces to the upper surface. The lower surfaces of each of the external electrodes 6A, 6B are located on the mounting surface side of the element body 2. In this case, the multilayer ceramic capacitor 1 can be mounted on a mounting board via solder layers attached to the lower surfaces of each of the external electrodes 6A, 6B.

[0033] In the length direction DL, the internal electrode layers 3A and 3B are arranged at alternately different positions within the laminate 2A. In this case, the internal electrode layer 3A can be arranged on one side surface of the element body 2 relative to the internal electrode layer 3B, and the internal electrode layer 3B can be arranged on the other side surface of the element body 2 relative to the internal electrode layer 3A. An end of the internal electrode layer 3A is exposed from the dielectric layer 4 at one side surface of the element body 2 in the length direction DL (referred to as the first surface of the element body 2) and is connected to the external electrode 6A. An end of the internal electrode layer 3B is exposed from the dielectric layer 4 at the other side surface of the element body 2 in the length direction DL (referred to as the second surface of the element body 2) and is connected to the external electrode 6B. On the other hand, in the width direction DW of the element body 2, the ends of the internal electrode layers 3A, 3B are covered with the dielectric layer 4. In the width direction DW, the positions of the ends of the internal electrode layers 3A, 3B may be aligned.

[0034] Each layer of the internal electrode layer 3A has anisotropy such that the current path is shorter in the direction toward the first surface of the element body 2 (the length direction DL of the element body 2) than in the direction perpendicular to the direction toward the first surface in the same plane as the element body 2. Also, each layer of the internal electrode layer 3B has anisotropy such that the current path is shorter in the direction toward the second surface of the element body 2 (the length direction DL of the element body 2) than in the direction perpendicular to the direction toward the second surface in the same plane as the element body 2. The anisotropy of each internal electrode layer 3A, 3B may be defined by the number of gaps in each layer of each internal electrode layer 3A, 3B, by the continuity rate of each layer of each internal electrode layer 3A, 3B, by the fracture direction of each layer of each internal electrode layer 3A, 3B, or by the resistivity of each layer of each internal electrode layer 3A, 3B.

[0035] 1B and 1C, in a cut surface (e.g., region ML) along the length direction DL of the element body 2 and a cut surface (e.g., region MW) along the width direction DW of the element body 2, the internal electrode layers 3A, 3B have gaps 8A, 8B. In this case, the number of gaps 8A of the internal electrode layers 3A in a region RLA of a predetermined length LT toward the first surface of the element body 2 is smaller than the number of gaps 8A of the internal electrode layers 3A in a region RWA of a predetermined length LT in a direction (width direction DW) perpendicular to the direction toward the first surface (length direction DL). In addition, the number of gaps 8B of the internal electrode layers 3B in a region RLB of a predetermined length LT toward the second surface of the element body 2 is smaller than the number of gaps 8B of the internal electrode layers 3B in a region RWB of a predetermined length LT in a direction (width direction DW) perpendicular to the direction toward the second surface of the element body 2 (length direction DL).

[0036] In this case, the continuity ratio of each of the internal electrode layers 3A, 3B in the length direction DL of the element body 2 is greater than the continuity ratio of each of the internal electrode layers 3A, 3B in the width direction DW of the element body 2. The continuity ratio of each of the internal electrode layers 3A, 3B can be, for example, the ratio of the total length of the metal portions of the internal electrode layers 3A, 3B to the predetermined length LT within a region of the predetermined length LT.

[0037] The continuity ratio of each of the internal electrode layers 3A, 3B in the length direction DL of the element body 2 is preferably 80% or more and less than 100%. The continuity ratio of each of the internal electrode layers 3A, 3B in the width direction DW of the element body 2 is preferably 70% or more and 90% or less. In this case, the continuity ratio of each of the internal electrode layers 3A, 3B in the length direction DL of the element body 2 can be 1.1 times or more and 1.4 times or less the continuity ratio of each of the internal electrode layers 3A, 3B in the width direction DW of the element body 2.

[0038] The resistivity of each of the internal electrode layers 3A, 3B in the length direction DL of the element body 2 may be smaller than the resistivity of each of the internal electrode layers 3A, 3B in the width direction DW of the element body 2. Alternatively, the component in the length direction DL of the fracture direction of each of the internal electrode layers 3A, 3B may be larger than the component in the width direction DW of the fracture direction of each of the internal electrode layers 3A, 3B.

[0039] The thickness of the internal electrode layers 3A, 3B in the stacking direction DS can be within a range of 0.05 μm to 0.5 μm. The internal electrode layers 3A, 3B preferably do not contain ceramic components. The material of the internal electrode layers 3A, 3B can be selected from metals such as Cu (copper), Ni (nickel), Ti (titanium), Ag (silver), Au (gold), Pt (platinum), Pd (palladium), Ta (tantalum), and W (tungsten), or may be an alloy containing these metals. In this case, the internal electrode layers 3A, 3B are preferably composed of a single metal or an alloy. The internal electrode layers 3A, 3B can be composed of, for example, a sputtered film. The internal electrode layers 3A, 3B may also be composed of a vapor-deposited film.

[0040] The thickness of the dielectric layer 4 in the stacking direction DS can be within a range of 0.5 μm to 1.5 μm. The material of the dielectric layer 4 can be, for example, mainly composed of an oxide ceramic material having a perovskite structure. The main component needs to be contained at a ratio of 50 at% or more. The ceramic material of the dielectric layer 4 can be selected from, for example, barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, calcium titanate zirconate, and titanium oxide. The dielectric layer 4 can be, for example, composed of a sintered body of a coating film containing an oxide ceramic material.

[0041] The material of the lower cover layer 5A and the upper cover layer 5B can be mainly composed of a ceramic material, for example. In this case, the main component of the ceramic material of the lower cover layer 5A and the upper cover layer 5B may be the same as the main component of the ceramic material of the dielectric layer 4.

[0042] Each of the external electrodes 6A, 6B includes an underlayer 7 formed on the element body 2 and a plating layer 9 formed on the underlayer 7. The underlayer 7 is formed continuously from the lower surface of the element body 2 across the side surfaces to the upper surface. The underlayer 7 may also be formed continuously from the lower surface of the element body 2 across the front and rear surfaces. In this case, the underlayer 7 is covered with the plating layer 9 from the lower surface to the side surfaces, front surface, and rear surface. The thickness of the mounting surface of each of the external electrodes 6A, 6B is, for example, 10 μm to 40 μm.

[0043] The metal used as the conductive material of the underlayer 7 may be primarily composed of a metal or alloy containing at least one selected from Cu, Fe (iron), Zn (zinc), Al (aluminum), Ni, Pt, Pd, Ag, Au, and Sn (tin). The underlayer 7 may also contain a common material containing a metal. The common material, when present in the underlayer 7 in the form of islands, can reduce the difference in thermal expansion coefficient between the element body 2 and the underlayer 7 and relieve stress on the underlayer 7. The common material may be, for example, an oxide ceramic component that is the primary component of the dielectric layer 4. The underlayer 7 may also contain a glass component. The glass component, when present in the underlayer 7, can densify the underlayer 7. The glass component may be, for example, an oxide of Ba (barium), Sr (strontium), Ca (calcium), Zn, Al, Si (silicon), or B (boron).

[0044] The underlayer 7 may contain a metal component contained in the element body 2. This metal component is, for example, Mg (which may contain trace amounts of Ni, Cr, Sr, Al, Na, and Fe). In this case, the underlayer 7 may contain, for example, a compound containing Mg, Ni, and O as a compound of the metal used as the conductive material of the underlayer 7, the metal contained in the element body 2, and oxygen.

[0045] The plating layer 9 is primarily composed of a metal such as Cu, Ni, Al, Zn, or Sn, or an alloy of two or more of these metals. The plating layer 9 may be composed of a single metal or multiple metals. The plating layer 9 may have a three-layer structure, for example, consisting of a Cu plating layer 9A formed on the base layer 7, a Ni plating layer 9B formed on the Cu plating layer 9A, and a Sn plating layer 9C formed on the Ni plating layer 9B. The Cu plating layer 9A improves adhesion of the plating layer 9 to the base layer 7. The Ni plating layer 9B improves the heat resistance of the external electrodes 6A and 6B during soldering. The Sn plating layer 9C improves the solder wettability of the plating layer 9. The plating layer 9 is formed on the base layer 7 and is electrically connected to the internal electrode layers 3A and 3B. The plating layer 9 is also electrically connected to the terminals of the mounting board via solder.

[0046] The external dimensions of the multilayer ceramic capacitor 1 may be, for example, length > width > height, or length > width = height. The height of the multilayer ceramic capacitor 1 is equal to the thickness of the multilayer ceramic capacitor 1 from the lower surface to the upper surface of the external electrodes 6A, 6B.

[0047] Here, by making the continuity ratio of each layer of the internal electrode layers 3A, 3B in the length direction DL of the element body 2 greater than the continuity ratio of each layer of the internal electrode layers 3A, 3B in the width direction DW of the element body 2, even if the internal electrode layers 3A, 3B are fractured due to differences in the materials between the internal electrode layers 3A, 3B and the dielectric layer 4, it is possible to suppress the increase in ESR in the direction from the internal electrode layer 3A to the external electrode 6A and in the direction from the internal electrode layer 3B to the external electrode 6B.

[0048] Furthermore, by forming the internal electrode layers 3A, 3B by sputtering, it is possible to reduce the thickness of the internal electrode layers 3A, 3B, which allows the number of layers of the internal electrode layers 3A, 3B to be increased, thereby increasing the capacitance of the multilayer ceramic capacitor 1 and reducing the height of the multilayer ceramic capacitor 1.

[0049] FIG. 2A is a plan view showing an example of a current path when the continuity ratio KLA of the internal electrode in the length direction DL is greater than the continuity ratio KWA of the internal electrode in the width direction DW. FIG. 2B is a plan view showing an example of a current path when the continuity ratio KLB of the internal electrode in the length direction DL is equal to the continuity ratio KLB of the internal electrode in the width direction DW. FIG. 2C is a plan view showing an example of a current path when the continuity ratio KLC of the internal electrode in the length direction DL is smaller than the continuity ratio KLC of the internal electrode in the width direction DW.

[0050] 2A shows the continuity ratio KLA when the internal electrode layer 11A is cut at the cutting position LA, and the continuity ratio KWA when the internal electrode layer 11A is cut at the cutting position WA. 2B shows the continuity ratio KLB when the internal electrode layer 11B is cut at the cutting position LB, and the continuity ratio KWB when the internal electrode layer 11B is cut at the cutting position WB. 2C shows the continuity ratio KLC when the internal electrode layer 11C is cut at the cutting position LC, and the continuity ratio KWC when the internal electrode layer 11C is cut at the cutting position WC.

[0051] In FIG. 2A, a gap KA is provided in the internal electrode layer 11A. Here, the continuity ratio KLA of the internal electrode layer 11A in the length direction DL of the multilayer ceramic capacitor is assumed to be greater than the continuity ratio KWA of the internal electrode layer 11A in the width direction DW of the multilayer ceramic capacitor. In this case, the path length in the width direction DW of the current path PA of the internal electrode layer 11A is shorter than the path length in the length direction DL. Furthermore, the volume of the region VA between the gaps KA is greater than the volume of the region VB between the gaps KB in FIG. 2B, and the resistance of the region VA between the gaps KA is smaller than the resistance of the region VB between the gaps KB.

[0052] 2B, a gap KB is provided in the internal electrode layer 11B. Here, it is assumed that the continuity ratio KLB of the internal electrode layer 11B in the length direction DL of the multilayer ceramic capacitor is equal to the continuity ratio KWB of the internal electrode layer 11B in the width direction DW of the multilayer ceramic capacitor. In this case, the path length in the length direction DL and the path length in the width direction DW of the current path PB of the internal electrode layer 11B are equal.

[0053] In FIG. 2C, assume that a gap KC is provided in the internal electrode layer 11C. Here, assume that the continuity rate KLC of the internal electrode layer 11C in the length direction DL of the multilayer ceramic capacitor is smaller than the continuity rate KWC of the internal electrode layer 11C in the width direction DW of the multilayer ceramic capacitor. In this case, in the current path PC of the internal electrode layer 11C, the path length in the width direction DW is longer than the path length in the length direction DL. Also, the volume of the region VC between the gaps KC is smaller than the volume of the region VB between the gaps KB in FIG. 2B, and the resistance of the region VC between the gaps KC is larger than the resistance of the region VB between the gaps KB.

[0054] Here, if the ESRs of the internal electrode layers 11A, 11B, and 11C in the length direction DL of the multilayer ceramic capacitor are RA, RB, and RC, respectively, then RA < RB < RC. Therefore, by making the continuity rate KLA of the internal electrode layer 11A in the length direction DL of the multilayer ceramic capacitor larger than the continuity rate KWA of the internal electrode layer 12 in the width direction DW of the multilayer ceramic capacitor, even when the internal electrode layer 11A is broken, an increase in the ESR of the internal electrode layer 11A in the length direction DL of the multilayer ceramic capacitor can be suppressed.

[0055] FIG. 3A is a plan view showing an example in which the cutting positions are different when calculating the continuity rate of the internal electrode, and FIG. 3B is a diagram showing an example of the relationship between the cutting position of the internal electrode and the continuity rate. In FIG. 3A, in order to obtain the continuity rates in the length direction DL and the width direction DW of the internal electrode layer 12, assume that the internal electrode layer 12 is cut along the length direction DL and the width direction DW. At this time, even if the cutting direction of the internal electrode layer 12 is the same, the continuity rate changes if the cutting position is different.

[0056] For example, if the internal electrode layer 12 is cut along the length direction DL at cutting positions L1 to L5 to determine the continuity ratio of the internal electrode layer 12 in the length direction DL, the continuity ratio of the internal electrode layer 12 in the length direction DL will change as shown in Figure 3B(a). Also, if the internal electrode layer 12 is cut along the width direction DW at cutting positions W1 to W5 to determine the continuity ratio of the internal electrode layer 12 in the width direction DW, the continuity ratio of the internal electrode layer 12 in the width direction DW will change as shown in Figure 3B(b).

[0057] At this time, depending on the cutting position of the internal electrode layers 12, the continuity ratio of the internal electrode layers 12 in the length direction DL of the multilayer ceramic capacitor may be smaller than the continuity ratio of the internal electrode layers 12 in the width direction DW of the multilayer ceramic capacitor. In order to suppress variations in the continuity ratio when cut in the same direction, the continuity ratio may be an average value at each cutting position when cut in the same direction at different positions on the same plane. For example, the continuity ratio of the internal electrode layers 12 in the length direction DL may be an average value AL of the continuity ratios at each cutting position L1 to L5, and the continuity ratio of the internal electrode layers 12 in the width direction DW may be an average value AW of the continuity ratios at each cutting position W1 to W5.

[0058] Fig. 4 is a flowchart showing the method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment, and Fig. 5A to Fig. 5H are cross-sectional views showing the method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. Note that Fig. 5C to Fig. 5H show an example in which only two layers of internal electrode layers 3A and 3B are alternately stacked with a dielectric layer 4 interposed therebetween.

[0059] In S1 of FIG. 4, an organic binder and an organic solvent serving as a dispersant and a molding aid are added to a dielectric material powder, which is then pulverized and mixed to produce a mud-like slurry. The dielectric material powder may include, for example, ceramic powder. The dielectric material powder may also include additives. The additives may be, for example, oxides or glass of Mg, Mn, V, Cr, Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Co, Ni, Li, B, Na, K, or Si. The organic binder may be, for example, polyvinyl butyral resin or polyvinyl acetal resin. The organic solvent may be, for example, ethanol or toluene.

[0060] Next, as shown in S2 of Fig. 4 and Fig. 5A, a slurry containing ceramic powder is applied to a carrier film 21 in the form of a sheet and dried to produce a green sheet 24. The carrier film 21 is, for example, a PET (polyethylene terephthalate) film. The slurry can be applied using a doctor blade method, a die coater method, a gravure coater method, or the like.

[0061] Next, as shown in S3 of FIG. 4 and FIG. 5B, an internal electrode pattern 23 is formed on a green sheet 24 of a layer that will form the internal electrode layers 3A and 3B of FIG. 1 among the multiple green sheets. The internal electrode pattern 23 can be formed by sputtering. At this time, multiple internal electrode patterns 23 separated in the longitudinal direction of the green sheet 24 can be formed on one green sheet 24. To form the internal electrode pattern 23 on the green sheet 24 by sputtering, an electrode material can be attached to the green sheet 24 through a metal mask having openings corresponding to the internal electrode patterns 23. The internal electrode pattern 23 can be composed of a single metal or an alloy. In this case, the internal electrode pattern 23 does not contain a ceramic component. The internal electrode pattern 23 can also be formed by vacuum deposition, ion plating, or other methods other than sputtering.

[0062] Next, as shown in S4 of FIG. 4 and FIG. 5C , a laminated block is produced by stacking a plurality of green sheets 24 on which the internal electrode pattern 23 is formed and green sheets on which no internal electrode pattern is formed in a predetermined order. The green sheets 24 are stacked such that the internal electrode patterns 23A and 23B of adjacent green sheets 24 in the longitudinal direction of the green sheets 24 are alternately shifted in the longitudinal direction of the green sheets 24. In this case, the green sheets 24 are stacked such that there are portions in the longitudinal direction of the green sheets 24 where only the internal electrode pattern 23A is stacked in the stacking direction with the green sheets 24 interposed therebetween, portions where the internal electrode patterns 23A and 23B are alternately stacked in the stacking direction with the green sheets 24 interposed therebetween, and portions where only the internal electrode pattern 23B is stacked in the stacking direction with the green sheets 24 interposed therebetween. Meanwhile, the green sheets 24 are stacked such that the ends of the internal electrode patterns 23A and 23B of adjacent green sheets 24 in the stacking direction are aligned in the lateral direction of the green sheets 24. At this time, in the short side direction of the green sheet 24, there are portions where the internal electrode patterns 23A, 23B are alternately stacked in the stacking direction with the green sheet 24 interposed therebetween, and portions where only the green sheet 24 is stacked.

[0063] Fig. 6A is a cross-sectional view showing an example of the longitudinal and widthwise configuration of one element region RE of the laminate block of Fig. 5C before isostatic pressing, Fig. 7A is a plan view showing the positional relationship of the charge storage section, electrode lead section, and side margin section of the element region RE, and Fig. 7B is a plan view showing the state of the internal electrode pattern of the charge storage section and electrode lead section of Fig. 7A before isostatic pressing. Note that Fig. 6A(a) is a cross-sectional view of one element region RE of the laminate block of Fig. 5C cut along the longitudinal direction DL, and Fig. 6A(b) is a cross-sectional view of one element region RE of the laminate block of Fig. 5C cut along the width direction DW.

[0064] 6A(a), 6A(b), 7A, and 7B, one element region RE of the laminate block of FIG. 5C includes a charge storage portion R1, electrode lead portions R2A and R2B, and side margin portions R3A and R3B. The charge storage portion R1 is a portion where the internal electrode patterns 23A and 23B are alternately stacked in the lamination direction via the green sheets 24. In the multilayer ceramic capacitor 1, charge is stored in the charge storage portion R1. The electrode lead portion R2A is a portion where the internal electrode pattern 23A is led out from the green sheet 24 to one side of the element region RE in the length direction DL. The electrode lead portion R2B is a portion where the internal electrode pattern 23B is led out from the green sheet 24 to the other side of the element region RE in the length direction DL. The side margin portions R3A and R3B are portions where only the green sheets 24 are stacked.

[0065] In this case, if the total number of stacked layers of the internal electrode patterns 23A, 23B is N (N=4 in the example of FIG. 6A) and the electrode thickness of each of the internal electrode patterns 23A, 23B is T, the total electrode thickness S1 of the internal electrode patterns 23A, 23B of the charge accumulation portion R1 is S1=N×T (S1=4×T in the example of FIG. 6A), the total electrode thickness S2 of the internal electrode patterns 23A, 23B of each of the electrode lead-out portions R2A, R2B is S2=N×T / 2 (S2=2×T in the example of FIG. 6A), and the total electrode thickness S3 of the internal electrode patterns 23A, 23B of each of the side margin portions R3A, R3B is S3=0.

[0066] Next, as shown in S5 and 5D of Fig. 4, the laminate block obtained in the molding step S4 of Fig. 4 is pressed to pressure-bond the green sheet 24. For example, the laminate block can be sandwiched between resin films and isostatically pressed. At this time, the laminate block can be compressed in the stacking direction so that the elongation rate in the planar direction of the laminate block is anisotropic.

[0067] Fig. 6B is a cross-sectional view showing the pressure distribution applied to one element region of the laminated block by isostatic pressing, and Fig. 7C is a plan view showing the state of the internal electrode pattern after isostatic pressing of the charge storage section and the electrode lead section of Fig. 7A. Fig. 6B(a) shows the pressure distribution in the cross section of Fig. 6A(a), and Fig. 6B(b) shows the pressure distribution in the cross section of Fig. 6A(b).

[0068] 6B(a) and 6B(b), in one element region RE, there is a difference in the total electrode thickness of the internal electrode patterns 23A and 23B, so a pressure distribution occurs when the laminated block is isostatically pressed. In this case, if the pressure on the charge storage portion R1 is P1, the pressure on each electrode lead portion R2A, R2B is P2, and the pressure on each side margin portion R3A, R3B is P3, then S1>S2>S3, and therefore P1>P2>P3.

[0069] 6B(b) and 7C, the difference in the total electrode thickness between the charge accumulation portion R1 and each of the side margin portions R3A and R3B is large, resulting in a large pressure difference during isostatic pressing. As a result, as the charge accumulation portion R1 compresses the green sheet 24 in the thickness direction, an extension force SW acts in the length direction DL of the green sheet 24.

[0070] If the green sheet 24 is formed by a coating film, the green sheet 24 contains a binder as well as dielectric material powder. Therefore, the green sheet 24 has fluidity and can stretch in response to the stretching force SW acting on the green sheet 24. On the other hand, if the internal electrode patterns 23A and 23B are formed by sputtering, the internal electrode patterns 23A and 23B contain only metal. Therefore, the internal electrode patterns 23A and 23B have almost no fluidity, and when the stretching force SW acts on the internal electrode patterns 23A and 23B, the internal electrode patterns 23A and 23B will fracture. Since the internal electrode patterns 23A and 23B are subjected to a larger stretching force SW in the width direction DW than in the length direction DL, fractured portions PA and PB are formed in each internal electrode pattern 23A and 23B, where the component of the length direction DL is larger than the component of the width direction DW.

[0071] Next, as shown in S6 of Fig. 4 and Fig. 5E, the pressed laminated block is cut and separated into rectangular parallelepiped elements. The laminated block is cut at a portion where only the internal electrode patterns 23A are stacked in the stacking direction and at a portion where only the internal electrode patterns 23B are stacked in the stacking direction. For example, a method such as blade dicing can be used to cut the laminated block.

[0072] 5F, internal electrode layers 3A and 3B are formed in each individual element body 2, stacked alternately with the dielectric layer 4 interposed therebetween. The internal electrode layer 3A is drawn out from the surface of the dielectric layer 4 on one side of the element body 2, and the internal electrode layer 3B is drawn out from the surface of the dielectric layer 4 on the other side of the element body 2.

[0073] Next, as shown in S7 of Fig. 4, the binder contained in the element body 2 singulated in S6 of Fig. 4 is removed. To remove the binder, the element body 2 is heated in an N2 atmosphere at about 350°C, for example.

[0074] Next, as shown in S8 of FIG. 4, a conductive paste for the base layer is applied to both side surfaces of the element body 2 from which the binder was removed in S7 of FIG. 4 and to the four peripheral surfaces of each side surface (top surface, bottom surface, front surface, and rear surface), and then dried. The conductive paste for the base layer can be applied, for example, by a dipping method. The conductive paste for the base layer contains a powder or filler of a metal used as the conductive material for the base layer 7. For example, if the metal used as the conductive material for the base layer 7 is Ni, the conductive paste for the base layer contains Ni powder or filler. The conductive paste for the base layer also contains, as a co-material, a ceramic component that is the main component of the dielectric layer 4. For example, the conductive paste for the base layer contains particles of an oxide ceramic (e.g., having a D50 particle size of 0.8 μm to 4 μm) whose main component is barium titanate as a co-material. The conductive paste for the base layer also contains a binder and a solvent.

[0075] Next, as shown in S9 of Fig. 4 and Fig. 5G, the element body 2 to which the conductive paste for the base layer has been applied in S8 of Fig. 4 is fired to integrate the internal electrode layers 3A, 3B and the dielectric layer 4, and to form a fired body in which the base layer 7 is integrated with the element body 2. The element body 2 and the conductive paste for the base layer are fired, for example, in a firing furnace at 1000 to 1400°C for 10 minutes to 2 hours. When a base metal such as Ni or Cu is used for the internal electrode layers 3A, 3B, firing can be performed in a reducing atmosphere in the firing furnace to prevent oxidation of the internal electrode layers 3A, 3B.

[0076] Next, as shown in S10 of Fig. 4 and Fig. 5H, plating layer 9 is formed on underlayer 7. For example, Cu plating, Ni plating, and Sn plating can be performed in that order to form plating layer 9. At this time, the element body 2 on which underlayer 7 has been formed is placed in a barrel together with a plating solution, and electricity is applied while the barrel is rotating, thereby forming plating layer 9.

[0077] Here, by forming fractures PA, PB in each internal electrode pattern 23A, 23B in which the component of the fracture direction in the length direction DL is larger than the component in the width direction DW, it is possible to make the continuity ratio of each layer of each internal electrode layer 3A, 3B in the length direction DL of the element body 2 larger than the continuity ratio of each layer of each internal electrode layer 3A, 3B in the width direction DW of the element body 2. Therefore, even if the internal electrode layers 3A, 3B are fractured due to a difference in material between the internal electrode layers 3A, 3B and the dielectric layer 4, it is possible to suppress an increase in ESR in the direction from the internal electrode layer 3A to the external electrode 6A and in the direction from the internal electrode layer 3B to the external electrode 6B.

[0078] Furthermore, by making the total electrode thickness of the internal electrode patterns 23A, 23B in each electrode lead portion R2A, R2B larger than the total electrode thickness of the internal electrode patterns 23A, 23B in each side margin portion R3A, R3B, a larger elongation force SW in the width direction DW than in the length direction DL can be applied to the internal electrode patterns 23A, 23B when the green sheet 24 is compressed by a hydrostatic press. Therefore, while suppressing an increase in the number of processes, it is possible to form fracture portions PA, PB in each internal electrode pattern 23A, 23B in which the component of the fracture direction in the length direction DL is larger than the component in the width direction DW, and it is possible to make the continuity ratio of each layer of each internal electrode layer 3A, 3B in the length direction DL of the element body 2 larger than the continuity ratio of each layer of each internal electrode layer 3A, 3B in the width direction DW of the element body 2.

[0079] Furthermore, by forming the internal electrode pattern 23 on the green sheet 24 by sputtering, the internal electrode layers 3A, 3B can be thinned. This makes it possible to ensure the mounting strength of the multilayer ceramic capacitor 1 while reducing the height of the multilayer ceramic capacitor 1, and also to increase the number of layers of the internal electrode layers 3A, 3B, thereby increasing the capacitance of the multilayer ceramic capacitor 1.

[0080] (Second embodiment) Fig. 8 is a perspective view showing a method for compressing a laminated block according to the second embodiment. Note that, in the first embodiment described above, an isostatic press is used to compress the laminated block of Fig. 5C, but in the second embodiment, an example is shown in which rolling is used to compress the laminated block of Fig. 5C.

[0081] 8, the rolling mill includes rollers 31A and 31B. The circumferential surfaces of rollers 31A and 31B are arranged facing each other with a predetermined gap between them. The gap between the circumferential surfaces of rollers 31A and 31B is smaller than the thickness of the laminated block of FIG. 5C.

[0082] The rotation directions RA and RB of the rollers 31A and 31B are set so that the laminated block is fed in the conveying direction DH of the laminated block in FIG. 5C. At this time, the conveying direction DH of the laminated block in FIG. 5C can be made to coincide with the length direction DL of the element body 2. When the laminated block in FIG. 5C is conveyed between the rollers 31A and 31B, the laminated block is rolled in the length direction DL of the element body 2 while being compressed in the stacking direction DS of the element body 2, and the green sheet 24 is pressure-bonded. At this time, a larger elongation force acts on the internal electrode patterns 23A and 23B in the width direction DW than in the length direction DL. Therefore, a fracture can be formed in each internal electrode pattern 23A and 23B in which the component of the fracture direction in the length direction DL is larger than the component in the width direction DW.

[0083] (Example) In the multilayer ceramic capacitor 1 of Fig. 1A, the continuity ratio of each internal electrode layer 3A, 3B was confirmed when 100 or more internal electrode layers 3A, 3B were laminated. The film thickness of each internal electrode layer 3A, 3B was 0.3 μm to 0.5 μm, and the film thickness of the dielectric layer 4 was 0.8 μm to 1.5 μm. In this case, the continuity ratio of each internal electrode layer 3A, 3B in the length direction DL was 64.8%, and the continuity ratio of each internal electrode layer 3A, 3B in the width direction DW was 58.2%, resulting in a continuity ratio ratio of 0.898. [Explanation of symbols]

[0084] 1A multilayer ceramic capacitor 2 Base 2A laminate 3A, 3B Internal electrode layer 4 Dielectric Layer 5A, 5B cover layer 6A, 6B external electrode 7 Base layer 9 Plating layer

Claims

1. applying a dielectric slurry film onto a carrier film; forming an electrode pattern containing only metal on the dielectric slurry film; a step of laminating the dielectric slurry films on which the electrode patterns are formed to form a laminated block; sandwiching the laminated block between resin films; compressing the laminated block sandwiched between the resin films in a lamination direction so that the laminated block has an anisotropic elongation rate in a planar direction; a step of dividing the compressed laminated block into individual pieces to form an element body in which ends of the electrode patterns are exposed from the dielectric slurry film; a step of applying a conductive paste for a base layer to the element body so as to contact the end of the electrode pattern; a step of firing the element body to which the conductive paste for the base layer has been applied, to form a fired body in which the internal electrode layers and the dielectric layers are integrated and the base layer is integrated with the element body; forming a plating layer on the underlayer, The laminated block is a first region in which the dielectric slurry film and the electrode pattern are alternately laminated; a second region in which the electrode patterns are alternately stacked with the dielectric slurry film interposed therebetween; a third region in which the electrode pattern is not present in the lamination direction of the dielectric slurry film, 10. A method for manufacturing a multilayer ceramic capacitor, wherein, when the laminated block is compressed in the stacking direction, the pressure applied to the first region is greater than the pressure applied to the second region, and the pressure applied to the second region is greater than the pressure applied to the third region.

2. 2. The method for manufacturing a multilayer ceramic capacitor according to claim 1, wherein the electrode pattern is formed by sputtering.

3. an elongation rate of the dielectric slurry film from the first region toward the third region is greater than an elongation rate of the dielectric slurry film from the first region toward the second region; 2. The method for manufacturing a multilayer ceramic capacitor according to claim 1, wherein the electrode pattern is broken due to the extension of the dielectric slurry film.

4. 4. The method for manufacturing a multilayer ceramic capacitor according to claim 3, wherein an end of the internal electrode layer is exposed from the dielectric layer in the second region and connected to the base layer.

5. 5. The method for manufacturing a multilayer ceramic capacitor according to claim 4, wherein a continuity ratio of the internal electrode layer from the first region toward the second region is greater than a continuity ratio of the internal electrode layer from the first region toward the third region.

6. An element body having a first surface, a second surface opposite to the first surface, a first internal electrode layer having an end exposed on the first surface side and anisotropy such that the current path in the direction toward the first surface is shorter than in a direction perpendicular to the direction toward the first surface in the same plane, a second internal electrode layer having an end exposed on the second surface side and anisotropy such that the current path in the direction toward the second surface is shorter than in a direction perpendicular to the direction toward the second surface in the same plane, and a dielectric layer provided between the first internal electrode layer and the second internal electrode layer; a first external electrode formed on a first surface of the element body and connected to the first internal electrode; a second external electrode formed on a second surface of the element body and connected to the second internal electrode.

7. An element body having a first surface, a second surface opposite to the first surface, a first internal electrode layer having an end exposed on the first surface side and a continuity rate in a direction toward the first surface that is greater than the continuity rate in a direction perpendicular to the direction toward the first surface in the same plane, a second internal electrode layer having an end exposed on the second surface side and a continuity rate in a direction toward the second surface that is greater than the continuity rate in a direction perpendicular to the direction toward the second surface in the same plane, and a dielectric layer provided between the first internal electrode layer and the second internal electrode layer; a first external electrode formed on a first surface of the element body and connected to the first internal electrode; a second external electrode formed on a second surface of the element body and connected to the second internal electrode.

8. a continuity ratio of the first internal electrode layer in a direction toward the first surface and a continuity ratio of the second internal electrode layer in a direction toward the second surface are equal to or greater than 80% and less than 100%, 8. The multilayer ceramic capacitor according to claim 7, wherein a continuity ratio of the first internal electrode layer in a direction perpendicular to the direction toward the first surface in the same plane and a continuity ratio of the second internal electrode layer in a direction perpendicular to the direction toward the second surface in the same plane are 70% or more and 90% or less.

9. a continuity ratio of the first internal electrode layer in a direction toward the first surface is 1.1 times or more and 1.4 times or less of a continuity ratio of the first internal electrode layer in a direction orthogonal to the direction toward the first surface in the same plane, 9. The multilayer ceramic capacitor according to claim 7, wherein a continuity ratio of the second internal electrode layer in a direction toward the second surface is 1.1 times or more and 1.4 times or less of a continuity ratio of the second internal electrode layer in a direction perpendicular to the direction toward the second surface in the same plane.

10. 10. The multilayer ceramic capacitor according to claim 7, wherein the continuity ratio is an average value at different cut positions when the capacitor is cut in the same direction at different positions on the same plane.

11. the first internal electrode layer has a first fracture portion fractured in a direction toward the first surface, The second internal electrode layer has a second fracture portion fractured in a direction toward the second surface.

11. The multilayer ceramic capacitor according to claim 6, wherein the first and second electrodes are electrically connected to each other.

12. the number of gaps of the first internal electrode layer in a region of a predetermined length toward the first surface is smaller than the number of gaps of the first internal electrode layer in a region of the predetermined length in a direction perpendicular to the direction toward the first surface in the same plane, 12. The multilayer ceramic capacitor according to claim 6, wherein the number of gaps in the second internal electrode layer in the region of the predetermined length toward the second surface is smaller than the number of gaps in the second internal electrode layer in the region of the predetermined length in a direction perpendicular to the direction toward the second surface in the same plane.

13. 13. The multilayer ceramic capacitor according to claim 6, wherein the first internal electrode layers and the second internal electrode layers do not contain a ceramic component.

14. 14. The multilayer ceramic capacitor according to claim 6, wherein the first internal electrode layer and the second internal electrode layer are made of a single metal or an alloy.

15. 15. The multilayer ceramic capacitor according to claim 6, wherein the first internal electrode layer and the second internal electrode layer are sputtered films.

16. 16. The multilayer ceramic capacitor according to claim 6, wherein the thickness of each of the first internal electrode layers and the second internal electrode layers is within a range of 0.05 μm to 0.5 μm.

17. 17. The multilayer ceramic capacitor according to claim 6, wherein the dielectric material is mainly composed of an oxide ceramic.

18. 18. The multilayer ceramic capacitor according to claim 6, wherein the dielectric is a sintered body of a coating film.

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