Reference voltage source circuit

Abstract

To provide a reference voltage source circuit capable of stably outputting reference voltage regardless of a base current amplification factor of a PNP bipolar transistor.SOLUTION: A reference voltage source circuit includes a first PNP bipolar transistor and a second PNP bipolar transistor in which a normalized emitter area ratio is set to m:1 (n is a positive number), bases are connected to each other, and collectors are respectively grounded. A base current acquisition part acquires a base current flowing to the bases of the first PNP bipolar transistor and the second PNP bipolar transistor. A bias current supply part sets a first bias current and a second bias current such that the sum of the first bias current and the second bias current becomes the base current.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a reference voltage source circuit. [Background technology]

[0002] For example, a reference voltage source circuit for supplying a reference voltage to a load is known as a type of analog circuit used in an integrated circuit mounted on a power supply IC such as a linear regulator or a DC-DC converter (for example, Non-Patent Documents 1 and 2). [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Kunihiro Asada and Yutaka Nagata, supervising translation, PR Gray, PJ Hulst, SH Levis, and RG Meyer, "Analog Integrated Circuit Design Techniques for System LSI (Basics) (Applications)", Baifukan, 2004 [Non-patent document 2] KAREL E. KUIJK, “A precision reference voltage source,” IEEE Journal of Solid-State Circuits, vol. 8, no. 3, pp.222-226, June. 1973 Summary of the Invention [Problem to be solved by the invention]

[0004] 5 shows an example of a reference voltage source circuit 1' according to the related art. The reference voltage source circuit 1' includes a bandgap reference circuit, and specifically includes a first PNP bipolar transistor Q whose collector and base are grounded and whose normalized emitter area ratio is set to m:1 (m is a positive number). p1p , and a second PNP bipolar transistor Q p2p Reference voltage V REFp Output terminal T for outputting OUTp The first resistor R1p One end of the output terminal T is connected to OUTp and the second PNP bipolar transistor Q p2p Between the emitter of 2p is connected to the first resistor R 1p and the other end of the first PNP bipolar transistor Q p1p Between the emitter and the third resistor R 3p is connected.

[0005] Differential amplifier circuit A 1p The non-inverting input terminal is connected to the first resistor R 1p and the third resistor R 3p and the inverting input terminal is connected to the node between the first and second PNP bipolar transistors Q p2p Connected to the emitter of differential amplifier A 1p output terminal and output terminal T OUTp Between 1p is connected to the differential amplifier A 1p The output terminal of the PMOS transistor M p1p The gate of the PMOS transistor M p1p The source is the power supply V DDp and the drain is connected to the output terminal T OUTp is connected to.

[0006] In the reference voltage source circuit 1' having such a circuit configuration, R 1p =R 2p If so, output terminal T outp The reference voltage V output from REFp , and the first resistor R 1p and second resistor R 2p The bias current I R1p and I R2p is expressed by the following equation: TIFF0007821691000001.tif31170Nao, V EBQp1p is the first PNP bipolar transistor Q p1p is the emitter-base voltage, q is the elementary charge, k is the Boltzmann constant, T is the absolute temperature, and V T is the thermal voltage.

[0007] According to the above Non-Patent Documents 1 and 2, the first term V in the above equation (1) EBQp1p has a negative slope with respect to the temperature T. In the above equation (1), the thermal voltage V T Since the second term, which includes REFp Therefore, a reference voltage source circuit 1' capable of stably outputting the voltage is obtained.

[0008] In the reference voltage source circuit 1' of FIG. 5, the first resistor R 1p and second resistor R 2p The bias current I R1p and I R2p is the first PNP bipolar transistor Q p1p , and a second PNP bipolar transistor Q p2p Therefore, the first PNP bipolar transistor Q p1p , and a second PNP bipolar transistor Q p2p The collector current I CQp is the first PNP bipolar transistor Q p1p , and a second PNP bipolar transistor Q p2p Base current amplification factor β Qp and saturation current I SSP Using this, it is expressed as follows: TIFF0007821691000002.tif31170

[0009] Here, the first PNP bipolar transistor Q p1p , and a second PNP bipolar transistor Q p2p The bipolar transistors used in this field have a base current amplification factor β Qp The mainstream devices have a base current gain β of 100 or more. Qp If is sufficiently large, β on the right side of the above equation (4) Qp / (1+β Qp ) can be considered to be approximately "1". However, in recent years, with changes in manufacturing methods, the base current amplification factor β Qpis small, for example, about 4 to 5. In this way, the base current amplification factor β Qp When becomes small, β on the right side of the above equation (4) Qp / (1+β Qp ) can no longer be considered as "1" (for example, β Qp (When ≠ 4, the value becomes "0.8", resulting in an error of approximately 20%). As a result, the base-emitter voltage V EBQp1p , V EBQp2p The base current amplification factor β Qp The reference voltage V output by the reference voltage source circuit 1' is refp will be affected.

[0010] The base current amplification factor β of the bipolar transistor Qp The base current amplification factor β varies depending on the manufacturing lot and individual differences. Qp The influence of variations in the base current amplification factor β Qp When becomes small, the reference voltage V output from the reference voltage source circuit 1' REFp It is more likely to appear in

[0011] FIG. 6 shows the reference voltage V output from the reference voltage source circuit 1' in FIG. REFp Figure 6 shows the results of a test showing the temperature characteristics of the base current gain β Qp = 2.0, 4.0, 8.0, the reference voltage V REFp As shown in Figure 6, the base current amplification factor β Qp The reference voltage V REFp The temperature characteristics of the

[0012] At least one embodiment of the present disclosure has been made in consideration of the above circumstances, and aims to provide a reference voltage source circuit that can stably output a reference voltage regardless of the base current amplification factor of a PNP bipolar transistor. [Means for solving the problem]

[0013] (1) In order to solve the above problem, a reference voltage source circuit according to at least one aspect of the present disclosure comprises: The normalized emitter area ratio is set to m:1 (m is a positive number), and the bases are connected to each other and the collectors are grounded. p1 ) and a second PNP bipolar transistor (Q p2 )and, a third resistor (R3) having one end connected to the emitter of the first PNP bipolar transistor; a first resistor (R1) connected between the other end of the third resistor and a reference voltage output terminal; a second resistor (R2) connected between the emitter of the second PNP bipolar transistor and the reference voltage output terminal; a differential amplifier (A1) having a non-inverting input terminal connected to a node provided between the first resistor and the third resistor and an inverting input terminal connected to the emitter of the second PNP bipolar transistor; a first capacitor (C1) connected between the output terminal of the differential amplifier and the reference voltage output terminal; A PMOS transistor (M p1 )and, a base current acquisition unit (2) for acquiring base currents flowing through the bases of the first PNP bipolar transistor and the second PNP bipolar transistor; a bias current supply unit (4) for supplying a first bias current and a second bias current corresponding to the base current acquired by the base current acquisition unit to the emitter of the first PNP bipolar transistor and the emitter of the second PNP bipolar transistor, respectively; Equipped with The bias current supply unit sets the first bias current and the second bias current so that the sum of the first bias current and the second bias current becomes the base current.

[0014] According to the above aspect (1), the base current acquisition unit acquires the base currents of the first PNP bipolar transistor and the second PNP bipolar transistor. The bias current supply unit supplies the base currents to the emitters of the first PNP bipolar transistor and the second PNP bipolar transistor as a first bias current and a second bias current. This prevents the reference voltage output from the reference voltage source circuit from being affected by the base current amplification factor of the first PNP bipolar transistor and the second PNP bipolar transistor. As a result, a stable reference voltage can be output from a reference voltage source circuit using PNP bipolar transistors with a relatively small base current amplification factor.

[0015] (2) In another embodiment, in the above embodiment (1), The base current acquisition unit is connected to the positive input terminal (TA ip ), a negative input terminal (TA) connected to the bases of the first PNP bipolar transistor and the second PNP bipolar transistor; im ), a first positive output terminal (TA out1 ), and a second positive output terminal (TA out2 ) is configured as a voltage-current converter.

[0016] According to the above aspect (2), the base current acquisition section is configured as a voltage-current converter, thereby making it possible to suitably realize the above reference voltage source circuit.

[0017] (3) In another aspect, in the above aspect (1) or (2), The bias current supply unit is configured as a current distributor having an input terminal (i1) to which the base current acquired by the base current acquisition unit is input, a first bias current output terminal (o1) for outputting the first bias current to the emitter of the first PNP bipolar transistor, and a second bias current output terminal (o2) for supplying the second bias current to the emitter of the second PNP bipolar transistor.

[0018] According to the above aspect (3), the bias current supply section is configured as a current distributor, thereby making it possible to suitably realize the above reference voltage source circuit.

[0019] (4) In another embodiment, in the above embodiment (3), The bias current supply unit includes a current mirror circuit (4B) for generating a first bias current corresponding to the base current input to the input terminal, and the second bias current.

[0020] According to the above aspect (4), the base current input from the base current acquisition unit to the bias current supply unit is divided into the first bias current and the second bias current by the current mirror circuit.

[0021] (5) In another embodiment, in any one of the above (1) to (4), The bias current supply unit receives the base current acquired by the base current acquisition unit via a current follower circuit (4A).

[0022] According to the above aspect (5), the base current acquired by the base current acquisition unit is input to the bias current supply unit via a current follower circuit, so that the bias current supply unit can detect the base current with high accuracy. [Effects of the Invention]

[0023] According to at least one embodiment of the present disclosure, it is possible to provide a reference voltage source circuit that can stably output a reference voltage regardless of the base current amplification factor of a PNP bipolar transistor. [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 is a circuit diagram illustrating a reference voltage source circuit according to an embodiment. [Figure 2] 2 is a circuit configuration example of a base current acquisition unit in FIG. 1. [Figure 3] 2 is a circuit configuration example of a bias current supply unit in FIG. 1; [Figure 4] 2 shows verification results showing the temperature characteristics of the reference voltage output from the output terminal of the reference voltage source circuit of FIG. 1. [Figure 5] 1 is an example of a reference voltage source circuit according to a reference technique. [Figure 6] 6 is a diagram showing verification results showing temperature characteristics of the reference voltage output from the reference voltage source circuit of FIG. 5. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, several embodiments will be described with reference to the accompanying drawings. However, the dimensions, materials, shapes, relative arrangements, etc. of the components described as embodiments or shown in the drawings are merely illustrative examples and are not intended to limit the scope of the invention.

[0026] 1 is a circuit diagram showing a reference voltage circuit 1 according to an embodiment. The reference voltage circuit 1 includes a bandgap reference voltage source, and specifically includes a first PNP bipolar transistor Q1, which has a normalized emitter area ratio set to m:1 (m is a positive number), has its bases connected to each other, and has its collectors grounded. p1 , and a second PNP bipolar transistor Q p2 Reference voltage V REF Output terminal T for outputting OUT One end of the first resistor R1 is connected to the output terminal T OUT and the second PNP bipolar transistor Q p2 A second resistor R2 is connected between the other end of the first resistor R1 and the emitter of the first PNP bipolar transistor Q. p1 A third resistor R3 is connected between the emitter of the

[0027] The differential amplifier circuit A1 has a non-inverting input terminal connected to a node between the first resistor R1 and the third resistor R3, and an inverting input terminal connected to a second PNP bipolar transistor Q p2 The output terminal of the differential amplifier A1 and the output terminal T OUTA first capacitor C1 is connected between the output terminal of the differential amplifier A1 and the PMOS transistor M p1 The gate of the PMOS transistor M p1 The source is the power supply V DD and the drain is connected to the output terminal T OUT is connected to.

[0028] The reference voltage source circuit 1 further includes a base current acquisition unit 2 and a bias current supply unit 4.

[0029] The base current acquisition unit 2 includes a first PNP bipolar transistor Q p1 and a second PNP bipolar transistor Q p2 In this embodiment, the base current acquisition unit 2 acquires the base current of the positive input terminal TA ip , negative input terminal TA im , first positive output terminal TA out1 , and the second positive output terminal TA out2 This voltage-current converter is configured as a voltage-current converter having a first positive output terminal TA out1 and the second positive output terminal TA out2 are configured so that the output currents of the

[0030] Specifically, the positive input terminal TA ip is the bias voltage V BIAS1 A bias power supply capable of outputting is connected to the negative input terminal TA im is the first PNP bipolar transistor Q p1 and a second PNP bipolar transistor Q p2 The first positive output terminal TA out1 is connected to the input terminal i1 of the bias current supply unit 4. The second positive output terminal TA out2 is the negative input terminal TA im In the base current acquisition unit 2 having such a configuration, the second positive output terminal TA out2 is the first PNP bipolar transistor Q p1 and a second PNP bipolar transistor Q p2Since it is connected to the base of the first positive output terminal TA out1 The output current is 2I, which is the sum of the base currents of the two PNP bipolar transistors. B This becomes:

[0031] Here, the first PNP bipolar transistor Q p1 The input resistance of r π1 , a second PNP bipolar transistor Q p2 The input resistance of r π2 , when the voltage-current gain of the base current acquisition unit 2 configured as a voltage-current converter is Gm1, the first PNP bipolar transistor Q p1 The base potential V BASE is the bias voltage V BIAS1 is approximately equal to TIFF0007821691000003.tif10170At this time, the first positive output terminal TA out1 The output current of the second positive output terminal TA out2 Output current 2I B becomes equal to

[0032] 2 shows an example of the circuit configuration of the base current acquisition unit 2 of FIG. 1. In this example of the circuit configuration, the base current acquisition unit 2 includes a differential amplifier circuit 6. The differential amplifier circuit 6 is a first current source I TA1 , the first PMOS transistor M pTA1 , the second PMOS transistor M pTA2 , the first NMOS transistor M nTA1 The first PMOS transistor M pTA1 and the second PMOS transistor M pTA2 The gates of the positive input terminals TA ip and negative input terminal TA im The first PMOS transistor M pTA1 and the second PMOS transistor M pTA2 The source of is the first current source I TA1 The first PMOS transistor M pTA1 The drain of the first NMOS transistor M nTA1 The drain and gate of the transistor are connected.

[0033] First NMOS transistor M nTA1 The gate of the second NMOS transistor M nTA2 , and the third NMOS transistor M nTA3 The gate of the second NMOS transistor M nTA2 , and the third NMOS transistor M nTA3 The drains of the second current source I TA2 and the third current source I TA3 and the first NMOS transistor M nTA1 , the second NMOS transistor M nTA2 , and the third NMOS transistor M nTA3 The sources of the are grounded.

[0034] In the differential amplifier circuit 6, the first PMOS transistor M pTA1 , the second PMOS transistor M pTA2 A current corresponding to the difference between the voltages input to the gates of the first NMOS transistor M nTA1 In this embodiment, as shown in FIG. pTA1 The gate of the positive input terminal TA ip to bias voltage V BIAS1 is input, and the second PMOS transistor M pTA2 The gate of the negative input terminal TA im to the first PNP bipolar transistor Q p1 The base potential V BASE are input, so the difference between these voltages, V BIAS1 A current corresponding to the first NMOS transistor M nTA1 flows into

[0035] First NMOS transistor M nTA1 In the first NMOS transistor M, the gate voltage is changed so as to be equal to the current. nTA1 The gate of the second NMOS transistor M nTA2 , and the third NMOS transistor M nTA3 Therefore, the second current source I TA2and the third current source I TA3 The current values ​​are equal (I TA2 =I TA3 ), and the second NMOS transistor M nTA2 and a third NMOS transistor M nTA3 When the shape ratio (W / L) of the third NMOS transistor M nTA3 The second positive output terminal TA connected to out2 to base current 2I B When the voltage flows, the second NMOS transistor M nTA2 The first positive output terminal TA connected to out1 The output is also a current of 2I B This becomes:

[0036] Next, returning to FIG. 1, the bias current supply unit 4 supplies the base current 2I acquired by the base current acquisition unit 2. B The first bias current and the second bias current corresponding to the first PNP bipolar transistor Q p1 and the emitter of the second PNP bipolar transistor Q p2 In this embodiment, the bias current supply unit 4 is configured as a current distributor having an input terminal i1, a first bias current output terminal o1, and a second bias current output terminal o2. This current distributor is configured to distribute the current input to the input terminal i1 into a first bias current output from the first bias current output terminal o1 and a second bias current output from the second bias current output terminal o2. In this embodiment, the first PNP bipolar transistor Q p1 and a second PNP bipolar transistor Q p2 Since these are elements with the same specifications, the current 2I input to the input terminal i1 B are equally distributed, resulting in the first and second bias currents I B is playing.

[0037] 3 shows an example of the circuit configuration of the bias current supply unit 4 shown in FIG. 1. In this example of the circuit configuration, the bias current supply unit 4 includes a current follower circuit 4A and a current mirror circuit 4B. The current follower circuit 4A includes an NMOS transistor M connected to the input terminal i1. nCD1 The differential amplifier A2 has an inverting input terminal connected to the input terminal i1 and a non-inverting input terminal connected to a bias voltage V BIAS2 A bias power supply capable of outputting is connected, and an NMOS transistor M nCD1 In this way, the bias current supply unit 4 has a current follower circuit 4A in the preceding stage of the current mirror circuit 4B. As a result, the base current 2I acquired by the base current acquisition unit 2 is input to the input terminal i1. B In addition, the bias voltage V supplied to the non-inverting input terminal BIAS2 The positive input terminal TA of the base current acquisition section 2 ip The bias voltage V supplied to BIAS1 By setting the voltage equal to the base current 2I acquired by the base current acquisition unit 2, B can be detected with even greater accuracy.

[0038] The current mirror circuit 4B receives the current 2I from the base current acquisition unit 2. B is input via the current follower circuit 4A. The current mirror circuit 4B includes a PMOS transistor M pCD1 ~M pCD6 and the base current 2I input to the current mirror circuit 4B. B , the first bias current I output from the first bias current output terminal о1 B , the second bias current I output from the second bias current output terminal о2 B The ratio is configured to be 2:1:1.

[0039] A first PNP bipolar transistor Q to which a first bias current and a second bias current are supplied from a bias current supply unit 4 p1 and a second PNP bipolar transistor Q p2 Then, the emitter current IE , base current I B , collector current I c The following relationship holds between TIFF0007821691000004.tif16170Then, from the above equations (8) and (9), the following relationship holds: TIFF0007821691000005.tif10170

[0040] Comparing the above equation (10) obtained in this way with the above equation (4), the base current amplification factor β Qp The element (β Qp / (1+β Qp )) is eliminated. This is because the reference voltage source circuit 1 of this embodiment has the above-described configuration, and the first PNP bipolar transistor Q p1 and a second PNP bipolar transistor Q p2 This means that the influence of the base current amplification factor β is eliminated.

[0041] Figure 4 shows the output terminal T of the reference voltage source circuit 1 in Figure 1. OUT The reference voltage V output from REF The temperature characteristics of the first PNP bipolar transistor Q p1 and a second PNP bipolar transistor Q p2 4 shows the temperature characteristics of the reference voltage Vref when the base current amplification factor β is set to 2.0, 4.0, and 8.0. As shown in FIG. 4, in this embodiment, even if the base current amplification factor β changes, the temperature characteristics of the reference voltage Vref do not change and are stable.

[0042] As described above, according to the embodiment, the base current acquisition unit 2 acquires the base current of the first PNP bipolar transistor Q p1 and a second PNP bipolar transistor Q p2 The base current is supplied to the first PNP bipolar transistor Q by the bias current supply unit 4. p1 and a second PNP bipolar transistor Q p2As a result, the reference voltage V output from the reference voltage source circuit 1 is REF The first PNP bipolar transistor Q p1 and a second PNP bipolar transistor Q p2 As a result, the reference voltage source circuit 1 using a PNP bipolar transistor with a relatively small base current amplification factor β can output a stable reference voltage. [Explanation of symbols]

[0043] 1. Reference voltage source circuit 2 Base current acquisition section 4. Bias current supply section 4A current follower circuit 4B Current mirror circuit 6 Differential amplifier circuit

Claims

1. a first PNP bipolar transistor and a second PNP bipolar transistor, the normalized emitter area ratio of which is set to m:1 (m is a positive number), the bases of which are connected to each other, and the collectors of which are grounded; a third resistor having one end connected to the emitter of the first PNP bipolar transistor; a first resistor connected between the other end of the third resistor and a reference voltage output terminal; a second resistor connected between the emitter of the second PNP bipolar transistor and the reference voltage output terminal; a differential amplifier having a non-inverting input terminal connected to a node provided between the first resistor and the third resistor and an inverting input terminal connected to the emitter of the second PNP bipolar transistor; a first capacitor connected between the output terminal of the differential amplifier and the reference voltage output terminal; a PMOS transistor having a gate connected to the output terminal of the differential amplifier, a source connected to a power supply, and a drain connected to the reference voltage output terminal; a base current acquisition unit for acquiring base currents flowing through the bases of the first PNP bipolar transistor and the second PNP bipolar transistor; a bias current supply unit for supplying a first bias current and a second bias current corresponding to the base current acquired by the base current acquisition unit to the emitter of the first PNP bipolar transistor and the emitter of the second PNP bipolar transistor, respectively; Equipped with The bias current supply unit sets the first bias current and the second bias current so that the sum of the first bias current and the second bias current becomes the base current.

2. 2. The reference voltage source circuit according to claim 1, wherein the base current acquisition unit is configured as a voltage-to-current converter having a positive input terminal connected to a bias power supply, a negative input terminal connected to the bases of the first PNP bipolar transistor and the second PNP bipolar transistor, a first positive output terminal connected to the bias current supply unit, and a second positive output terminal connected to the negative input terminal.

3. 3. The reference voltage source circuit according to claim 1, wherein the bias current supply unit is configured as a current distributor having an input terminal to which the base current acquired by the base current acquisition unit is input, a first bias current output terminal for outputting the first bias current to the emitter of the first PNP bipolar transistor, and a second bias current output terminal for supplying the second bias current to the emitter of the second PNP bipolar transistor.

4. 4. The reference voltage source circuit according to claim 3, wherein the bias current supply section includes a current mirror circuit for generating a first bias current corresponding to the base current input to the input terminal, and the second bias current.

5. 3. The reference voltage source circuit according to claim 1, wherein the base current acquired by the base current acquisition unit is input to the bias current supply unit via a current follower circuit.

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