Method and system for generating geometric data for electronic designs

Abstract

A method for generating shape data for a set of electronic designs includes inputting a set of shape data, the set of shape data representing a set of shapes for a device manufacturing process. A convolutional neural network is applied to the set of shape data to determine a generated set of shape data, the convolutional neural network including a generator trained with a set of predetermined classifiers. The generated set of shape data includes a scanning electron microscope (SEM) image.

Description

[Technical Field]

[0001] Related Applications This application claims priority to U.S. Patent Application No. 17 / 022,363, entitled "Method and System for Generating Geometry Data for Electronic Design," filed September 16, 2020, which is incorporated herein by reference. [Background technology]

[0002] This disclosure relates to lithography, and more particularly to the design and fabrication of surfaces, which may be reticles, wafers, or any other surfaces, using charged particle beam lithography and optical lithography.

[0003] Three common types of charged particle beam lithography are unshaped (Gaussian) beam lithography, shaped charged particle beam lithography, and multi-beam lithography. In all types of charged particle beam lithography, a beam of charged particles directs energy toward a resist-coated surface, exposing the resist.

[0004] In lithography, lithography masks, or reticles, contain geometric patterns that correspond to the circuit components to be integrated on a substrate. The patterns used to manufacture reticles may be generated using computer-aided design (CAD) software or programs. When designing the patterns, the CAD program may follow a set of predetermined design rules to create the reticle. These rules are set according to process, design, and end-use constraints. An example of an end-use constraint is defining the geometry of a transistor so that it cannot operate satisfactorily at a required power supply voltage. In particular, design rules may define the spacing tolerance between circuit devices or interconnect lines. Design rules are used, for example, to ensure that circuit devices or wiring do not interact with each other in undesirable ways. For example, design rules are used to prevent wiring from being too close to each other and potentially causing a short. Design rule constraints reflect, among other things, the minimum dimensions that can be reliably fabricated. When referring to these small dimensions, the concept of critical dimensions is usually employed. These are defined, for example, as the critical width or area of ​​a feature, or the critical spacing or critical spacing area between two features, and these dimensions require precise control.

[0005] One goal in integrated circuit fabrication using optical lithography is to reproduce the original circuit design on a substrate by using a reticle, sometimes called a mask or photomask. A reticle is a surface that can be exposed using charged particle beam lithography. Integrated circuit manufacturers are always striving to use the area of ​​semiconductor wafers as efficiently as possible. Engineers continue to reduce the size of circuits to allow integrated circuits to contain more circuit elements and use less power. As the size of the critical dimensions of integrated circuits decreases and their circuit density increases, the critical dimensions of the circuit pattern, or physical design, approach the resolution limit of the exposure tools used in traditional optical lithography. As the critical dimensions of the circuit pattern become smaller and approach the resolution value of the exposure tools, it becomes more difficult to accurately transfer the physical design into the actual circuit pattern developed on the resist layer. To further utilize optical lithography to transfer patterns with features smaller than the wavelength of light used in the optical lithography process, a process known as optical proximity correction (OPC) was developed. OPC modifies the physical design to compensate for distortions caused by effects such as optical diffraction and the optical interaction of nearby features. Resolution enhancement techniques implemented on the reticle include OPC and inverse lithography technology (ILT).

[0006] OPC allows the addition of subresolution lithographic features to mask patterns to reduce the differences between the original physical design pattern, i.e., the design, and the final transferred circuit pattern on the substrate. The subresolution lithographic features interact with the original pattern in the physical design and with each other to compensate for proximity effects and improve the final transferred circuit pattern. One feature added to improve pattern transfer is called a "serif." A serif is a small feature that enhances the accuracy or resilience to manufacturing variations in the printing of a particular feature. An example of a serif is a small feature placed at the corner of a pattern to sharpen the corners of the final transferred image. The pattern intended to be printed on the substrate is called the main feature. The serif is a part of the main feature. It is common to describe the OPC-decorated pattern written to the reticle in terms of the main feature, which is a feature that reflects the design before OPC decoration, and the OPC features, which include serifs, jogs, subresolution assist features (SRAFs), and negative features. OPC features are subject to various design rules, including rules based on the size of the smallest feature that can be printed onto the wafer using optical lithography. Other design rules may result from the mask manufacturing process, or from the stencil manufacturing process if a character projection charged particle beam writing system is used to form the pattern on the reticle.

[0007] In the fabrication of integrated circuits using photomasks, the fabrication of a photomask containing the original circuit design is a critical step in the process. Defects on the photomask will be reproduced on all wafers fabricated using that photomask, so the final photomask must be defect-free within a predetermined tolerance. Due to material and process limitations, most or all newly fabricated photomasks contain defects. In a process called mask inspection, newly fabricated photomasks are analyzed to find defects. Each of these defects, or potential defects, is then further analyzed to determine whether the defect is an actual defect that will cause defects in wafers fabricated with this photomask. Defects identified as actual defects are repaired in a subsequent process called mask repair, resulting in a defect-free photomask suitable for wafer fabrication. Summary of the Invention [Means for solving the problem]

[0008] A method for generating shape data for a set of electronic designs includes inputting a set of shape data, the set of shape data representing a set of shapes for a device manufacturing process. A convolutional neural network is applied to the set of shape data to determine a generated set of shape data, the convolutional neural network including a generator trained with a set of predetermined classifiers. The generated set of shape data includes a scanning electron microscope (SEM) image.

[0009] The method for generating SEM images of a set of electronic designs also includes inputting a set of shape data, the set of shape data representing a set of shapes for a device manufacturing process. A set of parameters including a set of convolutional layers of a Conditional Generative Adversarial Network (CGAN) is input. The CGAN includes a generator and a set of classifiers. The SEM images are generated with the set of shape data using the set of convolutional layers of the CGAN. A generator loss is calculated by combining a portion of the perceptual loss and the classifier loss, and the set of parameters including the set of convolutional layers is adjusted. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram of a method for creating an SEM image, according to some embodiments. [Figure 2] FIG. 1 is a diagram of a neural network architecture for generating SEM images, as known in the art. [Figure 3] FIG. 1 illustrates a neural network architecture for generating SEM images, according to some embodiments. [Figure 4] FIG. 2 illustrates details of a generator, according to some embodiments. [Figure 5] FIG. 1 illustrates a set of classifiers, according to some embodiments. [Figure 6] 10 provides details of the function used to calculate loss, according to some embodiments. [Figure 7] 1 is a schematic diagram of a GPU system, according to some embodiments. [Figure 8] 1 is a schematic diagram of a GPU system, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0011] Deep learning (DL) has solved problems across a wide range of industries, including retail, information technology (IT), healthcare, pharmaceuticals, biotechnology, and autonomous driving. Similarly, deep learning recipes for recommendation, segmentation, classification, anomaly detection, and digital modeling are highly relevant in photomask, printed circuit board (PCB), and flat panel display (FPD) manufacturing. Photomask shops face challenges with mask inspection and the detection and classification of hot spots, faults, and defects that impede production. Deep learning has the potential to solve these challenges before they cause real problems on the assembly line. Digital twins, which model the characteristics, conditions, and attributes of their real-world counterparts in electronics manufacturing, offer significant advantages over real-world data in simulating system behavior. Using digital twins, designers can observe, recreate, and detect system failures at the software level, long before they stop or slow down the assembly line.

[0012] The types of problems that deep learning can solve include natural language understanding to extract meaningful information from text documents, information retrieval, and language translation. In the speech domain, DL has made great strides in automatic speech recognition, text-to-speech, and realistic speech generation. Related to computer vision, DL provides effective solutions to a variety of problems, including object detection, object segmentation in MRI scans, image denoising, extracting text from images, performing image-based search, improving image quality, and even creating new images. DL has led to advances in discovering anomalies in the form of outliers by learning the exact distribution of normal data, so DL can flag anomalous data. DL even has the ability to assist in building digital twins that simulate physical environments.

[0013] Many of the photomask industry problems, including traditional optical proximity correction (OPC), inverse lithography techniques (ILT), lithography hotspot detection, fault detection and classification, automated classification and diagnosis of mask defects, SEM denoising and contour extraction, etc., benefit from deep learning.

[0014] Computer-aided engineering (CAE) techniques can also be applied to scanning electron microscope (SEM) images of physically fabricated masks or wafers. Such applications can help automatically classify potential defects, such as mask defects. In typical semiconductor manufacturing, potential defects on masks are identified through mask inspection, which generates an image of the entire mask. While the image is blurry and relatively low-resolution, it still captures the entire mask. This mask inspection process is designed to identify suspect areas that require additional inspection. Further inspection is performed by acquiring more accurate SEM images and analyzing these images. This further inspection is performed using a defect inspection SEM machine. Defect inspection SEM machines can capture highly detailed images but have a limited field of view, such as 1 μm x 1 μm to 10 μm x 10 μm. Therefore, potential defect areas are first identified in the full-field mask image generated by mask inspection, and then the details of the potential defect areas are inspected by SEM. At cutting-edge nodes, the number of suspect areas identified, and the number of actual defects on a typical production mask, are much higher than at previous nodes. At the beginning of the 21st century, a few dozen defects on a mask might be repaired. Masks with more errors than this were discarded and remanufactured. This evolved to the point where it was common for state-of-the-art masks to have hundreds of problems, all of which required repair. Because a remanufactured mask is likely to have hundreds of defects, mask remanufacturing has become less common. Defect repair is specific to the mask manufacturing process; the wafer is not repaired. Masks are worth repairing because errors on a mask will be reproduced on every wafer produced using that mask.

[0015] Thus, in some embodiments, the use of SEM images can be used to train the neural network of the present method to help identify mask defects. Simulations of mask images can also be used to train the neural network.

[0016] FIG. 1 illustrates the generation of an SEM image, starting with simulating a mask image 102 from a physical design 100. The input physical design 100 is also referred to as a set of shape data for an electronic design, and the set of shape data represents a set of shapes for a device manufacturing process. The set of shape data can be created using lithography simulation. The device manufacturing process can be, for example, a semiconductor manufacturing process or a flat panel display manufacturing process, and the process can include mask design, simulation, or manufactured shapes. Once the mask image 102 is input into a neural network 104, an SEM image 106 can be generated. Conventional methods for generating SEM images use only simulation methods and lack true edge roughness and SEM noise, which are attributes of actual SEM images used in defect analysis.

[0017] We used Pix2Pix, an example of a well-known deep learning architecture for general image-to-image translation, to create realistic-looking SEM images. Pix2Pix is ​​an image-to-image translation model that uses a conditional generative adversarial network (CGAN). Research has demonstrated the effectiveness of Pix2Pix for synthesizing photos from label maps, reconstructing objects from edge maps, and coloring images. The original Pix2Pix architecture, shown in Figure 2, generates a 256 x 256 pixel image. A simulated image 202 is input to a generator 204 to generate an SEM image 206. Pairs of generated and simulated images, as well as pairs of real and simulated SEM images, are input to a classifier 210, which determines whether the generated images are authentic (real SEM images, or whether the user has been "tricked" into thinking the generated images are real SEM images) or fake (generated SEM images). The architecture shown produces artifacts in some areas and corrupts color and geometry in others. As the image resolution increases (e.g., from 256 to 1024), the artifacts become more noticeable. This architecture uses an L1 loss and a GAN loss that preserves only the low-frequency components of the image.

[0018] A neural network is a framework of machine learning algorithms that work together to predict inputs based on a previous training process. In this embodiment, a CGAN neural network is used to convert a physical design into its corresponding SEM image. A diagram of one embodiment of a neural network is shown in the schematic diagram of FIG. 3, where a generator 300 uses a simulated image as input 301. The neural network architecture includes three separate classifiers 342, 344, and 346. In some embodiments, at least three predetermined classifiers, such as three or more, can be used. Each classifier outputs a classifier loss 347 and a perceptual loss 348. The neural network further includes a final classifier loss 350 and a final generator loss 352. The final classifier loss 350 combines the classifier losses 347 output from each of the three predetermined classifiers together. The generated SEM image 339 can then be compared to an actual SEM image 340 to determine the accuracy of the generator / classifier neural network. That is, in some embodiments, the method includes inputting an actual SEM image, which is used by a set of predetermined classifiers to compare with the set of generated shape data.

[0019] In some embodiments, a perceptual loss is calculated to preserve high-frequency components when generating a high-resolution image from a low-resolution image. All layers of each classifier are used to calculate the perceptual loss. The perceptual loss allows for the generation of SEM noise found in actual SEM images. In embodiments, the perceptual loss 348 from each classifier is combined with a portion of the classifier loss 349 to generate a final generator loss 352, which advantageously improves the accuracy of the generated SEM image compared to conventional methods. The classifier loss is calculated from each classifier that classifies a pair of actual SEM image f(X) and simulated CAD data f(Z) against an SEM image fG(Z) generated from the simulated CAD data f(Z) across the number of classifiers. The portion combined with the permanent loss includes only the loss from the generated SEM image (fG(Z)).

[0020] A more detailed embodiment of the generator 300 of Figure 3 is shown in Figure 4. The method involves using a generator to create a set of generated shape data, which includes an encoder and a decoder. A simulated image 301 (i.e., a set of shape data such as a simulated mask image or simulated CAD data) is input to the encoder (comprising encoder blocks 302, 304, 306, 308, 310, 312, 314, 316, 318, and 319), and an SEM image 339 is output from the decoder (comprising decoder blocks 321, 322, 324, 326, 328, 330, 332, 334, 336, and 338). The generator 300 includes multiple encoder blocks, from 302, 304, and 306 through blocks 308, 310, 312, 314, 316, 318, and 319, for a maximum of 10 blocks. A bottleneck layer 320 reduces the image to a 1x1 matrix with up to 512 channels, followed by multiple decoder blocks, from 321 through blocks 322, 324, 326, 328, 330, 332, 334, 336, and 338, for a maximum of 10 blocks. The maximum number of blocks is used to convolve a 1024-pixel image into a 1x1 matrix with 512 channels to better represent the input image. Except for the first encoder block 302, each encoder block after the first encoder block (e.g., blocks 304-319) includes a convolutional layer, a batch normalization layer, and a leaky ReLU (Rectified Linear Unit) activation layer. All decoder blocks 321-338 include a transposed convolutional layer. The first decoder block 321 has a transposed convolutional layer and a ReLU activation layer. Subsequent blocks after the first decoder block 321 in the first set of decoder blocks (e.g., the first 10 decoder blocks 322-328) include a transposed convolutional layer, a batch normalization layer, and a ReLU activation layer. The second set of decoder blocks (e.g., the last 10 decoder blocks 330-338) include the same layers as the first set plus a dropout layer.The encoder and decoder can contain up to 10 blocks, each with a kernel size of 4x4, and channels (depth) varying from 3, 64, 128, 256, and limited to 512 to conserve memory. For example, the encoder blocks may increase in stages from 3 channels in the first encoder block to 64 channels, 128 channels, 256 channels, and 512 channels in subsequent encoder blocks. Similarly, the decoder blocks may decrease in stages from 512 channels in the first decoder block to 256, 128, 64, and 3 channels in subsequent decoder blocks.

[0021] Unlike conventional techniques, this embodiment can generate 1024 x 1024 SEM images. These larger 1024 x 1024 images are necessary compared to the traditional 256 x 256 SEM image size because smaller images prevent noise generation. Larger images provide more data for generating SEM noise, which is present in real SEM images and used for defect analysis. When smaller images were used, no SEM noise was generated. Similar to GAN-based models, this embodiment's model generates images that can fool the classifier while allowing the classifier to distinguish between real images and images generated by the generator. The generator itself functions as an image translation network, such as a U-Net using skip connections. However, in some embodiments, since a CGAN is used rather than randomly generating images, the generator is conditioned to generate specific images. Generating specific images allows defects to be incorporated into the simulated CAD data and reflected in the generated SEM images. The classifier functions as a convolutional neural network (CNN) that classifies whether an image is real or generated by the generator.

[0022] To generate realistic SEM images, a model is trained using pairs of training images: simulated CAD data and the corresponding real SEM. The generator takes the simulated CAD data as input and attempts to create realistic SEM images from it. The classifier network takes the real SEM, the generated SEM images, and the simulated CAD data as input. The classifier then classifies the SEM images as generated (fake) or real.

[0023] In some embodiments, multiple classifiers with different input image sizes can be used to remove repetitive patterns. Figure 5 shows a model with multiple classifiers 512, 514, and 516, each processing a different input image size subsampled from image 508. The various classifiers act as hard and soft critics for the real or generated image. Each classifier is trained to receive different sized portions (e.g., 1, 1 / 2, and 1 / 4) of the original image (real or generated), using, for example, a 70x70 receptive field for patch penalization (each reduced portion should be twice the original image size, 140x140 for half-size portions, and 280x280 for quarter-size portions). The different patch penalties enable more accurate SEM features and noise distribution. With only one classifier, the network learns quickly, and the generator continues to generate images that are easily classified as fake. When multiple classifiers are used, each classifier in this embodiment is configured with a different receptive field, ranging from small to large, based on subsampling. This helps train the generator because at least one of the three or more classifiers may not be confident that an image is fake. Multiple classifiers also reduce the occurrence of repetitive patterns in the generated images, as seen in models with a single classifier.

[0024] The classifiers are predetermined. That is, the set of classifiers has predetermined image sizes they process and the types of layers and blocks they are composed of. In the embodiment of FIG. 5, the first predetermined classifier 512 is trained on 1024×1024 pixel images, the second predetermined classifier 514 is trained on 512×512 pixel images, and the third predetermined classifier 516 is trained on 256×256 pixel images. Each classifier includes multiple layers or classifier blocks. For example, each classifier may include multiple classifier blocks. In some embodiments, the first block (first layer) includes a convolutional layer, a leaky ReLU activation layer, and a padding layer. In addition, subsequent layers include a batch normalization layer. The final layer includes a convolutional layer, a padding layer, and a sigmoid activation layer. In addition, the size of the input to each classifier is halved in the first two layers, and the width and height are reduced by 1 in each subsequent layer. The classifier may include a 4x4 kernel size and channels (depth) that vary from 6, 64, 128, and 256, but are limited to 512 to conserve memory. In an exemplary embodiment, the second, third, fourth, fifth, and sixth blocks include a convolutional layer, a batch normalization layer, a leaky ReLU activation layer, and a padding layer, respectively, and the seventh block includes a convolutional layer, a padding layer, and a sigmoid activation layer. The number of blocks can be selected to balance training efficiency and accuracy. For example, a certain number of blocks may not produce significantly improved results due to the increased computation time of adding additional blocks.

[0025] In some embodiments, a method includes inputting a set of shape data, such as simulated image 301, where the set of shape data represents a set of shapes for a device manufacturing process, and inputting a set of parameters including a set of convolutional layers of a CGAN (e.g., convolutional layers 302-319 and 321-338 of FIG. 4 ). The method also includes generating an SEM image 339 with the set of shape data, such as simulated image 301, by using the set of convolutional layers of the CGAN. The method further includes calculating a loss including a perceptual loss 348 combined with a portion 349 of an accumulated classifier loss 350, and adjusting the set of parameters including the set of convolutional layers. The adjustment may be performed by repeatedly looping from final generator loss 352 to generator 300. Parameters that may be adjusted when training a CGAN include, for example, a learning rate, a perceptual loss weight, and the number of classifiers. In some embodiments, the set of parameters includes a 4x4 kernel size with channels varying among 3, 64, 128, 256, and 512 for each convolutional layer. For example, an encoder layer may increase from 3 channels to 64, 128, 256, and 512 in subsequent encoder layers, while a decoder layer may decrease from 512 channels to 256, 128, 64, and 3 in subsequent decoder layers.

[0026] FIG. 6 details an example function used to calculate loss, according to some embodiments. The classifier loss is calculated across the number of classifiers from each classifier that classifies a pair of real SEM images f(X) and simulated CAD data f(Z) against the SEM image f(G(Z)) generated from the simulated CAD data f(Z). The generator loss combines the classifier loss f(G(Z)) across the number of classifiers for the SEM image generated from the simulated CAD data f(Z) with a perceptual loss. The perceptual loss is an adversarial loss combined with a content loss motivated by perceptual similarity rather than pixel spacing similarity. The perceptual loss is calculated across all layers of classifiers from each classifier that classifies a pair of real SEM images f(X) and simulated CAD data f(Z) against the SEM image f(G(Z)) generated from the simulated CAD data f(Z).

[0027] FIG. 7 illustrates an example of a computing hardware device 700 that can be used to perform the computations described in this disclosure. Examples of computations include processing convolutional and deconvolutional layers of a neural network, computing and comparing losses, and compressing mask data using a trained neural network. The computing hardware device 700 includes a central processing unit (CPU) 702 with attached main memory 704. The CPU may include, for example, eight processing cores, thereby improving the performance of any portion of multithreaded computer software. The main memory 704 may be, for example, 64 GB in size. The CPU 702 is connected to a Peripheral Component Interconnect Express (PCIe) bus 720. A graphics processing unit (GPU) 714 is also connected to the PCIe bus. In the computing hardware device 700, the GPU 714 may or may not be connected to a graphics output device, such as a video monitor. When not connected to a graphics output device, the GPU 714 may be used purely as a high-speed parallel computation engine. Computing software may achieve significantly higher performance by using a GPU for a portion of its calculations compared to using the CPU 702 for all calculations. The CPU 702 communicates with the GPU 714 via a PCIe bus 720. In other embodiments (not shown), the GPU 714 may be integrated with the CPU 702 rather than connected to the PCIe bus 720. A disk controller 708 may also be attached to the PCIe bus, with, for example, two disks 710 connected to the disk controller 708. Finally, a local area network (LAN) controller 712 may also be attached to the PCIe bus, providing Gigabyte Ethernet (GbE) connectivity to other computers. In some embodiments, computer software and / or design data are stored on the disk 710.In other embodiments, either the computer program or the design data, or both the computer program and the design data, may be accessed from other computers or file serving hardware via GbE Ethernet.

[0028] FIG. 8 illustrates another embodiment of a system for performing the computations of the present invention. System 800, sometimes referred to as a computational design platform (CDP), includes a master node 810, an optional viewing node 820, an optional network file system 830, and a GPU-enabled computing node 840. The viewing node 820 may be absent, alternatively include only one node, or include other numbers of nodes. GPU-enabled computing node 840 may include one or more GPU-enabled nodes forming a cluster. Each GPU-enabled computing node 840 may be, for example, a GPU, a CPU, a GPU and CPU pair, multiple GPUs for a CPU, or other combinations of GPUs and CPUs. The GPU and / or CPU may be on a single chip, such as a GPU chip with a CPU accelerated by a GPU on that chip, or a CPU chip with a GPU accelerating the CPU. The GPU may be replaced with other coprocessors.

[0029] The master node 810 and the viewing nodes 820 may be connected to the network file system 830 and the GPU-enabled computing nodes 840 via switches and high-speed networks, such as networks 850, 852, and 854. In an exemplary embodiment, network 850 may be a 56 Gbps network, 852 may be a 1 Gbps network, and 854 may be a management network. In various embodiments, there may be fewer or more of these networks, and various combinations of network types, such as high-speed and low-speed networks. The master node 810 controls the CDP system 800. An external system may connect to the master node 810 from an external network 860. In some embodiments, jobs are launched from the external system. Job data is loaded into the network file system 830 before launching the job, and a program is used to dispatch and monitor tasks on the GPU-enabled computing nodes 840. Job progress can be viewed via a graphical interface, such as the viewing node 820, or by a user on the master node 810. Tasks are executed on the CPU using scripts that run the appropriate executable on the CPU. The executables connect to the GPU, perform various computational tasks, and then disconnect from the GPU. The master node 810 can also be used to disable a faulty GPU-enabled compute node 840 and then operate as if the node did not exist.

[0030] While this specification has been described in detail with reference to certain embodiments, it will be understood that, upon gaining an understanding of the foregoing, those skilled in the art will readily conceive of modifications, variations, and equivalents to these embodiments. These and other modifications and variations to this method may be practiced by those skilled in the art without departing from the scope of the present subject matter, which is more particularly set forth in the appended claims. Furthermore, those skilled in the art will understand that the above description is by way of example only and is not intended to be limiting. Steps may be added, deleted, or modified from the steps of this specification without departing from the scope of the invention. Generally, any flowchart presented is intended to illustrate only one possible sequence of basic operations to achieve a function, and many variations are possible. It is therefore intended that the present subject matter cover all such modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method for generating geometric data for a set of electronic designs, comprising: inputting a set of feature data, the set of feature data representing a set of features for a device manufacturing process; applying a convolutional neural network to the set of shape data to determine a set of generated shape data, the convolutional neural network including a generator trained with a set of predetermined classifiers; Including, the generated set of shape data includes a generated scanning electron microscope (SEM) image; each classifier in the predetermined set of classifiers processes a different input image size subsampled from the generated SEM image; The method.

2. The method of claim 1 , wherein the set of shape data is created using lithography simulation.

3. The method of claim 1 , wherein the set of predetermined classifiers includes at least three predetermined classifiers.

4. The method of claim 3 , wherein each predetermined classifier in the set of predetermined classifiers outputs a classifier loss and a perceptual loss.

5. The method of claim 4 , wherein the classifier losses from each of the predetermined classifiers are combined together to form a final classifier loss.

6. The method of claim 5 , wherein a portion of the classifier loss for each of the predetermined classifiers and the perceptual loss are combined to generate a final generator loss.

7. The predetermined set of classifiers is a first predetermined classifier trained with an input image size of 1024x1024 pixels; a second predetermined classifier trained with an input image size of 512x512 pixels; a third predetermined classifier trained with an input image size of 256x256 pixels; The method of claim 3, comprising:

8. The method of claim 3 , wherein each classifier comprises multiple classifier blocks.

9. the plurality of classifier blocks: a first block including a convolutional layer, a leaky rectified linear unit (ReLU) activation layer, and a padding layer; a second block, a third block, a fourth block, a fifth block, and a sixth block, each including a convolutional layer, a batch normalization layer, a leaky ReLU activation layer, and a padding layer; a seventh block including a convolutional layer, a padding layer, and a sigmoid activation layer; The method of claim 8, comprising:

10. further comprising inputting an actual SEM image; The method of claim 1 , wherein the actual SEM images are used by the set of predetermined classifiers to compare with the set of generated shape data.

11. using the generator to create the set of generated shape data, the generator including an encoder and a decoder; The method of claim 1 further comprising:

12. the encoder further comprising a plurality of encoder blocks; 12. The method of claim 11 , wherein each encoder block after a first encoder block in the plurality of encoder blocks includes a batch normalization layer, a convolutional layer, and a leaky ReLU activation layer.

13. the decoder further comprises a plurality of decoder blocks; The first decoder block of the plurality of decoder blocks includes a transposed convolutional layer and a ReLU activation layer, followed by: the first set of decoder blocks includes a transposed convolution layer, a batch normalization layer, and a ReLU activation layer; the second set of decoder blocks includes a transposed convolution layer, a batch normalization layer, a dropout layer, and a ReLU activation layer; The method of claim 11.

14. The method of claim 1 , wherein the device manufacturing process is a semiconductor manufacturing process.

15. The method of claim 1 , wherein the device manufacturing process is a flat panel display manufacturing process.

16. The method of claim 1 , wherein the set of shape data further comprises a simulated mask image.

17. 1. A method for training a conditional generative adversarial network (CGAN) to generate generated scanning electron microscope (SEM) images of a set of electronic designs, comprising: inputting a set of feature data, the set of feature data representing a set of features for a device manufacturing process; inputting a set of parameters including a set of convolutional layers of the CGAN including a set of generators and discriminators; generating the generated SEM image along with the set of shape data using the set of convolutional layers of the CGAN; calculating a generator loss that includes a perceptual loss combined with a portion of the discriminator loss; adjusting the set of parameters including the set of convolutional layers; Including, each classifier in the set of classifiers processes a different input image size subsampled from the generated SEM image; The method.

18. 18. The method of claim 17, wherein the set of parameters includes a 4x4 kernel size with channels varying among 3, 64, 128, 256, and 512 for each convolutional layer.

19. The method of claim 17 , wherein the portion of the classifier losses is combined from the set of classifiers.

20. The method of claim 17, wherein the generator further comprises a U-net.

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