Semiconductor Devices

Abstract

To provide a semiconductor device with excellent electric characteristics.SOLUTION: A semiconductor device includes: a transistor including a gate electrode, a source electrode, and a drain electrode; a first insulator on the transistor; a second insulator on the first insulator; a third insulator on the second insulator; a first electrode in contact with an upper surface of the source electrode; and a second electrode in contact with an upper surface of the drain electrode. The second insulator includes a first opening part overlapping with the source electrode, and a second opening part overlapping with the drain electrode. The third insulator is in contact with a side surface of the second insulator and an upper surface of the first insulator inside the first opening part and the second opening part. The first electrode is disposed through the first opening part. The second electrode is disposed through the second opening part.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] 1. Field of the Invention

[0003] One embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed significantly, especially in LSIs, CPUs, and memories. A CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) separated from a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in a non-conducting state. For example, a low-power CPU utilizing the low leakage current characteristic of transistors using oxide semiconductors has been disclosed (see Patent Document 1). Also, for example, a memory device capable of retaining stored data for a long period of time utilizing the low leakage current characteristic of transistors using oxide semiconductors has been disclosed (see Patent Document 2).

[0008] Furthermore, in recent years, with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits, and there is also a demand for improved productivity in semiconductor devices including integrated circuits. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 Summary of the Invention [Problem to be solved by the invention]

[0010] An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with little variation in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including: a transistor having a gate electrode, a gate insulating film, a source electrode, and a drain electrode; a first insulator over the transistor, a second insulator over the first insulator, a third insulator over the second insulator, a first electrode in contact with a top surface of the source electrode, and a second electrode in contact with a top surface of the drain electrode; the second insulator has a first opening overlapping with the source electrode and a second opening overlapping with the drain electrode; the third insulator is in contact with a side surface of the second insulator and a top surface of the first insulator inside the first opening and the second opening; the first electrode is disposed through the first opening; and the second electrode is disposed through the second opening.

[0013] In the above, it is preferable that the first insulator has a first groove overlapping the first opening and a second groove overlapping the second opening.

[0014] In addition, in the above, the side surface of the first electrode may be in contact with the third insulator at the first opening and the first groove, and the side surface of the second electrode may be in contact with the third insulator at the second opening and the second groove.

[0015] Furthermore, in the above, it is preferable that there is a fourth insulator provided in contact with a side surface of the first electrode and a fifth insulator provided in contact with a side surface of the second electrode, and that the side surface of the fourth insulator contacts the third insulator at the first opening and the first groove, and that the side surface of the fifth insulator contacts the third insulator at the second opening and the second groove.

[0016] In the above, the second insulator preferably contains aluminum oxide. In the above, the first insulator preferably contains silicon oxide, and the third insulator preferably contains silicon nitride. In the above, the transistor preferably includes an oxide semiconductor layer, and the oxide semiconductor layer preferably includes one or more selected from In, Ga, and Zn.

[0017] In the above, it is preferable that a gate insulating film, a source electrode, and a drain electrode are provided on the oxide semiconductor layer, a gate electrode is provided on the gate insulating film, the first insulator overlaps a region between the source electrode and the drain electrode, an opening is formed in the first insulator, and the gate insulating film and the gate electrode are disposed in the opening.

[0018] In the above, it is preferable that a sixth insulator covering the oxide semiconductor layer, the source electrode, and the drain electrode is provided, the sixth insulator has an opening overlapping a region between the source electrode and the drain electrode, and the first insulator is provided on the sixth insulator. It is also preferable that the sixth insulator contains silicon nitride.

[0019] In the above, it is preferable that the first insulator and the second insulator are formed in an island shape, and the third insulator covers the first insulator and the second insulator.

[0020] In addition, in the above, the second insulator may have a third opening in a region that does not overlap with the gate electrode, the source electrode, and the drain electrode, and the third insulator may be configured to contact a side surface of the second insulator and an upper surface of the first insulator inside the third opening.

[0021] Another embodiment of the present invention is a method for manufacturing a semiconductor device, the method including: forming a transistor having a source electrode and a drain electrode; and a first insulator over the source electrode and the drain electrode; depositing a second insulator containing aluminum oxide over the first insulator; forming, in the second insulator, a first opening overlapping with the source electrode and a second opening overlapping with the drain electrode; depositing a third insulator over the first insulator and the second insulator; forming a fourth insulator to fill a region of the third insulator overlapping with the first opening and the second opening; forming, in the first insulator, a third opening reaching the source electrode and a fourth opening reaching the drain electrode, in the first insulator, the third insulator, and the fourth insulator; the third opening being located inside the first opening in a top view and the fourth opening being located inside the second opening in a top view; and forming a first electrode in the third opening and a second electrode in the fourth opening.

[0022] In the above, it is preferable that the first insulator and the fourth insulator contain silicon oxide, and the third insulator contains silicon nitride.

[0023] In the above, the third opening and the fourth opening are preferably formed by dry etching using a gas containing fluorine.

[0024] Another embodiment of the present invention is a method for manufacturing a semiconductor device, including: forming a second insulator over a first insulator; forming an oxide semiconductor layer containing one or more selected from In, Ga, and Zn over the second insulator; processing the oxide semiconductor layer into an island shape by dry etching using a gas containing CH; and processing the second insulator into an island shape by dry etching using a gas containing halogen, thereby exposing a top surface of the first insulator.

[0025] In the above, it is preferable that the first insulator contains hafnium oxide and the second insulator contains silicon oxide.

[0026] In the above, it is preferable that after the second insulator is processed into an island shape, a third insulator is formed to cover the first insulator, the second insulator, and the oxide semiconductor layer, and the third insulator contains silicon nitride.

[0027] In the above method, a hard mask containing tungsten is preferably formed over the oxide semiconductor layer, and the oxide semiconductor layer is preferably processed into an island shape using the hard mask. [Effects of the Invention]

[0028] According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with favorable reliability can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced variation in transistor characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided.

[0029] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0030] [Figure 1] 1A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 1B to 1D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 2] 2A to 2D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 3] FIG. 3 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 4] Figure 4A is a diagram explaining the classification of IGZO crystal structures, Figure 4B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 4C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. [Figure 5] 5A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 5B to 5D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 6A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 6B to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 7A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 7B to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 8B to 8D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9]9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 9B to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 10B to 10D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 11B to 11D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 12A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 12B to 12D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 13B to 13D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 14A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 14B to 14D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 15B to 15D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 17A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 17B to 17D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] 18A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 18B to 18D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19] 19A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 19B to 19D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 20A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 20B to 20D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21] 21A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 21B to 21D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22] 22A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 22B to 22D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 23] 23A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 23B to 23D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 24] 24A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 24B to 24D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 25] FIG. 25 is a schematic diagram showing a model of dry etching processing of In-Ga-Zn oxide. [Figure 26] FIG. 26 is a top view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 27] FIG. 27 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 28] FIG. 28 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 29] FIG. 29 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 30] 30A and 30B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 31] 31A and 31B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 32] 32A and 32B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 33] 33A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 33B and 33C are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 34] FIG. 34 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 35] FIG. 35 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 36] FIG. 36 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 37] 37A and 37B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 38] FIG. 38 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 39] 39A and 39B are block diagrams illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 40] 40A to 40H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 41] 41A and 41B are block diagrams and schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 42] 42A and 42B are diagrams illustrating an example of an electronic component according to one embodiment of the present invention. [Figure 43] 43A to 43E are schematic diagrams of a memory device according to one embodiment of the present invention. [Figure 44] 44A to 44H are diagrams showing electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0031] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0032] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or resist masks may be unintentionally thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same reference numerals may be used in common between different drawings for identical parts or parts having similar functions, and repeated explanations may be omitted. When referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0033] In order to make the invention easier to understand, particularly in top views (also called "plan views") or perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0034] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc. in the description. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification.

[0035] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0036] Furthermore, when it is explicitly stated in this specification that X and Y are connected, it is understood that the present specification also discloses cases in which X and Y are electrically connected, cases in which X and Y are functionally connected, and cases in which X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0037] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. In this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0038] Furthermore, when a transistor with a polarity different from that described in the specification or drawings is used, or when the direction of current changes during circuit operation, the functions of the source and drain may be interchanged. For this reason, in this specification and the like, the terms source and drain may be used interchangeably depending on the situation.

[0039] Note that the channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0040] The channel width refers to, for example, the length of a channel formation region in a region where a semiconductor (or a portion of the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or the length of the channel formation region in a direction perpendicular to the channel length direction in the channel formation region. Note that the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a single transistor may not be determined to a single value. Therefore, in this specification, the channel width refers to any one value, maximum value, minimum value, or average value in the channel formation region.

[0041] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In such a case, the effective channel width is larger than the apparent channel width.

[0042] In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0043] In this specification, when simply referred to as a channel width, it may refer to an apparent channel width. Alternatively, when simply referred to as a channel width, it may refer to an effective channel width. Note that values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0044] Note that impurities in a semiconductor refer to, for example, anything other than the main component constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect state density of the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V) in the oxide semiconductor. O :oxygen vacancy) may be formed.

[0045] In this specification and the like, an oxynitride is a material whose composition contains more oxygen than nitrogen. For example, silicon oxynitride is a material whose composition contains more oxygen than nitrogen. Furthermore, a nitride oxide is a material whose composition contains more nitrogen than oxygen. For example, silicon nitride oxide is a material whose composition contains more nitrogen than oxygen.

[0046] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0047] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0048] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0049] Furthermore, in this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1 x 10 at 85°C -18 A or less, or 1 x 10 at 125°C -16 This means that it is A or below.

[0050] (Embodiment 1) In this embodiment, an example of a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[0051] One embodiment of the present invention can provide, for example, a semiconductor device including a plurality of transistors each having an oxide semiconductor layer. When impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor layer, the electrical characteristics of the transistor using the oxide semiconductor layer tend to fluctuate, and the reliability may be reduced. Furthermore, hydrogen near the oxygen vacancies may be introduced into the oxygen vacancies (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor layer, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in the oxide semiconductor layer, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor layer where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0052] In response to this problem, an insulator containing oxygen that is desorbed by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor layer, and heat treatment is performed. This supplies oxygen from the insulator to the oxide semiconductor layer, thereby eliminating oxygen vacancies and V O H can be reduced.

[0053] However, if an excessive amount of oxygen is supplied to the channel formation region of the oxide semiconductor layer or its vicinity (for example, the interface between the channel formation region and the gate insulating film), the electrical characteristics may be deteriorated (for example, the transistor may become excessively normally off) or the reliability may be deteriorated. Furthermore, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor may be reduced. Furthermore, variations in the amount of oxygen supplied within the substrate surface may cause variations in the electrical characteristics of the transistor.

[0054] Therefore, in the oxide semiconductor layer, it is preferable that a sufficient amount of oxygen be supplied to a region that functions as a channel formation region and its vicinity, but that an excessive amount of oxygen be prevented from being supplied.

[0055] Therefore, in the semiconductor device described in this embodiment, oxygen is diffused from an insulator containing oxygen that is released by heating into the oxide semiconductor layer, and simultaneously, oxygen is diffused outward from the insulator. This makes it possible to supply sufficient oxygen from the insulator containing oxygen that is released by heating to a region that functions as a channel formation region in the oxide semiconductor layer and its vicinity, while preventing excessive oxygen from being supplied.

[0056] <Configuration example of semiconductor device> A configuration example of a semiconductor device including a transistor 200 will be described with reference to FIGS. 1A to 1D. FIG. 1A is a top view of the semiconductor device. FIGS. 1B to 1D are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 1A, which is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 1A, which is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by a dashed dotted line A5-A6 in FIG. 1A, which is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted from the top view of FIG. 1A for clarity.

[0057] A semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, an insulator 280 over the transistor 200, an insulator 282 (insulator 282a and insulator 282b) over the insulator 280, an insulator 283 over the insulator 282, an insulator 286 over the insulator 283, and an insulator 274 over the sealing portion 265. The insulators 212, 214, 280, 282, 283, 286, and 274 function as interlayer films. The insulator 280 is an insulator containing oxygen that is released by heating and can supply oxygen to the oxide semiconductor layer of the transistor 200. The sealing portion 265 is provided to surround the plurality of transistors 200, the insulators 216, 280, and 282. In the sealing portion 265, the insulator 283 contacts the upper surface of the insulator 214.

[0058] [Aperture area 400] A semiconductor device of one embodiment of the present invention includes a conductor 240a electrically connected to a conductor 242a of a transistor 200 and functioning as a plug, and a conductor 240b electrically connected to a conductor 242b of the transistor 200 and functioning as a plug. An opening region 400a is provided in the insulators 280 and 282 near the conductor 240a functioning as a plug, and similarly, an opening region 400b is provided in the insulators 280 and 282 near the conductor 240b. As shown in FIG. 1B and other drawings, the opening region 400a overlaps with the conductor 242a, and the opening region 400b overlaps with the conductor 242b. An insulator 241a is provided in contact with a side surface of the conductor 240a functioning as a plug, and similarly, an insulator 241b is provided in contact with a side surface of the conductor 240b. Furthermore, a conductor 246a electrically connected to the conductor 240a and functioning as wiring is provided on the insulator 286 and the conductor 240a, and similarly, a conductor 246b electrically connected to the conductor 240b and functioning as wiring is provided on the insulator 286 and the conductor 240b. Furthermore, an insulator 271a is provided in contact with the top surface of the conductor 242a, and an insulator 271b is provided in contact with the top surface of the conductor 242b. Furthermore, an insulator 272 is provided so as to cover the conductors 242a, 242b, insulator 271a, and insulator 271b.

[0059] In the following, the conductors 242a and 242b may be collectively referred to as conductors 242. The conductors 240a and 240b may be collectively referred to as conductors 240. The opening region 400a and opening region 400b may be collectively referred to as opening region 400. The insulators 241a and 241b may be collectively referred to as insulators 241. The conductors 246a and 246b may be collectively referred to as conductors 246. The insulators 271a and 271b may be collectively referred to as insulators 271.

[0060] At least one of the insulators 212, 214, 271, 272, 282, and 283 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, at least one of the insulators 212, 214, 271, 272, 282, and 283 is preferably an insulating material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, it is preferably an insulating material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., through which the above oxygen is less likely to permeate).

[0061] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the term "barrier property" refers to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability). Alternatively, the term "barrier property" refers to a function of capturing and fixing (also referred to as gettering) a corresponding substance. For example, it is preferable to use insulating films that have a high function of suppressing the diffusion of hydrogen as the insulators 212, 272, and 283. It is also preferable to use insulating films that have a high function of capturing and fixing hydrogen as the insulators 214, 271, and 282.

[0062] Here, Fig. 2A shows an enlarged cross-sectional view of the vicinity of the conductor 240 shown in Fig. 1B etc. Fig. 2B shows an enlarged cross-sectional view of the configuration shown in Fig. 2A in a state before the conductor 240 is formed. Note that Figs. 2A and 2B are drawings corresponding to both the conductor 240a and the conductor 240b.

[0063] 2B, insulator 282 has an opening in opening region 400. In addition, insulator 280 may have a groove overlapping the opening of insulator 282 in opening region 400. The depth of the groove in insulator 280 may be at most deep enough to expose the top surface of insulator 272, and may be, for example, approximately ¼ to ½ of the maximum film thickness of insulator 280.

[0064] By performing heat treatment in a state where the opening region 400 is formed and the insulator 280 is exposed through the opening in the insulator 282, oxygen can be supplied to the oxide semiconductor layer of the transistor 200 while some of the oxygen contained in the insulator 280 diffuses outward from the opening region 400. This allows sufficient oxygen to be supplied from the insulator 280 containing oxygen released by heating to a region in the oxide semiconductor layer that functions as a channel formation region and its vicinity, while preventing excessive oxygen from being supplied.

[0065] At this time, hydrogen contained in the insulator 280 can be bonded to oxygen and released to the outside through the opening region 400. The hydrogen bonded to oxygen is released as water. Therefore, the hydrogen contained in the insulator 280 can be reduced, and the hydrogen contained in the insulator 280 can be prevented from entering the oxide semiconductor layer of the transistor 200.

[0066] 1A, the opening regions 400a and 400b are disposed above the conductors 242a and 242b, respectively, and are disposed in a substantially line-symmetrical manner with respect to the gate of the transistor 200. This allows approximately equal amounts of oxygen to be supplied to the oxide semiconductor layer of the transistor 200 from the source side and the drain side. This prevents a large imbalance in the amount of oxygen vacancies between the source side and the drain side in the channel formation region of the transistor 200.

[0067] 2B and other figures, insulator 283 contacts the side surface of insulator 282, the side surface of insulator 280, and the top surface of insulator 280 inside opening region 400. Also, as shown in FIG. 2B, before conductor 240 is formed, a portion of insulator 274 may be formed in opening region 400 so as to fill a recess formed in insulator 283. At this time, as shown in FIG. 2B, the top surface of insulator 274 and the top surface of insulator 283 may roughly coincide.

[0068] As shown in FIG. 2A and other figures, the conductor 240 is disposed so as to penetrate the opening region 400. In other words, the conductor 240 is disposed through the opening of the insulator 282 and is further provided so as to penetrate the bottom of the groove of the insulator 280. As shown in FIG. 2A, if the width of the opening region 400 is not sufficiently larger than the width of the conductor 240, most of the insulator 274 will be removed when forming the opening in which the conductor 240 is to be embedded. In this case, the side surface of the insulator 241 will contact the insulator 283 in the opening region 400.

[0069] In this way, by forming the opening region 400 and the conductor 240 functioning as a plug so as to overlap each other in a top view, the opening region 400 can be provided without significantly increasing the area occupied by the transistor 200. As a result, even in a design in which multiple transistors 200 are densely arranged, the opening region 400 can be provided without changing the arrangement of the transistors 200 to provide extra space. With this configuration, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0070] Although the above describes a configuration in which the insulator 241 is provided in contact with the side surface of the conductor 240, the present invention is not limited to this. For example, as shown in FIG. 2C , a configuration in which the insulator 241 is not provided on the side surface of the conductor 240 may be used. In this case, it is preferable that the amount of impurities such as excess oxygen or hydrogen contained in the insulator 280 is sufficiently reduced. Here, the side surface of the conductor 240 contacts the insulator 283 in the opening region 400 (which may also be referred to as the opening of the insulator 282 and the groove portion of the insulator 280). With this configuration, most of the side surface of the conductor 240 is covered with the insulator 283, and the amount of excess impurities such as oxygen or hydrogen in the insulator 280 is sufficiently reduced, thereby preventing impurities such as oxygen or hydrogen from entering the conductor 240.

[0071] Furthermore, although the above describes a configuration in which insulator 283 is provided in contact with the side surface of insulator 241, the present invention is not limited to this. For example, as shown in FIG. 2D , there is a case in which insulator 274 remains in opening region 400 and contacts the side surface of insulator 241. In this case, the width of opening region 400 (which may also be rephrased as the width of the opening of insulator 282 and the width of the groove portion of insulator 280) is sufficiently larger than the width of conductor 240. By providing opening region 400 in this manner, a sufficient margin can be secured for the opening in which conductor 240 is embedded.

[0072] 1A, the shape of opening region 400a and opening region 400b in top view is substantially square, but the present invention is not limited to this. For example, the shape of opening region 400a and opening region 400b in top view may be rectangular, elliptical, circular, diamond, or a combination thereof. The size of opening region 400a and opening region 400b can be set appropriately depending on the design of the semiconductor device including transistor 200.

[0073] [Transistor 200] As shown in FIGS. 1A to 1D , the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductors 205a, 205b, and 205c) disposed so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 243 (oxides 243a and 243b) on the oxide 230b, a conductor 242a on the oxide 243a, and an insulator 271 on the conductor 242a. a, a conductor 242b on the oxide 243b, an insulator 271b on the conductor 242b, an insulator 250a on the oxide 230b, an insulator 250b on the insulator 250a, a conductor 260 (conductor 260a and conductor 260b) located on the insulator 250b and overlapping with a portion of the oxide 230b, and an insulator 272 arranged to cover the insulator 224, the oxide 230 (oxide 230a and oxide 230b), the oxide 243, the conductor 242 (conductor 242a and conductor 242b), and the insulator 271 (insulator 271a and insulator 271b). Here, as shown in FIGS. 1B to 1D , the insulator 272 has a region in contact with a portion of the upper surface of the insulator 222. The upper surface of the conductor 260 is disposed so as to substantially coincide with the uppermost surface of the insulator 250 and the upper surface of the insulator 280. The insulator 282 contacts the upper surfaces of the conductor 260, the insulator 250, and the insulator 280.

[0074] In the following, the oxide 230a and the oxide 230b may be collectively referred to as the oxide 230. Furthermore, the insulator 250a and the insulator 250b may be collectively referred to as the insulator 250.

[0075] Openings that reach the oxide 230b are provided in the insulator 280 and the insulator 272. The insulator 250 and the conductor 260 are disposed in the openings. In addition, in the channel length direction of the transistor 200, the conductor 260 and the insulator 250 are provided between the insulator 271a, the conductor 242a, and the oxide 243a and the insulator 271b, the conductor 242b, and the oxide 243b. The insulator 250 contacts the side surface and the bottom surface of the conductor 260.

[0076] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulator 250 functions as a first gate insulating film, and the insulators 222 and 224 function as second gate insulating films. The conductor 242a functions as one of a source electrode and a drain electrode, and the conductor 242b functions as the other of the source electrode and the drain electrode. At least a part of a region of the oxide 230 overlapping with the conductor 260 functions as a channel formation region.

[0077] In the transistor 200, the oxide 230 including the channel formation region (the oxide 230a and the oxide 230b) is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0078] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0079] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 230. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230.

[0080] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.

[0081] In this way, by disposing the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a into the oxide 230b.

[0082] Furthermore, since the oxide 230a and the oxide 230b have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced. Because the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced, the effect of interface scattering on carrier conduction is reduced, and a high on-current can be obtained.

[0083] The oxide 230b preferably has crystallinity, and it is particularly preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b.

[0084] CAAC-OS has a highly crystalline and dense structure and is free of impurities or defects (e.g., oxygen vacancies (V O) and the like. In particular, by subjecting the formed metal oxide to heat treatment at a temperature (e.g., 400°C or higher and 600°C or lower) at which the metal oxide does not polycrystallize, the CAAC-OS can be made to have a dense structure with higher crystallinity. In this way, the density of the CAAC-OS can be increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0085] On the other hand, since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0086] Furthermore, crystalline oxides such as CAAC-OS have few impurities or defects (such as oxygen vacancies) and a dense structure with high crystallinity, which can suppress the extraction of oxygen from the oxide 230b by the source or drain electrode. This reduces the extraction of oxygen from the oxide 230b even during heat treatment, making the transistor 200 stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0087] Next, FIG. 3 shows an enlarged view of the vicinity of the channel formation region in FIG. 1B. As shown in FIG. 3, the oxide 230b has a region 230bc that functions as a channel formation region of the transistor 200, and regions 230ba and 230bb that are provided on either side of the region 230bc and function as source and drain regions. The region 230bc at least partially overlaps with the conductor 260. In other words, the region 230bc is provided in a region between the conductor 242a and the conductor 242b. The region 230ba is provided overlapping with the conductor 242a, and the region 230bb is provided overlapping with the conductor 242b.

[0088] The region 230bc, which functions as a channel formation region, has fewer oxygen vacancies or a lower impurity concentration than the regions 230ba and 230bb, and is therefore a high-resistance region with a low carrier concentration. The regions 230ba and 230bb, which function as a source region or drain region, have many oxygen vacancies or high impurity concentrations such as hydrogen, nitrogen, or metal elements, which increases the carrier concentration and reduces the resistance. In other words, the regions 230ba and 230bb have a higher carrier concentration and lower resistance than the region 230bc.

[0089] Here, the carrier concentration of the region 230bc that functions as a channel forming region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 230bc that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0090] In this embodiment, as described above, it is possible to supply sufficient oxygen to the region 230bc and its vicinity from the insulator 280 containing oxygen that is desorbed by heating, without supplying an excessive amount of oxygen. At this time, it is also possible to suppress the incorporation of hydrogen into the region 230bc. As a result, oxygen vacancies and V O By removing H, the region 230bc can be made i-type or substantially i-type. This can suppress fluctuations in the electrical characteristics of the transistor 200 and improve reliability. Furthermore, it can suppress variations in the electrical characteristics of the transistor 200 within the substrate plane.

[0091] By adopting the above-described structure, it is possible to provide a semiconductor device having good electrical characteristics, high reliability, and little variation in transistor characteristics.

[0092] Furthermore, a region having a carrier concentration equal to or lower than that of regions 230ba and 230bb and equal to or higher than that of region 230bc may be formed between region 230bc and regions 230ba or 230bb. That is, this region functions as a junction region between region 230bc and regions 230ba or 230bb. The junction region may have a hydrogen concentration equal to or lower than that of regions 230ba and 230bb and equal to or higher than that of region 230bc. The junction region may also have oxygen vacancies equal to or lower than those of regions 230ba and 230bb and equal to or higher than those of region 230bc.

[0093] 3 shows an example in which the regions 230ba, 230bb, and 230bc are formed in the oxide 230b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 230b but also in the oxide 230a.

[0094] Furthermore, it may be difficult to clearly detect the boundaries between regions in the oxide 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in regions closer to the channel formation region.

[0095] Furthermore, as shown in FIG. 3 , in a cross-sectional view of the transistor in the channel length direction, a groove may be formed in a region of the oxide 230b that overlaps with the insulator 250, and a portion of the insulator 250 may be embedded in the groove. In this case, the insulator 250 is formed in contact with the sidewalls and bottom surface of the groove. In this case, the thickness of the insulator 250 is preferably approximately the same as the depth of the groove. With this configuration, even if a damaged region is formed on the surface of the oxide 230b at the bottom of the opening when forming an opening for embedding a conductor 260 or the like, the damaged region can be removed. This can suppress poor electrical characteristics of the transistor 200 due to the damaged region.

[0096] 3 and other figures, the side of the opening into which the conductor 260 and the like are embedded, including the groove in the oxide 230b, is approximately perpendicular to the surface on which the oxide 230b is to be formed, but this embodiment is not limited to this. For example, the bottom of the opening may be gently curved, i.e., U-shaped. Also, for example, the side of the opening may be inclined relative to the surface on which the oxide 230b is to be formed.

[0097] 1C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (also referred to as rounded).

[0098] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape can improve the coverage of the oxide 230b with the insulator 250 and the conductor 260.

[0099] The oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the metal element that is the main component is preferably larger than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.

[0100] Here, the conduction band minimum changes gradually at the junction between the oxide 230a and the oxide 230b. In other words, the conduction band minimum at the junction between the oxide 230a and the oxide 230b changes continuously or can be said to be a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b.

[0101] Specifically, when the oxide 230a and the oxide 230b contain a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 230b is an In-M-Zn oxide, the oxide 230a may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0102] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. The oxide 230b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition, or an atomic ratio of In:M:Zn=5:1:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M.

[0103] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0104] By configuring the oxide 230a and the oxide 230b as described above, the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced, which reduces the influence of interface scattering on carrier conduction, and the transistor 200 can achieve a large on-state current and high frequency characteristics.

[0105] Note that, in the transistor 200, the oxide 230 has a two-layer structure of the oxide 230a and the oxide 230b, but the present invention is not limited to this. For example, the oxide 230 may have a single layer or a stacked structure of three or more layers. Furthermore, each of the oxide 230a and the oxide 230b may have a stacked structure. Furthermore, when the oxide 230 has a stacked structure of three or more layers, part of the stacked structure of the oxide 230 may be formed in the openings formed in the insulators 280 and 272, as in the case of the insulator 250.

[0106] For the insulators 212, 214, 271, 272, 282, and 283, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has a high hydrogen barrier property, for the insulators 212, 272, and 283. Furthermore, it is preferable to use aluminum oxide or magnesium oxide, which has a high hydrogen capture and fixation function, for the insulators 214, 271, and 282. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulators 212 and 214. Alternatively, it can suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film disposed outside the insulator 283 to the transistor 200 side. Alternatively, oxygen contained in the insulator 224 or the like can be prevented from diffusing toward the substrate through the insulator 212 and the insulator 214. Alternatively, oxygen contained in the insulator 280 or the like can be prevented from diffusing upward from the transistor 200 through the insulator 282 or the like. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 271, 272, 282, and 283, which have the function of preventing the diffusion of impurities such as water and hydrogen, and oxygen.

[0107] Here, oxides having an amorphous structure may be used as the insulators 212, 214, 271, 272, 282, and 283. In particular, it is preferable to use oxides having an amorphous structure as the insulators 214, 271, and 282. For example, AlO x (x is any number greater than 0), or MgO yIt is preferable to use a metal oxide such as y (where y is any number greater than 0). In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, hydrogen contained in the transistor 200 or hydrogen present around the transistor 200 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, a highly reliable transistor 200 and a semiconductor device can be manufactured that have excellent characteristics.

[0108] Furthermore, the insulators 212, 214, 271, 272, 282, and 283 may be made of oxides having an amorphous structure, or may have a polycrystalline structure region formed in part. Furthermore, the insulators 212, 214, 271, 272, 282, and 283 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0109] The insulators 212, 214, 216, 271, 272, 280, 282, 283, and 286 may be deposited by, for example, sputtering. Sputtering does not require the use of hydrogen as a deposition gas, and therefore can reduce the hydrogen concentration of the insulators 212, 214, 216, 271, 272, 280, 282, 283, and 286. Note that the deposition method is not limited to sputtering, and other methods such as chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and atomic layer deposition (ALD) may also be used as appropriate.

[0110] It may also be preferable to reduce the resistivity of the insulators 212 and 283. For example, it is preferable to reduce the resistivity of the insulators 212 and 283 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulator 212 and the insulator 283 may be able to reduce charge-up of the conductor 205, the conductor 242, the conductor 260, or the conductor 246 during treatment using plasma or the like in a semiconductor device manufacturing process. The resistivity of the insulator 212 and the insulator 283 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0111] Furthermore, the insulators 216, 274, 280, and 286 preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like can be used as the insulators 216, 274, 280, and 286 as appropriate.

[0112] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. Note that a portion of the conductor 205 may be embedded in the insulator 214.

[0113] The conductor 205 includes conductor 205a, conductor 205b, and conductor 205c. The conductor 205a is provided in contact with the bottom surface and sidewall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the top surface of the conductor 205b is lower than the top surface of the conductor 205a and the top surface of the insulator 216. The conductor 205c is provided in contact with the top surface of the conductor 205b and the side surface of the conductor 205a. Here, the height of the top surface of the conductor 205c is approximately the same as the height of the top of the conductor 205a and the height of the top surface of the insulator 216. In other words, the conductor 205b is configured to be enclosed by the conductors 205a and 205c.

[0114] Here, the conductors 205a and 205c are preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0115] By using a conductive material that reduces hydrogen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 224 or the like. Furthermore, by using a conductive material that suppresses oxygen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials that suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 205a may be made of titanium nitride.

[0116] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0117] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V compared to not applying a negative potential to the conductor 205.

[0118] The electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of the impurities into the oxide 230.

[0119] As shown in FIG. 1A, the conductor 205 is preferably larger than the area of ​​the oxide 230 that does not overlap with the conductors 242a and 242b. In particular, as shown in FIG. 1C, the conductor 205 preferably extends to areas outside the channel width direction ends of the oxide 230a and the oxide 230b. That is, outside the side surfaces of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator. This structure allows the channel formation region of the oxide 230 to be electrically surrounded by the electric field of the conductor 260, which functions as the first gate electrode, and the electric field of the conductor 205, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0120] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0121] 1C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Furthermore, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0122] Note that, in the transistor 200, the conductor 205 has a stacked structure of conductors 205a, 205b, and 205c, but the present invention is not limited to this. For example, the conductor 205 may have a single-layer, two-layer, or four or more-layer stacked structure. For example, the conductor 205 may have a two-layer structure of conductors 205a and 205b.

[0123] Insulator 222 and insulator 224 function as gate insulators.

[0124] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0125] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 to the substrate and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 can be prevented from reacting with oxygen contained in the insulator 224 or the oxide 230.

[0126] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0127] The insulator 222 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0128] The insulator 224 in contact with the oxide 230 may be made of, for example, silicon oxide or silicon oxynitride, as appropriate. The insulator 224 is preferably processed into an island shape so as to overlap with the oxide 230a. In this case, the insulator 272 is configured to contact the side surface of the insulator 224 and the top surface of the insulator 222. This configuration significantly reduces the volume of the insulator 224, and the insulator 224 and the insulator 280 can be separated by the insulator 272. Therefore, oxygen contained in the insulator 280 diffuses into the insulator 224, preventing excessive oxygen in the insulator 224.

[0129] The insulators 222 and 224 may have a stacked structure of two or more layers. In this case, the stacked structures are not limited to those made of the same material, and may be stacked structures made of different materials. While FIG. 1B and other figures show a configuration in which the insulator 224 is formed in an island shape by overlapping with the oxide 230a, the present invention is not limited to this. As long as the amount of oxygen contained in the insulator 224 can be appropriately adjusted, the insulator 224 may be configured without being patterned, similar to the insulator 222.

[0130] An oxide 243a and an oxide 243b are provided on the oxide 230b. The oxide 243a and the oxide 243b are provided to be spaced apart with the conductor 260 interposed therebetween.

[0131] The oxide 243 (oxide 243a and oxide 243b) preferably has a function of suppressing oxygen permeation. By disposing the oxide 243, which has a function of suppressing oxygen permeation, between the conductor 242 functioning as a source or drain electrode and the oxide 230b, the electrical resistance between the conductor 242 and the oxide 230b is reduced, which is preferable. This structure can improve the electrical characteristics and reliability of the transistor 200. Note that if the electrical resistance between the conductor 242 and the oxide 230b can be sufficiently reduced, the oxide 243 may not be provided.

[0132] A metal oxide containing element M may be used as oxide 243. In particular, aluminum, gallium, yttrium, or tin may be used as element M. Preferably, oxide 243 has a higher concentration of element M than oxide 230b. Alternatively, gallium oxide may be used as oxide 243. Alternatively, a metal oxide such as In-M-Zn oxide may be used as oxide 243. Specifically, the atomic ratio of element M to In in the metal oxide used for oxide 243 is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. Furthermore, the film thickness of oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. Furthermore, oxide 243 preferably has crystallinity. When oxide 243 has crystallinity, oxygen release from oxide 230 can be effectively suppressed. For example, oxide 243 with a hexagonal or other crystal structure may be able to suppress oxygen release from oxide 230.

[0133] The conductor 242a is preferably provided in contact with the top surface of the oxide 243a, and the conductor 242b is preferably provided in contact with the top surface of the oxide 243b. The conductor 242a and the conductor 242b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0134] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when they absorb oxygen.

[0135] Note that hydrogen contained in the oxide 230b and the like may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b and the like is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b and the like may be absorbed by the conductor 242a or the conductor 242b.

[0136] Preferably, no curved surface is formed between the side surface of the conductor 242 and the top surface of the conductor 242. The conductor 242 having no curved surface can increase the cross-sectional area of ​​the conductor 242 in the cross section in the channel width direction. This increases the conductivity of the conductor 242 and the on-state current of the transistor 200.

[0137] The insulator 271a is provided in contact with the top surface of the conductor 242a, and the insulator 271b is provided in contact with the top surface of the conductor 242b. Preferably, the top surface of the insulator 271a is in contact with the insulator 272 and a side surface of the insulator 271a is in contact with the insulator 250. Preferably, the top surface of the insulator 271b is in contact with the insulator 272 and a side surface of the insulator 271b is in contact with the insulator 250. The insulator 271 preferably functions as a barrier insulating film against at least oxygen. Therefore, the insulator 271 preferably has a function of suppressing oxygen diffusion. For example, the insulator 271 preferably has a function of suppressing oxygen diffusion more than the insulator 280. For example, a nitride containing silicon, such as silicon nitride, may be used as the insulator 271. Preferably, the insulator 271 has a function of capturing impurities such as hydrogen. In this case, an insulator such as a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide, may be used as the insulator 271. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 271 is preferable because hydrogen can be captured or fixed more effectively. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with favorable characteristics.

[0138] The insulator 272 is provided to cover the insulator 224, the oxide 230a, the oxide 230b, the oxide 243, the conductor 242, and the insulator 271. It is preferable that the insulator 272 has a function of further suppressing the diffusion of hydrogen. In this case, it is preferable that the insulator 272 includes an insulator such as silicon nitride. Alternatively, the insulator 272 may have a function of capturing and fixing hydrogen. In this case, it is preferable that the insulator 272 includes an insulator such as a metal oxide having an amorphous structure, for example, aluminum oxide or magnesium oxide.

[0139] The insulator 272 may have a stacked layer structure. For example, the insulator 272 may have a stacked layer structure of aluminum oxide and silicon nitride formed over the aluminum oxide. Such a stacked layer structure is preferable because it can improve the barrier property more than a single layer of aluminum oxide or a single layer of silicon nitride.

[0140] By providing the insulators 271 and 272 as described above, the conductor 242 can be wrapped in an insulator that has a barrier property against oxygen. That is, it is possible to prevent oxygen contained in the insulators 224 and 280 from diffusing into the conductor 242. This makes it possible to suppress the conductor 242 from being directly oxidized by the oxygen contained in the insulators 224 and 280, which would increase the resistivity and reduce the on-current.

[0141] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230b. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. Note that the insulator 250 preferably has a low carbon content in the film.

[0142] However, one embodiment of the present invention is not limited to this, and carbon may be contained in the film of the insulator 250. For example, the carbon concentration of the insulator 250 is preferably 1×10 18 atoms / cm 3 5x10 or more 20 atoms / cm 3 Less than or equal to 5×10 18 atoms / cm 3 More than 1×10 20 atoms / cm 3 The carbon concentration in the film of the insulator 250 can be measured by SIMS analysis or the like.

[0143] The insulator 250 preferably has a reduced concentration of impurities such as water and hydrogen, similar to the insulator 224. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0144] 1B and 1C, when the insulator 250 has a two-layer laminated structure, it is preferable that the lower insulator 250a be formed using an insulator that is easily permeable to oxygen, and the upper insulator 250b be formed using an insulator that has the function of suppressing oxygen diffusion. This configuration can suppress the diffusion of oxygen contained in the insulator 250a into the conductor 260. In other words, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. For example, the insulator 250a may be formed using a material that can be used for the insulator 250 described above, and the insulator 250b may be formed using an insulator containing one or both of aluminum and hafnium oxides. It is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like as the insulator. The thickness of the insulator 250b is 0.5 nm or more and 3.0 nm or less, and preferably 1.0 nm or more and 1.5 nm or less.

[0145] When silicon oxide or silicon oxynitride is used for the lower layer of the insulator 250, the upper layer of the insulator 250 may be made of an insulating material, such as a high-k material with a high dielectric constant. By forming the gate insulator into a layered structure of the insulator 250a and the insulator 250b, a layered structure that is stable against heat and has a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced.

[0146] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0147] The metal oxide may function as part of the first gate electrode. For example, the metal oxide that can be used as the oxide 230 may be used as the metal oxide. In this case, the electrical conductor 260a may be formed by sputtering to reduce the electrical resistance of the metal oxide, thereby making it a conductor. This may be called an OC (Oxide Conductor) electrode.

[0148] The inclusion of the metal oxide can improve the on-state current of the transistor 200 without weakening the influence of the electric field from the conductor 260. Furthermore, the physical thickness of the insulator 250 and the metal oxide can maintain a distance between the conductor 260 and the oxide 230, thereby suppressing leakage current between the conductor 260 and the oxide 230. Furthermore, the provision of a stacked structure of the insulator 250 and the metal oxide can easily and appropriately adjust the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230.

[0149] The conductor 260 functions as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in FIGS. 1B and 1C, the top surface of the conductor 260 is substantially flush with the top surface of the insulator 250. Although the conductor 260 is shown in FIGS. 1B and 1C as having a two-layer structure of the conductor 260a and the conductor 260b, it may have a single-layer structure or a stacked structure of three or more layers.

[0150] The conductor 260a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0151] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0152] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0153] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably placed in the region between the conductor 242a and the conductor 242b without alignment.

[0154] 1C , in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b, relative to the bottom surface of the insulator 222. The conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, making it easier for the electric field of the conductor 260 to act on the entire channel formation region of the oxide 230b. This increases the on-state current of the transistor 200 and improves its frequency characteristics. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxides 230a and 230b do not overlap with the conductor 260, relative to the bottom surface of the insulator 222, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0155] The insulator 280 is provided on the insulator 272, and has openings formed in the regions where the insulator 250 and the conductor 260 are to be provided. The top surface of the insulator 280 may be flattened.

[0156] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce the parasitic capacitance that occurs between wirings. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is released by heating.

[0157] It is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 280. Therefore, for example, the insulator 280 may be made of an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate.

[0158] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280 and preferably has a function of capturing impurities such as hydrogen. The insulator 282 also preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 282 may be an insulator made of a metal oxide having an amorphous structure, such as aluminum oxide. By providing the insulator 282, which is in contact with the insulator 280 and has a function of capturing impurities such as hydrogen, in the region sandwiched between the insulator 212 and the insulator 283, the insulator 282 can capture impurities such as hydrogen contained in the insulator 280 and maintain a constant amount of hydrogen in the region. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 282 is preferable because it may be able to capture or fix hydrogen more effectively. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with excellent characteristics.

[0159] The insulator 282a and the insulator 282b on the insulator 282a can be deposited by sputtering in an oxygen-containing atmosphere, which allows oxygen to be added to the insulator 280. It is preferable that the amount of oxygen added to the insulator 282a is less than that of the insulator 282b. For example, the RF power used to deposit the insulator 282a can be set lower than the RF power used to deposit the insulator 282b. This prevents excessive oxygen from being added to the insulator 280. Note that it may be difficult to clearly detect the boundary between the insulator 282a and the insulator 282b in the insulator 282.

[0160] Although the above describes an example in which the insulator 282 has a layered structure of the insulator 282a and the insulator 282b, the present invention is not limited to this. If the amount of oxygen added to the insulator 280 can be suitably adjusted, a configuration in which only either the insulator 282a or the insulator 282b is provided may be used.

[0161] The insulator 283 functions as a barrier insulating film that prevents impurities such as water and hydrogen from diffusing from above into the insulator 280. The insulator 283 is disposed on the insulator 282. The insulator 283 is preferably a nitride containing silicon, such as silicon nitride or silicon nitride oxide. For example, the insulator 283 may be formed using silicon nitride deposited by a sputtering method. By depositing the insulator 283 by a sputtering method, a silicon nitride film that is high in density and less likely to form voids can be formed. Alternatively, the insulator 283 may be formed by stacking a silicon nitride film deposited by an ALD method on a silicon nitride film deposited by a sputtering method. This structure is preferable because even if defects, such as voids, occur in the silicon nitride film deposited by the sputtering method, the voids can be filled by the silicon nitride film deposited by the ALD method, which has good coverage, thereby improving sealing performance.

[0162] The insulator 286 is provided on the insulator 283 and the insulator 274. Note that the region of the insulator 286 that overlaps with the conductor 246 may have a higher upper surface height than other regions of the insulator 286.

[0163] Insulator 241a is provided in contact with the inner wall of an opening formed in insulator 280, insulator 283, and insulator 286, in which conductor 240a is embedded, a first conductor of conductor 240a is provided in contact with the side surface of insulator 241a, and a second conductor of conductor 240a is provided further inward. Also, insulator 241b is provided in contact with the inner wall of an opening formed in insulator 280, insulator 283, and insulator 286, in which conductor 240b is embedded, a first conductor of conductor 240b is provided in contact with the side surface of insulator 241b, and a second conductor of conductor 240b is provided further inward. Here, it is preferable that conductors 240a, conductor 240b, insulator 241a, and insulator 241b are not in contact with insulator 282. Furthermore, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 286 in the area overlapping with the conductor 246 can be made approximately the same.

[0164] Although the above describes a configuration in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may be configured as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, ordinal numbers may be assigned to indicate the order of formation to distinguish them.

[0165] The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the second conductors of the conductors 240a and 240b may be made of a conductive material containing tungsten, copper, or aluminum as a main component.

[0166] Furthermore, it is preferable to use a conductive material for the first conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a multilayer structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 283 from being mixed into the oxide 230 through the conductor 240a and the conductor 240b.

[0167] 1A, the conductors 240a and 240b have a circular shape when viewed from above, but this is not limiting. For example, the conductors 240a and 240b may have a substantially circular shape such as an oval, a polygonal shape such as a square, or a polygonal shape such as a square with rounded corners when viewed from above.

[0168] The insulators 241a and 241b may be made of, for example, silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 241 may also have a layered structure. For example, a silicon nitride layer may be provided in contact with the conductor 240, and an aluminum oxide layer may be provided outside the silicon nitride layer. The insulators 241a and 241b are provided in contact with the insulators 286, 283, 280, 272, and 271, which can prevent impurities such as water and hydrogen contained in the insulator 280 from entering the oxide 230 through the conductors 240a and 240b. Silicon nitride is particularly suitable because of its high barrier properties against hydrogen. Furthermore, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a and 240b.

[0169] Conductors 246 (conductors 246a and 246b) may be disposed in contact with the upper surfaces of the conductors 240a and 240b, functioning as wiring. Conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as its main component. The conductor may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0170] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0171] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride and a metal oxide. Examples of other substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0172] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0173] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0174] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0175] Insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide with voids, and resin.

[0176] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0177] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0178] <<Conductors>> The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0179] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0180] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0181] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0182] <<Metal oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as the oxide 230. Hereinafter, metal oxides that can be used as the oxide 230 and the oxide 243 according to the present invention will be described.

[0183] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0184] Here, we consider a case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, there are cases where a combination of the aforementioned elements can be used as element M.

[0185] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0186] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be explained using Fig. 4A. Fig. 4A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0187] As shown in FIG. 4A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0188] The structure within the bold frame in Figure 4A is an intermediate state between "amorphous" and "crystal," and is a structure that belongs to a new boundary region (new crystalline phase). In other words, this structure can be described as a structure that is completely different from the energetically unstable "amorphous" or "crystal."

[0189] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 4B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by GIXD measurement shown in Figure 4B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 4B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 4B is 500 nm.

[0190] As shown in Figure 4B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Furthermore, as shown in Figure 4B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity is detected.

[0191] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). Figure 4C shows the diffraction pattern of a CAAC-IGZO film. Figure 4C shows a diffraction pattern observed using NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 4C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0192] As shown in Figure 4C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0193] <<Structure of oxide semiconductor>> Note that oxide semiconductors may be classified differently from that shown in FIG. 4A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0194] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0195] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0196] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0197] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0198] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0199] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0200] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction or the change in interatomic bond distance caused by metal atom substitution.

[0201] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0202] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, because the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the generation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budgets) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0203] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0204] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0205] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0206] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0207] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (also called a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0208] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0209] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0210] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0211] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0212] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0213] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0214] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0215] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0216] For the channel formation region of the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0217] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0218] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0219] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0220] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0221] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon at and near the interface between the insulator and the channel formation region of the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0222] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0223] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably17 atoms / cm 3 Do the following:

[0224] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0225] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0226] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 230 is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the oxide 230. For example, it is preferable to use a semiconductor of a simple element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also called an atomic layer material or a two-dimensional material). In particular, it is preferable to use a layered material that functions as a semiconductor.

[0227] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0228] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0229] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0230] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device illustrated in FIGS. 1A to 1D, which is one embodiment of the present invention, will be described with reference to FIGS. 5A to 24D.

[0231] 5A to 24D, A in each figure represents a top view. B in each figure represents a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in A of each figure, and is also a cross-sectional view in the channel length direction of the transistor 200. C in each figure represents a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in A of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. D in each figure represents a cross-sectional view corresponding to the portion indicated by the dashed dotted line A5-A6 in A of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. Note that some elements are omitted from the top view in A of each figure for clarity.

[0232] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or oxide materials for forming oxides can be formed as films using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate.

[0233] There are three types of sputtering methods: RF sputtering, which uses a high-frequency power supply for sputtering; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0234] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0235] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0236] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a plasma enhanced ALD method in which a plasma excited reactant is used, or the like can be used.

[0237] Furthermore, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, enabling the formation of ultrathin films, films with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. The PEALD method utilizes plasma, which can be preferable because it allows film formation at lower temperatures. Note that some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by the ALD method may contain higher amounts of impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0238] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0239] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0240] First, a substrate (not shown) is prepared, and the insulator 212 is formed on the substrate (see FIGS. 5A to 5D). The insulator 212 is preferably formed by sputtering. By using sputtering, which does not require the use of hydrogen as a deposition gas, the hydrogen concentration in the insulator 212 can be reduced. However, the method for forming the insulator 212 is not limited to sputtering, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0241] In this embodiment, a silicon nitride film is formed as the insulator 212 by pulsed DC sputtering using a silicon target in an atmosphere containing nitrogen gas. By using pulsed DC sputtering, particle generation due to arcing on the target surface can be suppressed, resulting in a more uniform film thickness distribution. Furthermore, by using a pulsed voltage, the rise and fall of the discharge can be made steeper than with a high-frequency voltage. This allows for more efficient supply of power to the electrodes, improving the sputtering rate and film quality.

[0242] By using an insulator that is impermeable to impurities such as water and hydrogen, such as silicon nitride, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in layers below the insulator 212. Furthermore, by using an insulator that is impermeable to copper, such as silicon nitride, as the insulator 212, even if a metal that easily diffuses, such as copper, is used for a conductor in a layer (not shown) below the insulator 212, it is possible to suppress the upward diffusion of the metal through the insulator 212.

[0243] Next, the insulator 214 is deposited on the insulator 212 (see FIGS. 5A to 5D). The insulator 214 is preferably deposited by sputtering. By using sputtering, which does not require the use of hydrogen as a deposition gas, the hydrogen concentration in the insulator 214 can be reduced. However, the deposition of the insulator 214 is not limited to sputtering, and CVD, MBE, PLD, ALD, or the like may also be used as appropriate.

[0244] In this embodiment, an aluminum oxide film is formed as the insulator 214 by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen implanted into the layer below the insulator 214 can be controlled by the magnitude of the RF power applied to the substrate. The RF power is set to 0 W / cm. 2Over 1.86W / cm 2 The following is true. In other words, the amount of oxygen suitable for the transistor characteristics can be changed and implanted by adjusting the RF power used when forming the insulator 214. Therefore, an amount of oxygen suitable for improving the reliability of the transistor can be implanted. Furthermore, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0245] It is preferable to use a metal oxide having an amorphous structure, such as aluminum oxide, which has a high ability to capture and fix hydrogen, as the insulator 214. This allows hydrogen contained in the insulator 216 to be captured or fixed and prevents the hydrogen from diffusing into the oxide 230. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 214 is preferable because it may be possible to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with favorable characteristics.

[0246] Next, the insulator 216 is deposited on the insulator 214 (see FIGS. 5A to 5D). The insulator 216 is preferably deposited by sputtering. By using sputtering, which does not require the use of hydrogen as a deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to sputtering, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0247] In this embodiment, a silicon oxide film is formed by pulse DC sputtering using a silicon target in an atmosphere containing oxygen gas as the insulator 216. By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0248] The insulators 212, 214, and 216 are preferably successively deposited without exposure to the atmosphere. For example, a multi-chamber deposition apparatus can be used. This allows the insulators 212, 214, and 216 to be deposited with reduced hydrogen content and also reduces the amount of hydrogen mixed into the films between deposition steps.

[0249] Next, an opening is formed in the insulator 216, reaching the insulator 214 (see FIGS. 5A to 5D). The opening may be, for example, a groove or a slit. The region where the opening is formed may also be referred to as an opening. The opening may be formed by wet etching, but dry etching is preferable for fine processing. A dry etching apparatus, described below, can be used for dry etching. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form the groove. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, silicon nitride, aluminum oxide, or hafnium oxide may be used for the insulator 214. Note that a recess may be formed in the insulator 214, overlapping the opening in the insulator 216.

[0250] After the openings are formed, a conductive film 205A is formed (see FIGS. 5A to 5D). The conductive film 205A preferably includes a conductor that suppresses oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film 205A may be a stacked film of a conductor that suppresses oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film 205A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0251] In this embodiment, titanium nitride is formed as the conductive film 205A. By using such a metal nitride as the lower layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 216 or the like. Furthermore, even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0252] Next, a conductive film 205B is formed (see FIGS. 5A to 5D). The conductive film 205B can be formed using tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as the conductive film 205B.

[0253] Next, CMP processing is performed to remove parts of the conductive film 205A and the conductive film 205B, thereby exposing the insulator 216 (see FIGS. 6A to 6D). As a result, the conductors 205a and 205b remain only in the openings. Note that the CMP processing may remove part of the insulator 216.

[0254] Next, etching is performed to remove the upper portion of the conductor 205b (see FIGS. 7A to 7D). As a result, the upper surface of the conductor 205b becomes lower than the upper surfaces of the conductor 205a and the insulator 216. The conductor 205b can be etched by dry etching or wet etching, but dry etching is preferable for fine processing.

[0255] Next, the conductive film 205C is formed over the insulator 216, the conductor 205a, and the conductor 205b (see FIGS. 8A to 8D). The conductive film 205C preferably includes a conductor that has a function of suppressing oxygen permeation, similar to the conductive film 205A.

[0256] In this embodiment, titanium nitride is formed as the conductive film 205C. By using such a metal nitride as the upper layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 222 or the like. Furthermore, even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205c.

[0257] Next, a portion of the conductive film 205C is removed by CMP processing, exposing the insulator 216 (see FIGS. 9A to 9D). As a result, the conductors 205a, 205b, and 205c remain only in the openings. This allows the formation of a conductor 205 with a flat upper surface. Furthermore, the conductor 205b is surrounded by the conductors 205a and 205c. This prevents impurities such as hydrogen from the conductor 205b from diffusing out of the conductors 205a and 205c, and also prevents oxygen from entering the conductors 205a and 205c and oxidizing the conductor 205b. Note that the CMP processing may remove a portion of the insulator 216.

[0258] Next, the insulator 222 is formed over the insulator 216 and the conductor 205 (see FIGS. 10A to 10D). The insulator 222 may be an insulator containing one or both of aluminum and hafnium oxides. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing one or both of aluminum and hafnium oxides. An insulator containing one or both of aluminum and hafnium oxides has barrier properties against oxygen, hydrogen, and water. The insulator 222 having barrier properties against hydrogen and water can prevent hydrogen and water contained in structures provided around the transistor 200 from diffusing into the inside of the transistor 200 through the insulator 222, thereby preventing oxygen vacancies from being generated in the oxide 230.

[0259] The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. In this embodiment, hafnium oxide is formed as the insulator 222 by an ALD method.

[0260] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment may be performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by another heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0261] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the insulator 222 as much as possible.

[0262] In this embodiment, after the insulator 222 is formed, heat treatment is performed at 400° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas set to 4 slm:1 slm. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. When an oxide containing hafnium is used as the insulator 222, the heat treatment may cause part of the insulator 222 to crystallize. The heat treatment can also be performed at a timing such as after the insulator 224 is formed.

[0263] Next, the insulator 224 is deposited on the insulator 222 (see FIGS. 10A to 10D). The insulator 224 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is deposited as the insulator 224 by a sputtering method. By using a sputtering method that does not require the use of hydrogen as a deposition gas, the hydrogen concentration in the insulator 224 can be reduced. Because the insulator 224 will come into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration be reduced in this manner.

[0264] Next, oxide films 230A and 230B are sequentially formed on insulator 224 (see FIGS. 10A to 10D). Note that oxide films 230A and 230B are preferably formed successively without being exposed to the atmospheric environment. By forming the films without being exposed to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to oxide films 230A and 230B, and it is possible to keep the vicinity of the interface between oxide films 230A and 230B clean.

[0265] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0266] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0267] In particular, during the deposition of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0268] When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by forming the oxide film while heating the substrate.

[0269] In this embodiment, oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. Oxide film 230B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. Each oxide film can be formed according to the desired characteristics of oxide 230a and oxide 230b by appropriately selecting the film formation conditions and atomic ratio.

[0270] Next, an oxide film 243A is formed on the oxide film 230B (see FIGS. 10A to 10D). The oxide film 243A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The atomic ratio of Ga to In in the oxide film 243A is preferably greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 243A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0271] It is preferable to form the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A by sputtering without exposing them to the atmosphere. For example, a multi-chamber film formation apparatus may be used. This allows the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A to be formed with reduced hydrogen content, and further reduces the incorporation of hydrogen into the films between film formation steps.

[0272] Next, it is preferable to perform a heat treatment. The heat treatment may be performed within a temperature range in which the oxide film 230A, the oxide film 230B, and the oxide film 243A do not become polycrystallized, and may be performed at a temperature of 250°C to 650°C, preferably 400°C to 600°C. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be about 20%. This supplies oxygen to the oxide 230, thereby eliminating oxygen deficiencies (V O The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in an atmosphere of nitrogen gas or an inert gas in order to compensate for the desorbed oxygen.

[0273] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the moisture content of the gas used in the heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and other substances from being absorbed into oxide film 230A, oxide film 230B, oxide film 243A, and the like as much as possible.

[0274] In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 400°C for one hour, followed by another heat treatment in an oxygen atmosphere at 400°C for one hour. This heat treatment can remove impurities such as water and hydrogen from the oxide film 230A, the oxide film 230B, and the oxide film 243A. Furthermore, this heat treatment can improve the crystallinity of the oxide film 230B, resulting in a denser, more compact structure. This reduces the diffusion of oxygen or impurities in the oxide film 230B.

[0275] In this way, by performing the oxygen addition process on the oxide film 230A, the oxide film 230B, and the oxide film 243A, the oxygen vacancies in the oxide film 230A, the oxide film 230B, and the oxide film 243A are repaired by the supplied oxygen. In other words, O Furthermore, the reaction of "+O→null" can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide film 230A, the oxide film 230B, and the oxide film 243A, and the hydrogen can be removed as H2O (dehydrated). As a result, the hydrogen remaining in the oxide 230 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0276] Next, a conductive film 242A is formed on the oxide film 243A (see FIGS. 10A to 10D). The conductive film 242A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, tantalum nitride may be formed as the conductive film 242A by sputtering. Note that heat treatment may be performed before the formation of the conductive film 242A. The heat treatment may be performed under reduced pressure, and the conductive film 242A may be formed successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide film 243A can be removed, and the moisture and hydrogen concentrations in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 200° C.

[0277] Next, an insulating film 271A is formed over the conductive film 242A (see FIGS. 10A to 10D). The insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 271A is preferably an insulating film that has a function of suppressing oxygen permeation. For example, aluminum oxide may be formed as the insulating film 271A by a sputtering method.

[0278] In this embodiment, the insulating film 271A is formed by pulse DC sputtering using an aluminum target in an atmosphere containing oxygen gas. The RF power applied to the substrate is 0.62 W / cm. 2 Preferably, 0 W / cm 2 More than 0.31W / cm 2 By reducing the RF power, the amount of oxygen implanted into the conductive film 242A can be suppressed, and oxidation of the conductive film 242A can be prevented.

[0279] Note that the conductive film 242A and the insulating film 271A are preferably formed by sputtering without exposure to the air. For example, a multi-chamber film formation apparatus may be used. This method can reduce the amount of hydrogen in the conductive film 242A and the insulating film 271A during film formation, and can also reduce the amount of hydrogen that gets mixed into the films between film formation steps.

[0280] Next, a hard mask layer 275A is formed on the insulating film 271A (see FIGS. 11A to 11D). The hard mask layer 275A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The hard mask layer 275A functions as a hard mask for forming the oxide 230b or the like in a later step. A metal material, an inorganic insulating material, or the like may be used as the hard mask layer 275A. For example, tungsten may be formed as the hard mask layer 275A by sputtering. Alternatively, the hard mask layer 275A may be formed continuously after the insulating film 271A is formed without exposure to the atmosphere.

[0281] Next, an organic coating film 276A is formed on the hard mask layer 275A (see FIGS. 11A to 11D). The organic coating film 276A may have the function of improving adhesion between a hard mask and a resist mask, which will be described later. The organic coating film 276A may be formed by, for example, spin coating. A non-photosensitive organic resin may be used as the organic coating film 276A. For example, an SOG (Spin On Glass) film or an SOC (Spin On Carbon) film may be formed as the organic coating film 276A. Alternatively, for example, a laminated film in which an SOC film and an SOG film are formed thereon may be used as the organic coating film 276A. Note that the organic coating film 276A may be provided as needed. If a resist mask, which will be described later, is sufficient, the organic coating film 276A may not be provided.

[0282] Next, a resist mask 277 is formed on the organic coating film 276A using lithography (see FIGS. 11A to 11D). The resist mask 277 may be made of a photosensitive organic resin also known as photoresist. For example, a positive photoresist or a negative photoresist may be used. The photoresist that will become the resist mask 277 can be formed to a uniform thickness by using, for example, spin coating.

[0283] In the lithography method, first, a photoresist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask 277. For example, the resist mask 277 may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Alternatively, an electron beam or an ion beam may be used instead of the light described above. Note that when an electron beam or an ion beam is used, a mask is not required.

[0284] Next, using a resist mask 277, the conductive film 242A, the insulating film 271A, the hard mask layer 275A, and the organic coating film 276A are processed into island shapes to form the conductive layer 242B, the insulating layer 271B, the hard mask 275, and the organic coating film 276 (see Figures 12A to 12D).

[0285] This processing can be performed using a dry etching method or a wet etching method. Dry etching processing is preferable because it is suitable for fine processing. A halogen-based etching gas containing one or more of fluorine, chlorine, and bromine can be used as the etching gas. Furthermore, oxygen gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or the like can be added to the halogen-containing etching gas as appropriate. Furthermore, the etching conditions can be appropriately changed depending on the target to be etched (the conductive film 242A, the insulating film 271A, the hard mask layer 275A, and the organic coating film 276A).

[0286] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source may be used. For example, an inductively coupled plasma (ICP) etching apparatus may be used as the dry etching apparatus having a high-density plasma source.

[0287] Next, the oxide film 230A, the oxide film 230B, and the oxide film 243A are processed into an island shape using a hard mask 275 to form an oxide 230a, an oxide 230b, and an oxide layer 243B (see FIGS. 13A to 13D).

[0288] This processing can be performed using a dry etching method or a wet etching method. Dry etching is preferable because it is suitable for fine processing. As the etching gas, it is preferable to use an etching gas containing a hydrocarbon such as methane (CH4) gas. Examples of hydrocarbons used in the etching gas include methane (CH4), ethane (C2H6), propane (C3H8), and butane (C4H 10 ), ethylene (C2H4), propylene (C3H6), acetylene (C2H2), and propyne (C3H4) can be used. Oxygen gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or the like can be added to the etching gas containing hydrocarbon. The dry etching apparatus described above can be used in the etching process.

[0289] In this embodiment, a case where methane (CH4) is used as the etching gas is exemplified. When oxides containing one or more selected from In, Ga, and Zn are used as the oxide films 230A, 230B, and 243A, etching can be performed relatively easily by using methane (CH4) gas.

[0290] Here, an example of a model in which an oxide film 230B made of In-Ga-Zn oxide is etched using a mixed gas of CH4 gas and Ar gas will be described with reference to Fig. 25. In Fig. 25, In, Ga, and Zn are collectively referred to as metal atoms M e It is expressed as:

[0291] The Ar gas is ionized in the plasma to generate Ar ions. As shown in FIG. 25, the Ar ions are accelerated by a bias voltage applied to the electrode on the substrate side and collide with the surface of the oxide film 230B. Here, oxygen atoms in the oxide film 230B are converted into metal atoms M e Since the oxygen atom is lighter than the metal atom M, it is relatively easily desorbed by the collision of the Ar ion. e The bond with the oxygen atom is broken, and an oxygen vacancy V is formed at the site where the oxygen atom was located. O In this way, oxygen atoms are removed from the oxide film 230B.

[0292] Furthermore, CH4 gas is decomposed in the plasma to generate CH3 radicals 295. Here, the metal atom M e Therefore, as shown in Figure 25, the generated CH3 radical 295 reacts with the metal atom M e can be coordinated relatively easily to

[0293] Metal atom M coordinated with CH3 radical 295 e Further oxygen atom detachment proceeds around the metal atom M coordinated with CH3 radical 295. e and the metal atom M e The bond between the metal atom M and the adjacent oxygen atom is broken. e By repeating this cycle, the metal atom M e is sublimated as a metal complex 296. In this way, the metal complex 296 is formed, and the metal atom M e is removed.

[0294] Here, metal complexes 296, such as In(CH3)3, Ga(CH3)3, and Zn(CH3)2, are formed. These metal complexes all have boiling points below 70°C and are relatively volatile. Therefore, even if the substrate temperature is relatively low, the reaction shown in the model in FIG. 25 can proceed. In this way, by using a mixed gas of CH4 gas and Ar gas, it is possible to easily process In-Ga-Zn oxide, which is a difficult-to-etch material.

[0295] Although the etching model for the oxide film 230B has been described above, the oxide film 230A and the oxide film 243A can also be etched according to a similar model.

[0296] As described above, when dry etching is performed using CH gas or the like, by-products may be formed on the side surfaces of the organic coating film 276 and the resist mask 277. Therefore, it is preferable to remove the organic coating film 276 and the resist mask 277 during the etching step shown in Fig. 12 or at an early stage of the etching step shown in Fig. 13, and then perform the etching step using the hard mask 275 as a mask.

[0297] Furthermore, during dry etching using CH gas or the like, the organic coating film 276 and the resist mask 277 may be lost. For this reason, it is preferable to provide a hard mask 275 under the resist mask 277 that will not be lost during the etching process.

[0298] Furthermore, when the hard mask 275 contains tungsten and the insulator 224 contains silicon oxide, it is preferable to etch the oxide film 230A, the oxide film 230B, and the oxide film 243A using methane (CH4) gas. By performing etching in this manner, the etching selectivity of the oxide film 230A, the oxide film 230B, and the oxide film 243A can be significantly higher than that of the hard mask 275 and the insulator 224. Therefore, in this process, the oxide film 230A, the oxide film 230B, and the oxide film 243A can be formed in an island shape while the insulator 224 remains flat. This allows the regions of the insulator 224 that do not overlap with the oxide 230a to be completely removed and prevents the insulator 222 from being overetched in the process of forming the insulator 224 in an island shape, which will be described later.

[0299] If the resist mask 277 and the organic coating film 276 remain after the process shown in FIG. 13, they may be removed by performing a dry etching process such as ashing, a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.

[0300] Next, an etching process is performed to process the insulator 224 into an island shape, overlapping with the oxide 230a (see FIGS. 14A to 14D). This etching process can be performed using a dry etching method or a wet etching method. Dry etching is preferable because it is suitable for fine processing. As the etching gas, a halogen-based etching gas containing one or more of fluorine, chlorine, and bromine can be used. Furthermore, oxygen gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or the like can be appropriately added to the halogen-containing etching gas. Furthermore, the above-mentioned dry etching apparatus can be used for this etching process.

[0301] Here, it is preferable that the insulator 222 is not over-etched during processing of the insulator 224. Therefore, it is preferable to perform etching under conditions that provide a high etching selectivity relative to the insulator 222. For example, when the insulator 224 contains silicon oxide and is etched with a gas containing fluorine, it is preferable that the insulator 222 contains hafnium oxide. By etching in this manner, the insulator 272 can be provided in contact with the side surface of the insulator 224 and the top surface of the insulator 222 in a process described below. In other words, the insulator 224 can be separated from the insulator 280 by the insulator 272. This configuration can prevent excessive amounts of impurities such as oxygen or hydrogen from being mixed into the oxide 230 from the insulator 280 via the insulator 224.

[0302] As described above, it is preferable to perform this etching step while the insulator 224 remains flat, that is, while the variation in the thickness of the insulator 224 is small within the substrate surface. This reduces the variation in the time it takes to remove the insulator 224 within the substrate surface, thereby preventing the insulator 222 from being over-etched and losing part of the insulator 222. Alternatively, it is possible to prevent part of the insulator 224 from remaining on the insulator 222.

[0303] Furthermore, the hard mask 275 may be removed in this etching step (see FIGS. 14A to 14D). The hard mask 275 can be removed by dry etching or wet etching. However, if the material of the hard mask 275 does not affect a subsequent step or can be used in the subsequent step, it is not necessarily necessary to remove the hard mask 275.

[0304] Furthermore, in the process of removing the hard mask 275, the insulating layer 271B functions as a mask for the conductive layer 242B, so that the conductive layer 242B does not have a curved surface between its side surface and top surface, as shown in FIGS. 14B and 14C. As a result, the conductors 242a and 242b shown in FIG. 1B have angular ends where their side surfaces and top surfaces intersect. Because the angular ends where the side surfaces and top surfaces of the conductor 242 intersect are angular, the cross-sectional area of ​​the conductor 242 is larger than when the ends have a curved surface. This reduces the resistance of the conductor 242, thereby increasing the on-current of the transistor 200.

[0305] When the insulating layer 271B functions as a mask for the conductive layer 242B, the hard mask 275 may be removed before processing the insulator 224 into islands. Furthermore, the hard mask 275 may be removed in parallel with processing the insulator 224 into islands.

[0306] 12 to 14 may be performed consecutively without exposure to the outside air. For example, the etching steps may be performed consecutively in the same chamber, or a multi-chamber etching apparatus may be used to perform the etching steps without exposure to the outside air.

[0307] 12 to 14, the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B are formed so as to at least partially overlap with the conductor 205. Preferably, the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B are approximately perpendicular to the top surface of the insulator 222. When the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B are approximately perpendicular to the top surface of the insulator 222, a smaller area and higher density can be achieved when providing multiple transistors 200. Alternatively, the angles formed by the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B and the upper surface of the insulator 222 may be small. In this case, the angles formed by the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B and the upper surface of the insulator 222 are preferably 60 degrees or more and less than 70 degrees. By using such a shape, the coverage of the insulator 272 and the like can be improved in subsequent processes, and defects such as voids can be reduced.

[0308] 12 to 14 may be formed in layers on the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B. In this case, the layer-like by-products are formed in the insulator 224, the oxide 230a, the oxide 230b, the oxide 243, the conductor 242, and between the insulators 271 and 272. If the transistor 200 is fabricated in the state where the layer-like by-products are formed, the reliability of the transistor 200 may be deteriorated. Therefore, it is preferable to remove the layer-like by-products.

[0309] Next, the insulator 272 is formed on the insulator 222, the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B (see FIGS. 15A to 15D). The insulator 272 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the insulator 272 is formed by a pulse DC sputtering method using an aluminum target in an atmosphere containing oxygen gas. Alternatively, the insulator 272 may be formed by a silicon nitride method. The insulator 272 is in close contact with a portion of the upper surface of the insulator 222.

[0310] The insulator 272 may have a layered structure. For example, an aluminum oxide film may be formed by sputtering, and then a silicon nitride film may be formed on the aluminum oxide by sputtering. Such a multilayer structure of the insulator 272 may improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0311] In this way, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B can be covered with the insulator 272 and the insulating layer 271B, which have the function of suppressing oxygen diffusion, thereby reducing the diffusion of oxygen into the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B in a later process.

[0312] Next, an insulating film to be the insulator 280 is formed on the insulator 272. The insulating film can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, a silicon oxide film can be formed by sputtering. The insulating film to be the insulator 280 can be formed by sputtering in an oxygen-containing atmosphere, thereby forming the insulator 280 containing excess oxygen. Furthermore, the hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require hydrogen as a deposition gas. Heat treatment may be performed before the formation of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be formed successively without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 272 can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, the oxide layer 243B, and the insulator 224 can be reduced. The heat treatment conditions described above can be used for the heat treatment.

[0313] Next, the insulating film that will become the insulator 280 is subjected to CMP processing to form the insulator 280 with a flat upper surface (see FIGS. 15A to 15D). Alternatively, a silicon nitride film may be formed on the insulator 280 by, for example, a sputtering method, and the CMP processing may be performed until the silicon nitride reaches the insulator 280.

[0314] Next, a portion of the insulator 280, a portion of the insulator 272, a portion of the insulating layer 271B, a portion of the conductive layer 242B, and a portion of the oxide layer 243B are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the insulator 271a, the insulator 271b, the conductor 242a, the conductor 242b, the oxide 243a, and the oxide 243b are formed (see FIGS. 16A to 16D).

[0315] When forming the opening, the upper portion of the oxide 230b may be removed. By removing a portion of the oxide 230b, a groove is formed in the oxide 230b. Depending on the depth of the groove, the groove may be formed in the same process as the opening or in a different process.

[0316] Furthermore, a portion of the insulator 280, a portion of the insulator 272, a portion of the insulating layer 271B, a portion of the conductive layer 242B, and the oxide layer 243B can be processed by dry etching or wet etching. Processing by dry etching is suitable for fine processing. Furthermore, the processing may be performed under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 272 and a portion of the insulating layer 271B may be processed by wet etching, and a portion of the conductive layer 242B and a portion of the oxide layer 243B may be processed by dry etching. Furthermore, processing of a portion of the conductive layer 242B and a portion of the oxide layer 243B may be performed under different conditions.

[0317] Here, impurities may adhere to the side surfaces of the oxide 230a, the top and side surfaces of the oxide 230b, the side surfaces of the conductor 242, the side surfaces of the insulator 280, etc., or may diffuse into these surfaces. A process for removing such impurities may be performed. Furthermore, the dry etching may result in damaged regions being formed on the surface of the oxide 230b. Such damaged regions may be removed. Examples of such impurities include those derived from components contained in the insulator 280, the insulator 272, part of the insulating layer 271B, the conductive layer 242B, and the insulator 222, components contained in the materials used in the device used to form the opening, and components contained in the gas or liquid used in etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0318] In particular, impurities such as aluminum or silicon inhibit the formation of a CAAC-OS oxide 230b. Therefore, it is preferable to reduce or eliminate impurity elements such as aluminum or silicon that inhibit the formation of a CAAC-OS oxide. For example, the concentration of aluminum atoms in and around the oxide 230b may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0319] Note that the region of the metal oxide where the CAAC-OS transformation is inhibited by impurities such as aluminum or silicon and becomes an amorphous-like oxide semiconductor (a-like OS) is sometimes called a non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, so V O A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the non-CAAC region of the oxide 230b be reduced or eliminated.

[0320] In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the oxide 230b has the CAAC structure up to the bottom edge of the drain. Here, in the transistor 200, the conductor 242a or the conductor 242b and its vicinity function as the drain. In other words, it is preferable that the oxide 230b near the bottom edge of the conductor 242a (conductor 242b) has the CAAC structure. In this way, even at the drain edge, which significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed, and by having the CAAC structure, fluctuations in the electrical characteristics of the transistor 200 can be further suppressed. Furthermore, the reliability of the transistor 200 can be improved.

[0321] In order to remove the above-mentioned impurities, a cleaning process is performed. The cleaning method includes wet cleaning using a cleaning solution, plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.

[0322] For wet cleaning, cleaning treatment may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be used in combination as appropriate.

[0323] In this specification, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be referred to as "diluted hydrofluoric acid," and an aqueous solution obtained by diluting commercially available ammonia water with pure water may be referred to as "diluted ammonia water." The concentration, temperature, and other parameters of the aqueous solution may be adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be set to 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be set to 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0324] It is preferable to use a frequency of 200 kHz or more, and more preferably 900 kHz or more, for ultrasonic cleaning, as this frequency can reduce damage to the oxide 230b and the like.

[0325] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0326] In this embodiment, the cleaning process involves wet cleaning using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. By performing this cleaning process, impurities attached to the surfaces of or diffused into the oxides 230a and 230b can be removed. Furthermore, the crystallinity of the oxide 230b can be improved.

[0327] If the above-mentioned impurities are not removed before forming the insulating film 250A described later, the impurities may remain between the oxide 230a, the oxide 230b, the conductor 242, the insulator 280, etc. and the insulator 250a.

[0328] After the etching or cleaning, a heat treatment may be performed. The heat treatment may be performed at a temperature of 100°C or higher and 450°C or lower, preferably 350°C or higher and 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230a and the oxide 230b, thereby reducing the oxygen vacancy V. O The heat treatment can reduce the amount of oxide 230b. In addition, by performing such heat treatment, the crystallinity of the oxide 230b can be improved. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0329] Next, an insulating film 250A that will become the insulator 250a is formed (see FIGS. 17A to 17D). A heat treatment may be performed before forming the insulating film 250A. The heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed continuously without exposure to the atmosphere. The heat treatment is preferably performed in an oxygen-containing atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0330] The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This reduces the hydrogen concentration in the insulating film 250A. The insulating film 250A will become the insulator 250a that contacts the oxide 230b in a later process, so it is preferable that the hydrogen concentration be reduced in this way.

[0331] Furthermore, the insulating film 250A is preferably formed using the ALD method. The insulator 250, which functions as the gate insulating film of the miniaturized transistor 200, must be extremely thin (e.g., between 5 nm and 30 nm) and have minimal variation. In contrast, the ALD method is a film formation method in which a precursor and a reactant (oxidizer) are alternately introduced. The film thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness adjustment. This allows for the precision of the gate insulating film required by the miniaturized transistor 200 to be achieved. Furthermore, as shown in FIGS. 17B and 17C , the insulating film 250A must be formed with good coverage on the bottom and side surfaces of the opening formed by the insulator 280, etc. Because atomic layers can be deposited one by one on the bottom and side surfaces of the opening, the insulating film 250A can be formed with good coverage on the opening.

[0332] Furthermore, when the insulating film 250A is formed by using the PECVD method, the film forming gas containing hydrogen is decomposed in the plasma, generating a large amount of hydrogen radicals. The reduction reaction of the hydrogen radicals extracts oxygen from the oxide 230b, forming V. O When H is formed, the hydrogen concentration in the oxide 230b increases. However, when the insulating film 250A is formed using the ALD method, the generation of hydrogen radicals can be suppressed both when introducing the precursor and when introducing the reactant. Therefore, by forming the insulating film 250A using the ALD method, the hydrogen concentration in the oxide 230b can be prevented from increasing.

[0333] Next, microwave processing may be performed in an oxygen-containing atmosphere (see FIGS. 17A to 17D). Here, microwave processing refers to processing using, for example, a device with a power source that generates high-density plasma using microwaves. The dotted lines in FIGS. 17B to 17D indicate microwaves, high-frequency waves such as RF, oxygen plasma, or oxygen radicals. For the microwave processing, a microwave processing device with a power source that generates high-density plasma using microwaves is preferably used. The microwave processing device may also have a power source that applies RF to the substrate side. Using high-density plasma can generate high-density oxygen radicals. Applying RF to the substrate side can efficiently introduce oxygen ions generated by high-density plasma into the oxide 230b. The microwave processing is preferably performed under reduced pressure, with a pressure of 60 Pa or higher, preferably 133 Pa or higher, more preferably 200 Pa or higher, and even more preferably 400 Pa or higher and 700 Pa or lower. The oxygen flow ratio (O2 / O2+Ar) is preferably 50% or lower, preferably 10% or higher and 30% or lower. The treatment temperature may be 750° C. or less, preferably 500° C. or less, for example, about 400° C. After the oxygen plasma treatment, a heat treatment may be performed successively without exposure to the outside air.

[0334] As shown in Figures 17B to 17D, microwave processing is performed in an atmosphere containing oxygen, whereby oxygen gas is converted into plasma using microwaves or high-frequency waves such as RF, and the oxygen plasma can be applied to the region between the conductors 242a and 242b of the oxide 230b. At this time, microwaves or high-frequency waves such as RF can also be irradiated onto the region 230bc. In other words, microwaves, high-frequency waves such as RF, oxygen plasma, etc. can be applied to the region 230bc shown in Figure 3. The action of plasma, microwaves, etc., can increase the V of the region 230bc. O H can be split off and hydrogen H can be removed from the region 230bc. O H → H + V O" occurs, and the hydrogen concentration in the region 230bc can be reduced. Therefore, oxygen vacancies and V O By supplying oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancies formed in the region 230bc, the oxygen vacancies in the region 230bc can be further reduced, and the carrier concentration can be lowered.

[0335] On the other hand, conductors 242a and 242b are provided on regions 230ba and 230bb shown in Fig. 3. As shown in Figs. 17B to 17D, conductors 242a and 242b shield the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc., so that these effects do not reach regions 230ba and 230bb. As a result, V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0336] In this way, oxygen vacancies and V are selectively formed in the oxide semiconductor region 230bc. O By removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb, which function as source and drain regions, can be prevented, maintaining the n-type conductivity. This prevents fluctuations in the electrical characteristics of the transistor 200 and prevents the electrical characteristics of the transistor 200 from varying across the substrate.

[0337] Therefore, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device with good electrical characteristics.

[0338] In microwave processing, electromagnetic interaction between microwaves and molecules in the oxide 230b can transfer thermal energy directly to the oxide 230b. This thermal energy can heat the oxide 230b. This type of heat treatment is sometimes called microwave annealing. Performing microwave processing in an oxygen-containing atmosphere can sometimes achieve the same effect as oxygen annealing. Furthermore, if the oxide 230b contains hydrogen, this thermal energy can be transferred to the hydrogen in the oxide 230b, which can then activate and release the hydrogen from the oxide 230b.

[0339] Next, an insulating film 250B that will become the insulator 250b is formed (see FIGS. 18A to 18D). The insulating film 250B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 250B is preferably formed using an insulator that has a function of suppressing oxygen diffusion. This configuration can suppress the oxygen contained in the insulator 250a from diffusing into the conductor 260. That is, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. For example, the insulating film 250A can be formed using a material that can be used for the insulator 250 described above, and the insulating film 250B can be formed using a material similar to that of the insulator 222.

[0340] Specifically, the insulating film 250B can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.

[0341] In this embodiment, the insulating film 250A is formed from silicon oxynitride by CVD, and the insulating film 250B is formed from hafnium oxide by thermal ALD.

[0342] A microwave treatment may be performed after the formation of the insulating film 250B. The microwave treatment may be performed under the same conditions as those for the microwave treatment performed after the formation of the insulating film 250A. Alternatively, the microwave treatment may be performed after the formation of the insulating film 250B without performing the microwave treatment performed after the formation of the insulating film 250A.

[0343] Furthermore, after the formation of the insulating film 250A and the formation of the insulating film 250B, a heat treatment may be performed while maintaining the reduced pressure after each microwave treatment. By performing such a treatment, hydrogen in the insulating film 250A, the insulating film 250B, the oxide 230b, and the oxide 230a can be efficiently removed. Some of the hydrogen may be gettered to the conductor 242 (the conductor 242a and the conductor 242b). Alternatively, a heat treatment step may be performed multiple times while maintaining the reduced pressure after the microwave treatment. Repeated heat treatments can more efficiently remove hydrogen from the insulating film 250A, the oxide 230b, and the oxide 230a. The heat treatment temperature is preferably 300°C or higher and 500°C or lower. The microwave treatment, i.e., microwave annealing, may also serve as the heat treatment. If the oxide 230b and the like are sufficiently heated by microwave annealing, the heat treatment may not be necessary.

[0344] Furthermore, by modifying the film quality of the insulating film 250A and the insulating film 250B by microwave treatment, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. through the insulator 250 by a post-process such as film formation of a conductive film that becomes the conductor 260 or a post-treatment such as heat treatment.

[0345] Next, a conductive film that will become the conductor 260a and a conductive film that will become the conductor 260b are formed in this order. The conductive film that will become the conductor 260a and the conductive film that will become the conductor 260b can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a titanium nitride film that will become the conductor 260a is formed by an ALD method, and a tungsten film that will become the conductor 260b is formed by a CVD method.

[0346] Next, the insulating film 250A, the insulating film 250B, the conductive film that will become the conductor 260a, and the conductive film that will become the conductor 260b are polished by CMP until the insulator 280 is exposed, thereby forming the insulators 250a, 250b, the conductors 260a, and 260b (see FIGS. 19A to 19D). As a result, the insulator 250 is arranged to cover the inner walls (side walls and bottom surface) of the opening that reaches the oxide 230b and the groove in the oxide 230b. The conductors 260a and 260b are arranged to fill the opening and the groove via the insulator 250.

[0347] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0348] Next, the insulator 282a and the insulator 282b are successively formed on the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 20A to 20D). The insulator 282a and the insulator 282b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 282a and the insulator 282b are preferably formed by a sputtering method. By using a sputtering method that does not require the use of hydrogen as a deposition gas, the hydrogen concentration in the insulator 282a and the insulator 282b can be reduced.

[0349] In this embodiment, aluminum oxide films are formed as the insulators 282a and 282b by pulse DC sputtering using an aluminum target in an atmosphere containing oxygen gas. At this time, oxygen can be added to the insulator 280. Furthermore, by using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Furthermore, the RF power applied to the substrate is 1.86 W / cm. 2 Preferably, 0 W / cm 2 More than 0.31W / cm 2 By reducing the RF power, it is possible to reduce the amount of oxygen implanted into the insulator 280. In this embodiment, the insulator 282a is formed by applying an RF power of 0 W / cm 2 to the substrate. 2 The insulator 282b is formed as follows: the RF power applied to the substrate is 0.31 W / cm 2 The film is formed as follows.

[0350] Next, a portion of the insulator 282a and a portion of the insulator 282b are processed to form the opening region 400a and the opening region 400b (see FIGS. 21A to 21D). The opening region 400a overlaps at least a portion of the conductor 242a, and the opening region 400b overlaps at least a portion of the conductor 242b. A groove may be formed in the insulator 280, overlapping with the opening of the insulator 282 in the opening region 400. The portions of the insulator 282a, the insulator 282b, and the insulator 280 may be processed using wet etching, but dry etching is preferable for fine processing. The depth of the groove in the insulator 280 should be at most 1 / 4 to 1 / 2 of the maximum film thickness of the insulator 280, as long as the top surface of the insulator 272 is exposed. For example, the depth may be approximately 1 / 4 to 1 / 2 of the maximum film thickness of the insulator 280.

[0351] Next, the insulators 282a, 282b, 280, 272, 222, and 216 are processed until they reach the top surface of the insulator 214 (see FIGS. 22A to 22D). This processing may be performed by wet etching, but dry etching is preferable for fine processing.

[0352] Next, heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 400°C to 600°C. The heat treatment temperature is preferably lower than the heat treatment temperature performed after the formation of the oxide film 243A. The heat treatment is performed in a nitrogen gas or inert gas atmosphere. By performing the heat treatment, oxygen contained in the insulator 280 and hydrogen bonded to the oxygen can be released to the outside through the opening region 400. At the same time, the oxygen contained in the insulator 280 and hydrogen bonded to the oxygen can be released to the outside from the side surface of the formed insulator 280 by processing the insulators 282a, 282b, 280, 272, 222, and 216. The hydrogen bonded to the oxygen is released as water. Therefore, unnecessary oxygen and hydrogen contained in the insulator 280 can be reduced. The heat treatment may be performed after the opening region 400 is formed, and further after the insulators 282a, 282b, 280, 272, 222, and 216 are processed.

[0353] In this way, it is possible to supply sufficient oxygen to the region 230bc and its vicinity from the insulator 280 containing oxygen that is desorbed by heating, without supplying an excessive amount of oxygen. At this time, it is also possible to suppress the incorporation of hydrogen into the region 230bc. As a result, oxygen vacancies and V O By removing H, the region 230bc can be made i-type or substantially i-type. This can suppress fluctuations in the electrical characteristics of the transistor 200 and improve reliability. Furthermore, it can suppress variations in the electrical characteristics of the transistor 200 within the substrate plane.

[0354] Next, the insulator 283 is formed on the insulator 214, the insulator 282b, etc. (see FIGS. 23A to 23D). The insulator 283 is preferably in contact with the insulator 280 in the opening regions 400a and 400b. The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 283 is preferably formed by a sputtering method. The hydrogen concentration in the insulator 283 can be reduced by using a sputtering method, which does not require hydrogen as a deposition gas. The insulator 283 may also have a multilayer structure. For example, a silicon nitride film may be formed by a sputtering method, and then a silicon nitride film may be formed on the silicon nitride by an ALD method.

[0355] Here, the insulator 283 is provided to cover the island-shaped insulators 216, 222, 272, 280, 282a, and 282b. Therefore, by enclosing the transistor 200 with the insulators 283 and 214, which have high barrier properties, moisture and hydrogen can be prevented from entering from the outside.

[0356] 22A to 22D , the insulator 214 may also be processed into an island shape, the upper surface of the insulator 212 may be exposed, and the transistor 200 may be enclosed by the insulators 283 and 212. In this case, the upper surface of the insulator 283 contacts the upper surface of the insulator 212 in the sealing portion 265.

[0357] Next, an insulating film to be the insulator 274 is formed on the insulator 283 (see FIGS. 24A to 24D). The insulating film to be the insulator 274 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon oxide is formed as the insulating film to be the insulator 274 by CVD.

[0358] Next, the insulator 274 is polished by CMP until the insulator 283 is exposed, thereby forming the insulator 274 so as to be embedded in the sealing portion 265, the opening region 400a, and the opening region 400b (see FIGS. 23A to 23D). Here, the upper surface of the insulator 274 is planarized, and the height of the upper surface of the insulator 274 and the height of the upper surface of the insulator 283 are approximately the same. The CMP process may remove a portion of the upper surface of the insulator 283. Furthermore, the insulator 274 may be formed so as to fill recesses formed in the insulator 283 in the opening region 400a and the opening region 400b.

[0359] Next, an insulator 286 is formed over the insulator 274 and the insulator 283 (see FIGS. 24A to 24D). The insulator 286 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulator 286 by a sputtering method.

[0360] Next, an opening that penetrates the opening region 400a to reach the conductor 242a and an opening that penetrates the opening region 400b to reach the conductor 242b are formed (see FIGS. 24A to 24D). Here, it is preferable that the opening that reaches the conductor 242a is located inside the opening of the insulator 282 in the opening region 400a in top view, and the opening that reaches the conductor 242b is located inside the opening of the insulator 282 in the opening region 400b in top view.

[0361] The opening reaching the conductor 242 can be formed by forming a mask using lithography and removing the insulators 286, 274, 283, 280, 272, and 271 by anisotropic etching. Because the opening reaching the conductor 242 has a high aspect ratio, it is preferable to use dry etching. The above-mentioned dry etching apparatus can be used for this etching process.

[0362] Here, when the opening region 400 and the conductor 240 do not overlap, to form an opening that reaches the conductor 242, it is necessary to open the insulators 286, 283, 282, and 280, which are thick interlayer insulating films. The insulators 286 and 280 are mainly composed of silicon oxide, the insulator 283 is mainly composed of silicon nitride, and the insulator 282 is mainly composed of aluminum oxide. Therefore, when the above openings are formed all at once using an etching gas containing fluorine, it is relatively easy to form openings in the insulators 286, 280, and 283, but it is difficult to form an opening in the insulator 282.

[0363] When removing the insulator 282 using an etching gas containing fluorine, it is preferable that the kinetic energy of the ions incident on the insulator 282 be high, so dry etching is performed by applying a high-power bias to the substrate. If the pattern of the opening reaching the conductor 242 is formed using only a resist mask, the resist mask may be destroyed during the dry etching. Therefore, a hard mask made of tungsten or the like must be formed separately from the resist mask. Furthermore, when removing the insulator 282 using an etching gas containing fluorine, the cross-sectional shape of the opening in the insulator 282 may be significantly tapered compared to the cross-sectional shape of the opening in the insulator 280.

[0364] 21A to 21D, the insulator 282 in the opening region 400 is removed, and therefore, there is no need to remove the insulator 282 when forming the opening that reaches the conductor 242. Therefore, in this embodiment, the insulator 282 does not need to be removed under the strict conditions described above, and the opening that reaches the conductor 242 can be formed more easily and in a shape that is closer to vertical. In this way, by using the method described in this embodiment, semiconductor devices can be manufactured with good productivity.

[0365] When aluminum oxide is used for the insulators 271 and 272, they also need to be etched to form an opening that reaches the conductor 242. However, since the insulators 271 and 272 are thinner than the insulator 282, the insulators 271 and 272 can be easily removed using a dry etching method.

[0366] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 in the opening that reaches the conductor 242. The insulating film that will become the insulator 241 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film that will become the insulator 241, it is preferable to use an insulating film that has the function of suppressing oxygen permeation. For example, it is preferable to form a film of aluminum oxide using the ALD method. Alternatively, it is preferable to form a film of silicon nitride using the PEALD method. Silicon nitride is preferable because it has a high barrier property against hydrogen.

[0367] Furthermore, dry etching, for example, may be used for anisotropic etching of the insulating film that will become the insulator 241. By providing the insulator 241 on the sidewall of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent oxidation of the conductors 240a and 240b that will be formed next. It is also possible to prevent impurities such as water and hydrogen from being mixed into the oxide 230 through the conductors 240a and 240b.

[0368] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed in the opening that reaches the conductor 242. The conductive film that will become the conductor 240a and the conductor 240b is preferably a layered structure that includes a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a layered structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that will become the conductor 240 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0369] Next, CMP processing is performed to remove portions of the conductive film that will become the conductors 240a and 240b, exposing the upper surface of the insulator 286. As a result, the conductive film remains only in the openings that reach the conductor 242, thereby forming the conductors 240a and 240b with flat upper surfaces (see FIGS. 1A to 1D). When the insulator 241 and the conductor 240 are formed inside the opening region 400 in this manner, the insulator 241 and the conductor 240 do not come into contact with the insulator 282. Furthermore, the CMP processing may remove a portion of the upper surface of the insulator 286.

[0370] In this way, by forming the opening region 400 and the conductor 240 functioning as a plug so as to overlap each other in a top view, the opening region 400 can be provided without significantly increasing the area occupied by the transistor 200. As a result, even in a design in which multiple transistors 200 are densely arranged, the opening region 400 can be provided without changing the arrangement of the transistors 200 to provide extra space. With this configuration, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0371] Next, a conductive film is formed to become the conductor 246. The conductive film to become the conductor 246 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0372] Next, the conductive film that will become the conductor 246 is processed by lithography to form the conductor 246a that contacts the upper surface of the conductor 240a and the conductor 246b that contacts the upper surface of the conductor 240b. Although not shown, at this time, part of the insulator 286 may be removed in a region where the conductor 246a and the conductor 246b do not overlap with the insulator 286.

[0373] Dicing lines (sometimes called scribe lines, division lines, or cutting lines) may be provided overlapping the sealing portion 265. The substrate on which the semiconductor device is formed is divided along the dicing lines, so that the group of transistors surrounded by the sealing portion 265 is extracted as one chip.

[0374] 1A to 1D can be manufactured. As shown in FIGS. 1A to 1D and 5A to 24D, the transistor 200 can be manufactured with high productivity by using the manufacturing method of a semiconductor device described in this embodiment.

[0375] <Microwave processing equipment> A microwave processing apparatus that can be used in the method for manufacturing the semiconductor device will be described below.

[0376] First, the configuration of a manufacturing apparatus that minimizes the inclusion of impurities during the manufacture of semiconductor devices and the like will be described with reference to FIGS. 26, 27 and 28. FIG.

[0377] 26 is a schematic top view of a single-wafer processing multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 has an atmosphere-side substrate supply chamber 2701 equipped with a cassette port 2761 for accommodating substrates and an alignment port 2762 for aligning the substrates, an atmosphere-side substrate transfer chamber 2702 for transferring substrates from the atmosphere-side substrate supply chamber 2701, a load lock chamber 2703a for loading substrates and for switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 2703b for unloading substrates and for switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring substrates in a vacuum, chambers 2706a, 2706b, 2706c, and 2706d.

[0378] The atmospheric side substrate transfer chamber 2702 is connected to a load lock chamber 2703a and an unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to a transfer chamber 2704, and the transfer chamber 2704 is connected to chambers 2706a, 2706b, 2706c and 2706d.

[0379] A gate valve GV is provided at the connection between each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmosphere-side substrate supply chamber 2701 and the atmosphere-side substrate transfer chamber 2702. A transfer robot 2763a is provided in the atmosphere-side substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. Substrates can be transferred within the manufacturing apparatus 2700 by the transfer robots 2763a and 2763b.

[0380] The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 -4 Pa or less, preferably 3 x 10 -5 Pa or less, more preferably 1×10 -5 The partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 28 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 44 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0381] The total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using a mass spectrometer, for example, a quadrupole mass spectrometer (also called Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc.

[0382] It is also desirable that the transfer chamber 2704 and each chamber have a configuration with little external or internal leakage. For example, the leak rate of the transfer chamber 2704 and each chamber is 3×10 -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less. For example, if the leak rate of a gas molecule (atom) with m / z of 18 is 1×10 -7 Pa·m 3 / s or less, preferably 3 × 10 -8 Pa·m 3 / s or less. For example, if the leak rate of a gas molecule (atom) with m / z of 28 is 1×10 -5 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z 44 is 3 × 10 -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less.

[0383] The leak rate can be derived from the total pressure and partial pressure measured using the mass spectrometer mentioned above. The leak rate depends on external and internal leaks. External leaks are caused by gases entering from outside the vacuum system due to tiny holes or poor seals. Internal leaks are caused by leaks from partitions such as valves within the vacuum system or gases released from internal components. In order to keep the leak rate below the above-mentioned values, measures must be taken to prevent both external and internal leaks.

[0384] For example, it is advisable to seal the opening and closing portions of the transfer chamber 2704 and each chamber with a metal gasket. It is preferable to use a metal gasket coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have higher adhesion than O-rings and can reduce external leakage. Furthermore, by using a passivated metal coated with iron fluoride, aluminum oxide, chromium oxide, or the like, the release of gas containing impurities from the metal gasket can be suppressed, thereby reducing internal leakage.

[0385] Furthermore, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emit little impurity-containing gases, are used as components constituting the manufacturing apparatus 2700. Furthermore, the aforementioned metals that emit little impurity-containing gases may be coated on alloys containing iron, chromium, nickel, and the like. Alloys containing iron, chromium, nickel, and the like are rigid, heat-resistant, and suitable for processing. Here, reducing the surface roughness of the components by polishing or the like to reduce the surface area can reduce the amount of emitted gases.

[0386] Alternatively, the components of the manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0387] It is preferable that the components of the manufacturing apparatus 2700 be constructed solely from metal as much as possible, and even if a viewing window made of quartz or the like is installed, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide, or the like to suppress gas emissions.

[0388] The adsorbed matter present in the transfer chamber 2704 and each chamber is adsorbed to the inner walls and does not affect the pressure of the transfer chamber 2704 or each chamber. However, it can cause gas emissions when the transfer chamber 2704 or each chamber is evacuated. Therefore, although there is no correlation between the leak rate and the evacuation speed, it is important to use a pump with high evacuation capacity to desorb as much adsorbed matter as possible from the transfer chamber 2704 and each chamber and evacuate them in advance. To promote the desorption of adsorbed matter, the transfer chamber 2704 and each chamber may be baked. Baking can increase the desorption rate of adsorbed matter by approximately 10 times. Baking can be performed at temperatures between 100°C and 450°C. In this case, introducing an inert gas into the transfer chamber 2704 and each chamber while removing adsorbed matter can further increase the desorption rate of water and other substances that are difficult to desorb by evacuation alone. Heating the introduced inert gas to the same temperature as the baking temperature can further increase the desorption rate of adsorbed matter. A rare gas is preferably used as the inert gas.

[0389] Alternatively, it is preferable to increase the pressure in the transfer chamber 2704 and each chamber by introducing an inert gas such as a heated rare gas or oxygen, and then evacuating the transfer chamber 2704 and each chamber again after a certain period of time has elapsed. The introduction of heated gas can desorb adsorbed substances from the transfer chamber 2704 and each chamber, thereby reducing impurities present in the transfer chamber 2704 and each chamber. It is effective to repeat this process two to 30 times, preferably five to 15 times. Specifically, by introducing an inert gas or oxygen at a temperature of 40°C to 400°C, preferably 50°C to 200°C, the pressure in the transfer chamber 2704 and each chamber can be adjusted to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa. The pressure can be maintained for a period of 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Thereafter, the transfer chamber 2704 and each chamber are evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

[0390] Next, chamber 2706b and chamber 2706c will be described with reference to the cross-sectional schematic diagram shown in FIG.

[0391] Chamber 2706b and chamber 2706c are chambers capable of, for example, performing microwave processing on an object to be processed. Note that chamber 2706b and chamber 2706c differ only in the atmosphere during microwave processing. Since the other configurations are common, they will be described together below.

[0392] Chamber 2706b and chamber 2706c have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Also provided outside chamber 2706b and chamber 2706c are a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818.

[0393] The high-frequency generator 2803 is connected to a mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is disposed in contact with a dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is delivered to chambers 2706b and 2706c via a gas pipe 2806 that passes through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809. The vacuum pump 2817 evacuates gases and other gases from chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. The high-frequency power supply 2816 is connected to a substrate holder 2812 via a matching box 2815.

[0394] The substrate holder 2812 has a function of holding the substrate 2811. For example, it has a function of electrostatically or mechanically chucking the substrate 2811. It also has a function as an electrode to which power is supplied from a high-frequency power supply 2816. It also has an internal heating mechanism 2813 and has a function of heating the substrate 2811.

[0395] For example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbomolecular pump can be used as the vacuum pump 2817. A cryotrap may also be used in addition to the vacuum pump 2817. The use of a cryopump or a cryotrap is particularly preferable because it allows water to be efficiently pumped out.

[0396] The heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element or the like for heating. Alternatively, it may be a heating mechanism that uses heat conduction or heat radiation from a medium such as a heated gas for heating. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heating processing using high-temperature gas. An inert gas is used as the gas.

[0397] The gas supply source 2801 may be connected to a refiner via a mass flow controller. The gas used preferably has a dew point of -80°C or lower, preferably -100°C or lower. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) may be used.

[0398] The dielectric plate 2809 may be made of, for example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria). Furthermore, another protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of, for example, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Because the dielectric plate 2809 is exposed to a particularly high-density region of the high-density plasma 2810 (described later), providing a protective layer can mitigate damage. As a result, an increase in particles during processing can be suppressed.

[0399] The high-frequency generator 2803 has the function of generating microwaves in the range of, for example, 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to a mode converter 2805 via a waveguide 2804. The mode converter 2805 converts the microwaves transmitted in TE mode to TEM mode. The microwaves are then transmitted to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 has multiple slot holes, and the microwaves pass through the slot holes and a dielectric plate 2809. An electric field is then generated below the dielectric plate 2809, generating a high-density plasma 2810. The high-density plasma 2810 contains ions and radicals depending on the gas species supplied from the gas supply source 2801. For example, oxygen radicals are present.

[0400] At this time, the ions and radicals generated by the high-density plasma 2810 can modify the film or the like on the substrate 2811. It may be preferable to apply a bias to the substrate 2811 side using a high-frequency power supply 2816. For example, an RF (Radio Frequency) power supply with a frequency of 13.56 MHz, 27.12 MHz, or the like may be used as the high-frequency power supply 2816. By applying a bias to the substrate side, ions in the high-density plasma 2810 can be efficiently delivered to the depths of openings in the film or the like on the substrate 2811.

[0401] For example, oxygen radical treatment using high density plasma 2810 can be performed in chamber 2706b or chamber 2706c by introducing oxygen from gas supply source 2801.

[0402] Next, chamber 2706a and chamber 2706d will be described with reference to the cross-sectional schematic diagram shown in FIG.

[0403] Chamber 2706a and chamber 2706d are chambers capable of irradiating an object to be treated with electromagnetic waves, for example. Chamber 2706a and chamber 2706d differ only in the type of electromagnetic waves. Since the other configurations are largely common, they will be described together below.

[0404] Chamber 2706a and chamber 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. Also, outside chamber 2706a and chamber 2706d, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided.

[0405] The gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. The vacuum pump 2828 is connected to an exhaust port 2830 via a valve 2829. The lamp 2820 is disposed opposite a substrate holder 2825. The substrate holder 2825 has a function of holding a substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 that has a function of heating the substrate 2824.

[0406] A light source capable of emitting electromagnetic waves such as visible light or ultraviolet light may be used as the lamp 2820. For example, a light source capable of emitting electromagnetic waves having a peak wavelength of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0407] For example, the lamp 2820 may be a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp.

[0408] For example, the electromagnetic waves emitted from the lamps 2820 can be partially or completely absorbed by the substrate 2824, thereby modifying the film on the substrate 2824. For example, defects can be generated or reduced, or impurities can be removed. Note that if the process is performed while the substrate 2824 is heated, defects can be generated or reduced, or impurities can be removed efficiently.

[0409] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamp 2820, thereby heating the substrate 2824. In this case, the substrate holder 2825 does not need to have the heating mechanism 2826 inside.

[0410] For the vacuum pump 2828, refer to the description of the vacuum pump 2817. For the heating mechanism 2826, refer to the description of the heating mechanism 2813. For the gas supply source 2821, refer to the description of the gas supply source 2801.

[0411] The microwave processing apparatus that can be used in this embodiment is not limited to the above. A microwave processing apparatus 2900 shown in Fig. 29 can be used. The microwave processing apparatus 2900 has a quartz tube 2901, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a gas pipe 2806, a vacuum pump 2817, a valve 2818, and an exhaust port 2819. The microwave processing apparatus 2900 also has a substrate holder 2902 that holds multiple substrates 2811 (2811_1 to 2811_n, n is an integer of 2 or more) inside the quartz tube 2901. The microwave processing apparatus 2900 may also have heating means 2903 outside the quartz tube 2901.

[0412] Microwaves generated by a high-frequency generator 2803 are irradiated onto a substrate placed in a quartz tube 2901 via a waveguide 2804. A vacuum pump 2817 is connected to an exhaust port 2819 via a valve 2818, allowing adjustment of the pressure inside the quartz tube 2901. A gas supply source 2801 is connected to a gas pipe 2806 via a valve 2802, allowing a desired gas to be introduced into the quartz tube 2901. A heating means 2903 can heat the substrate 2811 in the quartz tube 2901 to a desired temperature. Alternatively, the heating means 2903 may heat the gas supplied from the gas supply source 2801. The microwave processing device 2900 can simultaneously perform a heat treatment and a microwave treatment on the substrate 2811. Alternatively, the microwave treatment can be performed after the substrate 2811 is heated. Alternatively, a heat treatment can be performed on the substrate 2811 after the microwave treatment.

[0413] The substrates 2811_1 to 2811_n may all be processing substrates for forming semiconductor devices or memory devices, or some of the substrates may be dummy substrates. For example, the substrates 2811_1 and 2811_n may be dummy substrates, and the substrates 2811_2 to 2811_n-1 may be processing substrates. Alternatively, the substrates 2811_1, 2811_2, 2811_n-1, and 2811_n may be dummy substrates, and the substrates 2811_3 to 2811_n-2 may be processing substrates. Using dummy substrates is preferable because multiple processing substrates can be uniformly processed during microwave processing or heat treatment, reducing variations between processing substrates. For example, placing a dummy substrate on the processing substrate closest to the high-frequency generator 2803 and the waveguide 2804 is preferable because it prevents the processing substrate from being directly exposed to microwaves.

[0414] By using the above manufacturing apparatus, it is possible to modify the film while suppressing the inclusion of impurities in the processed object.

[0415] <Modification of Semiconductor Device> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS.

[0416] <Semiconductor Device Modification 1> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIG.

[0417] Fig. 30A shows a top view of the semiconductor device. Fig. 30B shows a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 30A. For a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 30A, refer to transistor 200 shown in Fig. 1B. Note that some elements are omitted from the top view in Fig. 30A for clarity.

[0418] 30, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Configuration example of semiconductor device>. In this section, the materials described in detail in <Configuration example of semiconductor device> can also be used as the materials constituting the semiconductor device.

[0419] The semiconductor device illustrated in Figure 30 is a modified example of the semiconductor device illustrated in Figure 1. In the semiconductor device illustrated in Figure 30, the transistor 200 has a configuration including n oxides 230 (oxides 230_1 to 230_n: n is a natural number), which is different from the semiconductor device illustrated in Figure 1. Each of the oxides 230_1 to 230_n has a channel formation region.

[0420] 30, a conductor 260 is provided on the top surface and side surface of multiple channel formation regions via an insulator 250. The conductor 246 (conductor 246a and conductor 246b) extends in the A3-A4 direction and is electrically connected to the oxides 230_1 to 230_n via the conductor 240. Similarly to the semiconductor device shown in FIG. 1, the conductor 240a penetrates the opening region 400a, and the conductor 240b penetrates the opening region 400b.

[0421] That is, in the semiconductor device shown in FIG. 30, the transistor 200 has multiple channel formation regions for one gate electrode. The transistor 200 shown in FIG. 30 can obtain a large on-state current by having multiple channel formation regions. Furthermore, each channel formation region has a structure covered with the gate electrode, i.e., an s-channel structure, and therefore a large on-state current can be obtained in each channel formation region. Alternatively, in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the conductor 260 does not overlap with the oxide 230b, relative to the bottom surface of the insulator 222, is lower than the height of the interface between the top surface of the oxide 230b and the insulator 250. Therefore, a large on-state current can be obtained in each channel formation region.

[0422] Note that the other configurations can be referred to the configuration of the semiconductor device shown in FIG.

[0423] <Modification 2 of Semiconductor Device> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIG.

[0424] Fig. 31A shows a top view of the semiconductor device. Fig. 31B shows a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 31A. For a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 31A, refer to transistor 200 shown in Fig. 1B. Note that some elements are omitted from the top view in Fig. 31A for clarity.

[0425] 31, structures having the same functions as those constituting the semiconductor device shown in <Configuration example of semiconductor device> are denoted by the same reference numerals. Also in this section, the materials described in detail in <Configuration example of semiconductor device> can be used as the constituent materials of the semiconductor device.

[0426] The semiconductor device illustrated in Figure 31 is a modification of the semiconductor device illustrated in Figure 30. In the semiconductor device illustrated in Figure 31, the transistor 200 has n oxides 230 (oxides 230_1 to 230_n: n is a natural number). Each of the oxides 230_1 to 230_n has a channel formation region.

[0427] 31, a conductor 260 is provided on the top surface and side surface of multiple channel formation regions via an insulator 250. The conductor 246 (conductor 246a and conductor 246b) extends in the A3-A4 direction and is electrically connected to the oxides 230_1 to 230_n via the conductor 240. Similarly to the semiconductor device shown in FIG. 1, the conductor 240a penetrates the opening region 400a, and the conductor 240b penetrates the opening region 400b.

[0428] 31, a transistor 200 having a plurality of channel formation regions is arranged adjacent to an oxide 230_1 arranged at an end of the transistor 200, and a transistor 200D having at least an oxide 230D is arranged adjacent to an oxide 230_n arranged at an end of the transistor 200. Similarly, a transistor 200D is arranged adjacent to an oxide 230_n arranged at an end of the transistor 200.

[0429] That is, the semiconductor device shown in FIG. 31 differs from the semiconductor device shown in FIG. 30 in that a transistor 200D is provided at one or both ends of the direction in which a plurality of channel formation regions of the transistor 200 are arranged in parallel.

[0430] Here, the transistor 200D may not be electrically connected to any one or all of the gate wiring, source wiring, and drain wiring. That is, the transistor 200D may be provided in a state where it does not function as a transistor. Therefore, the transistor 200D may be referred to as a dummy transistor (sacrificial transistor).

[0431] Furthermore, it is preferable that the shortest distance between the oxide 230_D and the oxide 230_1 and the shortest distance between the oxide 230_1 and the oxide 230_2 are approximately equal. Similarly, it is preferable that the shortest distance between the oxide 230_D and the oxide 230_n and the shortest distance between the oxide 230_n-1 and the oxide 230_n are approximately equal. Note that, when n is 1, it is preferable that the shortest distance between one oxide 230_D and the oxide 230_1 and the shortest distance between the other oxide 230_D and the oxide 230_1 are approximately equal.

[0432] Furthermore, the shortest distance between the conductor 242a and the conductor 242b in the oxide 230_D may be approximately equal to or greater than the shortest distance between the conductor 242a and the conductor 242b in the oxide 230_1. Similarly, the shortest distance between the conductor 242a and the conductor 242b in the oxide 230_D may be approximately equal to or greater than the shortest distance between the conductor 242a and the conductor 242b in the oxide 230_n.

[0433] When multiple oxides 230 are formed in parallel, the oxides 230 located at the edge are likely to have variations in shape due to processing. In addition, in the process of removing a part of the insulator 280 and the stacked structure on the channel formation region of the oxide 230 to form an opening and expose a part of the top surface of the oxide 230, the area of ​​the exposed top surface of the oxide 230 may vary depending on the shape of the edge of the removed region (also called the opening) or the distance between the oxide 230 and the edge of the opening.

[0434] Therefore, by providing transistor 200D as shown in Figure 31, even if a shape defect occurs in oxide 230_D of transistor 200D or in the opening on oxide 230_D, the shape of oxide 230 formed in the area sandwiched between transistors 200D becomes uniform.

[0435] Therefore, by arranging the transistor 200D adjacent to the transistor 200, when a plurality of transistors 200 are provided, the variation in characteristics among the plurality of transistors 200 can be reduced.

[0436] Furthermore, when a plurality of oxides 230 are provided at equal intervals in a certain region, the circuit design can be easily performed by changing the wiring layout.

[0437] 31, the transistor 200 has multiple channel formation regions for one gate electrode. The transistor 200 shown in FIG. 31 can obtain a large on-state current by having multiple channel formation regions. Furthermore, each channel formation region has a structure covered with the gate electrode, i.e., an s-channel structure, and therefore a large on-state current can be obtained in each channel formation region. Alternatively, in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the conductor 260 does not overlap with the oxide 230b, relative to the bottom surface of the insulator 222, is lower than the height of the interface between the top surface of the oxide 230b and the insulator 250. Therefore, a large on-state current can be obtained in each channel formation region.

[0438] Note that the other configurations can be referred to the configuration of the semiconductor device shown in FIG.

[0439] <Semiconductor Device Modification 3> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIG.

[0440] Fig. 32A shows a top view of the semiconductor device. Fig. 32B shows a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 32A. For a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 32A, refer to transistor 200 shown in Fig. 1B. Note that some elements are omitted from the top view in Fig. 32A for clarity.

[0441] 32, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Configuration example of semiconductor device>. In this section, the materials described in detail in <Configuration example of semiconductor device> can also be used as the materials constituting the semiconductor device.

[0442] The semiconductor device described in this section is a modified example of the semiconductor device shown in FIG. 31. Therefore, the transistor 200 differs from the semiconductor device shown in FIG. 31 in that it has an oxide 230 having n channel formation regions (note that the n channel formation regions are channel formation regions 235_1 to 235_n: n is a natural number). In addition, a conductor 260 is provided on the top surface and side surface of the multiple channel formation regions via an insulator 250.

[0443] 1, the conductor 240a penetrates the opening region 400a, and the conductor 240b penetrates the opening region 400b.

[0444] 32 shows the case where n=2 for ease of explanation. Therefore, the transistor 200 has an oxide 230 having two channel formation regions (a channel formation region 235_1 and a channel formation region 235_2).

[0445] In the oxide 230, the source region and the drain region are electrically connected to the conductor 242a or the conductor 242b. Therefore, for example, the conductor 242a and the conductor 246a are electrically connected via at least one or more conductors 240a, so that a voltage can be applied to multiple channel formation regions (channel formation regions 235_1 to 235_n).

[0446] That is, it is not necessary to provide n conductors 240 for a transistor 200 having n channel formation regions 235. For a transistor having n channel formation regions 235, it is preferable to provide one or more conductors 240, preferably one or more but less than n.

[0447] As transistors become smaller, the size of the plug that electrically connects the transistor to the conductor that functions as wiring also needs to be smaller. Also, the contact area between the conductor that functions as a plug and the conductor that functions as wiring becomes smaller, which tends to increase the wiring resistance.

[0448] In the semiconductor device described in this section, since a transistor 200 having n channel formation regions is provided with a number of plugs less than n, the size of each conductor 240 functioning as a plug can be made larger than, for example, the conductor 240 described in the semiconductor device shown in Figure 31, thereby reducing power consumption.

[0449] 32, a transistor 200 having a plurality of channel formation regions includes a transistor 200D having at least an oxide 230D arranged adjacent to an oxide 230_1 arranged at an end of the transistor 200. Similarly, a transistor 200D is arranged adjacent to an oxide 230_n arranged at an end of the transistor 200.

[0450] 32, a conductor 260 is provided on the top and side surfaces of multiple channel formation regions via an insulator 250. In addition, the conductor 246a and the conductor 246b extend in the A3-A4 direction and are electrically connected to the oxide 230_n.

[0451] 32, a transistor 200 having a plurality of channel formation regions includes a transistor 200D having at least an oxide 230D arranged adjacent to a channel formation region 235_1 arranged at an end of the transistor 200. Similarly, a transistor 200D is arranged adjacent to a channel formation region 235_n arranged at an end of the transistor 200.

[0452] That is, the transistor 200D is provided at one end or both ends in the direction in which the plurality of channel formation regions of the transistor 200 are arranged in parallel.

[0453] Here, the transistor 200D may not be electrically connected to any one or all of the gate wiring, source wiring, and drain wiring. That is, the transistor 200D may be provided in a state where it does not function as a transistor. Therefore, the transistor 200D may be referred to as a dummy transistor (sacrificial transistor).

[0454] Furthermore, it is preferable that the shortest distance between the oxide 230_D and the oxide 230_1 and the shortest distance between the oxide 230_1 and the oxide 230_2 are approximately equal. Similarly, it is preferable that the shortest distance between the oxide 230_D and the oxide 230_n and the shortest distance between the oxide 230_n-1 and the oxide 230_n are approximately equal. Note that, when n is 1, it is preferable that the shortest distance between one oxide 230_D and the oxide 230_1 and the shortest distance between the other oxide 230_D and the oxide 230_1 are approximately equal.

[0455] Furthermore, the shortest distance between the conductor 242a and the conductor 242b in the oxide 230_D may be approximately equal to or greater than the shortest distance between the conductor 242a and the conductor 242b in the oxide 230_1. Similarly, the shortest distance between the conductor 242a and the conductor 242b in the oxide 230_D may be approximately equal to or greater than the shortest distance between the conductor 242a and the conductor 242b in the oxide 230_n.

[0456] In addition, the difference between the shortest distance between conductor 242a and conductor 242b in oxide 230_D and the shortest distance between conductor 242a and conductor 242b in oxide 230_1 may be larger than the difference between the shortest distance between conductor 242a and conductor 242b in oxide 230_1 and the shortest distance between conductor 242a and conductor 242b in oxide 230_2.

[0457] When multiple channel formation regions 235 are formed in parallel, the channel formation regions 235 located at the edge are likely to have variations in shape due to processing. In addition, in the process of removing a part of the insulator 280 and the stacked structure on the channel formation region of the oxide 230 to form an opening and expose a part of the top surface of the oxide 230, the area of ​​the exposed top surface of the oxide 230 may vary depending on the shape of the edge of the removed region (also referred to as the opening) or the distance between the oxide 230 and the edge of the opening.

[0458] Therefore, by providing transistor 200D as shown in Figure 32, even if a shape defect occurs in oxide 230_D of transistor 200D or in the opening on oxide 230_D, the shape of oxide 230 formed in the area sandwiched between transistors 200D becomes uniform.

[0459] Therefore, by arranging the transistor 200D adjacent to the transistor 200, when a plurality of transistors 200 are provided, the variation in characteristics among the plurality of transistors 200 can be reduced.

[0460] 32, the transistor 200 has multiple channel formation regions for one gate electrode. The transistor 200 shown in FIG. 32 can obtain a large on-state current by having multiple channel formation regions. Furthermore, each channel formation region has a structure covered with the gate electrode, i.e., an s-channel structure, and therefore a large on-state current can be obtained in each channel formation region. Alternatively, in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the conductor 260 does not overlap with the oxide 230b, relative to the bottom surface of the insulator 222, is lower than the height of the interface between the top surface of the oxide 230b and the insulator 250. Therefore, a large on-state current can be obtained in each channel formation region.

[0461] Note that the other configurations can be referred to the configuration of the semiconductor device shown in FIG.

[0462] <Modification 4 of the semiconductor device> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIG.

[0463] FIG. 33A shows a top view of semiconductor device 500. The x-axis in FIG. 33A is parallel to the channel length direction of transistor 200, and the y-axis is perpendicular to the x-axis. FIG. 33B is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in FIG. 33A, and is also a cross-sectional view of transistor 200 in the channel length direction. FIG. 33C is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in FIG. 33A, and is also a cross-sectional view of opening region 400c. Note that some elements have been omitted from the top view in FIG. 33A for clarity.

[0464] 33, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Configuration example of semiconductor device>. In this section, the materials described in detail in <Configuration example of semiconductor device> can also be used as the materials constituting the semiconductor device.

[0465] The semiconductor device 500 shown in Fig. 33 is a modification of the semiconductor device shown in Fig. 1. The semiconductor device 500 shown in Fig. 33 differs from the semiconductor device shown in Fig. 1 in that an opening region 400c is formed in a region of the insulator 282 and the insulator 280 that does not overlap with the transistor 200.

[0466] The semiconductor device 500 has a plurality of transistors 200, a plurality of opening regions 400a, a plurality of opening regions 400b, and a plurality of opening regions 400c arranged in a matrix. Furthermore, a plurality of conductors 260, which function as gate electrodes of the transistors 200, are provided extending in the y-axis direction. The opening regions 400a and 400b are disposed on the oxide 230, as in the semiconductor device shown in FIG. 1 , but the opening region 400c is formed in a region that does not overlap with the oxide 230 and the conductors 260. Furthermore, a sealing portion 265 is formed to surround the plurality of transistors 200, the plurality of conductors 260, the plurality of opening regions 400a, the plurality of opening regions 400b, and the plurality of opening regions 400c. The number, arrangement, and size of the transistors 200, the conductors 260, the opening regions 400a, the opening regions 400b, and the opening regions 400c are not limited to the structure shown in FIG. 33 and may be appropriately set according to the design of the semiconductor device 500.

[0467] As shown in Fig. 2B, opening region 400a and opening region 400b are arranged to overlap conductor 240a and conductor 240b. In contrast, as shown in Fig. 2C, opening region 400c does not have conductor 240 arranged to overlap, but the other structures are similar to opening region 400a and opening region 400b. Therefore, for details of opening region 400c, the description of opening region 400 in Fig. 2B above can be referred to.

[0468] By providing the opening region 400c that does not overlap with the transistor 200 and performing heat treatment, a larger amount of oxygen contained in the insulator 280 can be out-diffused while supplying oxygen to the oxide 230 of the transistor 200. This can prevent excessive oxygen from being supplied to the transistor 200 even when the arrangement density of the transistors 200 is low, that is, when the transistors 200 are sparsely arranged.

[0469] 33A, the shape of the opening region 400c in top view is substantially rectangular, but the present invention is not limited to this. For example, the shape of the opening region 400c in top view may be rectangular, elliptical, circular, diamond-shaped, or a combination thereof. The area and spacing of the opening regions 400c can be appropriately set in accordance with the design of the semiconductor device including the transistors 200. For example, in a region where the density of the transistors 200 is low, the area of ​​the opening regions 400c can be increased or the spacing between the opening regions 400c can be narrowed. For example, in a region where the density of the transistors 200 is high, the area of ​​the opening regions 400c can be narrowed or the spacing between the opening regions can be widened.

[0470] According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with favorable reliability can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to another embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided.

[0471] The structures, methods, and the like described in this embodiment can be used in appropriate combination with other structures, methods, and the like described in this embodiment or other embodiments.

[0472] (Embodiment 2) In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0473] [Storage device 1] 34 illustrates an example of a semiconductor device (memory device) according to one embodiment of the present invention. In the semiconductor device according to one embodiment of the present invention, a transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistors 300 and 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.

[0474] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. The transistor 200 has a low off-state current; therefore, when used in a memory device, the stored data can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the memory device can be sufficiently reduced.

[0475] 34, a wiring 1001 is electrically connected to the source of a transistor 300, and a wiring 1002 is electrically connected to the drain of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of a transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of a capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0476] Moreover, the memory device shown in FIG. 34 can be arranged in a matrix to form a memory cell array.

[0477] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel type or an n-channel type.

[0478] Here, in the transistor 300 shown in FIG. 34, a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. In addition, a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. In addition, although the case where the convex portion is formed by processing a part of the semiconductor substrate has been shown, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0479] Note that the transistor 300 illustrated in FIG. 34 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0480] <Capacitor element 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 functioning as a first electrode, a conductor 120 functioning as a second electrode, and an insulator 130 functioning as a dielectric. Here, the insulator 130 is preferably the same as the insulator 286 described in the above embodiment.

[0481] The conductor 112 and the conductor 110 can be formed at the same time. The conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 112 and the conductor 110 correspond to the conductor 246 in the above embodiment.

[0482] 34, the conductor 112 and the conductor 110 are shown as having a single layer structure, but are not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0483] The insulator 130 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be formed as a stacked layer or a single layer.

[0484] For example, it is preferable to use a layered structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitor 100 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitor 100 can improve its dielectric strength by having an insulator with high dielectric strength, thereby preventing electrostatic breakdown of the capacitor 100.

[0485] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0486] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide or resin with pores, etc.

[0487] <Wiring layer> Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductor functioning as a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0488] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328 and 330 electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings.

[0489] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0490] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 34, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0491] Similarly, a conductor 218 and a conductor (conductor 205) constituting the transistor 200 are embedded in the insulators 210, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided over the conductor 120 and the insulator 130.

[0492] Here, similar to the insulator 241 described in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 that functions as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0493] The insulator 217 may be, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 217 is provided in contact with the insulators 210, 212, 214, and 222, and therefore can prevent impurities such as water or hydrogen from the insulator 210 or the insulator 216 from mixing into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because it has a high barrier property against hydrogen. In addition, the insulator 217 can prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0494] The insulator 217 can be formed by a method similar to that of the insulator 241. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0495] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0496] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0497] For example, insulators 150, 210, 352, and 354 preferably have an insulator with a low dielectric constant. For example, the insulator preferably includes fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, pore-containing silicon oxide, or resin. Alternatively, the insulator preferably has a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or pore-containing silicon oxide, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with resin to form a thermally stable layered structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (e.g., nylon, aramid), polyimide, polycarbonate, and acrylic.

[0498] Furthermore, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of oxygen and impurities such as hydrogen. Therefore, the insulators 214, 212, and 350 can be formed using insulators that have a function of suppressing the permeation of oxygen and impurities such as hydrogen.

[0499] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0500] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0501] For example, the conductors 328, 330, 356, conductor 218, and conductor 112 can be formed using a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. High-melting-point materials such as tungsten or molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed using a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce wiring resistance.

[0502] <Wiring or plug in layer provided with oxide semiconductor> When an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0503] 34, for example, an insulator 241 may be provided between the insulator 280 and the insulator 286 and the conductor 240. When the insulator 241 is provided in contact with the insulator 222, the insulator 282, and the insulator 283, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties.

[0504] That is, the insulator 241 can prevent excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 240. Furthermore, the insulator 241 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 240.

[0505] The insulator 241 may be an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide. Silicon nitride is particularly preferable because it has a high barrier property against hydrogen. Other examples that can be used include metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide.

[0506] As described in the above embodiment, the transistor 200 may be sealed with the insulators 212, 214, 282, and 283. Such a structure can reduce the intrusion of hydrogen contained in the insulators 274, 150, and the like into the insulator 280 and the like.

[0507] Here, conductor 240 penetrates insulator 283, and conductor 218 penetrates insulator 214 and insulator 212. As described above, insulator 241 is provided in contact with conductor 240, and insulator 217 is provided in contact with conductor 218. This makes it possible to reduce hydrogen that gets mixed into the inside of insulators 212, 214, 282, and 283 via conductors 240 and 218. In this way, transistor 200 is sealed with insulators 212, 214, 282, 283, insulator 241, and insulator 217, making it possible to reduce the intrusion of impurities such as hydrogen contained in insulator 274 from the outside.

[0508] As described in the previous embodiment, the opening region 400 is formed in the insulator 282 and the insulator 280, and the conductor 240 penetrates the opening region 400. The opening region 400 is provided not only around the conductor 240 in contact with the source electrode or drain electrode of the transistor 200, but also around the conductor 240 in contact with the conductor 218. With this configuration, an opening in which the conductor 240 in contact with the source electrode or drain electrode of the transistor 200 is embedded and an opening in which the conductor 240 in contact with the conductor 218 is embedded can be formed relatively easily at the same time.

[0509] <Dicing line> The following describes dicing lines (sometimes called scribe lines, dividing lines, or cutting lines) that are provided when dividing a large-area substrate into individual semiconductor elements to extract multiple semiconductor devices in chip form. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (divide) the multiple semiconductor devices.

[0510] 34, for example, it is preferable to design the insulator 282, the insulator 280, the insulator 272, the insulator 222, and the insulator 216 so that the area where the insulator 283 and the insulator 214 contact each other overlaps with the dicing line. That is, openings are provided in the insulators 282, 280, 272, 222, and 216 near the area that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200.

[0511] That is, the insulator 214 and the insulator 283 are in contact with each other at the openings provided in the insulators 282 , 280 , 272 , 222 , and 216 .

[0512] With this structure, the transistor 200 can be surrounded by the insulator 212, the insulator 214, the insulator 282, and the insulator 283. At least one of the insulators 212, 214, 282, and 283 has a function of suppressing diffusion of oxygen, hydrogen, and water. Therefore, even when the substrate is divided into a plurality of chips by dividing the substrate into each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side surface of the divided substrate and diffusing into the transistor 200.

[0513] Furthermore, this structure can prevent excess oxygen in the insulator 280 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 is efficiently supplied to the oxide in which a channel is formed in the transistor 200. The oxygen can reduce oxygen vacancies in the oxide in which a channel is formed in the transistor 200. This allows the oxide in which a channel is formed in the transistor 200 to be an oxide semiconductor with a low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

[0514] 34, the shape of the capacitor 100 is a planar type, but the shape of the capacitor 100 in the memory device of this embodiment is not limited to this. For example, as shown in FIG. 35, the shape of the capacitor 100 may be a cylindrical type. Note that the memory device shown in FIG. 35 has the same configuration below the insulator 150 as the semiconductor device shown in FIG.

[0515] The capacitor 100 shown in FIG. 35 includes an insulator 150 on an insulator 130, an insulator 142 on the insulator 150, a conductor 115 disposed in an opening formed in the insulator 150 and the insulator 142, an insulator 145 on the conductor 115 and the insulator 142, a conductor 125 on the insulator 145, and an insulator 152 on the conductor 125 and the insulator 145. At least a portion of the conductor 115, the insulator 145, and the conductor 125 are disposed in the openings formed in the insulator 150 and the insulator 142. An insulator 154 is disposed on the insulator 152, and a conductor 153 and an insulator 156 are disposed on the insulator 154. The conductor 140 is disposed in an opening formed in the insulator 130, the insulator 150, the insulator 142, the insulator 145, the insulator 152, and the insulator 154.

[0516] The conductor 115 functions as the lower electrode of the capacitor 100, the conductor 125 functions as the upper electrode of the capacitor 100, and the insulator 145 functions as the dielectric of the capacitor 100. The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surfaces of the openings in the insulators 150 and 142, allowing for a larger capacitance per unit area. Therefore, the deeper the openings, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0517] The insulator 152 may be an insulator that can be used for the insulator 280. The insulator 142 preferably functions as an etching stopper when forming an opening in the insulator 150, and may be an insulator that can be used for the insulator 214.

[0518] The shape of the openings formed in the insulator 150 and the insulator 142 when viewed from above may be rectangular, a polygonal shape other than a rectangular, a polygonal shape with curved corners, or a circular shape including an ellipse. Here, it is preferable that the area over which the openings and the transistor 200 overlap in the top view is large. With such a configuration, the area occupied by a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0519] The conductor 115 is disposed in contact with the insulator 142 and an opening formed in the insulator 150. The top of the conductor 115 preferably roughly coincides with the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening in the insulator 130. The conductor 115 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using, for example, a conductor that can be used for the conductor 205.

[0520] The insulator 145 is disposed to cover the conductor 115 and the insulator 142. For example, the insulator 145 is preferably formed by an ALD method, a CVD method, or the like. The insulator 145 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer. For example, the insulator 145 can be an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order.

[0521] Furthermore, it is preferable to use a material with high dielectric strength, such as silicon oxynitride, or a high dielectric constant (high-k) material for the insulator 145. Alternatively, a stacked structure of a material with high dielectric strength and a material with high dielectric constant (high-k) may be used.

[0522] Examples of high-dielectric-constant (high-k) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. Using such high-k materials ensures sufficient capacitance of the capacitor 100 even when the insulator 145 is thick. By thickening the insulator 145, leakage current between the conductor 115 and the conductor 125 can be suppressed.

[0523] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with vacancies, and resin. For example, silicon nitride (SiN) formed using the ALD method is x ), silicon oxide (SiO x ), silicon nitride (SiN x ) can be used. Alternatively, an insulating film can be used in which zirconium oxide, silicon oxide formed by ALD, and zirconium oxide are stacked in this order. By using such an insulator with high dielectric strength, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0524] The conductor 125 is arranged to fill the openings formed in the insulator 142 and the insulator 150. The conductor 125 is electrically connected to the wiring 1005 via the conductor 140 and the conductor 153. The conductor 125 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using, for example, a conductor that can be used for the conductor 205.

[0525] The conductor 153 is provided over the insulator 154 and is covered with the insulator 156. The conductor 153 may be any conductor that can be used for the conductor 112, and the insulator 156 may be any insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the top surface of the conductor 140 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[0526] [Storage device 2] An example of a semiconductor device (memory device) according to one embodiment of the present invention is illustrated in FIG.

[0527] <Memory device configuration example 1> 36 is a cross-sectional view of a semiconductor device having a memory device 290. The memory device 290 shown in FIG. 36 includes a capacitor device 292 in addition to the transistor 200 shown in FIGS. 1A to 1D. FIG. 36 corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

[0528] The capacitor 292 includes a conductor 242b, an insulator 271b provided on the conductor 242b, an insulator 272 provided in contact with the top surface of the insulator 271b, a side surface of the insulator 271b, and a side surface of the conductor 242b, and a conductor 294 on the insulator 272. That is, the capacitor 292 constitutes a metal-insulator-metal (MIM) capacitor. Note that one of a pair of electrodes included in the capacitor 292, i.e., the conductor 242b, can also serve as a source electrode of a transistor. Furthermore, a dielectric layer included in the capacitor 292 can also serve as a protective layer provided in the transistor, i.e., the insulator 271 and the insulator 272. Therefore, part of the manufacturing process for the transistor can be used in the manufacturing process for the capacitor 292, resulting in a highly productive semiconductor device. Furthermore, one of the pair of electrodes of the capacitor 292, that is, the conductor 242b, also serves as the source electrode of the transistor, so that the area in which the transistor and the capacitor are arranged can be reduced.

[0529] The conductor 294 may be made of, for example, a material that can be used for the conductor 242.

[0530] As described in the previous embodiment, the opening regions 400a and 400b are formed in the insulators 282 and 280, respectively, and the conductor 240a penetrates the opening region 400a. However, the conductor 240 is not provided in the opening region 400b, and the recess on the insulator 283 is filled with the insulator 274. The opening regions 400a and 400b are disposed above the conductors 242a and 242b, respectively, and are disposed approximately symmetrically with respect to the conductor 260 of the transistor 200 as the axis of symmetry. Therefore, approximately equal amounts of oxygen can be supplied to the oxide 230 of the transistor 200 from the source side and the drain side. This prevents a large imbalance in the amount of oxygen vacancies between the source side and the drain side in the channel formation region of the transistor 200.

[0531] <Modifications of memory devices> Hereinafter, an example of a semiconductor device including a transistor 200, an opening region 400, and a capacitor 292 according to one embodiment of the present invention, which is different from those shown in the previous <Configuration Example 1 of Memory Device>, will be described with reference to FIGS. 37A , 37B , and 38 . Note that in the semiconductor devices shown in FIGS. 37A , 37B , and 38 , structures having the same functions as those in the semiconductor device shown in the previous embodiment and <Configuration Example 1 of Memory Device> (see FIG. 36 ) are denoted by the same reference numerals. Note that in this section, the transistor 200, the opening region 400, and the capacitor 292 can be made of materials described in detail in the previous embodiment and <Configuration Example 1 of Memory Device>. Note that although the memory device shown in FIG. 36 is used as the memory device in FIGS. 37A , 37B , 38 , and the like, the memory device is not limited to this.

[0532] <<Memory Device Variation 1>> An example of a semiconductor device 600 including a transistor 200a, a transistor 200b, a capacitor 292a, and a capacitor 292b according to one embodiment of the present invention will be described below with reference to FIG. 37A.

[0533] 37A is a cross-sectional view in the channel length direction of a semiconductor device 600 including a transistor 200a, a transistor 200b, a capacitor 292a, and a capacitor 292b. The capacitor 292a includes a conductor 242a, an insulator 271a on the conductor 242a, an insulator 272 in contact with the top surface of the insulator 271a, a side surface of the insulator 271a, and a side surface of the conductor 242a, and a conductor 294a on the insulator 272. The capacitor 292b includes a conductor 242b, an insulator 271b on the conductor 242b, an insulator 272 in contact with the top surface of the insulator 271b, a side surface of the insulator 271b, and a side surface of the conductor 242b, and a conductor 294b on the insulator 272.

[0534] As shown in FIG. 37A , the semiconductor device 600 has a symmetrical configuration with the dashed line A3-A4 as the axis of symmetry. Conductor 242c serves as both the source electrode or drain electrode of transistor 200a and the source electrode or drain electrode of transistor 200b. An insulator 271c is provided on conductor 242c. An oxide 243c is provided below conductor 242c. Conductor 246, which functions as wiring, and transistors 200a and 200b are also connected by conductor 240, which functions as a plug. By configuring the two transistors, two capacitance devices, and the wiring and plug connections as described above, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0535] The configuration example of the semiconductor device shown in FIG. 36 can be referred to for the configurations and effects of the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b.

[0536] As described in the previous embodiment, opening regions 400a, 400b, and 400d are formed in insulator 282 and insulator 280, and conductor 240 penetrates opening region 400d. However, conductor 240 is not provided in opening regions 400a and 400b, and insulator 274 is embedded in the recess on insulator 283. Opening regions 400a, 400b, and 400d are disposed above conductor 242a, conductor 242b, and conductor 242c, respectively. Opening regions 400a and 400d are disposed approximately axisymmetrically with respect to conductor 260 of transistor 200a, and opening regions 400b and 400d are disposed approximately axisymmetrically with respect to conductor 260 of transistor 200b. Therefore, the oxide 230 of the transistor 200a and the transistor 200b can be supplied with approximately equal amounts of oxygen from the source side and the drain side, which prevents a large imbalance in the amount of oxygen vacancies between the source side and the drain side in the channel formation regions of the transistor 200a and the transistor 200b.

[0537] <<Memory Device Variation 2>> In the above, the transistor 200a, the transistor 200b, the capacitor 292a, and the capacitor 292b are given as examples of the configuration of the semiconductor device. However, the semiconductor device described in this embodiment is not limited to this. For example, as shown in FIG. 37B , a configuration may be adopted in which a semiconductor device 600 and a semiconductor device having a similar configuration to the semiconductor device 600 are connected via a capacitor. Furthermore, a configuration may be adopted in which an opening region 400 is disposed between adjacent semiconductor devices 600 and semiconductor devices having a similar configuration to the semiconductor device 600. In this specification, a semiconductor device including the transistor 200a, the transistor 200b, the capacitor 292a, and the capacitor 292b is referred to as a cell. The configurations of the transistor 200a, the transistor 200b, the capacitor 292a, and the capacitor 292b can be understood by referring to the above descriptions of the transistor 200a, the transistor 200b, the capacitor 292a, and the capacitor 292b.

[0538] FIG. 37B is a cross-sectional view of a semiconductor device 600 having a transistor 200a, a transistor 200b, a capacitance device 292a, and a capacitance device 292b, and a cell having a configuration similar to that of the semiconductor device 600, connected via a capacitance section.

[0539] As shown in FIG. 37B, the conductor 294b, which functions as one electrode of the capacitance device 292b of the semiconductor device 600, also serves as one electrode of the capacitance device of a semiconductor device 601 having a similar configuration to the semiconductor device 600. Although not shown, the conductor 294a, which functions as one electrode of the capacitance device 292a of the semiconductor device 600, also serves as one electrode of the capacitance device of the semiconductor device adjacent to the left side of the semiconductor device 600, i.e., in the A1 direction in FIG. 37B. The same configuration is also true for the cells on the right side of the semiconductor device 601, i.e., in the A2 direction in FIG. 37B. In other words, a cell array (also referred to as a memory device layer) can be configured. This cell array configuration reduces the spacing between adjacent cells, thereby reducing the projected area of ​​the cell array and enabling higher integration. Furthermore, by arranging the cell array configuration shown in FIG. 37B in a matrix, a matrix cell array can be configured.

[0540] As described above, by forming the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b in the configuration shown in this embodiment, the cell area can be reduced, and miniaturization or high integration of a semiconductor device having a cell array can be achieved.

[0541] Furthermore, the cell array may be configured not only in a plane but also in a stacked configuration. Fig. 38 shows a cross-sectional view of a configuration in which cell arrays 610 are stacked in n layers. As shown in Fig. 38, by stacking multiple cell arrays (cell arrays 610_1 to 610_n), cells can be integrated and arranged without increasing the area occupied by the cell arrays. In other words, a 3D cell array can be configured.

[0542] The structures, methods, and the like described in this embodiment can be used in appropriate combination with other structures, methods, and the like described in this embodiment or other embodiments.

[0543] (Embodiment 3) 39A, 39B, and 40A to 40H will be used to describe a transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a memory device including a capacitor (hereinafter also referred to as an OS memory device) according to one embodiment of the present invention. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Because the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

[0544] <Storage device configuration example> 39A shows an example of the configuration of an OS memory device. The memory device 1400 has a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 has a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0545] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is connected to a memory cell in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 also includes, for example, a row decoder, a word line driver circuit, etc., and can select a row to access.

[0546] The memory device 1400 is supplied with a low power supply voltage (VSS) from the outside as power supply voltages, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470. Control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are also input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0547] The control logic circuit 1460 processes control signals (CE, WE, RE) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0548] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0549] 39A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited to this. For example, as shown in FIG. 39B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0550] 40A to 40H illustrate examples of memory cell configurations that can be applied to the above-described memory cell MC.

[0551] [DOSRAM] 40A to 40C show circuit configuration examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 40A includes a transistor M1 and a capacitor CA. The transistor M1 includes a gate (sometimes referred to as a top gate) and a back gate.

[0552] A first terminal of the transistor M1 is connected to a first terminal of the capacitor CA, a second terminal of the transistor M1 is connected to a wiring BIL, a gate of the transistor M1 is connected to a wiring WOL, a back gate of the transistor M1 is connected to a wiring BGL, and a second terminal of the capacitor CA is connected to a wiring LL.

[0553] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring LL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, the wiring LL may be set to ground potential or a low-level potential. It is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decr...

Claims

[Claim 1] an oxide semiconductor layer, a gate electrode, a source electrode, a drain electrode, a first insulator, a second insulator, a third insulator, a first conductor, and a second conductor; the gate electrode has a region located above the oxide semiconductor layer, the first insulator has a region located above the oxide semiconductor layer, the second insulator has a region located above the first insulator; the third insulator has a region located above the second insulator, the second insulator has a first opening overlapping the source electrode and a second opening overlapping the drain electrode; the third insulator contacts the side surface of the second insulator inside the first opening and the second opening and the top surface of the first insulator; the first conductor is electrically connected to the source electrode through the first opening; the second conductor is electrically connected to the drain electrode through the second opening; the first insulator has a third opening in a region between the source electrode and the drain electrode; The semiconductor device, wherein the gate electrode is disposed in the third opening.

Images