Semiconductor memory device and recording device, and method for controlling writing to semiconductor memory device in recording device

Abstract

To provide a semiconductor storage device, a recording device, and a writing control method for the semiconductor storage device in the recording device in order to solve the following problem: there is a case where a write state of an anti-fuse element cannot be accurately determined when a resistive element is connected in parallel to the anti-fuse element to improve ESD resistance.SOLUTION: A semiconductor storage device that controls writing to a memory unit having an anti-fuse element includes comparing means for comparing a voltage generated on both ends of a resistive element connected in series with a power supply line that energizes the anti-fuse element and a reference voltage and controls writing to the anti-fuse element of the memory unit based on the output of the comparing means when writing to the memory unit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device and a recording device that include an antifuse element, and a method for controlling writing to the semiconductor memory device in the recording device. [Background technology]

[0002] In recent years, semiconductor memory devices have been using OTP (One Time Programmable) memories to record product-specific information such as chip IDs and setting parameters after the product is completed. There are two types of OTP memories: those that use fuse elements and those that use anti-fuse elements. For example, Patent Document 1 discloses a configuration as a conventional technology that uses anti-fuse elements. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-196079 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-described conventional technology, the write state of the antifuse element is determined in a power supply state in which the voltage used for writing to the antifuse element is kept constant during a program operation. Therefore, when a resistance element is connected in parallel to the antifuse element to improve ESD (Electrostatic Discharge) resistance, the write state of the antifuse element may not be accurately determined.

[0005] An object of the present invention is to overcome the above-mentioned problem of the prior art, that is, the inability to accurately determine the written state of the anti-fuse element.

[0006] An object of the present invention is to provide a semiconductor memory device and a recording device that can accurately determine the write state of an anti-fuse element with improved surge resistance. [Means for solving the problem]

[0007] In order to achieve the above object, a semiconductor memory device according to one aspect of the present invention has the following configuration: A semiconductor memory device that controls writing to a memory unit having an anti-fuse element, A power supply line connected in series to the anti-fuse element 1st a comparison means for comparing a voltage generated across the resistor element with a reference voltage; a control means for controlling writing to the anti-fuse element of the memory unit based on the output of the comparison means when writing to the memory unit; death, The memory unit a second resistive element connected in parallel with the antifuse element; a driving element for controlling the conduction of the anti-fuse element; a third resistance element connected in series between the first resistance element connected in series to the power supply line and the anti-fuse element; It is characterized by: [Effects of the Invention]

[0008] According to the present invention, it is possible to accurately determine the write state of an anti-fuse element with improved surge resistance.

[0009] Other features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings, in which the same or similar elements are designated by the same reference numerals. [Brief explanation of the drawings]

[0010] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. [Figure 1] 1 is a circuit diagram including a memory unit of a semiconductor memory device according to a first embodiment of the present invention. [Figure 2] FIG. 4 is a circuit diagram including a memory section of a semiconductor memory device showing another aspect of the first embodiment. [Figure 3] FIG. 10 is a block diagram illustrating connections with a print head in a printing apparatus according to a second embodiment. [Figure 4] 10 is a flowchart for explaining a write operation to an anti-fuse element by a recording device control circuit of a recording device according to the second embodiment. [Figure 5] FIG. 10 is a diagram showing the timing of a write operation to an anti-fuse element by a recording device control circuit according to the second embodiment. [Figure 6] FIG. 10 is a perspective view of a recording head as a liquid ejection head unit that can be mounted on a recording apparatus according to a second embodiment. [Figure 7] FIG. 10 is an external perspective view of a mechanism part of a recording device according to a second embodiment with the cover removed. [Figure 8] FIG. 11 is a block diagram illustrating connections with a print head in a printing apparatus according to a third embodiment. [Figure 9] FIG. 10 is a block diagram illustrating connections with a print head in a printing apparatus according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0012] [Embodiment] FIG. 1 is a circuit diagram including a memory section 10 of a semiconductor memory device according to a first embodiment of the present invention, showing a state before information is written to an anti-fuse element 11 of the memory section 10. In FIG.

[0013] This memory unit 10 has a first transistor MP1, a second transistor MN1, a third transistor MD1, an anti-fuse element 11, and a resistance element Rp (first resistance element) connected in parallel with the anti-fuse element 11. Here, the first transistor MP1 and the second transistor MN1 form an inverter circuit that drives the third transistor MD1, which is the driving element for the anti-fuse element 11, and the output of this circuit is input to the gate of the third transistor MD1.

[0014] The write state detection unit 12 includes a resistor Rsh (second resistor), an amplifier (operational amplifier) ​​OP0, and a comparator CP0. The resistor Rsh is connected in series to the power supply line of the high voltage VHT supplied from terminal A, and both ends of the resistor Rsh are connected to the input terminals of the amplifier OP0. The resistor Rsh converts the current flowing from terminal A to the anti-fuse element 11 into a voltage value and inputs it to the amplifier OP0. The amplifier OP0 amplifies the potential difference generated across the resistor Rsh and inputs it to the input terminal (+) of the comparator CP0. The comparator CP0 compares this input potential with a reference voltage Vref and outputs the result as an output signal (END) to terminal C. The current supply terminal A is grounded via an ESD protection element EP. A resistor Rs (third resistor) is connected between the anti-fuse element 11 and the resistor Rsh.

[0015] The control circuit 13 controls the first transistor MP1 and the second transistor MN1.

[0016] FIG. 1 shows the state before information is written in the anti-fuse element 11, and therefore the anti-fuse element 11 is represented by a capacitance Ca.

[0017] The first transistor MP1 is a P-type transistor, the second transistor MN1 is an N-type transistor, and a control signal Sig is input to the gates of the first transistor MP1 and the second transistor MN1 from the control circuit 13. A first terminal TP1 of the first transistor MP1 is connected to a logic power supply voltage VDD, and a second terminal TP2 of the second transistor MN1 is connected to the ground wiring GND.

[0018] The third transistor MD1 is a high-voltage transistor that controls the application of voltage to the anti-fuse element 11. A first terminal of the third transistor MD1 is connected to a first terminal T111 of the anti-fuse element 11, and a second terminal of the third transistor MD1 is connected to the ground wiring GND. A second terminal T112 of the anti-fuse element 11 is connected to a first terminal TS1 of the resistor element Rs. Here, a high-voltage transistor refers to a transistor that is formed so as not to break down even when a large voltage that cannot be withstood by transistors in general logic circuits such as a control unit is applied.

[0019] The control circuit 13 outputs a control signal Sig based on an external write control signal WEN and an output signal END of the comparator CP0.

[0020] Terminal A is a pad for electrically connecting the memory unit 10 to an external element, and is a terminal for applying a voltage to the anti-fuse element 11. Terminal A is also connected to a first terminal TEP1 of the ESD protection element EP at node B, and a second terminal TEP2 of the ESD protection element EP is connected to the ground wiring GND. Resistor elements Rsh and Rs are provided in the current path between the anti-fuse element 11 and node B, and a first terminal TS1 of the resistor element Rs is connected to a second terminal T112 of the anti-fuse element 11, and a second terminal TS2 of the resistor element Rs is connected to the resistor element Rsh.

[0021] In semiconductor memory devices that use antifuse elements as memory, information is recorded by the conduction and non-conduction of the antifuse elements. In such semiconductor memory devices, electrostatic discharge (ESD) can cause a very large surge current to enter the semiconductor memory device from terminal A. That is, ESD can apply a surge voltage that is much larger than a normal write voltage or read voltage to the antifuse element 11, causing an antifuse element 11 that was not intended to be conductive to become conductive. This can cause the information recorded in the semiconductor memory device to change.

[0022] Therefore, an ESD protection element EP is provided between terminal A and ground wiring GND to provide ESD protection. In this case, if a resistive element Rs is provided between node B, to which terminal A and ESD protection device EP are connected, and anti-fuse element 11, the resistive element Rs makes it difficult for current to flow in the current path between terminal A and anti-fuse element 11. This makes it easier for a large surge current to flow through the ESD protection element, and the anti-fuse element 11 can be more effectively protected from ESD surge currents. In the memory unit 10, a resistance element Rp is arranged in parallel with the anti-fuse element 11. When the high-voltage NMOS transistor MD1 is in the off state, the resistance element Rp has the effect of equalizing the potentials across the capacitance Ca of the anti-fuse element 11, thereby further improving resistance to surges. To achieve this effect of equalizing the potentials across the capacitance Ca, the resistance element Rp should have a low resistance value.

[0023] Next, the operation during writing will be described.

[0024] When writing information to the anti-fuse element 11, the control signal WEN is set to a write state, causing the control circuit 13 to output the control signal Sig at a low level. This turns on the third transistor MD1, a high-voltage NMOS transistor. This causes a high voltage VHT to be applied to the two electrodes, the upper electrode and the lower electrode, that make up the anti-fuse element 11. At this time, the current flowing from terminal A to the GND wiring is defined as i.

[0025] Before the gate oxide film between the two electrodes of the anti-fuse element 11 is broken down, the anti-fuse element 11 is a capacitance element, so a current flows through the resistance element Rp. If the current before the anti-fuse element 11 is written is a current ia, then the current ia is expressed as follows: ia=VHT / (Rs+Rsh+Rp) This becomes:

[0026] For example, when the resistance value of the resistor element Rs is 1 [kΩ], the resistance value of the resistor element Rp is 80 [kΩ], the resistance value of the resistor element Rsh is 0.5 [kΩ], and the high voltage VHT is 24 [V], the current ia is 296 [μA].

[0027] Thereafter, the gate oxide film between the two electrodes of the anti-fuse element 11 is broken down, and information is written into the anti-fuse element 11. As a result, the anti-fuse element 11 was a capacitance element before writing, but after writing, it becomes a resistance element Rb, and a current flows through the resistance elements Rb and Rp. At this time, if the current after writing into the anti-fuse element 11 is current ib, then the current ib is ib=VHT / (Rs+Rsh+Rp×Rb / (Rp+Rb)) This becomes:

[0028] For example, when the resistance value of resistor element Rs is 1 kΩ, the resistance value of resistor element Rp is 80 kΩ, the resistance value of resistor element Rb is 8 kΩ, the resistance value of resistor element Rsh is 1 Ω, and the high voltage VHT is 24 V, the current ib is 2.90 mA. In this way, after writing to the anti-fuse element 11, the value of the current flowing through the anti-fuse element 11 increases.

[0029] Next, a method for determining whether or not information has been written in the anti-fuse element 11 will be described.

[0030] Before the voltage VHT is applied to the anti-fuse element 11 and writing is performed on the anti-fuse element 11, that is, before dielectric breakdown occurs, the potential difference VRsh_a across both ends of the resistance element Rsh is VRsh_a=ia×Rsh=VHT / (Rs+Rsh+Rp)×Rsh This VRsh_a is amplified by the amplifier circuit OP0, and the comparator circuit CP0 compares the output voltage of the amplifier circuit OP0 with the reference voltage Vref. In this case, since the output voltage of the amplifier circuit OP0 is smaller than the reference voltage Vref, the comparator circuit CP0 outputs the output signal END at a low level indicating an unwritten state.

[0031] For example, when the resistance value of the resistor element Rs is 1 [kΩ], the resistance value of the resistor element Rp is 80 [kΩ], the resistance value of the resistor element Rsh is 1 [Ω], and the high voltage VHT is 24 [V], the amplifier circuit OP0 outputs VRsh. _a is differentially amplified by a factor of 1. At this time, the output voltage VPO0_a of the amplifier circuit OP0 is VPO0_a=VRsh_a=0.296 [mV].

[0032] On the other hand, after the voltage VHT is applied to the anti-fuse element 11 and information is written in the anti-fuse element 11, that is, after dielectric breakdown occurs, the potential difference VRsh_b across the both ends of the resistance element Rsh is VRsh_b=ib×Rsh =VHT / (Rs+Rsh+Rp×Rb / (Rp+Rb))×Rsh This VRsh_b is amplified by the amplifier circuit OP0, and the comparator circuit CP0 compares the output voltage of the amplifier circuit OP0 with the reference voltage Vref. In this case, the output voltage of the amplifier circuit OP0 becomes larger than the reference voltage Vref, and the comparator circuit CP0 outputs the output signal END at a high level indicating the write state.

[0033] For example, when the resistance value of resistor element Rs is 1 [kΩ], the resistance value of resistor element Rp is 80 [kΩ], the resistance value of resistor element Rb is 8 [kΩ], the resistance value of resistor element Rsh is 1 [Ω], and the high voltage VHT is 24 [V], then VRsh is _b In this case, the output voltage VPO0_b of the amplifier circuit OP0 is VPO0_b=VRsh_b=2.90[mV].

[0034] The reference voltage Vref is the output voltage V of the amplifier circuit OP0 before and after writing to the anti-fuse element 11. PO For example, the resistance value is set to a value such that the potential difference across the resistor Rsh is 2.0 mV and the current i is 2.0 mA, making it easy to determine whether the current i is 2.0 mA or less. As a result, as described above, before writing to the anti-fuse element 11, the output voltage of the amplifier circuit OP0 is smaller than the reference voltage Vref, and therefore the output signal END is output at a low level. On the other hand, after writing to the anti-fuse element 11, the output voltage of the amplifier circuit OP0 is larger than the reference voltage Vref, and therefore the output signal END is output at a high level.

[0035] Next, the use of the result of determining whether information has been written in the anti-fuse element 11 will be described.

[0036] When the output signal END of the comparison circuit CP0 is output at a low level indicating that the antifuse element 11 is in an unwritten state, the control circuit 13 continues writing to the antifuse element 11. When the output signal END of the comparison circuit CP0 is output at a high level indicating that the antifuse element 11 is in a written state, the control circuit 13 ends writing to the antifuse element 11 after a certain period of time has elapsed.

[0037] 2 is a circuit diagram including a memory unit 10 of a semiconductor memory device showing another aspect of embodiment 1, and shows a state before information is written to the antifuse element 11 of the memory unit 10. Note that parts common to those in FIG. 1 are given the same reference numerals and symbols, and their explanation will be omitted.

[0038] In Figure 2, the ESD protection element EP in Figure 1 is N The gate, source, and back gate of the high-voltage NMOS transistor, which is the ESD protection element EP, are grounded.

[0039] The operation when writing to the antifuse element 11, the method of determining whether information has been written to the antifuse element 11, and the use of the determination result whether information has been written to the antifuse element 11 are the same as those in FIG. 1 described above.

[0040] As described above, according to the first embodiment, the write state of the anti-fuse element 11 is determined by the output signal END, so that the write state of the semiconductor memory device with improved ESD resistance can be reliably determined.

[0041] [Embodiment 2] In the second embodiment, an example in which the semiconductor memory device of FIG. 2 is applied to a recording device will be described as an application example of the semiconductor memory device described in the first embodiment.

[0042] FIG. 3 is a block diagram illustrating the connection with the print head in the printing apparatus according to the second embodiment.

[0043] The printhead substrate 100 has the semiconductor memory device shown in Fig. 1 or 2. The main body of the printing apparatus also has a printing apparatus control substrate 300 that controls the printhead substrate 100, and a carriage substrate 306 that transfers power and signals from the printing apparatus control substrate 300 to the printhead substrate 100.

[0044] The printing apparatus control board 300 includes a power supply generating circuit 301 , a printing apparatus control circuit 302 , a VDD control circuit 303 , a VH control circuit 304 , and a VHT control circuit 305 .

[0045] The power supply generating circuit 301 supplies the first power supply voltage VDD, the second power supply voltage VH, the third power supply voltage VHT, and the ground potential GND, which are necessary to operate the printing apparatus. The printing apparatus control circuit 302 is a control circuit that controls the printing apparatus, and has a CPU 310. It outputs a clock signal CLK, an image data signal DATA, a latch signal LT, and a heater control signal HE, which control the printhead substrate 100. Furthermore, it controls a VDD control circuit 303 that controls the output of the first power supply voltage VDD, a VH control circuit 304 that controls the output of the second power supply voltage VH, and a VHT control circuit 305 that controls the output of the third power supply voltage VHT, and controls the capture of the output signal from the printhead substrate 100.

[0046] The carriage board 306 is a board that electrically connects signals and power between the printhead board 100 and the printing apparatus control board 300 .

[0047] The printhead substrate 100 has a printing unit 101 having heat generating elements (ejection elements) (Rh) for ejecting ink from the ejection ports and their drive elements, a memory unit 102 corresponding to the memory unit 10 described above, printhead control circuits 103a and 103b, and a step-down circuit 107. It also has a ROM write power control element 110, an input terminal and wiring circuit for a first power supply voltage VDD, an input terminal and wiring circuit for a second power supply voltage VH, an input terminal and wiring circuit for a third power supply voltage VHT, a connection terminal and ground wiring for a ground wiring GND, and the write state detection unit 12 described above.

[0048] The step-down circuit 107 is a power supply circuit that reduces the third power supply voltage VHT to generate a fourth power supply voltage VHTM. The ROM write power supply control element 110 is an element that applies an antifuse element write power supply to the antifuse element 11 when the recording device control circuit 302 sets the antifuse element 11 of the memory unit 102 to a write state via the recording head control circuit 103b.

[0049] The memory unit 102 includes an inverter having a first transistor MP1 and a second transistor MN1, a third transistor MD1, an anti-fuse element 11, a resistor Rs, a node B, and an ESD protection element EP. The recording unit 101 also includes a heater Rh (an electrothermal transducer) and a driver (for example, a transistor MD2 and a logical AND circuit) for driving the heater Rh. 108 By driving the heater Rh, that is, by energizing the heater Rh to generate heat, a recording material (for example, ink) is ejected, thereby making it possible to perform recording.

[0050] The printhead control circuits 103a and 103b can be configured with, for example, a shift register, a latch circuit, etc. (not shown). A clock signal CLK, an image data signal DATA, a latch signal LT, and a heater control signal HE may be input to the printhead control circuits 103a and 103b from the printing device control circuit 302 via a host PC (not shown) or the like. A fourth power supply voltage VHTM (e.g., 3 to 5 V) is supplied as a power supply voltage for driving transistors to the AND circuit AND 108, the AND circuit NAND 109, and the printhead control circuits 103a and 103b. Therefore, the heater Rh of the printing unit 101 and the memory unit 102 (semiconductor memory device) are respectively connected to the printhead control circuit 103a. and 103b is electrically connected to It is possible to record the results.

[0051] Here, the printhead control circuit 103a can perform time-division driving, controlling the operation of the printing units 101 for each of m groups, each having n printing units 101, to drive the heaters Rh. In time-division driving, the printhead control circuit 103a outputs an m-bit block selection signal 104 and an n-bit time-division selection signal 105, so that the selected printing units 101 in the selected block are driven according to the print data and perform printing. The corresponding block selection signal 104 and time-division selection signal 105 are input to the AND circuit AND108, which in response turns on the transistor MD2 and drives the heater Rh connected in series with the transistor MD2. Here, a second power supply voltage VH (e.g., 24 V) is supplied to the printing units 101 as a power supply voltage for driving the heaters, and the ground potential is GND.

[0052] A control signal 106 and a time-division selection signal 105 are input to the AND circuit NAND 109, and a signal corresponding to the control signal is output from the inverter to the transistor MD1, switching the transistor MD1 between a conductive state and a non-conductive state. In the semiconductor memory device of Fig. 1, a third power supply voltage VHT (e.g., 24.0 V) for writing information to the anti-fuse element 11 is supplied, and the ground potential is GND.

[0053] At least one ESD protection element EP is arranged between the VHT terminal and the ground terminal. In this case, the memory unit 102 includes, for example, an inverter, a third transistor MD1, an anti-fuse element 11, and resistors Rs and Rp.

[0054] In FIG. 3, the recording unit 101 and the memory unit 102 are each Control circuit 103 and 103b However, they may be connected to separate control circuits. 。 The write state detection unit 12 outputs the write state of the antifuse element 11 for which the recording device control circuit 302 has set the write setting via the recording head control circuit 103b as an output signal END. The output signal END is output at a low level when the antifuse element 11 is in an unwritten state, and at a high level when the antifuse element 11 is in a written state. The recording device control circuit 302 uses the state of the output signal END from the write state detection unit 12 to control the continuation or stop of the write operation based on the written state of the antifuse element 11.

[0055] 4 is a flowchart illustrating the write operation of the antifuse element 11 by the recording device control circuit 302 of the recording device according to embodiment 2. The processing shown in this flowchart is achieved by the CPU 310 of the recording device control circuit 302 executing a program stored in a memory (not shown).

[0056] First, in S401, the CPU 310 sets information to be written to each antifuse element 11 of the memory units 102 of the printhead substrate 100 in response to an instruction via a host PC (not shown) or the like of the printing apparatus. Next, the process proceeds to S402, where the CPU 310 selects the first memory unit 102 to be written to. Then, the process proceeds to S403, where the CPU 310 determines whether the selected memory unit 102 is the memory unit to be written to, based on the write information set in S401. If it is determined here that the memory unit 102 is not the memory unit to be written to, the process proceeds to S413, where the next memory unit 102 is selected, and the process proceeds to S403.

[0057] On the other hand, if S403 determines that the memory unit 102 is the write target, the process proceeds to S404, where the CPU 310 sets the write state of the antifuse element 11 of the selected memory unit 102 via the printhead control circuit 103b. Then, the process proceeds to S405, where the CPU 310 controls the VHT control circuit 305 and the ROM write power control element 110 to apply a voltage of 24.0 V to the antifuse element 11 of the memory unit 102. Then, the process proceeds to S406, where the CPU 310 drives the control signal Sig of the AND circuit NAND so that it goes high and low at a constant cycle (e.g., 6.25 MHz). That is, the printhead control circuit 103b is pulse-driven by applying a pulse signal that alternates between high and low levels to the control signal 106. Here, when the pulse signal is high, a current flows through the corresponding antifuse element, and writing is performed.

[0058] Next, the process proceeds to S407, where the CPU 310 checks the state of the output signal END of the write state detection unit 12 and determines whether the output signal END has become high level, i.e., whether writing to the antifuse element 11 of the memory unit 102 to be written has been completed. If the output signal END is in an unwritten state (low level), the process proceeds again to S406, where a pulse signal is applied to the recording head control circuit 103b such that the control signal 106 alternates between high level and low level.

[0059] Then, in S407, when the CPU 310 confirms that the output signal END has entered the write state (high level), the process proceeds to S408, where it outputs a pulse signal in the same manner as in S406 described above. Then, in S409, it outputs this pulse signal for the period set by the write completion determination timer, and then proceeds to S410. This is because, when the high level indicating the write state of the antifuse element 11 is output, writing to the antifuse element 11 is completed after a certain period of time has elapsed, as described above.

[0060] Then, the process proceeds to S410, where the CPU 310 stops outputting the pulse signal as the control signal 106. Then, the process proceeds to S411, where the CPU 310 controls the VHT control circuit 305 and the ROM write power supply control element 110 to set the voltage applied to the anti-fuse element 11 of the memory unit 102 to 0.0 [V]. Then, the process proceeds to S412, where the CPU 310 determines whether the memory unit 102 that was the target of writing is the last memory unit 102. Here, Memory unit 102 If it is the anti-fuse element 11, the write operation of the printhead substrate 100 is completed, but if it is not the last memory unit 102, the process proceeds to S413, the next memory unit 102 is selected, and the same process as above is executed.

[0061] In this way, writing to the anti-fuse element 11 of the memory unit 102 can be performed reliably.

[0062] The recording device control circuit 302 also has the function of reading out the data stored in the anti-fuse element 11 of the memory unit 102.

[0063] FIG. 5 is a diagram showing the timing of the write operation of the anti-fuse element 11 by the recording device control circuit 302 according to the second embodiment.

[0064] FIG. 5 shows the applied voltage to the VHT terminal, the control signal Sig, the current i flowing through the VHT terminal, and the write state of the anti-fuse element 11. show 5 shows the state of the output signal END and the write current threshold of 2.0 [mA]. ​​Note that steps S405 to S411 shown in FIG.

[0065] In FIG. 5, timing T1 is the timing at which a voltage of 24.0 [V] is applied to the anti-fuse element 11 of the memory unit 102 in S405. Timing T2 is the timing at which the first write pulse is applied. TetaTiming T3 is the timing at which it is confirmed in S407 that the output signal END has entered the write state (high level). The period from timing T3 to T4 indicates the elapsed time of the write completion determination timer. Thus, after a certain time has elapsed since the output signal END entered the high level, the output of the pulse signal is stopped, and the voltage VHT applied to the anti-fuse element 11 of the memory unit 102 is set to 0.0 [V].

[0066] FIG. 6 is a perspective view of a recording head 810 as a liquid ejection head unit that can be mounted on a recording apparatus according to the second embodiment.

[0067] The recording head 100 as a liquid ejection head provided in the recording head 810 is electrically connected to a contact pad 615 that connects to the recording apparatus via a flexible film wiring board 614. The recording head 810 is configured such that the recording head 100 and the ink tank 612 are integrated, but it may also be a separate type in which the ink tank can be separated.

[0068] The print head 810 receives electrical signals from a carriage board mounted on a carriage 920 (FIG. 7) via contact pads 615, and ejects ink in accordance with the electrical signals to perform the above-described printing. The ink tank 612 has, for example, a fibrous or porous ink retention material (not shown), which can retain ink.

[0069] FIG. 7 is a perspective view showing the appearance of the mechanical part of the recording device 900 according to the second embodiment with the cover removed.

[0070] The recording head 810 is a recording head partially shown in FIG. 6 and can be mounted on a carriage 920. The carriage 920 is attached to a lead screw 904 having a spiral groove 921. As the lead screw 904 rotates, the recording head 810 moves together with the carriage 920 along a guide 919 in the direction of arrow a or arrow b. The rotation of the lead screw 904 is linked to the rotation of a drive motor 901 via drive force transmission gears 902 and 903.

[0071] The recording paper P is transported onto a platen 906 by a transport unit (not shown). A paper pressing plate 905 presses the recording paper P against the platen 906 along the carriage movement direction. The recording device 900 confirms the position of a lever 909 provided on the carriage 920 via photocouplers 907 and 908, and switches the rotation direction of the drive motor 901, etc. A support member 910 supports a cap member 911 that caps each nozzle of the recording head 810. A suction unit 912 sucks the inside of the cap member 911 and performs a suction recovery process for the recording head 810 through an opening 913 inside the cap.

[0072] A well-known cleaning blade is used as the cleaning blade 914, and a moving member 915 moves the cleaning blade 914 in the front-to-rear direction. A main body support plate 916 supports the moving member 915 and the cleaning blade 914. A lever 917 is provided for starting the suction recovery process.

[0073] The lever 917 moves in accordance with the movement of the cam 918 that engages with the carriage 920. The driving force from the drive motor 901 is controlled by a known transmission means such as a clutch switch. The recording device 900 is provided with a recording control unit (not shown), which controls the driving of each mechanism in accordance with electrical signals such as recording data from the outside. The recording device 900 can complete recording on the recording paper P by repeating the reciprocating movement of the recording head 810 and the transport of the recording paper P by a transport unit (not shown).

[0074] As described above, by using the method for determining the written state of an anti-fuse element described in embodiment 2, it is possible to reliably determine the written state of an anti-fuse element in a recording device including a semiconductor memory device with improved ESD resistance.

[0075] [Embodiment 3] In the third embodiment, the writing state detection unit 12 of the recording device 900 described in the second embodiment is mounted on the carriage board. 801This section explains an example of the system being installed in a vehicle.

[0076] Fig. 8 is a block diagram for explaining the connection with the print head in the printing apparatus according to embodiment 3. In Fig. 8, parts that are common to Fig. 3 above are given the same reference numerals, and their explanation will be omitted.

[0077] Here, the circuit configuration of a printhead substrate 1100 having the semiconductor memory device according to the first embodiment, the circuit configuration of a printing apparatus control substrate 300 that controls the printhead substrate 1100, and a carriage substrate that transfers power and signals from the printing apparatus control substrate 300 to the printhead substrate 1100 are shown. 801 9 shows an example of a control circuit for a recording device 900 including:

[0078] The carriage board 801 is a board that electrically connects signals and power between the printhead board 1100 and the printing apparatus control board 300, and has the write state detection unit 12 described above.

[0079] Recording device control circuit 302 but The operation of controlling the continuation or stop of the write operation from the write state of the anti-fuse element 11 using the state of the output signal END of the write state detection unit 12, and the flowchart showing the procedure of the determination processing of the recording device control circuit 302 are the same as those of the second embodiment described above.

[0080] According to the third embodiment, by determining the write state of the anti-fuse element 11 using the output signal END, it is possible to reliably determine the write state of a semiconductor memory device with enhanced ESD resistance even when the write state detection unit is mounted on a carriage substrate.

[0081] [Embodiment 4] In the fourth embodiment, an example will be described in which the write state detection unit 12 of the recording device 900 described in the second embodiment is mounted on a recording device control board 2930.

[0082] Fig. 9 is a block diagram for explaining the connection with the print head in the printing apparatus according to embodiment 4. In Fig. 9, parts common to those in Fig. 3 above are given the same reference numerals, and their explanation will be omitted.

[0083] This figure shows an example of the circuit configuration of a printhead substrate 1100 having the semiconductor memory device described in embodiment 1, the circuit configuration of a print device control substrate 2930 that controls the printhead substrate 1100, and a control circuit of a print device 900 that has a carriage substrate 2921 that transfers power and signals from the print device control substrate 2930 to the printhead substrate 1100.

[0084] The carriage board 2921 is a board that electrically connects signals and power between the printhead board 1100 and the printing device control board 2930. The printing device control board 2930 has a power generation circuit 301, a printing device control circuit 302, a VDD control circuit 303, a VH control circuit 304, a VHT control circuit 305, and a write state detection unit 12.

[0085] The write state detection unit 12 outputs the write state of the antifuse element 11, for which the recording device control circuit 302 has set the write setting via the recording head control circuit 103b, as an output signal END. The recording device control circuit 302 uses the state of the output signal END of the write state detection unit 12 to control the continuation or stop of the write operation based on the write state of the antifuse element 11. These operations are the same as those in the second embodiment described above.

[0086] According to the fourth embodiment, even if the write state detection unit is mounted on the recording device control board, it is possible to reliably determine the write state of the semiconductor memory device with improved ESD resistance.

[0087] As described above, according to the embodiment, by converting the current flowing during writing to the antifuse element into a voltage and comparing it with a reference voltage, it is possible to accurately determine the write state of the antifuse element with improved surge resistance. This makes it possible to stop the write operation of the antifuse element at the correct timing, thereby achieving power savings by shortening the write time and reducing the write current.

[0088] (Other embodiments) The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0089] The present invention is not limited to the above-described embodiments, and various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the following claims are appended to apprise the public of the scope of the present invention. [Explanation of symbols]

[0090] 10...Memory section, 11...Antifuse element, 12...Write state detection section, 13...Control circuit, 100...Recording head, 101...Recording unit, 102...Memory unit, 103a, 103b...Recording head control circuit, 110...ROM write power supply control element, 300...Recording device control board, 302...Recording device control circuit, 303...VDD control circuit, 306, 801, 2921...Carriage board

Claims

1. A semiconductor memory device that controls writing to a memory unit having an anti-fuse element, a comparison means for comparing a voltage generated across both ends of a first resistance element connected in series to a power supply line that energizes the anti-fuse element with a reference voltage; a control means for controlling writing to the anti-fuse element of the memory unit based on an output of the comparison means when writing to the memory unit; The memory unit a second resistive element connected in parallel with the antifuse element; a driving element for controlling the conduction of the anti-fuse element; a third resistance element connected in series between the first resistance element connected in series to the power supply line and the anti-fuse element;

2. The comparison means an amplifier circuit that receives and amplifies a voltage generated across the first resistor element; a comparison circuit that compares the output of the amplifier circuit with a reference voltage; 2. The semiconductor memory device according to claim 1, wherein said control means determines whether or not writing to said anti-fuse elements of said memory units has been completed based on the output of said comparison circuit.

3. 3. The semiconductor memory device according to claim 1, further comprising power supply control means for applying a write voltage to a power supply line that energizes said anti-fuse element when writing to said memory unit.

4. 4. The semiconductor memory device according to claim 1, wherein, when writing to the memory unit, the control means writes to the anti-fuse element by applying a pulse signal to the anti-fuse element.

5. 5. The semiconductor memory device according to claim 4, wherein when the output of the comparison means indicates that writing to the anti-fuse element of the memory unit has been completed, the control means further applies the pulse signal to the anti-fuse element for a certain period of time, and then completes writing to the anti-fuse element.

6. 6. The semiconductor memory device according to claim 1, wherein the current supply side of the power supply line is grounded via an ESD protection element.

7. A recording apparatus including a recording head having a plurality of ejection ports and a recording head substrate, the printhead substrate has ejection elements provided to correspond to the plurality of ejection ports, and a drive unit electrically connected to the ejection elements; The recording device A semiconductor memory device according to any one of claims 1 to 6, a recording device control means for controlling writing and reading of data to and from the semiconductor memory device; A recording device comprising:

8. 8. The recording apparatus according to claim 7, wherein said recording apparatus control means determines whether writing to said anti-fuse elements of said memory units has been completed based on the output of said comparison means when writing to said memory units.

9. 9. The recording apparatus according to claim 7, wherein the comparison means of the semiconductor memory device is provided on the recording head substrate.

10. 9. The recording apparatus according to claim 7, wherein the comparison means of said semiconductor memory device is provided on a board that electrically connects signals and power between a recording head board and a control board of said recording apparatus.

11. 7. A method for controlling writing to a semiconductor memory device in a recording device having the semiconductor memory device according to claim 1, comprising: selecting an antifuse element to be written; energizing the selected antifuse element via a power supply line; a step of controlling writing to the anti-fuse element of the memory unit based on an output of the comparison means which compares a voltage generated across both ends of the first resistance element connected in series to the power supply line by the energization with a reference voltage; A write control method comprising:

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