Power semiconductor device and method for manufacturing a power semiconductor device - Patents.com

Abstract

The power semiconductor device (100) includes a semiconductor body (1) having an upper surface (10), a main electrode (2) on the upper surface, and a gate electrode (3) on the upper surface and disposed adjacent to the main electrode in a first lateral direction (L1). The semiconductor body includes a drift layer (11) of a first conductivity type, a base region (12) of a second conductivity type disposed between the drift layer and the upper surface in the longitudinal direction, and a contact region (13) of the first conductivity type disposed between the drift layer and the upper surface in the longitudinal direction. The contact region is adjacent to the base region and the upper surface. Further, the semiconductor body includes a drift region (14) of the first conductivity type disposed adjacent to the base region in the first lateral direction and adjacent to the base region. The main electrode is in electrical contact with the contact region. In a plan view of the upper surface, the gate electrode at least partially covers a channel portion (12a) of the base region located between the contact region and the drift region in the first lateral direction. On the upper surface, at least one of the contact region and the drift region protrudes beyond the base region in the longitudinal direction.

Description

[Technical Field]

[0001] The present disclosure relates to power semiconductor devices and methods for manufacturing power semiconductor devices. [Background technology]

[0002] There is a need for improved power semiconductor devices, for example, having good contact resistance and / or reduced parasitic capacitance. Additionally, there is a need for improved methods for manufacturing such power semiconductor devices. Summary of the Invention [Means for solving the problem]

[0003] SUMMARY OF THE INVENTION

[0003] Embodiments of the present disclosure relate to improved power semiconductor devices. Other embodiments relate to improved methods for manufacturing power semiconductor devices.

[0004] First, the power semiconductor device is specified. The power semiconductor device is configured to handle, for example, a current of at least 1 A and / or a voltage of at least 100 V. The power semiconductor device is, for example, a so-called vertical power semiconductor device.

[0005] According to one embodiment, a power semiconductor device includes a semiconductor body having a top surface, a main electrode on the top surface, and a gate electrode on the top surface and disposed adjacent to the main electrode in a first lateral direction. The semiconductor body includes a drift layer of a first conductivity type, a base region of a second conductivity type disposed vertically between the drift layer and the top surface, and a contact region of the first conductivity type disposed vertically between the drift layer and the top surface. The contact region is adjacent to the base region and the top surface. The semiconductor body further includes a drift region of the first conductivity type disposed adjacent to the base region in the first lateral direction and adjacent to the base region. The main electrode is in electrical contact with the contact region. In a plan view of the top surface, the gate electrode at least partially covers a channel portion of the base region located between the contact region and the drift region in the first lateral direction. At least one of the contact region and the drift region protrudes vertically beyond the base region at the top surface.

[0006] Today, most commercially available power semiconductor devices are based on cell designs with planar channels aligned with the top surface of the semiconductor body. However, boosting current density in such devices is hindered by the parasitic junction field effect transistor (JFET) beneath the gate electrode and the increasing contact resistance that accompanies downscaling. Furthermore, the parasitic gate-drain capacitance Cgd, which is strongly associated with the JFET, increases significantly with decreasing pitch dimensions. While trench designs originally promised to reduce or even eliminate the JFET, current trench power semiconductor devices still rely on the JFET in practice.

[0007] The device concept proposed here is based, among other things, on the idea of ​​using raised source and / or drift regions, which significantly reduces contact resistance and eliminates parasitic gate / drain capacitance Cgd, resulting in unparalleled switching performance and enabling significant chip size reduction.

[0008] The semiconductor body is based on, for example, Si, SiC, or GaN. The main electrode on the top surface is, for example, a metal electrode. The gate electrode may be made of metal or heavily doped polysilicon. The gate electrode is electrically isolated from the semiconductor body by an electrically insulating material, for example, SiO2. The power semiconductor device may therefore be an insulated gate device. In particular, the gate electrode and the main electrode are electrically isolated from each other and can be set to different potentials for operation.

[0009] The gate electrode is arranged next to or adjacent to the main electrode in a first lateral direction. In this specification, the lateral direction is, for example, a direction parallel to the main extension plane of the semiconductor body. The vertical direction is therefore defined as a direction perpendicular to the main extension plane of the semiconductor body.

[0010] The drift layer is of a first conductivity type. The first conductivity type can be either electron conductivity or hole conductivity. The second conductivity type is different from the first conductivity type, i.e., either hole conductivity or electron conductivity. The electron conductive regions or layers are n-doped, and the hole conductive regions or layers are p-doped. For example, the doping concentration of the first drift layer is at least 10 8 cm -3 and a maximum of 10 15 cm -3 is.

[0011] The base region is disposed vertically between the drift layer and the top surface, i.e., vertically between the top surface and the drift layer. For example, the base region is adjacent to the drift layer and / or the top surface. For example, the doping concentration in the base region is greater than the doping concentration in the drift layer, e.g., at least 10 times or at least 100 times greater. For example, the doping concentration in the base region is at least 10 times greater than the doping concentration in the drift layer. 15 cm -3 and / or up to 10 18 cm -3 is.

[0012] In this specification, when comparing the doping concentrations of layers or regions, the average doping concentration or the maximum doping concentration of these layers or regions is compared. When defining upper and lower limits of the doping concentration in a layer or region, this means that the maximum doping concentration in the respective layer / region does not exceed the upper limit, and the minimum doping concentration in the respective layer / region does not fall below the lower limit. The regions referred to in this specification are, for example, each continuous region, in particular without holes or interruptions.

[0013] The contact region is of the same conductivity type as the drift region. For example, the doping concentration of the contact region is greater than the doping concentration of the drift layer and / or base region, for example, at least 10 times or at least 100 times greater. For example, the doping concentration in the contact region is at least 10 17 cm -3 or at least 10 18 cm -3 or at least 10 19 cm -3 is.

[0014] The contact region is adjacent to the base region and the top surface, i.e., forms part of the top surface. The contact region may be adjacent to the base region in a vertical direction and / or a horizontal direction, particularly a first horizontal direction. For example, the contact region is partially or completely laterally surrounded by the base region. The contact region may be embedded in the base region.

[0015] The drift region is of the same conductivity type as the contact region and the drift layer. For example, the doping concentration in the drift region is less than the doping concentration in the contact region, for example, at most 10 times or at most 100 times. However, the doping concentration in the drift region may be greater than the doping concentration in the drift layer, for example, at least 10 times or at least 100 times greater. For example, the doping concentration in the drift region is at least 10 times or at least 100 times greater. 15 cm -3 and / or up to 10 18cm -3 The drift region is also known as the JFET region.

[0016] The drift region is disposed next to the base region in a first lateral direction and is adjacent to the base region in the first lateral direction. The drift region is separated from the contact region in the first lateral direction by a portion of the base region, which portion is referred to herein as the "channel portion." The drift region and / or the channel portion may be adjacent to, i.e., form part of, a top surface of the semiconductor body.

[0017] The main electrode is in electrical contact with the contact region, i.e., in direct electrical contact with the contact region. The main electrode may be adjacent to the contact region on the top surface. In this specification, electrical contact means, for example, an ohmic electrical contact.

[0018] The gate electrode is disposed laterally adjacent to the main electrode and aligned in a first lateral direction with the channel portion of the base region. Thus, in a top plan view, the gate electrode partially or completely covers or overlaps the channel portion, respectively. The gate electrode may also overlap a portion of the contact region and / or the drift region in this plan view. However, the gate electrode may be electrically insulated from the channel portion, the contact region, and the base region by an electrically insulating material.

[0019] The semiconductor body may include several drift regions, base regions, and corresponding contact regions. All features disclosed in connection with one drift region, one base region, and one contact region are also disclosed for all other drift regions, base regions, and contact regions. For example, a drift region may be disposed between every pair of base regions in a first lateral direction. Furthermore, each channel portion of the base region may be assigned a gate electrode that overlaps the channel portion in a top plan view.

[0020] The channel portion is a portion through which charge carriers flow from the contact region to the drift region during operation. For example, a power semiconductor device may be configured to deplete the channel portion facing the gate electrode with the aid of a gate electrode, thereby allowing current to flow from the main electrode through the contact region to the drift region via the depleted channel portion.

[0021] At least one of the contact region and the drift region protrudes vertically beyond the base region at the top surface. For example, the contact region and / or the drift region protrudes beyond the base region by at least 50 nm or at least 100 nm, and / or by at most 1 μm or at most 5 μm. In other words, the contact region and / or the drift region terminates at a height relative to the drift layer that is greater than that of the base region. For example, both the contact region and the drift region protrude vertically beyond the base region at the top surface. The protruding contact region and / or the drift region may be tapered in the vertical direction away from the drift layer.

[0022] The raised contact region can reduce contact resistance. The raised drift region can, for example, reduce Cgd.

[0023] According to further embodiments, at least one of the contact region and the drift region is epitaxially grown. For example, both the contact region and the drift region are epitaxially grown. The contact region and / or the drift region may be grown on a base semiconductor body comprising a drift layer. The drift layer and / or the base region may be formed by implantation of dopants.

[0024] According to at least one embodiment, at least one epitaxially grown region, i.e., the contact region and / or the drift region, has, for example, a reverse doping profile over its entire volume, with the doping concentration decreasing in a direction from the interior to the top surface of the semiconductor body. Additionally or alternatively, at least one of the epitaxially grown regions has, for example, a uniform doping profile over its entire volume. Both regions can have a reverse doping profile or a uniform doping profile. It is also possible for the epitaxially grown contact region to have a uniform doping profile and the epitaxially grown drift region to have a reverse doping profile, or vice versa.

[0025] An epitaxially grown region with a reverse doping profile has, for example, a minimum doping concentration that is at least one or at least two orders of magnitude lower than the maximum doping concentration within said region. An epitaxially grown region with a uniform doping profile has, for example, a maximum deviation from the average doping concentration of at most 20% or at most 10%.

[0026] At least one of the epitaxially grown regions may have a doping profile in which the doping concentration decreases from the top surface toward the interior of the semiconductor body. The difference between the maximum and minimum doping concentrations may be the same as in a reverse doping profile.

[0027] By growing the contact and / or drift regions epitaxially, it is possible to form these regions so that they extend beyond the base region, and also to set the doping concentrations of these regions individually and independently. Furthermore, the doping concentrations of these regions can be set higher than, for example, if these regions were formed by implantation. Furthermore, the doping concentrations of these regions can be made very uniform throughout the entire volume of the region or to have special doping profiles, such as reverse doping profiles.

[0028] According to a further embodiment, at the top surface, the drift region protrudes beyond the base region in the vertical direction. In a plan view of the top surface, the gate electrode covers a large portion of the drift region. For example, in a plan view of the top surface, the gate electrode covers at most 50% or at most 25% of the drift region. In one example, the gate electrode does not cover the drift region at all, for example, it is spaced apart from the drift region in the first lateral direction or terminates flush with the drift region in the first lateral direction.

[0029] The raised / protruding drift region allows the gate electrode to be formed without completely overlapping the drift region, thus significantly reducing Cgc.

[0030] According to a further embodiment, the contact region and the channel portion are at least partially aligned in the vertical direction. For example, when viewed along a first horizontal direction, the contact region and the channel portion at least partially overlap each other. For example, in this view, the contact region and the channel portion completely overlap each other. The vertical alignment allows for efficient injection of charge carriers from the contact region into the channel portion.

[0031] Starting from the top surface, the contact region may extend deeper into the semiconductor body than the base region, or the base region may extend deeper into the semiconductor body than the contact region. In the second case, a portion of the base region may be disposed vertically between the contact region and the drift layer. In other words, the distance between the contact portion and the back surface of the semiconductor body may be greater or smaller than the distance between the base region and the back surface. The back surface is the surface of the semiconductor body opposite the top surface.

[0032] According to further embodiments, the doping concentration in the drift region is greater than the doping concentration in the drift layer, for example at least 10 times or at least 100 times greater.

[0033] According to a further embodiment, in a top plan view, the gate electrode partially covers the contact region and / or the drift region. The gate electrode may have a first section that tapers toward the top surface, i.e., a first lateral extension that decreases in a direction toward the top surface. This first section may overlap the contact region and / or the drift region in a top view. The taper may be, for example, the result of a manufacturing process.

[0034] The gate electrode may also have a second section tapering away from the top surface, and the first section may be disposed longitudinally between the top surface and the second section.

[0035] According to a further embodiment, the power semiconductor device is a MOSFET or an IGBT or a JFET or a MISFET or a thyristor.

[0036] According to a further embodiment, the semiconductor body is based on a wide bandgap semiconductor such as SiC or GaN.

[0037] According to a further embodiment, the gate electrode and at least one of the contact region and the drift region protruding beyond the base region are at least partially aligned in the vertical direction, e.g., when viewed along a first lateral direction, the gate electrode and the protruding contact region and / or the protruding drift region at least partially overlap each other.

[0038] Next, a method for manufacturing a power semiconductor device is specified. The method may be used, among other things, to manufacture a power semiconductor device according to any of the embodiments described herein. Accordingly, all features disclosed for the power semiconductor device are also disclosed for the method, and vice versa.

[0039] According to one embodiment, the method includes fabricating a semiconductor body having a top surface, the semiconductor body having a drift layer of a first conductivity type, a base region of a second conductivity type arranged vertically between the drift layer and the top surface, a contact region of the first conductivity type arranged vertically between the drift layer and the top surface and adjacent to the base region and the top surface, and a drift region of the first conductivity type arranged next to the base region in a first lateral direction. In a further step, a main electrode is applied to the top surface, and electrical contact is established between the main electrode and the contact region. In a further step, a gate electrode is fabricated at an end such that the gate electrode is arranged on the top surface and next to the main electrode in the first lateral direction, and such that in a plan view of the top surface, the gate electrode at least partially overlaps a channel portion of the base region that is between the contact region and the drift region in the first lateral direction. The semiconductor body is fabricated such that at least one of the contact region and the drift region protrudes vertically beyond the base region at the top surface.

[0040] The gate electrode may be fabricated before or after applying the main electrode. Additionally, the gate electrode may be fabricated before or after forming the raised, i.e., protruding, contact region and / or drift region.

[0041] According to a further embodiment, fabricating the semiconductor body includes providing a base semiconductor body having a drift layer and a base region. Prior to this, the base region and / or the drift layer may be formed in the base semiconductor body by implantation of dopants. The base semiconductor body may be based on a wide bandgap semiconductor such as SiC or GaN.

[0042] According to a further embodiment, fabricating the semiconductor body includes epitaxially growing at least one of a contact region and a drift region on the base semiconductor body.

[0043] According to at least one embodiment, epitaxial growth is performed by Chemical Vapor Deposition (CVD).

[0044] According to at least one embodiment, at least one of the following precursors is used for epitaxial growth: monosilane, disilane, trisilane, chlorinated precursors such as DCS (Dichlorsilane), carbon precursors such as methane.

[0045] According to at least one embodiment, at least one of the following doping precursors is used for doping during epitaxial growth: diborane or phosphine.

[0046] According to at least one embodiment, the doping profile of the epitaxially grown region is set by adjusting the mass flow rate of the doping precursors. For example, a reverse doping profile is created by reducing the mass flow rate of the doping precursors during epitaxial growth.

[0047] According to a further embodiment, before growing the contact region, a portion of the base semiconductor is removed in the area where the contact region is to be formed, and then the contact region is grown in that area.

[0048] For example, holes are etched into the base semiconductor body to define areas for contact region growth. The depth of the holes, measured vertically, is, for example, at least 1 μm or at least 2 μm. For example, the holes are etched vertically completely through the base region. Alternatively, the holes may be etched to a depth that opens into the base region.

[0049] According to a further embodiment, before growing the drift region, a portion of the base semiconductor body is removed in the area where the drift region is to be formed, and then the drift region is grown in that area.

[0050] For example, holes are etched into the base semiconductor body to define areas for growth of the drift region, the holes having a depth measured vertically of, for example, at least 1 μm or at least 2 μm.

[0051] According to a further embodiment, the gate electrode is formed on the base semiconductor body. For example, this is done after the base region and / or the drift layer are formed. The gate electrode may be formed before the drift region and / or the contact region are fabricated, for example by epitaxial growth.

[0052] To form the gate electrode, a gate electrode layer may first be applied to the top surface of the base semiconductor body, whereby the gate electrode layer may be electrically insulated from the top surface by a layer of electrically insulating material disposed between the gate electrode layer and the top surface.

[0053] In a further step, the gate electrode layer and the underlying electrically insulating layer may be structured to form a gate electrode, whereby parts of the gate electrode layer and the underlying insulating layer may be removed, for example by etching. A mask may be used for structuring the gate electrode layer and the electrically insulating layer.

[0054] According to a further embodiment, an electrically insulating material is applied to at least the side surfaces of the gate electrode, the side surfaces being surfaces that define the gate electrode in a lateral direction, in particular in a first lateral direction, the side surfaces extending obliquely or perpendicularly to a main extension plane of the (base) semiconductor body.

[0055] The electrically insulating material may be deposited on the gate electrode by non-directional or conformal deposition methods, respectively.

[0056] According to a further embodiment, at least one of the contact region and the drift region is selectively grown adjacent to a gate electrode having an insulating material applied thereon. That is, the gate electrode having the insulating material applied thereon is used as a mask for the selective growth process. For example, the contact region is grown on one side of the gate electrode and the drift region is grown on the other side of the gate electrode, where "side" and "other side" are meant with respect to the first lateral direction.

[0057] For example, when growing the contact region and / or the drift region, each region is grown adjacent to the electrically insulating material in the first lateral direction.

[0058] Hereinafter, a power semiconductor device and a method for manufacturing a power semiconductor will be described in more detail based on exemplary embodiments with reference to the drawings. The accompanying drawings are included to provide a further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the drawings are exemplary representations and are not necessarily drawn to scale. To the extent that elements or components correspond to each other in terms of their functions in different figures, their description will not be repeated for each of the following figures. For clarity, elements may not be labeled with corresponding reference numerals in all figures. [Brief explanation of the drawings]

[0059] [Figure 1] 1 illustrates an exemplary embodiment of a power semiconductor device. [Figure 2] 1 illustrates an exemplary embodiment of a power semiconductor device. [Figure 3] 1 illustrates an exemplary embodiment of a power semiconductor device. [Figure 4] 1 illustrates an exemplary embodiment of a power semiconductor device. [Figure 5] 1 shows a flowchart of an exemplary embodiment of a method for manufacturing a power semiconductor device. [Figure 6] 1 illustrates a location in an exemplary embodiment of a method for manufacturing a power semiconductor device. [Figure 7] 1 illustrates a location in an exemplary embodiment of a method for manufacturing a power semiconductor device. [Figure 8] 1 illustrates a location in an exemplary embodiment of a method for manufacturing a power semiconductor device. [Figure 9] 1 illustrates a location in an exemplary embodiment of a method for manufacturing a power semiconductor device. [Figure 10] 1 illustrates a location in an exemplary embodiment of a method for manufacturing a power semiconductor device. [Figure 11] 1 illustrates a location in an exemplary embodiment of a method for manufacturing a power semiconductor device. [Figure 12] 1 illustrates a location in an exemplary embodiment of a method for manufacturing a power semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0060] 1 comprises a semiconductor body 1 based on a wide bandgap material such as 6H-SiC or 3C-SiC. A main electrode 2 and two gate electrodes 3 are arranged on a top surface 10 of the semiconductor body 1.

[0061] The semiconductor body 1 comprises a drift layer 11 of a first conductivity type. In the following, the first conductivity type will be referred to as electron conductivity or n-conductivity, respectively. The drift layer 11 is therefore n-doped. The second conductivity type is hole conductivity or p-conductivity, respectively, and therefore the corresponding doping is p-type doping. However, the overall concept also works when different regions or layers have opposite types of doping. For example, the doping concentration of the drift layer 11 can be 10 8 cm -3 ~10 15 cm -3 The range is.

[0062] A substrate 15, i.e., a SiC substrate 15, is arranged on the bottom side of the drift layer 11 and adjacent to the drift layer 11. The substrate 15 is also of the first conductivity type, i.e., in this case, n-doped. For example, the doping concentration is in the same range as for the drift layer 11. In a longitudinal direction V perpendicular to the main extension plane of the semiconductor body 1, the substrate 15 is arranged between the further main electrode 6 and the drift layer 11. The further main electrode 6 is adjacent to the substrate 15 and is in electrical contact with it. For example, the further main electrode is made of metal.

[0063] The semiconductor body 1 comprises two base regions 12 spaced apart from each other in a first lateral direction L1, which is parallel to a main extension plane of the semiconductor body 1. The semiconductor body 1 further comprises a drift region 14 arranged between the two base regions 12 in the first lateral direction L1. The base region 12 is of a second conductivity type, i.e., p-doped, and the drift region 14 is of a first conductivity type, i.e., n-doped. The base region 12 is adjacent to the drift region 14 in the first lateral direction L1. The base region 12 and the drift region 14 are arranged between the drift layer 11 and the top surface 10 of the semiconductor body 1 in the vertical direction V. Thus, the drift region 14 and the base region 12 are adjacent to the drift layer 11 and the top surface 10 in the vertical direction V.

[0064] As an example, each of the base regions 12 may have a thickness of 10 15 cm-3 ~10 18 cm -3 The doping concentration is in the range of .gtoreq. ...

[0065] The doping concentration of the drift region 14 may be greater than the doping concentration of the drift layer 11, for example, 10 15 cm -3 ~10 18 cm -3 may be in the range of

[0066] The semiconductor body 1 further comprises two contact regions 13, each assigned to a base region 12. The contact regions 13 are of a first conductivity type and adjoin the respective assigned base region 12 and the upper surface 10 of the semiconductor body 1. In the exemplary embodiment of Fig. 1, the contact regions 13 adjoin the respective assigned base region 12 in a vertical direction V and in a first lateral direction L1. The doping concentration of the first contact regions 13 is, for example, in each case at least 10 19 cm -3 is.

[0067] In the exemplary embodiment of FIG. 1 , the contact regions 13 and the drift regions 14 protrude beyond the base regions 12 in the longitudinal direction V, for example, by at least 1 μm in each case. Thus, the top surface 10 is not flat but has raised sections due to the protruding regions. The contact regions 13 are in electrical contact with the main electrodes 2, which are made of, for example, metal. Gate electrodes 3 are arranged in each case between the contact regions 13 and the drift regions 14 in the first lateral direction L1 and are made of, for example, highly doped polysilicon. Each gate electrode 3 is assigned to a base region 12 and covers the channel portion 12 a of the respective base region 12 in the plan view of the top surface 10. However, in this plan view, the gate electrodes 3 do not overlap the protruding drift regions 14 in the first lateral direction L1, i.e., are not aligned with the drift regions.

[0068] The gate electrode 3 is electrically insulated from the semiconductor body 1 by an electrically insulating material 5, for example SiO2. The electrically insulating material 5 covers the gate electrode 3 on the side facing the semiconductor body 1, on the side facing away from the semiconductor body 1, and on side surfaces extending obliquely to a main extension plane of the semiconductor body 1. In a first lateral direction L1, the contact region 13 and the drift region 14 adjoin the insulating material 5 covering the side surfaces of the gate electrode 3. This is possible because the raised contact region 13 and the raised drift region 14 are partially aligned with the gate electrode 3 in the vertical direction V.

[0069] 1, the contact region 13 projects into the assigned base region 12 such that the channel portion 12a of the base region 12 is partially aligned with the contact region 13 in the longitudinal direction V. The drift region 14 projects deeper into the semiconductor body 1 than the base region 12, i.e., closer to the further main electrode 6 in the longitudinal direction V.

[0070] The power semiconductor device 100 of FIG. 1 is a vertical MOSFET. The electron paths during operation are indicated by arrows. During operation and in the on-state of the MOSFET, the channel portion 12a of the base region 12 is partially depleted with the aid of the gate electrode 3. This allows current, i.e., electrons, to flow from the main electrode 2 through the contact region 13 and the depleted portion of the channel portion 12a to the drift region 14, and from there through the drift layer 11 to the further main electrode 6. The contact region 13 protrudes beyond the base region 12, thereby reducing contact resistance. The laterally misaligned protruding drift region 14 and gate electrode 3 keep the capacitance between the gate electrode 3 and the further main electrode 6 small. The protruding contact region 13 into the base region 12 allows efficient injection of electrons from the contact region 13 into the depleted portion of the channel portion 12a.

[0071] 2 shows a second exemplary embodiment of a power semiconductor device 100, which is also a vertical power MOSFET. In this case, only one base region 12, one contact region 13, and one gate electrode 3 are shown. However, again, there may be several base regions 12 and assigned contact regions 13, as well as several gate electrodes 3.

[0072] As can be inferred from Figure 2, the gate electrode 3 covers or overlaps the contact region 13 and the drift region 14, respectively, in a plan view of the upper surface 10. Furthermore, a first section of the gate electrode 3 tapers in a direction toward the upper surface 10, and a second section tapers in a direction away from the upper surface 10. Thus, in the cross-sectional view of Figure 2, the gate electrode 3 is diamond-shaped. Such a structure can occur if the gate electrode 3 is formed after the contact region 13 and / or after the drift region 14.

[0073] 3 shows a third exemplary embodiment of a power semiconductor device 100 in which only the contact region 13 protrudes beyond the base region 12 at the top surface 10. The gate electrode 3 completely overlaps the drift region 14 in a plan view of the top surface 10.

[0074] FIG. 4 shows a fourth exemplary embodiment of a power semiconductor device 100, in which, in contrast to the previous exemplary embodiments, the contact region 13 protrudes completely through the base region 12 and protrudes deeper into the semiconductor body 1 than the base region 12.

[0075] In all exemplary embodiments of the power semiconductor device 100 shown thus far, the contact region 13 and / or the drift region 14 that protrude beyond the base region 12 may be epitaxially grown.

[0076] FIG. 5 shows a flowchart of an exemplary embodiment of a method for manufacturing a power semiconductor device. In step S1, a semiconductor body having a top surface is manufactured, the semiconductor body having a drift layer of a first conductivity type, a base region of a second conductivity type located vertically between the drift layer and the top surface, a contact region of the first conductivity type located vertically between the drift layer and the top surface and adjacent to the base region and the top surface, and a drift region of the first conductivity type located next to the base region in a first lateral direction. In a further step S2, a main electrode is applied to the top surface, and electrical contact is established between the main electrode and the contact region. In a further step S3, a gate electrode is manufactured such that, at its edge, the gate electrode is located on the top surface and next to the main electrode in the first lateral direction, and in a plan view of the top surface, the gate electrode at least partially overlaps a channel portion of the base region located between the contact region and the drift region in the first lateral direction. In step S1, the semiconductor body is manufactured such that, at the top surface, at least one of the contact region and the drift region protrudes vertically beyond the base region.

[0077] 6 illustrates a position in an exemplary embodiment of a method for manufacturing a power semiconductor device, such as the power semiconductor device 100 of FIG. 1. At this position, a base semiconductor body 1′ is provided, for example, based on the same material system as the semiconductor body of FIG. 1. The base semiconductor body 1′ comprises a substrate 15, an n-doped drift layer 11, and a p-doped base region 12 adjacent to an upper surface of the base semiconductor body 1′. The drift layer 11 and / or the base region 12 may be formed by implantation of dopants. A mask may be used during implantation to produce the laterally spaced-apart base regions 12.

[0078] 7, a gate electrode layer 30 is applied to the top surface of the base semiconductor body 1'. A layer of electrically insulating material 5 is disposed between the base semiconductor body 1' and the gate electrode layer 30.

[0079] 8, the gate electrode layer 30 has been structured in such a way that individual gate electrodes 3 are produced which are spaced apart from one another in a first lateral direction L1. The gate electrodes 3 are electrically insulated from the base semiconductor body 1′ by an electrically insulating material 5 which is structured together with the gate electrode layer 30. A mask-assisted etching process may be used for structuring the gate electrode layer 30 and the underlying electrically insulating material 5.

[0080] 9, an electrically insulating material 5 has been applied onto the side surfaces of the gate electrode 3, these side surfaces extending obliquely relative to the main extension plane of the base semiconductor body 1'. Conformal or non-directional deposition methods may be used to deposit the electrically insulating material 5. Any electrically insulating material that may have been deposited on the top surface of the semiconductor substrate 1' has been removed.

[0081] 10, holes are etched in the base semiconductor body 1', i.e., in the areas where the contact and drift regions are to be fabricated. In the areas where the contact regions are to be fabricated, the etched holes do not protrude completely into the base region 12, but open into it. However, alternatively, the holes in these areas may be etched completely through the base region 12. In the areas where the drift region is to be fabricated, the etched holes are deeper.

[0082] FIG. 11 shows the position where the contact region 13 and the drift region 14 are selectively epitaxially grown in the previously etched area. The growth is performed so that the contact region 13 and the drift region 14 ultimately protrude beyond the base region 12 at the upper surface 10 in the vertical direction V. To grow the contact region 13 and the drift region 14, the gate electrode 3 having the electrically insulating material 5 on each side may be used as a mask for the selective growth process. The growth of the contact region 13 and the drift region 14 has the advantage that the doping concentrations of these regions can be adjusted independently and, for example, can be set to be greater than in an implantation process. FIG. 11 shows the final position in the fabrication of the semiconductor body 1.

[0083] FIG. 12 shows the position where a master electrode 2, for example of metal, is applied onto the top surface 10 of the semiconductor body 1 and an electrical connection is established to a contact area 13 of the master electrode 2.

[0084] To complete the power semiconductor device, a further main electrode may be applied to the back side of the semiconductor body 1 (see FIG. 1).

[0085] As noted above, the illustrated embodiments represent exemplary embodiments of the improved power semiconductor devices and improved methods for manufacturing power semiconductor devices, and therefore, they do not constitute an exhaustive list of all embodiments of the improved power semiconductor devices and methods. Actual power semiconductor devices and methods may differ from the illustrated embodiments, for example, in terms of layout, elements, and order of method steps. [Explanation of symbols]

[0086] Reference sign 1. Semiconductor body 1' base semiconductor body 2 Main electrode 3. Gate electrode 5 Electrical insulating materials 6 Further main electrodes 10 Top side 11 Drift layer 12 Base Area 12a Channel part 13 Contact Area 14 Drift Region 15 PCB 30 gate electrode layer 100 Power Semiconductor Devices L1 First lateral direction V vertical direction Si method steps.

Claims

1. a semiconductor body (1) having a top surface (10); a main electrode (2) on said upper surface (10); a gate electrode (3) located on said top surface (10) and arranged next to said main electrode (2) in a first lateral direction (L1), said gate electrode (3) being electrically insulated from said semiconductor body (1) by an electrically insulating material (5); A power semiconductor device (100) comprising: The semiconductor body (1) a drift layer (11) of the first conductivity type, a base region (12) of a second conductivity type arranged vertically between said drift layer (11) and said top surface (10); a contact region (13) of the first conductivity type arranged vertically between the drift layer (11) and the top surface (10) and adjacent to the base region (12) and the top surface (10); a drift region (14) of the first conductivity type arranged next to the base region (12) in the first lateral direction (L1) and adjacent to the base region (12); Equipped with The main electrode (2) is in electrical contact with the contact area (13), In a plan view of the upper surface (10), the gate electrode (3) at least partially covers a channel portion (12 a) of the base region (12) located between the contact region (13) and the drift region (14) in the first lateral direction (L1), and the channel portion (12 a) is a portion through which charge carriers flow from the contact region (13) to the drift region (14) during operation; At the top surface (10), the drift region (14) projects beyond the base region (12) in a longitudinal direction (V), In a plan view of the upper surface (10), the gate electrode (3) covers at most a part of the drift region (14), The power semiconductor device (100) has a gate electrode (3) and a contact region (13) that protrudes beyond the base region (12), and the gate electrode (3) and the contact region (13) at least partially overlap each other when viewed along the first lateral direction (L1).

2. At least one of the contact region (13) and the drift region (14) is epitaxially grown. The power semiconductor device (100) of claim 1.

3. At least one of the epitaxially grown regions (13, 14) a reverse doping profile in which the doping concentration decreases in a direction from the interior of the semiconductor body (1) towards the top surface (10), or Uniform doping profile The power semiconductor device (100) of claim 2, comprising:

4. the contact region (13) and the channel portion (12a) at least partially overlap each other when viewed along the first lateral direction (L1); A power semiconductor device (100) according to any one of claims 1 to 3.

5. The drift region (14) has a higher doping concentration than the drift layer (11). A power semiconductor device (100) according to any one of claims 1 to 3.

6. In a plan view of the upper surface (10), the gate electrode (3) partially covers the contact region (13). A power semiconductor device (100) according to any one of claims 1 to 3.

7. MOSFET or IGBT or MISFET, A power semiconductor device (100) according to any one of claims 1 to 3.

8. the semiconductor body (1) is based on a wide bandgap semiconductor, A power semiconductor device (100) according to any one of claims 1 to 3.

9. Manufacture of a semiconductor body (1) having a top surface (10), said semiconductor body (1) comprising: a drift layer (11) of the first conductivity type, a base region (12) of a second conductivity type arranged vertically between said drift layer (11) and said top surface (10); a contact region (13) of the first conductivity type arranged vertically between the drift layer (11) and the top surface (10) and adjacent to the base region (12) and the top surface (10); a drift region (14) of the first conductivity type arranged next to the base region (12) in a first lateral direction (L1) and adjacent to the base region (12); and applying a master electrode (2) onto said top surface (10) and establishing electrical contact between said master electrode (2) and said contact area (13); manufacturing the gate electrode (3) so that, at an end, the gate electrode (3) is arranged on the top surface (10) and next to the main electrode (2) in the first lateral direction (L1) and so that, in a plan view of the top surface (10), the gate electrode (3) overlaps at least a channel portion (12a) of the base region (12) between the contact region (13) and the drift region (14) in the first lateral direction (L1), the channel portion (12a) being a portion through which charge carriers flow from the contact region (13) to the drift region (14) during operation, and the gate electrode (3) is electrically insulated from the semiconductor body (1) by an electrically insulating material (5); the semiconductor body (1) is manufactured such that, at the top surface (10), the drift region (14) protrudes beyond the base region (12) in a vertical direction (V), the gate electrode (3) covers at most a part of the drift region (14) in a plan view of the top surface (10), and the gate electrode (3) and the contact region (13) protruding beyond the base region (12) at least partially overlap each other when viewed along the first lateral direction (L1).

10. The manufacturing of the semiconductor body (1) providing a base semiconductor body (1') having said drift layer (11) and said base region (12); epitaxially growing at least one of the contact region (13) and the drift region (14) on the base semiconductor body (1'); 10. The method of claim 9, comprising:

11. 11. The method of claim 10, wherein the reverse doping profile of the epitaxially grown regions (13, 14) is created by reducing the mass flow rate of doping precursors during the epitaxial growth.

12. Before growing the contact region (13), a portion of the base semiconductor body (1') is removed in the area where the contact region (13) is to be formed, The contact region (13) is grown in that area.

12. The method according to claim 10 or 11.

13. Before growing the drift region (14), a portion of the base semiconductor body (1') is removed in the area where the drift region (14) is to be formed, the drift region (14) is grown in that area; 12. The method according to claim 10 or 11.

14. the gate electrode (3) is formed on the base semiconductor body (1'), an electrically insulating material (5) is applied to at least the sides of said gate electrode (3); At least one of the contact region (13) and the drift region (14) is selectively grown adjacent to the gate electrode (3) to which the insulating material (5) is applied.

12. The method according to claim 10 or 11.

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