Electronic device and manufacturing method thereof

Abstract

To improve the performance of an electronic device.SOLUTION: An electronic device includes a substrate 10, a wire 31 formed on the substrate 10, an inorganic insulating layer 14 covering the wire 31, and a bump electrode 33 connected to the wire 31 at a position overlapping with a first opening part formed in the inorganic insulating layer 14 and protruding from the inorganic insulating layer 14. The wire 31 is a multilayer film including a first conductor layer formed of titanium or titanium alloy and formed on the substrate 10, and a second conductor layer formed of aluminum or aluminum alloy and stacked on the first conductor layer. The bump electrode 33 includes a conductor part 33A formed of copper or copper alloy and bonded to the wire 31, and a conductor part 33B formed of solder containing tin and formed on the conductor part 33A.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to electronic devices and methods for manufacturing the same. [Background technology]

[0002] There is an electronic device in which electronic components are mounted on a plurality of electrodes arranged on a substrate. For example, Japanese Patent Application Laid-Open No. 2021-85904 (Patent Document 1) describes an LED (Light Emitting Diode) display device in which a plurality of light-emitting elements are mounted on a plurality of electrodes arranged on a substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-85904 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, in the case of electronic devices with large planar dimensions, such as LED display devices, a titanium-aluminum-titanium laminate film (hereinafter, this laminate film may be referred to as a TAT laminate film) may be used as a wiring material for transmitting power and signals to drive multiple electronic components. When forming bump electrodes on this wiring to connect to electronic components, it is preferable to form the bump electrodes made of a metal material with low electrical resistance, such as copper. However, when forming copper bump electrodes on wiring made of TAT, it has been found that there is room for improvement in terms of the shape of the bump electrodes and the complexity of the manufacturing process.

[0005] An object of the present invention is to provide a technique for improving the performance of electronic devices. [Means for solving the problem]

[0006] An electronic device according to one embodiment includes a first substrate made of glass or resin, a first wiring formed on the first substrate, an inorganic insulating layer made of an inorganic material and covering the first wiring, and a bump electrode connected to the first wiring at a position overlapping a first opening formed in the first insulating layer and protruding from the first insulating layer. The first wiring is a laminated film including a first conductor layer made of titanium or a titanium alloy and formed on the first substrate, and a second conductor layer made of aluminum or an aluminum alloy and laminated on the first conductor layer. The bump electrode includes a first conductor portion made of copper or a copper alloy and joined to the first wiring, and a second conductor portion made of solder containing tin and formed on the first conductor portion.

[0007] A method for manufacturing an electronic device according to another embodiment includes the steps of: (a) preparing a substrate structure including a first substrate made of glass or resin, a first wiring formed on the first substrate, and a first insulating layer made of an inorganic material and covering the first wiring; (b) removing an aluminum oxide film formed on an exposed surface of the first wiring at a position overlapping a first opening formed in the first insulating layer; and (c) forming, after step (b), a bump electrode connected to the first wiring at a position overlapping the first opening and protruding from the first insulating layer. The first wiring is a laminated film including a first conductor layer made of titanium or a titanium alloy and formed on the first substrate; and a second conductor layer made of aluminum or an aluminum alloy and laminated on the first conductor layer. The step (c) includes the steps of: (c1) selectively depositing a first conductor portion made of copper or a copper alloy by electroplating at a position overlapping with and around the first opening while current is flowing through the first wiring; and (c2) after the step (c1), selectively depositing a second conductor portion made of solder containing tin on the first conductor portion while current is flowing through the first wiring. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view showing a configuration example of a micro LED display device that is an embodiment of an electronic device. [Figure 2] 2 is a circuit diagram showing an example of the configuration of a circuit around the pixel shown in FIG. 1. [Figure 3] 2 is an enlarged transparent plan view showing an example of a peripheral structure of LED elements arranged in each of a plurality of pixels of the display device shown in FIG. [Figure 4] FIG. 4 is an enlarged cross-sectional view taken along line AA in FIG. 3. [Figure 5] FIG. 4 is an enlarged plan view showing a state in which the LED element shown in FIG. 3 has been removed. [Figure 6] 5 is an enlarged cross-sectional view of the vicinity of the bonding interface between the wiring and the bump electrode shown in FIG. 4. [Figure 7] FIG. 7 is an enlarged cross-sectional view showing a modification of FIG. 6. [Figure 8] FIG. 7 is an enlarged cross-sectional view showing another modified example of FIG. 6. [Figure 9] FIG. 7 is an enlarged cross-sectional view showing another modified example of FIG. 6. [Figure 10] FIG. 5 is an enlarged cross-sectional view showing a modification of FIG. 4. [Figure 11] 1A to 1C are explanatory diagrams showing an example of a process flow of a method for manufacturing a display device, which is an embodiment of an electronic device. [Figure 12] 12 is an enlarged plan view of a substrate structure prepared in a substrate structure preparing step shown in FIG. 11. FIG. [Figure 13] FIG. 13 is an enlarged cross-sectional view taken along line BB in FIG. [Figure 14] FIG. 14 is an enlarged cross-sectional view showing a modification of FIG. [Figure 15] 12 is an enlarged cross-sectional view showing a state in which the aluminum oxide film has been removed by etching in the oxide film removing step shown in FIG. 11. FIG. [Figure 16] FIG. 12 is an enlarged cross-sectional view showing a state in which an aluminum oxide film has been removed by zincate treatment in the oxide film removing step shown in FIG. 11. [Figure 17] 12 is an enlarged cross-sectional view showing a first film forming step shown in FIG. 11. FIG. [Figure 18] FIG. 12 is an enlarged cross-sectional view showing the second film forming step shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, in order to clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment. However, these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, elements similar to those described above with reference to the previous drawings may be designated by the same or related reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] In the following embodiments, a micro LED display device equipped with multiple micro LED elements and a bump electrode array device before the micro LED elements are mounted will be described as examples of electronic devices in which a bump electrode array for mounting multiple electronic components is arranged.

[0011] <Electronic equipment> First, a configuration example of a micro LED display device, which is an electronic device of this embodiment, will be described. Fig. 1 is a plan view showing a configuration example of a micro LED display device, which is an embodiment of the electronic device. In Fig. 1, the boundary between the display area DA and the peripheral area PFA, the control circuit 5, the drive circuit 6, and the multiple pixels PIX are each indicated by a two-dot chain line. Fig. 2 is a circuit diagram showing a configuration example of the circuit around the pixels shown in Fig. 1.

[0012] As shown in Fig. 1, the display device DSP1 of this embodiment has a display area DA, a peripheral area PFA that surrounds the periphery of the display area DA in a frame shape, and a plurality of pixels PIX arranged in rows and columns within the display area DA. The display device DSP1 also has a substrate 10, a control circuit 5 formed on the substrate 10, and a drive circuit 6 formed on the substrate 10. The substrate 10 is made of glass or resin. The substrate 10 has a surface 10t and a surface 10b opposite to the surface 10t.

[0013] The control circuit 5 is a control circuit that controls the driving of the display function of the display device DSP1. For example, the control circuit 5 is a driver IC (Integrated Circuit) mounted on the substrate 10. In the example shown in FIG. 1, the control circuit 5 is arranged along one of the four short sides of the substrate 10. In the example of the present embodiment, the control circuit 5 includes a signal line drive circuit that drives the wiring (video signal wiring) VL (see FIG. 2) connected to the multiple pixels PIX. However, the position and configuration of the control circuit 5 are not limited to the example shown in FIG. 1 and various modifications are possible. For example, in FIG. 1, a circuit board such as a flexible board may be connected to the position shown as the control circuit 5, and the above-mentioned driver IC may be mounted on the circuit board. In addition, for example, the signal line drive circuit that drives the wiring VL may be formed separately from the control circuit 5.

[0014] The drive circuit 6 includes a circuit that drives the scanning signal lines GL (see FIG. 2, described later) of the multiple pixels PIX. The drive circuit 6 also includes a circuit that supplies a reference potential to the LED elements mounted on each of the multiple pixels PIX. The drive circuit 6 drives the multiple scanning signal lines GL based on control signals from the control circuit 5. In the example shown in FIG. 1, the drive circuit 6 is arranged along each of two of the four long sides of the substrate 10. However, the position and configuration of the drive circuit 6 are not limited to the example shown in FIG. 1, and various modifications are possible. For example, in FIG. 1, a circuit board such as a flexible board may be connected to the position shown as the control circuit 5, and the above-mentioned drive circuit 6 may be mounted on the circuit board.

[0015] Next, an example of the circuit configuration of a pixel PIX will be described using Fig. 2. Note that Fig. 2 shows four pixels PIX as representative examples, but each of the multiple pixels PIX shown in Fig. 1 has a circuit similar to that of the pixel PIX shown in Fig. 2. Hereinafter, the switch provided in the pixel PIX and the circuit including the LED element 20 may be referred to as the pixel circuit. The pixel circuit is a voltage signal type circuit that controls the light emission state of the LED element 20 in response to the video signal Vsg supplied from the control circuit 5 (see Fig. 1).

[0016] As shown in FIG. 2, the pixel PIX includes an LED element 20. The LED element 20 is the above-described micro light-emitting diode. The LED element 20 has an anode electrode 20EA and a cathode electrode 20EK. The cathode electrode 20EK of the LED element 20 is connected to a wiring VSL to which a reference potential (fixed potential) PVS is supplied. The anode electrode 20EA of the LED element 20 is electrically connected to the drain electrode ED of the switching element SW via a wiring 31.

[0017] The pixel PIX includes a switching element SW. The switching element SW is a transistor that controls the connection state (on or off state) between the pixel circuit and the wiring VL in response to a control signal Gs. The switching element SW is, for example, a thin film transistor. When the switching element SW is in the on state, a video signal Vsg is input to the pixel circuit from the wiring VL.

[0018] The drive circuit 6 includes a shift register circuit, an output buffer circuit, etc. not shown in the figure. The drive circuit 6 outputs a pulse based on a horizontal scan start pulse transmitted from the control circuit 5 (see FIG. 1) and outputs a control signal Gs.

[0019] Each of the plurality of scan signal lines GL extends in the X direction. The scan signal line GL is connected to the gate electrode of the switching element SW. When a control signal Gs is supplied to the scan signal line GL, the switching element SW becomes in the on state, and a video signal Vsg is supplied to the LED element 20.

[0020] <Peripheral Structure of LED Element> Next, the peripheral structure of the LED elements arranged in each of the plurality of pixels PIX shown in FIG. 1 will be described. FIG. 3 is an enlarged transparent plan view showing an example of the peripheral structure of the LED elements arranged in each of the plurality of pixels of the display device shown in FIG. 1. In FIG. 3, the inorganic insulating layer 14 shown in FIG. 4 is omitted. In FIG. 3, the outlines of the semiconductor layer, electrodes, and scanning signal lines are indicated by dotted lines. FIG. 4 is an enlarged cross-sectional view taken along line AA in FIG. 3. FIG. 5 is an enlarged plan view showing a state in which the LED elements shown in FIG. 3 have been removed. FIG. 6 is an enlarged cross-sectional view of the vicinity of the bonding interface between the wiring and the bump electrode shown in FIG. 4. FIGS. 7, 8, and 9 are enlarged cross-sectional views showing modifications of FIG. 6.

[0021] As shown in FIG. 3, the display device DSP1 has a plurality of pixels PIX including pixel PIX1 (pixels PIX1, PIX2, and PIX3 in the example shown in FIG. 4). Each of the plurality of pixels PIX has a switching element SW, an LED element (light-emitting element) 20, wiring 31, and wiring 32. Each of the pixels PIX1, PIX2, and PIX3 is equipped with an LED element 20 that emits visible light of one color, for example, red, green, or blue, and is provided with a switching element SW that drives the LED element 20. Color display is possible by controlling the output and timing of the visible light emitted from the LED elements of the pixels PIX1, PIX2, and PIX3. When a plurality of pixels PIX emitting visible light of different colors are combined in this manner, the pixels PIX for each color are sometimes called subpixels, and a set of the plurality of pixels PIX is sometimes called a pixel. In this embodiment, the portion corresponding to the subpixel is called a pixel PIX.

[0022] The wiring 31 is electrically connected to the drain electrode ED of the switching element SW and the anode electrode 20EA of the LED element 20. The wiring 32 is connected to the source electrode ES of the switching element SW. In the example shown in FIG. 3, the wiring 32 has a bent structure, with one end connected to the source electrode ES of the switching element SW and the other end connected to the wiring VL. The scanning signal line GL is used as the gate electrode EG of the switching element SW.

[0023] The display device DSP1 further includes a wiring VL extending across multiple pixels PIX (see FIG. 2) along the Y direction and electrically connected to the wiring 32, and a wiring VSL extending across multiple pixels PIX along the X direction intersecting the Y direction (orthogonal in FIG. 3) and electrically connected to the cathode electrode 20EK of the LED element 20. The wiring VL and the wiring VSL intersect at a wiring intersection LXP shown in FIG. 3 via an insulating layer 41. The insulating layer 41 intervenes between the wiring VL and the wiring VSL, electrically isolating the wiring VL and the wiring VSL. Note that the layout shown in FIG. 3 is merely an example, and various modifications are possible. For example, as a modification of FIG. 3, the switching element SW may have a gate electrode (not shown) connected to the scanning signal line GL. In this modification, the scanning signal line GL may be positioned so as not to overlap with the semiconductor layer 50.

[0024] As shown in Figure 4, display device DSP1 is an electronic device including a substrate 10 made of glass or resin and a plurality of insulating layers laminated on substrate 10. The plurality of insulating layers included in display device DSP1 include inorganic insulating layer 11, inorganic insulating layer 12, inorganic insulating layer 13, and inorganic insulating layer 14 laminated on substrate 10. Substrate 10 has a surface 10f and a surface 10b opposite surface 10f. Each of inorganic insulating layers 11, 12, 13, and 14 is laminated on surface 10f of substrate 10.

[0025] The switching element SW includes an inorganic insulating layer 12 formed on a substrate 10, a semiconductor layer 50 formed on the inorganic insulating layer 12, a drain electrode ED connected to the drain region of the semiconductor layer 50, a source electrode ES connected to the source region of the semiconductor layer 50, and an inorganic insulating layer 13 covering the semiconductor layer 50. As shown in FIG. 6, each of the wiring 31 and the wiring 32 is a laminated film of a conductor layer 30A and a conductor layer 30B. The conductor layer 30A is made of titanium or a titanium alloy and is formed on the inorganic insulating layer 13. The conductor layer 30B is made of aluminum or an aluminum alloy and is laminated on the conductor layer 30A.

[0026] The example shown in FIG. 4 is a bottom-gate example in which the gate electrode EG is located between the semiconductor layer 50 and the substrate 10. In the bottom-gate example, the portion of the inorganic insulating layer 12 located between the gate electrode EG and the semiconductor layer 50 functions as a gate insulating layer. The inorganic insulating layer 12 also functions as a base layer for forming the semiconductor layer 50. The position of the gate electrode EG is not limited to the example shown in FIG. 4, and may be, for example, a top-gate example, which will be described later as a modified example.

[0027] There are no particular limitations on the material constituting each of the inorganic insulating layers 11, 12, 13, and 14. Examples include silicon oxide (SiO2) and silicon nitride (SiN). The semiconductor layer 50 is a semiconductor film in which a silicon film made of silicon is doped with impurities of P-type or N-type conductivity.

[0028] The source electrode ES and the drain electrode ED are each a contact plug for making electrical contact with either the source region or the drain region of the semiconductor layer 50. Examples of materials for the contact plugs include tungsten. As a variation of FIG. 4 , contact holes exposing the source region and the drain region of the semiconductor layer 50 are formed in the inorganic insulating layer 13, and portions of the wiring 31 and the wiring 32 are embedded in the contact holes. In this case, the portions of the wiring 31 and the wiring 32 embedded in the contact holes contact the semiconductor layer 50, and the contact interfaces between the wiring 31 and the wiring 32 and the semiconductor layer 50 can be regarded as the drain electrode ED and the source electrode ES.

[0029] 5, the display device DSP1 is provided with a plurality of bump electrodes 33 that are regularly arranged in a plan view. The bump electrodes 33 are terminals for mounting electronic components on the substrate 10 (see FIG. 4). In the present embodiment, the bump electrodes 33 are terminals for mounting the LED element 20 shown in FIG. 4. Therefore, one of the two bump electrodes is connected to the anode electrode 20EA of the LED element 20, and the other is connected to the cathode electrode 20EK of the LED element 20. Therefore, in the present embodiment, the plurality of bump electrodes 33 are arranged two next to each other in the region where the LED element 20 (see FIG. 3) is to be mounted.

[0030] 6, the bump electrode 33 is connected to the wiring 31 at a position overlapping with the opening 14H formed in the inorganic insulating layer 14, and protrudes from the inorganic insulating layer 14. The bump electrode 33 also includes a conductor portion 33A made of copper or a copper alloy and connected to the conductor layer 30B of the wiring 31, and a conductor portion 33B made of solder containing tin and formed on the conductor portion 33A. In this way, the use of the conductor portion 33A made of copper or a copper alloy can improve the electrical characteristics of the bump electrode 33.

[0031] However, when a bump electrode 33 made of copper or a copper alloy is bonded to a wiring made of a TAT laminate film, it has been found that the connection reliability between the titanium in the top layer of the TAT laminate film and the copper of the bump electrode is low. To address this issue, we investigated methods such as roughening the surface of the titanium in the top layer of the TAT laminate film and depositing a titanium film and a copper film in sequence on the TAT laminate film, but in neither case was we able to achieve the high connection reliability we aimed for. In particular, when a bump electrode is formed by depositing a uniform copper film and then removing the unnecessary copper film by etching using a resist mask, the side surfaces become cliff-like. As a result, the bonding interface between the bump electrode and the wiring is easily destroyed by stress acting in a direction intersecting the side surfaces.

[0032] Therefore, the inventors of the present application investigated the possibility of forming a laminated film structure of the wiring 31 (and wiring VSL) connected to the bump electrode 33 shown in FIG. 4, including conductor layers 30A and 30B, and joining the conductor layer 30B made of aluminum or an aluminum alloy to the conductor portion 33A made of copper or a copper alloy. An oxide film is easily formed on the surface of the conductor layer 30B, which mainly contains aluminum. Therefore, after the opening 14H is formed, a process for removing the oxide film is performed before forming the conductor portion 33A of the bump electrode 33. Examples of methods for removing this oxide film include etching, zincating, or a combination of these processes, as described below. Forming the conductor portion 33B on the conductor layer 30B after removing the oxide film can improve the bonding strength at the bonding interface between copper and aluminum. Furthermore, the strength of the bonding interface between aluminum and copper is stronger than the strength of the bonding interface between copper and titanium. Therefore, in this embodiment, the bonding strength between the wiring 31 (or wiring VSL) and the bump electrode 33 can be improved.

[0033] Among the methods for removing the oxide film described above, the zincate treatment is a treatment for replacing the aluminum oxide film with a zincate film. Therefore, when the zincate treatment is performed as a treatment for removing the oxide film, a conductor layer 30C containing zinc is further formed on the conductor layer 30B in the portion of the wiring 31 (or wiring VSL) that overlaps with the opening 14H, as shown in a modified example in FIG. 7 .

[0034] Furthermore, among the methods for removing the oxide film described above, the etching process is a process in which a portion of the conductor layer 30B exposed through the opening 14H is brought into contact with an etching solution (or etching gas) to remove a portion of the conductor layer 30B. Therefore, by controlling the etching rate and etching time, the portion of the conductor layer 30B that is covered by the inorganic insulating layer 14 around the opening 14H is also removed, as shown in FIG. 8. In this case, when the conductor portion 33A of the bump electrode 33 is formed after the etching process, a portion of the conductor portion 33A is buried directly below the inorganic insulating layer 14, as shown in FIG. 8. In other words, in the case of the modified example shown in FIG. 8, a region in which a portion of the conductor portion 33A of the bump electrode 33 is buried exists around the opening 14H between the inorganic insulating layer 14 and the conductor layer 30B of the wiring 31 (or wiring VSL).

[0035] In the structure shown in FIG. 8, the portion of the conductor portion 33A embedded directly below the inorganic insulating layer 14 acts as an anchor. Therefore, even when stress acting in a direction along the surface 10t of the substrate 10 shown in FIG. 4 is applied to the bump electrode 33, the bump electrode 33 is unlikely to peel off from the wiring 31 (or wiring VSL). In other words, in the structure shown in FIG. 8, the anchor effect of the portion of the conductor portion 33A embedded directly below the inorganic insulating layer 14 can improve the connection reliability between the bump electrode 33 and the wiring 31 (or wiring VSL). Note that FIG. 8 is shown as a modification of FIG. 6, but as shown in FIG. 9, the technique for roughening the bonding interface between the conductor layer 30B and the conductor portion 33A can be applied in combination with the modification shown in FIG. 7. When the modification shown in FIG. 7 and the modification shown in FIG. 8 are combined, the conductor layer 30C shown in FIG. 7 is formed between the conductor layer 30B and the conductor portion 33A shown in FIG. 8.

[0036] As another modification, as shown in FIG. 9, there is a method for improving the connection reliability between the bump electrode 33 and the wiring 31 (or wiring VSL) by roughening the bonding interface between the bump electrode 33 and the wiring 31 (or wiring VSL). In the example shown in FIG. 9, the surface roughness of the bonding interface (surface 30Bt1 in FIG. 9) with the conductor portion 33A of the bump electrode 33 in the conductor layer 30B of the wiring 31 (or wiring VSL) is rougher than the surface roughness of the portion (surface 30Bt2 in FIG. 9) covered with the inorganic insulating layer 14. This improves the bonding strength between the conductor portion 33A and the conductor layer 30B. Note that FIG. 9 is shown as a modification of FIG. 6, but the technique for roughening the bonding interface between the conductor layer 30B and the conductor portion 33A as shown in FIG. 9 can be applied in combination with the modification shown in FIG. 7 or the modification shown in FIG. 8. When the modified example shown in Fig. 7 is combined with the modified example shown in Fig. 9, the bonding interface between the conductor layer 30C and the conductor portion 33A shown in Fig. 7 is a surface that is roughened more than the surface roughness of the surface 30Bt2, similar to the surface 30Bt1 shown in Fig. 9. Furthermore, when the modified example shown in Fig. 8 is combined with the modified example shown in Fig. 9, the bonding interface between the conductor layer 30B and the conductor portion 33A shown in Fig. 8 is a surface that is roughened more than the surface roughness of the surface 30Bt2, similar to the surface 30Bt1 shown in Fig. 9.

[0037] 4 shows an example in which the wiring 31 is connected to the semiconductor layer 50 via the drain electrode ED. However, as in the display device DSP2 shown as a modified example in FIG. 10, the wiring 31 connected to the bump electrode 33 may be connected to another wiring 34. FIG. 10 is an enlarged cross-sectional view showing a modified example of FIG. 4.

[0038] The display device DSP2 shown in FIG. 10 differs from the display device DSP1 shown in FIG. 4 in that it further includes wiring 34 formed on the substrate 10 and an organic insulating layer 15 covering the wiring 34. The organic insulating layer 15 is made of a visible light-transmitting organic material (e.g., a resin material) such as acrylic resin. The wiring 31 is formed on the organic insulating layer 15 and is connected to the wiring 34 through an opening 15H formed in the organic insulating layer 15. The organic insulating layer 15 has better hole-filling properties than the inorganic insulating layer 14. Therefore, by arranging the organic insulating layer 15 below the wiring 31 connected to the bump electrode 33, the flatness of the base layer for forming the bump electrode 33 can be improved.

[0039] Furthermore, a TAT laminated film can be used for a conductive pattern that does not contact the conductor portion 33A made of copper or a copper alloy, such as the wiring 34. In the example shown in Fig. 10, the wiring 34 is a laminated film including a conductor layer 30D made of titanium or a titanium alloy, a conductor layer 30E made of aluminum or an aluminum alloy and laminated on the conductor layer 30D, and a conductor layer 30F made of titanium or a titanium alloy and laminated on the conductor layer 30E. The conductor layer 30F of the wiring 34 and the conductor layer 30A of the wiring 31 are joined at the opening 15H.

[0040] <Electronic Device Manufacturing Method> Next, a method for manufacturing an electronic device according to this embodiment will be described, taking as a representative example the method for manufacturing the display device DSP1 shown in Fig. 3. The following description will focus on the process of forming bump electrodes 33 in openings 14H shown in Fig. 4. Fig. 11 is an explanatory diagram showing an example of the process flow of the method for manufacturing a display device, which is one embodiment of an electronic device.

[0041] 11, the method for manufacturing an electronic device according to this embodiment includes a substrate structure preparation step, an oxide film removal step, a bump electrode formation step, and an electronic component mounting step. Note that if the substrate structure before the electronic components are mounted is shipped as a semi-finished product, the electronic component mounting step can be omitted.

[0042] In the substrate structure preparation step shown in FIG. 11, a substrate structure SUB1 shown in FIGS. 12 and 13 is prepared. FIG. 12 is an enlarged plan view of the substrate structure prepared in the substrate structure preparation step shown in FIG. 11. FIG. 13 is an enlarged cross-sectional view taken along line BB in FIG. 12. As shown in FIG. 13, in the substrate structure preparation step, a substrate structure SUB1 is prepared, which includes a substrate 10 made of glass or resin, wiring 31 formed on the substrate 10, and an inorganic insulating layer 14 covering the wiring 31. In the example shown in FIG. 13, inorganic insulating layers 11, 12, 13, and 14 are stacked on the substrate 10, and the wiring 31 is disposed between the inorganic insulating layer 13 and the inorganic insulating layer 14. Most of the substrate structure SUB1 is covered by the inorganic insulating layer 14. Openings 14H are formed in the inorganic insulating layer 14 at positions overlapping the wiring 31 and the wiring VSL. At the bottom of the opening 14H, the wiring 31 and the wiring VSL are exposed from the inorganic insulating layer 14.

[0043] As shown in Fig. 12, in a plan view, each of the plurality of openings 14H is regularly arranged in an area where an electronic component (LED element 20 shown in Fig. 3) is to be mounted. In other words, in a plan view, each of the plurality of openings 14H is formed in an area where a bump electrode 33 shown in Fig. 4 is to be formed. When manufacturing the display device DSP1 described using Fig. 10, in the substrate structure preparation step shown in Fig. 11, a substrate structure SUB2 shown in Fig. 14 is prepared. Fig. 14 is an enlarged cross-sectional view showing a modification of Fig. 13.

[0044] The substrate structure SUB2 shown in FIG. 14 differs from the substrate structure SUB1 shown in FIG. 13 in the following respects. Specifically, in addition to the structure shown in the substrate structure SUB1 shown in FIG. 13, the substrate structure SUB2 further includes wiring 34 formed on the substrate 10 and an organic insulating layer 15 covering the wiring 34. The wiring 31 is formed on the organic insulating layer 15 and is connected to the wiring 34 through an opening 15H formed in the organic insulating layer 15. The wiring 34 is a laminated film including a conductor layer 30D made of titanium or a titanium alloy, a conductor layer 30E made of aluminum or an aluminum alloy and laminated on the conductor layer 30D, and a conductor layer 30F made of titanium or a titanium alloy and laminated on the conductor layer 30E. The conductor layer 30F of the wiring 34 and the conductor layer 30A of the wiring 31 are joined together through the opening 15H.

[0045] Next, in the oxide film removal step shown in Fig. 11, the aluminum oxide film formed on the exposed surface of the wiring 31 (and wiring VSL) at a position overlapping with the opening 14H formed in the insulating layer 14 shown in Fig. 13 or 14 is removed. Figs. 15 and 16 are enlarged cross-sectional views showing the state after the aluminum oxide film has been removed in the oxide film removal step shown in Fig. 11. Examples of methods for removing the aluminum oxide film include an etching process exemplified in Fig. 15, a zincate process exemplified in Fig. 16, or a combination of these processes.

[0046] In the example shown in FIG. 13 or 14 , an oxide film is formed on the portion of the wiring 31 (and wiring VSL) exposed in the opening 14H. In the example shown in FIG. 15 , the conductor layer 30B is selectively etched by bringing an etching solution or etching gas into contact with the exposed surface of the wiring 31 (and wiring VSL). If an etching material that etches isotropically from the contact surface with the etching material is used in the etching process, a portion of the conductor layer 30B sandwiched between the inorganic insulating layer 14 and the conductor layer 30A is also etched. Therefore, as shown in FIG. 15 , a space exists around the opening 14H between the inorganic insulating layer 14 and the conductor layer 30B of the wiring 31 (or wiring VSL). As a result, as described with reference to FIG. 8 , a portion of the conductor portion 33A is buried directly below the inorganic insulating layer 14. In addition, by adjusting the etching time and etching material in the etching process, the exposed portion of the etched conductor layer 30B may be roughened. 15, after the oxide film removal step, the surface roughness of the portion of the conductor layer 30B of the wiring 31 (or wiring VSL) that is exposed from the inorganic insulating layer 14 (surface 30Bt1 in FIG. 15) is rougher than the surface roughness of the portion that is covered with the inorganic insulating layer 14 (surface 30Bt2 in FIG. 9). In this case, as described with reference to FIG. 9, the bonding strength between the conductor portion 33A and the conductor layer 30B can be improved.

[0047] In the example shown in FIG. 16, a zincate treatment is performed on the aluminum oxide film formed on the exposed surface of the wiring 31 (and the wiring VSL), replacing the aluminum oxide film with a zincate film. The zincate treatment involves dissolving aluminum by contacting it with a zincate solution, and reducing the zinc in the zincate solution to deposit a zincate film on the surface of the conductor layer 30B. As a result, as described with reference to FIG. 7, a conductor layer 30C containing zinc is further formed on the conductor layer 30B in the portion of the wiring 31 (or the wiring VSL) overlapping the opening 14H. The conductor layer 30C is less susceptible to oxidation than the conductor layer 30B, and therefore can improve the reliability of electrical connection with the conductor portion 33A (see FIG. 7) of the bump electrode 33 (see FIG. 7) made of copper or a copper alloy.

[0048] Note that the zincate treatment described with reference to FIG. 16 may be performed after the etching treatment described with reference to FIG. 15 . In this case, the conductor layer 30C shown in FIG. 16 is formed on the entire surface of the conductor layer 30B shown in FIG. 15 that is exposed from the inorganic insulating layer 14. When the etching treatment and the zincate treatment are combined, even if the surface of the etched conductor layer 30B is oxidized after the etching treatment and before the start of the bump electrode formation process shown in FIG. 11 , the oxide film can be removed again. When the etching treatment and the zincate treatment are combined, the roughening treatment by etching described with reference to FIG. 15 can also be performed at the same time. The conductor layer 30C is formed according to the surface condition of the underlying conductor layer 30B. Therefore, if the surface of the conductor layer 30B is roughened as shown in FIG. 15 , the surface roughness of the conductor layer 30C formed on the conductor layer 30B will be rougher than the surface roughness of the surface 30Bt2 shown in FIG. 15 .

[0049] Next, in the bump electrode formation step shown in FIG. 11, the bump electrode 33 described with reference to FIG. 4 or FIG. 10 is formed. In the following, the step of forming the bump electrode 33 shown in FIG. 4 will be illustrated and described as a representative example, but the method of forming the bump electrode 33 shown in FIG. 10 is also similar. FIG. 17 is an enlarged cross-sectional view showing the first film formation step shown in FIG. 11. FIG. 18 is an enlarged cross-sectional view showing the second film formation step shown in FIG. 11. Each of FIG. 17 and FIG. 18 corresponds to the cross section shown in FIG. 13.

[0050] First, in the first film formation process, the conductor portion 33A shown in FIG. 17 is formed. One method for forming a metal film made of copper or a copper alloy involves uniformly growing a copper film on the inorganic insulating layer 14 and then removing the unnecessary copper film using a resist mask (hereinafter referred to as the bump electrode formation method of the study example). However, in this case, as described above, the side surfaces of the resulting bump electrode become cliff-like, making the bonding interface between the bump electrode and the wiring susceptible to damage due to stress acting in a direction intersecting the side surfaces. Furthermore, from the perspective of the manufacturing method, in addition to the copper film formation process, the process of forming a resist mask, selectively forming openings in the resist mask using photolithography, selectively etching the copper film through the resist mask with the openings, and removing the resist mask are required. As such, the bump electrode formation method of the study example requires a complex manufacturing process, leaving room for improvement in terms of improving manufacturing efficiency. Furthermore, to perform the resist mask exposure process with high precision, an exposure device such as a stepper is required, and a large exposure device corresponding to the size of the substrate 10 must be prepared.

[0051] In this embodiment, while a current is applied to the wiring 31 (or wiring VSL), a conductor portion 33A made of copper or a copper alloy is formed by electroplating. Specifically, while a current is applied to the wiring 31 (or wiring VSL), the conductor portion 33A made of copper or a copper alloy is selectively formed by electroplating at a position overlapping with the opening 14H and its periphery. In this case, a copper film (or a copper alloy film) can be selectively grown from the contact interface with the wiring 31 (or wiring VSL). Therefore, compared to the bump electrode formation method of the study example, the manufacturing process can be made more efficient. Furthermore, in this embodiment, a copper film can be selectively grown on the portion of the wiring 31 (or wiring VSL) that is exposed from the inorganic insulating layer 14. Therefore, there is no need to newly prepare a large-scale exposure device such as a large stepper. Note that, since current can be applied to the wiring 31 and the wiring VSL simultaneously, the conductor portion 33A on the wiring 31 and the conductor portion 33A on the wiring VSL can be formed simultaneously.

[0052] In the first film formation process, the conductor portion 33A made of copper or a copper alloy is formed by electroplating. The conductor portion 33A grows within the opening 14H, conforming to the shape of the opening 14H. Above the opening 14H, the conductor portion 33A grows isotropically around the opening 14H. Therefore, the conductor portion 33A spreads around the opening 14H. The conductor portion 33A that spreads around the opening 14H adheres closely to the inorganic insulating layer 14. Therefore, by increasing the area of ​​the portion that spreads around the opening 14H, the adhesion area between the conductor portion 33A and the inorganic insulating layer 14 can be increased. Furthermore, when a portion of the conductor portion 33A spreads isotropically around the opening 14H, as in this embodiment, each of the multiple bump electrodes 33 forms a circle in a plan view, as shown in FIG. 3 . In the example shown in FIG. 12 , the opening 14H is also circular. However, even if the opening 14H were rectangular, the planar shape of the bump electrode 33 would still be circular. As shown in FIG. 17, the cross section of the conductor portion 33A has a mushroom shape with the cap portion extending above the inorganic insulating layer 14.

[0053] Next, in the second film-forming process shown in FIG. 11, after the first film-forming process, as shown in FIG. 18, a conductor portion 33B made of solder containing tin is selectively formed on the conductor portion 33A while the wiring 31 (or wiring VSL) is energized. When forming the solder film, similar to the case of forming the copper film in the first film-forming process, electroplating is used to form the conductor portion 33B by spreading the solder film isotropically on the surface of the energized conductor portion 33A. The shape of the conductor portion 33B shown in FIG. 18 differs from the shape of the conductor portion 33B shown in FIG. 4. This is because the shape changes when the solder melts during a reflow process performed when mounting electronic components in the electronic component mounting process shown in FIG. 11. Immediately after the second film-forming process is completed, a dome-shaped conductor portion 33B is formed, covering the entire umbrella portion of the mushroom-shaped conductor portion 33A.

[0054] In the step of forming the conductor portion 33A, copper or a copper alloy may not be filled entirely in the opening 14H. In this case, in the second film-forming step, a portion of the conductor portion 33B may be filled in the opening 14H. Furthermore, as described with reference to FIG. 16, when a space is formed between the inorganic insulating layer 14 and the conductor layer 30A, a portion of the solder may be filled in the space.

[0055] As described above, there are cases where the substrate structure SUB1 before electronic components are mounted is shipped as a semi-finished product. In this case, the electronic component mounting step shown in Fig. 11 is omitted, and the substrate structure SUB1 shown in Fig. 18 undergoes the necessary inspection and packaging before being prepared for shipping. That is, the substrate structure SUB1 as an electronic device is obtained by the second film formation step shown in Fig. 18.

[0056] Next, in the electronic component mounting process shown in FIG. 11, after the bump electrode formation process, the bump electrode 33 and the electronic component (the LED element 20 in the example of FIG. 4) are electrically connected as shown in FIG. 4. In this process, the conductor portion 33B shown in FIG. 18 is melted by a reflow process and bonded to the anode electrode 20EA or the cathode electrode 20EK of the LED element 20. Note that, prior to this process, a solder film may be formed in advance on each of the anode electrode 20EA and the cathode electrode 20EK of the LED element 20. In this case, the conductor portion 33B made of solder and the solder film formed on the electrode can be easily integrated, thereby ensuring a reliable connection between the bump electrode 33 and the cathode electrode 20EK (or the anode electrode 20EA).

[0057] Through the above steps, the display device DSP1 is obtained as an electronic device as shown in Fig. 3. After this step, the display device DSP1 undergoes the necessary inspection and packaging, and then preparations for shipment begin.

[0058] Although the embodiment and representative modifications have been described above, the above-described technology can be applied to various modifications other than the modifications exemplified. For example, the above-described modifications may be combined with each other.

[0059] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications and alterations, and it is understood that these modifications and alterations also fall within the scope of the present invention. For example, to the above-described embodiments, a person skilled in the art may appropriately add, delete, or modify components, or add, omit, or change conditions of steps, and these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention. [Industrial Applicability]

[0060] The present invention can be used in display devices and electronic devices incorporating display devices. [Explanation of symbols]

[0061] 5 Control circuit 6 Drive circuit 10 Substrate 10b,10f side 11, 12, 13, 14 Inorganic insulating layer 14H,15H opening 15 Organic insulating layer 20 LED elements (light-emitting elements, electronic components) 20EA anode electrode 20EK cathode electrode 30A, 30B, 30C, 30D, 30E, 30F Conductor layers 30Bt1,30Bt2 side 31,32,34,VL,VSL wiring 33 Bump electrode 33A, 33B Conductor part 41 Insulating layer 50 Semiconductor layer DA display area DSP1,DSP2 Display device ED drain electrode EG gate electrode ES source electrode GL scanning signal line Gs control signal LXP Wire crossing PFA surrounding area PIX, PIX1, PIX2 pixels PVS reference potential (fixed potential) R1,R2,R3 area SUB1, SUB2 substrate structure SW Switching element Vsg video signal

Claims

1. a first substrate made of glass or resin; a first wiring formed on the first substrate; a first insulating layer made of an inorganic material and covering the first wiring; a bump electrode connected to the first wiring at a position overlapping a first opening formed in the first insulating layer and protruding from the first insulating layer; and The first wiring is a first conductor layer formed on the first substrate and made of titanium or a titanium alloy; a second conductor layer made of aluminum or an aluminum alloy and laminated on the first conductor layer; It is a laminated film of The bump electrode is a first conductor portion made of copper or a copper alloy and joined to the first wiring; a second conductor portion formed on the first conductor portion and made of solder containing tin; 2. An electronic device comprising:

2. In claim 1, An electronic device, wherein a third conductor layer containing zinc is further formed on a portion of the first wiring that overlaps with the first opening, and is stacked on the second conductor layer.

3. In claim 1 or 2, an area in which a portion of the first conductor portion of the bump electrode is embedded between the first insulating layer and the second conductor layer of the first wiring, around the first opening;

4. In claim 1, an electronic device, wherein the surface roughness of the bonding interface between the second conductor layer of the first wiring and the first conductor portion of the bump electrode is greater than the surface roughness of the portion covered with the first insulating layer.

5. In claim 1, In a plan view, the bump electrode has a circular planar shape.

6. In claim 1, a second wiring formed on the first substrate; a second insulating layer made of an organic material and covering the second wiring; and The electronic device, wherein the first wiring is formed on the second insulating layer and is connected to the second wiring at a second opening formed in the second insulating layer.

7. In claim 6, The second wiring is a fourth conductor layer made of titanium or a titanium alloy; a fifth conductor layer made of aluminum or an aluminum alloy and laminated on the fourth conductor layer; a sixth conductor layer made of titanium or a titanium alloy and laminated on the fifth conductor layer; It is a laminated film of the sixth conductor layer of the second wiring and the first conductor layer of the first wiring are joined in the second opening.

8. (a) preparing a substrate structure including a first substrate made of glass or resin, a first wiring formed on the first substrate, and an inorganic insulating layer made of an inorganic material, the first insulating layer covering the first wiring; (b) removing an aluminum oxide film formed on the exposed surface of the first wiring at a position overlapping with a first opening formed in the first insulating layer; (c) after the step (b), forming a bump electrode connected to the first wiring at a position overlapping the first opening and protruding from the first insulating layer; Including, The first wiring is a first conductor layer formed on the first substrate and made of titanium or a titanium alloy; a second conductor layer made of aluminum or an aluminum alloy and laminated on the first conductor layer; It is a laminated film of The step (c) (c1) selectively depositing a first conductor portion made of copper or a copper alloy at a position overlapping the first opening and around the first opening by electroplating while energizing the first wiring; (c2) after the step (c1), selectively depositing a second conductor made of solder containing tin on the first conductor while the first wiring is energized; A method for manufacturing an electronic device, comprising:

9. In claim 8, The method for manufacturing an electronic device, wherein the step (b) includes a step of replacing the aluminum oxide film with a zincate film.

10. In claim 8, The method for manufacturing an electronic device, wherein the step (b) includes a step of removing the aluminum oxide film by bringing the aluminum oxide film into contact with an etching agent.

11. In claim 10, a space being present around the first opening between the first insulating layer and the second conductor layer of the first wiring after the step (b).

12. In claim 10, a surface roughness of the bonding interface between the second conductor layer of the first wiring and the first conductor portion of the bump electrode after the step (b) is greater than a surface roughness of the portion covered with the first insulating layer.

13. In claim 8, The substrate structure prepared in the step (a) includes a second wiring formed on the first substrate; a second insulating layer made of an organic material and covering the second wiring; and The method for manufacturing an electronic device, wherein the first wiring is formed on the second insulating layer and is connected to the second wiring in a second opening formed in the second insulating layer.

14. In claim 13, The second wiring is a fourth conductor layer made of titanium or a titanium alloy; a fifth conductor layer made of aluminum or an aluminum alloy and laminated on the fourth conductor layer; a sixth conductor layer made of titanium or a titanium alloy and laminated on the fifth conductor layer; It is a laminated film of The sixth conductor layer of the second wiring and the first conductor layer of the first wiring are joined in the second opening.

15. In claim 8, (d) after the step (c), a step of electrically connecting the bump electrodes and an electronic component; The method for manufacturing an electronic device further comprises:

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