Semiconductor Devices

Abstract

To provide a semiconductor device capable of reducing inductance.SOLUTION: A semiconductor device 1 includes: a first semiconductor element 10 which has two faces facing away from each other and in which a first electrode 11 is provided on one face and a second electrode 12 is provided on the other face; a second semiconductor element 20 in which a third electrode 21 is provided on one face and a fourth electrode 22 is provided on the other face; an insulating base material 41 to which each semiconductor element is bonded; first wiring 63 which penetrates through the insulating base material and which is electrically connected to the first electrode and laminated on the insulating base material; second wiring 64 which penetrates through the insulating base material and which is electrically connected to the third electrode and laminated on the insulating base material; a first wiring member 110 which is provided in the first semiconductor element and electrically connected to the second electrode; and a second wiring member 120 which is provided in the insulating base material and electrically connected to the second wiring. The insulating base material is folded and the second wiring member is bonded to the first wiring, and the first wiring member and the second wiring member have currents flowing therethrough in opposite directions from one another.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Conventionally, a semiconductor device has been known in which a semiconductor element is attached to a resin film such as polyimide via an adhesive layer, and a wiring layer is formed on the surface of the resin film opposite to the adhesive layer (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-046523 Summary of the Invention [Problem to be solved by the invention]

[0004] Further reduction in inductance is desired for high-speed switching operations and the like.

[0005] An object of the present disclosure is to provide a semiconductor device capable of reducing inductance. [Means for solving the problem]

[0006] According to one embodiment of the present disclosure, there is provided a semiconductor device comprising: a first semiconductor element having a first surface and a second surface opposite to the first surface, the first electrode being provided on the first surface and the second electrode being provided on the second surface; a second semiconductor element having a third surface and a fourth surface opposite to the third surface, the third electrode being provided on the third surface and the fourth electrode being provided on the fourth surface; an insulating substrate having a fifth surface to which the first semiconductor element and the second semiconductor element are bonded and a sixth surface opposite to the fifth surface; a first wiring penetrating the insulating substrate and electrically connected to the first electrode and laminated on the sixth surface of the insulating substrate; A semiconductor device is provided, which includes: a second wiring electrically connected to the third electrode and laminated on the sixth surface of the insulating base; a first wiring member provided on the second surface side of the first semiconductor element and electrically connected to the second electrode; a second wiring member having a seventh surface and an eighth surface opposite to the seventh surface, the seventh surface being provided on the sixth surface side of the insulating base and electrically connected to the second wiring; the insulating base is bent with the sixth surface facing inward, and the eighth surface of the second wiring member is joined to the first wiring; and currents flowing in opposite directions between the first wiring member and the second wiring member. [Effects of the Invention]

[0007] According to the present disclosure, inductance can be reduced. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. [Figure 2] 1 is a circuit diagram illustrating a semiconductor device according to a first embodiment. [Figure 3] 1A to 1C are cross-sectional views (part 1) illustrating a method for manufacturing a semiconductor device according to a first embodiment. [Figure 4] 5A and 5B are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 5A to 5C are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6]4A and 4B are cross-sectional views (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 9] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to a third embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that in this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description. In this disclosure, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction will be referred to as the XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction will be referred to as the YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction will be referred to as the ZX plane. For convenience, the Z1-Z2 direction will be defined as the up-down direction, with the Z1 side referred to as the upper side and the Z2 side referred to as the lower side. A planar view refers to viewing an object from the Z1 side, and a planar shape refers to the shape of an object viewed from the Z1 side. However, the semiconductor device can be used upside down or positioned at any angle.

[0010] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a semiconductor device.

[0011] [Configuration of semiconductor device] First, a description will be given of the cross-sectional configuration of the semiconductor device according to the first embodiment. Fig. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0012] As shown in FIG. 1 , the semiconductor device 1 according to the first embodiment includes a semiconductor element 10, a semiconductor element 20, a conductive member 30, and a flexible wiring substrate 40. The semiconductor elements 10 and 20 may be, for example, devices using silicon (Si) or silicon carbide (SiC). The semiconductor elements 10 and 20 may also be, for example, devices using gallium nitride (GaN) or gallium arsenide (GaAs). For example, the semiconductor elements 10 and 20 may be active semiconductor elements (e.g., silicon chips such as CPUs), insulated gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), diodes, etc. The semiconductor elements 10 and 20 according to the present embodiment are semiconductor elements having electrodes on their front and back surfaces. The planar shapes of the semiconductor elements 10 and 20 may be any shape and size. The planar shapes of the semiconductor elements 10 and 20 are, for example, rectangular. The thickness of the semiconductor elements 10 and 20 can be, for example, about 50 μm to 500 μm.

[0013] The semiconductor element 10 has one surface 10A and another surface 10B opposite to the one surface 10A. The semiconductor element 10 also has a main body 15, an electrode 11, an electrode 12, and an electrode 13. The electrodes 11 and 13 are provided on the one surface 10A, and the electrode 12 is provided on the other surface 10B. For example, the electrodes 11, 12, and 13 can be a source electrode, a drain electrode, and a gate electrode, respectively.

[0014] The semiconductor element 20 has one surface 20A and another surface 20B opposite to the one surface 20A. The semiconductor element 20 also has a main body 25, an electrode 21, an electrode 22, and an electrode 23. The electrodes 21 and 23 are provided on the one surface 20A, and the electrode 22 is provided on the other surface 20B. For example, the electrodes 21, 22, and 23 can be a source electrode, a drain electrode, and a gate electrode, respectively.

[0015] Materials for electrodes 11, 12, 13, 21, 22, and 23 (hereinafter, these may be collectively referred to as "electrodes") include, for example, metals such as aluminum (Al) and copper (Cu), or alloys containing at least one metal selected from these metals. If necessary, a surface treatment layer may be formed on the surface of the electrode. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer formed by laminating a Ni layer and an Au layer in this order), and a Ni layer / palladium (Pd) layer / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and an Au layer in this order). The Au layer, Ni layer, and Pd layer may be, for example, a metal layer formed by electroless plating (electroless plated metal layer). The Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or an Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy.

[0016] The conductive member 30 is a metal plate such as a Cu plate. The planar shape of the conductive member 30 can be any shape and any size. The planar shape of the conductive member 30 is, for example, rectangular. The thickness of the conductive member 30 is approximately the same as the thickness of the semiconductor elements 10 and 20, and can be, for example, about 50 μm to 500 μm.

[0017] The flexible wiring substrate 40 has an insulating base material 41, an insulating adhesive layer 42, and a wiring layer 45. The insulating base material 41 has one surface 41A and another surface 41B opposite to the one surface 41A. The adhesive layer 42 is provided on the one surface 41A, and the wiring layer 45 is provided on the other surface 41B. The adhesive layer 42 may be provided over the entire one surface 41A. The wiring layer 45 is laminated on the other surface 41B. The wiring layer 45 has a seed layer 43 and a metal layer 44.

[0018] The insulating substrate 41 may be, for example, a resin film. The resin film may be made of an insulating resin such as a polyimide resin, a polyethylene resin, or an epoxy resin. The insulating substrate 41 may be, for example, flexible. Here, flexibility refers to the ability to bend or flex. The insulating substrate 41 may have any shape and any size in plan view. The insulating substrate 41 may have, for example, a rectangular shape in plan view. The insulating substrate 41 may have a thickness of, for example, about 50 μm to 100 μm.

[0019] The semiconductor element 10, the semiconductor element 20, and the conductive member 30 are adhered to one surface 41A of the insulating base material 41 by an adhesive layer 42. One surface 10A of the semiconductor element 10 and one surface 20A of the semiconductor element 20 face one surface 41A of the insulating base material 41. The insulating base material 41 and the adhesive layer 42 are formed with a through-hole 51 exposing the electrode 11, a through-hole 52 exposing the electrode 21, a through-hole 53 exposing the conductive member 30, a through-hole 54 exposing the electrode 13, and a through-hole 55 exposing the electrode 23.

[0020] For example, an epoxy-based, polyimide-based, or silicone-based adhesive can be used as the material of the adhesive layer 42. The thickness of the adhesive layer 42 can be, for example, about 20 μm to 40 μm.

[0021] A plurality of pairs of electrodes 11 and through-holes 51 may be provided, and a plurality of pairs of electrodes 21 and through-holes 52 may be provided.

[0022] The wiring layer 45 has a wiring 61 connected to the electrode 11 through a through hole 51, a wiring 62 connected to the electrode 21 through a through hole 52, a wiring 63 connected to the electrode 13 through a through hole 54, and a wiring 64 connected to the electrode 23 through a through hole 55. The wiring 61 is also connected to the conductive member 30 through a through hole 53.

[0023] The wiring 61 includes a via wiring filled in the through hole 51, a via wiring filled in the through hole 53, and a wiring pattern formed on the other surface 41B of the insulating substrate 41. The wiring 62 includes a via wiring filled in the through hole 52 and a wiring pattern formed on the other surface 41B of the insulating substrate 41. The wiring 63 includes a via wiring filled in the through hole 54 and a wiring pattern formed on the other surface 41B of the insulating substrate 41. The wiring 64 includes a via wiring filled in the through hole 55 and a wiring pattern formed on the other surface 41B of the insulating substrate 41.

[0024] The seed layer 43 covers the other surface 41B of the insulating base material 41 and the inner surfaces of the through holes 51 to 55. The seed layer 43 is formed so as to continuously cover the other surface 41B of the insulating base material 41, the inner surfaces of the through holes 51 to 55, and the surfaces of the electrodes exposed at the bottoms of the through holes 51 to 55. A metal film (sputtered film) formed by a sputtering method can be used as the seed layer 43. For example, the seed layer 43 formed by a sputtering method can be a two-layer metal film in which a Ti layer made of titanium (Ti) and a Cu layer made of copper (Cu) are sequentially stacked on the other surface 41B of the insulating base material 41 and the inner surfaces of the through holes 51 to 55. In this case, the thickness of the Ti layer can be, for example, approximately 10 nm to 300 nm, and the thickness of the Cu layer can be, for example, approximately 100 nm to 1000 nm. The Ti layer functions as an adhesion layer that improves adhesion between the insulating base material 41, the electrodes, etc., and the seed layer 43. The Ti layer also functions as a metal barrier layer that suppresses copper from diffusing from the Cu layer etc. into the insulating base material 41 etc. As the material of the metal film that functions as such an adhesion layer and metal barrier layer, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), chromium (Cr), etc. can be used in addition to Ti.

[0025] For example, copper or a copper alloy can be used as the material of the metal layer 44. For example, the metal layer 44 can be a metal layer formed by electrolytic plating (electrolytic plated metal layer).

[0026] The flexible wiring board 40 is bent with the other surface 41B facing inward and the one surface 41A facing outward. Specifically, the flexible wiring board 40 is bent so that the through holes 52, 53, and 55 are located above (on the Z1 side of) the through holes 51 and 54. Therefore, the wires 62 and 64 of the wiring layer 45 are located above (on the Z1 side of) the wire 63, and the wire 61 is bent midway. Furthermore, the semiconductor element 10 and the semiconductor element 20 overlap in the Z1-Z2 direction. The semiconductor element 20 is located above (on the Z1 side of) the semiconductor element 10, and one surface 10A of the semiconductor element 10 and one surface 20A of the semiconductor element 20 face each other. The flexible wiring board 40 has a bent portion due to being bent.

[0027] For example, when the flexible wiring board 40 is bent, the electrode 11 and the through hole 51 are on the X1 side of the electrode 13 and the through hole 54, and the electrode 21 and the through hole 52 are on the X2 side of the electrode 23 and the through hole 55. Furthermore, the conductive member 30 and the through hole 53 are on the X1 side of the semiconductor element 20 and the through hole 55.

[0028] The semiconductor device 1 further includes a lead terminal 110, a lead terminal 120, a lead terminal 130, and a lead terminal 140. The lead terminals 110, 120, 130, and 140 are formed of, for example, a lead frame. The lead terminals 110, 120, and 130 are examples of wiring members.

[0029] The lead terminal 110 is bonded to the electrode 12 of the semiconductor element 10 by a conductive adhesive layer 71. The lead terminal 120 is bonded to the wiring 62 of the wiring layer 45 by a conductive adhesive layer 72. The lead terminal 130 is bonded to the conductive member 30 by a conductive adhesive layer 73, and is also bonded to the electrode 22 of the semiconductor element 20 by a conductive adhesive layer 74. The lead terminal 140 is bonded to the wiring 64 of the wiring layer 45 by a conductive adhesive layer 75. The conductive adhesive layers 71 to 75 are, for example, solder layers or sintered metal layers. The conductive adhesive layers 71 to 75 may be made of a conductive paste.

[0030] The lead terminals 120 and 140 are joined to the wires 61 and 63 of the wiring layer 45 by an insulating adhesive layer 70. The insulating adhesive layer 70 can be made of, for example, an epoxy-based, polyimide-based, or silicone-based adhesive. The semiconductor elements 10 and 20 are fixed to each other via the insulating adhesive layer 70.

[0031] The lead terminals 110 and 120 extend parallel to each other toward the X2 side when viewed from the semiconductor elements 10 and 20. The distance between the lead terminals 110 and 120 is approximately the same as the sum of the thickness of the semiconductor element 10 and the thickness of the flexible wiring board 40, and is, for example, 1 mm or less. Furthermore, the lead terminal 130 extends toward the X1 side when viewed from the semiconductor elements 10 and 20.

[0032] An electrode 12 of the semiconductor element 10 is electrically connected to the lead terminal 110. An electrode 21 of the semiconductor element 20 is electrically connected to the lead terminal 120. An electrode 11 of the semiconductor element 10 and an electrode 22 of the semiconductor element 20 are electrically connected to the lead terminal 130. That is, the wiring 61 of the wiring layer 45 and the electrode 22 of the semiconductor element 20 are electrically connected via the conductive member 30 and the lead terminal 130. Furthermore, the lead terminal 140 is electrically connected to the electrode 23 of the semiconductor element 20. A lead terminal (not shown) is also connected to the wiring 63 of the wiring layer 45, and this lead terminal is electrically connected to the electrode 13 of the semiconductor element 10.

[0033] Here, a description will be given of the circuit configuration of the semiconductor device 1 according to the first embodiment. Fig. 2 is a circuit diagram showing the semiconductor device according to the first embodiment.

[0034] 2, electrode 12 of semiconductor element 10 is electrically connected to the P terminal via lead terminal 110. Electrode 21 of semiconductor element 20 is electrically connected to the N terminal via lead terminal 120. Electrode 11 of semiconductor element 10 and electrode 22 of semiconductor element 20 are electrically connected to the O terminal via lead terminal 130. The P terminal is a positive input terminal, the N terminal is a negative input terminal, and the O terminal is an output terminal. Therefore, currents flow in opposite directions through lead terminal 110 and lead terminal 120.

[0035] [Method of manufacturing a semiconductor device] Next, a method for manufacturing a semiconductor device according to the first embodiment will be described. Figures 3 to 6 are cross-sectional views showing the method for manufacturing a semiconductor device according to the first embodiment. In the following description, a so-called multi-piece manufacturing method will be described, in which the parts that will become the semiconductor device 1 are manufactured in a lump, and then separated into individual parts to manufacture a large number of semiconductor devices 1. For ease of explanation, the parts that will ultimately become the components of the semiconductor device 1 will be described using the reference numerals of the final components.

[0036] First, as shown in FIG. 3(a), a large insulating base material 41 having one surface 41A and the other surface 41B is prepared. The large insulating base material 41 has, for example, a plurality of individual regions in which semiconductor devices 1 are formed, arranged in a matrix pattern. Here, the individual regions are regions that will eventually be cut along predetermined cutting lines to form individual semiconductor devices 1. Note that the number of individual regions that the large insulating base material 41 has is not particularly limited. An insulating adhesive layer 42 that covers the entire one surface 41A of the insulating base material 41 is provided on one surface 41A.

[0037] 3(b), through holes 51 to 55 are formed in required locations of the insulating base material 41 and the adhesive layer 42, penetrating the insulating base material 41 and the adhesive layer 42 in the thickness direction. The through holes 51 to 55 can be formed by, for example, a laser processing method using a CO2 laser, a UV-YAG laser, or the like, or a punching method. For example, the through hole 51 is formed on the X1 side of the through hole 54, the through hole 53 is formed on the X1 side of the through hole 51, the through hole 55 is formed on the X1 side of the through hole 53, and the through hole 52 is formed on the X1 side of the through hole 55.

[0038] 3(c), the semiconductor element 10, the semiconductor element 20, and the conductive member 30 are bonded to the insulating base material 41 by the adhesive layer 42. At this time, one surface 10A of the semiconductor element 10 is opposed to one surface 41A of the insulating base material 41, and alignment is performed so that the electrode 11 overlaps the through hole 51 and the electrode 13 overlaps the through hole 54 in a plan view. Furthermore, one surface 20A of the semiconductor element 20 is opposed to one surface 41A of the insulating base material 41, and alignment is performed so that the electrode 21 overlaps the through hole 52 and the electrode 23 overlaps the through hole 55 in a plan view. Furthermore, alignment is performed so that one surface (the surface on the Z1 side) of the conductive member 30 overlaps the through hole 53 in a plan view.

[0039] 4(a), a wiring layer 45 including a seed layer 43 and a metal layer 44 is formed on the other surface 41B of the insulating base material 41. The wiring layer 45 can be formed by, for example, a semi-additive method.

[0040] Specifically, the seed layer 43 is formed so as to cover the entire other surface 41B of the insulating base material 41 and the entire inner surfaces of the through holes 51-55. The seed layer 43 can be formed by, for example, a sputtering method or an electroless plating method. For example, when forming the seed layer 43 by a sputtering method, first, titanium is deposited by sputtering to form a Ti layer so as to cover the other surface 41B of the insulating base material 41 and the inner surfaces of the through holes 51-55. Then, copper is deposited by sputtering on the Ti layer to form a Cu layer. This makes it possible to form the seed layer 43 with a two-layer structure (Ti layer / Cu layer). When forming the seed layer 43 by an electroless plating method, for example, the seed layer 43 made of a Cu layer (single-layer structure) can be formed by electroless copper plating.

[0041] Next, a plating resist layer (not shown) having openings formed in the portions where the wiring layer 45 is to be formed, i.e., the portions where the wirings 61 to 64 are to be formed, is formed on the seed layer 43. Subsequently, a metal layer 44 made of copper or the like is formed in the openings of the plating resist layer by electrolytic plating using the seed layer 43 as a plating power supply path. Thereafter, the plating resist layer is removed. Next, the seed layer 43 is removed by wet etching using the metal layer 44 as a mask. In this manner, the wiring layer 45 including the seed layer 43 and the metal layer 44 can be formed. The wiring layer 45 has the wirings 61 to 64. The insulating base material 41, the adhesive layer 42, and the wiring layer 45 constitute the flexible wiring substrate 40.

[0042] 4(b), after the wiring layer 45 is formed, a conductive adhesive layer 71 is provided on the other surface 10B of the semiconductor element 10, a conductive adhesive layer 73 is provided on the other surface (Z2 side surface) of the conductive member 30, and a conductive adhesive layer 74 is provided on the other surface 20B of the semiconductor element 20. In addition, a conductive adhesive layer 72 is provided on the upper surface (Z1 side surface) of the wiring 62 of the wiring layer 45, and a conductive adhesive layer 75 is provided on the upper surface (Z1 side surface) of the wiring 64. The conductive adhesive layers 71 to 75 are in an uncured state.

[0043] 5(a), the lead terminal 110 is bonded to the electrode 12 with a conductive adhesive layer 71, and the lead terminal 130 is bonded to the conductive member 30 with a conductive adhesive layer 73 and to the electrode 22 with a conductive adhesive layer 74. Furthermore, the lead terminal 120 is bonded to the wiring 62 with a conductive adhesive layer 72, and the lead terminal 140 is bonded to the wiring 64 with a conductive adhesive layer 75. During this bonding, the conductive adhesive layers 71 to 75 are cured.

[0044] Next, as shown in FIG. 5(b), the wiring 6 of the wiring layer 45 2 and 6 4 The insulating adhesive layer 70 is provided on the upper surface (surface on the Z1 side) of the wiring 6. 2 and 6 4 The insulating adhesive layer 70 is left uncured.

[0045] Next, as shown in FIG. 6(a), the flexible wiring board 40 is bent between the through holes 51 and 53 so that the other surface 41B of the insulating base material 41 faces inward and the one surface 41A faces outward.

[0046] 6(b), the insulating adhesive layer 70 is pressed and spread against the upper surfaces (surfaces on the Z1 side) of the wires 61 and 63 of the wiring layer 45. Next, the insulating adhesive layer 70 is cured, and the lead terminal 120 is fixed also to the wires 61 and 63 of the wiring layer 45.

[0047] In this way, the semiconductor device 1 according to the first embodiment can be manufactured. Note that the large insulating base material 41 can be divided, for example, after the wiring layer 45 is formed (see FIG. 4(a)) and before the conductive adhesive layers 71 to 75 are provided (see FIG. 4(b)).

[0048] In the semiconductor device 1 according to the first embodiment, a current flows from the P terminal to the N terminal. Therefore, in the lead terminal 110, a current flows from the X2 side to the X1 side, and in the lead terminal 120, a current flows from the X1 side to the X2 side. In addition, in this embodiment, the distance between the lead terminals 110 and 120 is approximately the same as the sum of the thickness of the semiconductor element 10 and the thickness of the flexible wiring substrate 40. Therefore, inductance can be significantly reduced.

[0049] Furthermore, the wiring layer 45 can be formed finely and with high precision on the other surface 41B of the insulating base material 41 by a semi-additive method. The wiring layer 45 can also be formed on the other surface 41B of the insulating base material 41 by a subtractive method. Furthermore, by adhering the semiconductor elements 10 and 20 to one surface 41A of the insulating base material 41 with the adhesive layer 42, the positions of the semiconductor elements 10 and 20 can be fixed relative to the insulating base material 41 and the wiring layer 45. Therefore, according to this embodiment, excellent positional precision and connection reliability can be obtained.

[0050] As a reference example, assume that a semiconductor device (power module) is manufactured in which a semiconductor element is fixed to a metal foil (e.g., copper foil) provided on the surface of an insulating substrate (e.g., a ceramic substrate). When manufacturing such a semiconductor device, solder reflow is performed to fix the semiconductor element, and this reflow may cause some misalignment of the semiconductor element. For this reason, a relatively large margin is required for the placement of the semiconductor element at the design stage.

[0051] On the other hand, in this embodiment, the semiconductor elements 10 and 20 are bonded to the insulating substrate 41 in which the through holes 51 to 55 are formed, and the wiring layer 45 is formed by a semi-additive method. Therefore, excellent positional accuracy and connection reliability can be obtained, and a large margin as in the reference example is not required.

[0052] (Second embodiment) Next, a second embodiment will be described below with reference to Fig. 7, which is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0053] 7, the semiconductor device 2 according to the second embodiment has a wiring board 210 instead of the lead terminal 110, a wiring board 220 instead of the lead terminals 120 and 140, and a wiring board 230 instead of the lead terminal 130. The wiring boards 210, 220, and 230 are examples of wiring members.

[0054] The wiring substrate 210 has an insulating layer 211 and a wiring layer 212. The wiring layer 212 is provided on the upper surface (surface on the Z1 side) of the insulating layer 211. The material of the insulating layer 211 may be an inorganic material, an organic material, or a composite material. The material of the wiring layer 212 is, for example, copper or a copper alloy. The wiring layer 212 is bonded to the electrode 12 of the semiconductor element 10 by a conductive adhesive layer 71.

[0055] The wiring substrate 220 has an insulating layer 221, a wiring layer 222, and a wiring layer 223. The wiring layers 222 and 223 are provided on the upper surface (the surface on the Z1 side) of the insulating layer 221. The material of the insulating layer 221 may be an inorganic material, an organic material, or a composite material. The material of the wiring layers 222 and 223 is, for example, copper or a copper alloy. The wiring layer 222 is bonded to the wiring 62 of the wiring layer 45 by a conductive adhesive layer 72, and the wiring layer 223 is bonded to the wiring 64 of the wiring layer 45 by a conductive adhesive layer 75. The insulating layer 221 is also bonded to the wiring 61 and 63 of the wiring layer 45 by an insulating adhesive layer 70.

[0056] The wiring substrate 230 has an insulating layer 231 and a wiring layer 232. The wiring layer 232 is provided on the Z2-side surface of the insulating layer 231. The material of the insulating layer 231 may be an inorganic material, an organic material, or a composite material. The material of the wiring layer 232 is, for example, copper or a copper alloy. The wiring layer 232 is bonded to the conductive member 30 by a conductive adhesive layer 73, and is also bonded to the electrode 22 of the semiconductor element 20 by a conductive adhesive layer 74.

[0057] The wiring board 210 includes a wiring layer (for example, wiring layer 212) extending on the X2 side as viewed from the semiconductor elements 10 and 20, and the wiring board 220 includes a wiring layer (for example, wiring layer 222) extending on the X2 side as viewed from the semiconductor elements 10 and 20. Furthermore, the wiring board 230 includes a wiring layer (for example, wiring layer 232) extending on the X1 side as viewed from the semiconductor elements 10 and 20.

[0058] The other configurations are the same as those in the first embodiment.

[0059] When manufacturing the semiconductor device 2 according to the second embodiment, the wiring substrates 210, 220, and 230 are prepared in advance. Then, the wiring substrate 210 is bonded to the semiconductor element 10 instead of the lead terminals 110, the wiring substrate 220 is bonded to the wiring layer 45 instead of the lead terminals 120 and 140, and the wiring substrate 230 is bonded to the semiconductor element 20 and the conductive member 30 instead of the lead terminal 130. In this manner, the semiconductor device 2 can be manufactured.

[0060] In the semiconductor device 2 according to the second embodiment, a current also flows from the P terminal to the N terminal. Therefore, in the wiring board 210, a current flows from the X2 side to the X1 side, and in the wiring board 220, a current flows from the X1 side to the X2 side. Furthermore, in this embodiment, the distance between the wiring boards 210 and 220 is approximately the same as the sum of the thickness of the semiconductor element 10 and the thickness of the flexible wiring board 40. Therefore, similar to the first embodiment, the inductance can be significantly reduced.

[0061] As in the first embodiment, the semiconductor elements 10 and 20 are bonded to the insulating substrate 41 having the through holes 51 to 55 formed therein, and the wiring layer 45 is formed by a semi-additive method, thereby achieving excellent positional accuracy and connection reliability.

[0062] (Third embodiment) Next, a third embodiment will be described.

[0063] [Configuration of semiconductor device] First, a description will be given of the cross-sectional configuration of the semiconductor device according to the third embodiment. Fig. 8 is a cross-sectional view showing the semiconductor device according to the third embodiment.

[0064] 8, the semiconductor device 3 according to the third embodiment has an adhesive layer 342 instead of the adhesive layer 42. Like the adhesive layer 42, the adhesive layer 342 is provided on one surface 41A of the insulating base material 41. The material and thickness of the adhesive layer 342 are the same as those of the adhesive layer 42.

[0065] The adhesive layer 342 has an adhesive portion 342A that adheres the semiconductor element 10 to the one surface 41A, and an adhesive portion 342B that adheres the semiconductor element 20 to the one surface 41A. Between the adhesive portion 342A and the adhesive portion 342B, the one surface 41A of the folded portion of the insulating base material 41 is exposed from the adhesive layer 342.

[0066] The other configurations are the same as those in the first embodiment.

[0067] [Method of manufacturing a semiconductor device] Next, a method for manufacturing a semiconductor device according to a third embodiment will be described. Fig. 9 is a cross-sectional view showing the method for manufacturing a semiconductor device according to the third embodiment. In the following description, a so-called multi-piece manufacturing method will be described, in which the parts that will become the semiconductor device 3 are manufactured in a lump, and then separated into individual parts to manufacture a large number of semiconductor devices 3. For ease of explanation, the parts that will ultimately become the components of the semiconductor device 3 will be described using the reference numerals of the final components.

[0068] 9(a), a large insulating base material 41 having one surface 41A and the other surface 41B is prepared, as in the first embodiment. However, instead of the adhesive layer 42, an insulating adhesive layer 342 having adhesive portions 342A and 342B and having an opening 342X formed between the adhesive portions 342A and 342B is provided on the one surface 41A of the insulating base material 41. The opening 342X can be formed, for example, by punching the adhesive layer.

[0069] Next, as shown in FIG. 9(b), through-holes 51 to 55 are formed at required locations of the insulating base material 41 and the adhesive layer 342, penetrating the insulating base material 41 and the adhesive layer 342 in the thickness direction.

[0070] 9(c), the semiconductor element 10, the semiconductor element 20, and the conductive member 30 are adhered to the insulating base material 41 by an adhesive layer 342. At this time, the semiconductor element 10 is adhered to the insulating base material 41 by an adhesive portion 342A, and the semiconductor element 20 and the conductive member 30 are adhered to the insulating base material 41 by an adhesive portion 342B. Furthermore, alignment is performed in the same manner as in the first embodiment.

[0071] Thereafter, similarly to the first embodiment, the processes subsequent to the formation of the wiring layer 45 including the seed layer 43 and the metal layer 44 are carried out. In this manner, the semiconductor device 3 according to the third embodiment can be manufactured.

[0072] The third embodiment can also achieve the same effects as the first embodiment. Furthermore, one surface 41A of the folded portion of the insulating substrate 41 is exposed from the adhesive layer 342 between the adhesive portions 342A and 342B. Therefore, the adhesive layer 342 does not include the folded portion associated with the folding of the insulating substrate 41, or if it does, the folded portion is narrower than in the first embodiment. In the first embodiment, depending on the material of the adhesive layer 42, the toughness of the adhesive layer 42 after curing may be low, and the adhesive layer 42 may crack when bent. If the adhesive layer 42 cracks, the adhesive layer 42 may peel off from the insulating substrate 41, or the semiconductor element 10, the semiconductor element 20, or the conductive member 30 may peel off from the insulating substrate 41. In contrast, in the third embodiment, the adhesive layer 342 is hardly bent, so even if the toughness of the adhesive layer 342 after curing is low, the adhesive layer 342 is less likely to crack.

[0073] (Fourth embodiment) Next, a fourth embodiment will be described with reference to Fig. 10, which is a cross-sectional view showing a semiconductor device according to the fourth embodiment.

[0074] As shown in FIG. 10, the semiconductor device 4 of the fourth embodiment, like the second embodiment, has a wiring board 210 instead of the lead terminal 110, a wiring board 220 instead of the lead terminals 120 and 140, and a wiring board 230 instead of the lead terminal 130.

[0075] The other configurations are the same as those of the third embodiment.

[0076] According to the fourth embodiment, it is possible to obtain the same effects as those of the second and third embodiments.

[0077] The structure of the wiring board is not limited to the above, and a ceramic substrate or a build-up substrate may be used, and is not limited to a single-layer structure. For example, it may be embodied as a laminated structure in which one or more wiring layers and multiple insulating layers are laminated. The wiring layers may be provided on both the front and back surfaces.

[0078] Furthermore, a semiconductor device may be configured by combining the lead terminals 110, 120, and 130 with the wiring substrates 210, 220, and 230. For example, the lead terminal 120 in FIG.

[0079] The above describes in detail preferred embodiments, but the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0080] 1, 2, 3, 4 Semiconductor device 10, 20 Semiconductor elements 10A, 10B, 20A, 20B side 11, 21 electrode 12, 22 electrodes 13, 23 electrode 30 Conductive material 40 Flexible wiring board 41 Insulating substrate 42, 342 Adhesive layer 45 Wiring layer 51, 52, 53, 54, 55 Through holes 61, 62, 63, 64 Wiring 70 Insulating adhesive layer 71, 72, 73, 74, 75 Conductive adhesive layer 110, 120, 130, 140 lead terminal 210, 220, 230 Wiring board 211, 221, 231 Insulating layer 212, 222, 223, 232 wiring layer 342A, 342B: Adhesive part

Claims

1. a first semiconductor element having a first surface and a second surface opposite to the first surface, a first electrode provided on the first surface, and a second electrode provided on the second surface; a second semiconductor element having a third surface and a fourth surface opposite to the third surface, a third electrode provided on the third surface, and a fourth electrode provided on the fourth surface; an insulating substrate having a fifth surface to which the first semiconductor element and the second semiconductor element are bonded and a sixth surface opposite to the fifth surface; a first wiring that penetrates the insulating base material, is electrically connected to the first electrode, and is laminated on the sixth surface of the insulating base material; a second wiring that penetrates the insulating base material, is electrically connected to the third electrode, and is laminated on the sixth surface of the insulating base material; a first wiring member provided on the second surface side of the first semiconductor element and electrically connected to the second electrode; a second wiring member having a seventh surface and an eighth surface opposite to the seventh surface, the seventh surface being provided on the sixth surface side of the insulating base material and electrically connected to the second wiring; and the insulating base material is bent with the sixth surface facing inward, and the eighth surface of the second wiring member is joined to the first wiring; A semiconductor device in which currents flow in opposite directions through the first wiring member and the second wiring member.

2. The semiconductor device according to claim 1 , wherein the insulating substrate is flexible.

3. a first conductive adhesive layer that bonds the first wiring member and the second electrode to each other; a second conductive adhesive layer that bonds the second wiring member and the second wiring to each other; 3. The semiconductor device according to claim 1, further comprising:

4. 3. The semiconductor device according to claim 1, further comprising a first insulating adhesive layer that bonds the second wiring member and the first wiring to each other.

5. the first wiring member has a first lead terminal, 3. The semiconductor device according to claim 1, wherein the second wiring member has a second lead terminal.

6. the first wiring member has a first wiring substrate, 3. The semiconductor device according to claim 1, wherein the second wiring member comprises a second wiring substrate.

7. a conductive member adhered to the fifth surface; a third wiring member provided on the fourth surface side of the second semiconductor element and electrically connected to the conductive member and the fourth electrode; and The semiconductor device according to claim 1 , wherein the first wiring penetrates the insulating base material and is electrically connected to the conductive member.

8. a third conductive adhesive layer that bonds the third wiring member and the conductive member to each other; a fourth conductive adhesive layer that bonds the third wiring member and the fourth electrode to each other; The semiconductor device according to claim 7 , comprising:

9. The semiconductor device according to claim 7 , wherein the third wiring member has a third lead terminal.

10. The semiconductor device according to claim 7 , wherein the third wiring member includes a third wiring substrate.

11. the first semiconductor element has a fifth electrode provided on the first surface, the second semiconductor element has a sixth electrode provided on the third surface, a third wiring that penetrates the insulating base material, is electrically connected to the fifth electrode, and is laminated on the sixth surface of the insulating base material; a fourth wiring that penetrates the insulating base material, is electrically connected to the sixth electrode, and is laminated on the sixth surface of the insulating base material; 3. The semiconductor device according to claim 1, further comprising:

12. The semiconductor device according to claim 1 , further comprising a second insulating adhesive layer provided on the fifth surface of the insulating base material.

13. The second insulating adhesive layer is a first adhesive portion that adheres the first semiconductor element to the fifth surface; a second adhesive portion that adheres the second semiconductor element to the fifth surface; and The semiconductor device according to claim 12 , wherein the fifth surface of the folded portion of the insulating base material is exposed from the second insulating adhesive layer between the first adhesive portion and the second adhesive portion.

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