Semiconductor Devices

Abstract

A semiconductor device having a seal ring that can suppress damage due to charge buildup during manufacturing and ensure moisture resistance is realized. [Solution] The semiconductor device includes a semiconductor substrate, an interlayer insulating film and an element region provided thereon, and first and second seal rings surrounding the element region. The first and second seal rings are made of stacked conductive films including at least one line-shaped wiring layer and at least one line-shaped via layer, and are insulated from each other or electrically connected only at the uppermost layer of the conductive layers. The first seal ring is electrically insulated from the semiconductor substrate. The second seal ring is electrically connected to the semiconductor substrate.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] In semiconductor devices, a structure in which an annular seal ring structure is formed around the logic and analog sections to ensure reliability, including moisture resistance, is known. In particular, for semiconductor devices whose wiring structure includes a low-dielectric-constant insulating film, such as a low-k film, it is important to form a stable seal ring structure to ensure moisture resistance within the device. Furthermore, seal ring structures are sometimes provided to channel charge buildup within the device to the substrate during the semiconductor device manufacturing process.

[0003] The seal ring structure is formed as a circular line in which, for example, metal wiring and / or metal vias are continuously formed, and is made of a material such as Cu (copper).

[0004] As a document disclosing a seal ring structure, for example, Japanese Patent Application Laid-Open No. 2006-147668 (Patent Document 1) is known. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-147668 Summary of the Invention [Problem to be solved by the invention]

[0006] When a seal ring structure is formed using Cu, the Cu is embedded in grooves or holes in an insulating layer. However, the Cu may not be embedded properly or may be removed after being embedded, resulting in an inability to form a seal ring with the required shape. As a result, discontinuities (holes, etc.) may occur in the seal ring, and moisture resistance may not be ensured.

[0007] Furthermore, if charge buildup occurs during the manufacturing process of a semiconductor device, it can cause damage to the device being manufactured.

[0008] An object of the present disclosure is to realize a semiconductor device having a seal ring structure that can suppress damage due to charge buildup during the manufacturing process and ensure moisture resistance. [Means for solving the problem]

[0009] The inventors of the present invention have newly discovered that seal rings that are structured to allow charge buildup to flow to a semiconductor substrate during the manufacturing process of a semiconductor device are prone to formation defects. On the other hand, seal rings that are structured not to allow charge buildup to flow to a semiconductor substrate are prone to damage due to charge buildup.

[0010] In the past, when multiple seal rings were provided, it was common for each seal ring to be connected to the conductor substrate in the same manner and for each seal ring to be electrically connected to each other, in order to prevent charge-up in each seal ring or to prevent problems during formation. However, the semiconductor device of the present disclosure has a configuration that includes both electrically connected seal rings and insulated seal rings, thereby ensuring moisture resistance and preventing the problem of charge-up in each seal ring.

[0011] Specifically, the semiconductor device of the present disclosure includes a semiconductor substrate, an interlayer insulating film provided on the semiconductor substrate, an element region provided on the semiconductor substrate, a first seal ring embedded in the interlayer insulating film and surrounding the element region, and a second seal ring surrounding the element region on the inside or outside of the first seal ring. The first seal ring and the second seal ring are made of stacked conductive films including at least one line-shaped wiring layer and at least one line-shaped via layer, and are insulated from each other or electrically connected only at the uppermost layer of the conductive layers. The first seal ring is electrically insulated from the semiconductor substrate. The second seal ring is electrically connected to the semiconductor substrate. [Effects of the Invention]

[0012] According to the semiconductor device of the present disclosure, by providing a first seal ring electrically connected to a semiconductor substrate and a second seal ring electrically insulated from the semiconductor substrate, it is possible to realize a seal ring structure that allows charge buildup during the manufacturing process to flow to the semiconductor substrate while also ensuring moisture resistance. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a cross-sectional view showing the seal ring region of the semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a plan view showing a seal ring region of the semiconductor device of FIG. [Figure 3] FIG. 3 is a plan view showing a seal ring region and an element region of the semiconductor device of FIG. [Figure 4] FIG. 4 is a diagram showing a top view taken along line IV-IV in FIG. [Figure 5] FIG. 5 is a cross-sectional view showing a semiconductor device according to Modification 1 of the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view showing a semiconductor device according to Modification 2 of the first embodiment. [Figure 7]FIG. 7 is a cross-sectional view showing a semiconductor device according to Modification 3 of the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view showing a semiconductor device according to the fourth modification of the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a semiconductor device according to a first modification of the second embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing a semiconductor device according to Modification 2 of the second embodiment. [Figure 12] FIG. 12 is a cross-sectional view showing a semiconductor device according to Modification 3 of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments will be described with reference to the accompanying drawings. The following description is merely an example and is not intended to be limiting. Furthermore, modifications can be made as appropriate within the scope of the present invention.

[0015] (First embodiment) 1 to 4 are diagrams illustrating a semiconductor device 100 according to this embodiment. The semiconductor device 100 includes seal rings 110, and FIG. 1 illustrates a cross section of a seal ring region 101 including four seal rings 110. FIG. 2 is a plan view, schematically illustrating that an element region 103 is surrounded by the seal ring region 101 including the four seal rings 110. A scribe region 102 is located outside the seal ring region 101. FIG. 3 illustrates a cross section of each of the seal ring region 101 and the element region 103. In the seal ring region 101, a seal ring 110 is formed by stacked conductive films 121. In the element region 103, multilayer wiring is formed by the stacked conductive films 121, and elements such as transistors including gate electrodes 23 are also formed. FIG. 4 is a plan view illustrating the arrangement of the first contact 5, second contact 6, active layer 3, STI 4, etc. in the seal ring region 101; details will be described later.

[0016] The semiconductor device 100 shown in FIG. 1 has an SOI (Silicon On Insulator) structure. A first insulating layer 2A is provided on a semiconductor substrate 1. The first insulating layer 2A is a buried insulating film, also called a BOX (Buried Oxide). An active layer 3 is formed on the first insulating layer 2A. A second insulating layer 4 is provided to separate the active layer 3. The second insulating layer 4 may have an STI (Shallow Trench Isolation) structure.

[0017] An interlayer insulating film 20 is formed above the semiconductor substrate 1, the first insulating layer 2A, and the active layer 3 (hereinafter referred to as a substrate layer 22). The interlayer insulating film 20 includes a plurality of stacked layers, but the detailed configuration is omitted for clarity of the drawing.

[0018] The seal ring 110 is made of a laminated conductive film 121 and is embedded in the interlayer insulating film 20. In this embodiment, the conductive film 121 is configured by laminating a wiring layer M1, a via layer V1, a wiring layer M2, a via layer V2, and a wiring layer M3 in this order from the bottom. The wiring layers M1, M2, and M3 and the via layers V1 and V2 are all configured in a line shape extending with a predetermined width, and surround the element region 103 without any gaps.

[0019] In the element region 103, metal wiring made up of multiple layers is formed by the conductive film 121. Via layers V1 and V2 in the metal wiring mainly serve as plugs that connect upper and lower wiring layers together at predetermined locations.

[0020] These wiring systems are called fine wiring. For the purpose of high-speed operation of semiconductor devices, a low-dielectric-constant insulating film called a low-k film is used as the interlayer insulating film 20 around the wiring. The use of a low-k film has the advantage of reducing the electrical capacitance between wiring. On the other hand, low-k films tend to have low moisture resistance. In other words, if moisture penetrates into the element region 103, it can cause problems such as short circuits between wiring. To address this issue, a seal ring 110 is provided to surround the element region 103, preventing moisture from penetrating into the element region 103.

[0021] The laminated conductive films 121 that constitute the seal ring 110 (and the metal wiring of the element region 103) are formed sequentially, for example, by filling grooves or holes provided in each layer of the interlayer insulating film 20 consisting of multiple layers with a conductive material such as Cu.

[0022] However, there are cases where the filling of such materials is not performed properly or is lost after filling. If a portion (void) where Cu is not filled in the seal ring 110 occurs in this way, moisture may enter the element region 103 through that portion. In this case, the effectiveness of the seal ring 110 is not achieved.

[0023] Such voids are more likely to occur as the dimensions of the metal wiring and seal ring 110 become smaller due to device miniaturization, etc., and are particularly problematic in fine wiring. Furthermore, the via layers V1 and V2 constituting the seal ring 110 have a linear shape (line via). In this case, due to factors such as differences in dry etching rate with the via as a plug, a Cu-containing polymer that is difficult to remove is likely to be formed at the bottom of the line via. As a result, Cu may not be properly embedded, which may cause voids. Furthermore, voids are more likely to occur when the seal ring is electrically connected to a semiconductor substrate. These facts were newly discovered by the present inventors.

[0024] Furthermore, during the manufacturing process of a semiconductor device, charge accumulation (charge-up) may occur in the conductive film 121, etc. during manufacturing. The accumulated charge may cause arcing (abnormal discharge) and melt metal parts, thereby damaging the semiconductor device during manufacturing. Therefore, it is desirable to release the charge.

[0025] In contrast to the above, of the multiple (four in this example) seal rings 110 included in the semiconductor device 100, the first seal ring 110a is electrically connected to the active layer 3 via a first contact 5. The second seal ring 110b is electrically connected to the semiconductor substrate 1 via a second contact 6 that penetrates the first insulating layer 2A and the second insulating layer 4.

[0026] Fig. 4 shows a top view taken along line IV-IV in Fig. 1. However, assuming that the interlayer insulating film 20 is transparent, the figure shows cross sections of the first contact 5 and second contact 6, as well as the arrangement of the active layer 3 and second insulating layer 4 below each of them.

[0027] As described above, voids are likely to occur in the conductive film 121 when a current flows through the semiconductor device 100. In contrast, the first seal ring 110a is electrically connected to the active layer 3 and is not electrically connected to the semiconductor device 100, and therefore voids are less likely to occur. Therefore, by providing the first seal ring 110a, the occurrence of voids is suppressed, and the intrusion of moisture into the element region 103 can be more reliably suppressed.

[0028] On the other hand, by providing the second seal ring 110b electrically connected to the semiconductor substrate 1, it is possible to flow charges to the semiconductor substrate 1. As a result, charge-up in the second seal ring 110b electrically connected to the semiconductor substrate 1 is substantially prevented, and charge-up is also reduced in the first seal ring 110a insulated from the semiconductor substrate 1. This is because the second seal ring 110b functions as a path for dissipating current, thereby reducing charges that may build up in various locations, and as a result, the charge that builds up in the first seal ring 110a is also reduced.

[0029] Conventionally, when the purpose is to suppress charge-up, all seal rings are electrically connected to the semiconductor substrate 1. However, as a countermeasure against charge-up, as described above, it is not essential that all seal rings 110 are electrically connected to the semiconductor substrate 1.

[0030] As described above, in the semiconductor device 100 of this embodiment, the occurrence of voids can be suppressed particularly in the first seal ring 110a, and charge-up can be prevented in the second seal ring 110b and reduced in the first seal ring 110a.

[0031] The other seal rings 110 in the semiconductor device 100 may have the structure of either the first seal ring 110a or the second seal ring 110b.

[0032] In addition, in the example of this embodiment, the innermost seal ring 110 (the side closest to the element region 103) is the first seal ring 110a and the adjacent seal ring 110 is the second seal ring 110b, but this may be reversed.

[0033] Furthermore, when three or more seal rings 110 are provided, it is preferable that the first seal rings 110a electrically connected to the active layer 3 and the second seal rings 110b electrically connected to the semiconductor device 100 are alternately arranged. In this way, the effect of reducing charge buildup in the second seal ring 110b via the first seal ring 110a is easily achieved.

[0034] In this embodiment, four seal rings 110 are provided, but the effect is achieved as long as there is at least one first seal ring 110a and one second seal ring 110b. A different number of second seal rings 110b than the number of first seal rings 110a may be provided. Therefore, the number of seal rings 110 may be three or more than four.

[0035] Furthermore, in the semiconductor device 100 of this embodiment, the four seal rings 110 are not electrically connected to one another. Therefore, the suppression of voids and charge-up is an independent effect of each seal ring 110.

[0036] (Modification 1 of the first embodiment) A first modification of the first embodiment will be described below. Fig. 5 shows a schematic cross section of a semiconductor device 100a of this modification.

[0037] In addition to the configuration of the semiconductor device 100 (FIG. 1) of the first embodiment, the semiconductor device 100a includes an upper interlayer insulating film 21 formed on the interlayer insulating film 20, and an upper conductive film 122 embedded in the upper interlayer insulating film 21. The upper conductive film 122 has a stacked structure including an upper via layer VF and an upper wiring layer MF, and forms a second wiring system on a wiring system (hereinafter also referred to as a first wiring system) made up of the conductive film 121.

[0038] Furthermore, the wiring layer M3, which is the uppermost layer of the conductive film 121, has a width sufficient to connect the vias V2 of the adjacent first seal ring 110a and second seal ring 110b. The upper via layer VF is wider than the via layer V1, and one upper via layer VF is formed for the wiring layer M3. The upper wiring layer MF is wider than the wiring layers M2 and M3, and is similar to the wiring layer M3. Furthermore, the upper wiring layer MF is thicker than the wiring layers M1 to M3.

[0039] While the interlayer insulating film 20 is a low-k film, the upper interlayer insulating film 21 is not a low-k film but a general interlayer insulating film. Note that a low-k film generally refers to a film made of a material with a relative dielectric constant of 3 or less, such as SiOC or SiOCH. General interlayer insulating films that are not low-k films have a relative dielectric constant of 4 or more, such as SiO2, SiN, and SiON.

[0040] The first wiring system made of the conductive film 121 has strict design rules (small design dimensions such as width and thickness), and the interlayer insulating film 20 is made of a low-k film, so voids are likely to occur. In contrast, the wiring system (hereinafter also referred to as the second wiring system) made of the upper conductive film 122, which is provided above the wiring layer M3, has looser design rules. Furthermore, because the upper conductive film 122 is not a low-k film, voids are unlikely to occur, and even if voids do occur, they are unlikely to cause problems with moisture resistance.

[0041] On the other hand, charge-up also occurs in the upper conductive film 122 during the manufacturing process of the semiconductor device 100a.

[0042] In response to this, the width of the wiring layer M3 is increased to connect the vias V2 of the adjacent first seal ring 110a and second seal ring 110b. As a result, the potentials separated for each seal ring 110 are connected in the via layer V2 and in layers further below. In this way, even if charge-up occurs in the process of forming the second wiring system, the charge can be released to the semiconductor device 100.

[0043] Voids occur during the manufacturing process of the first wiring system (conductive film 121, etc.). Therefore, even if the first seal ring 110a, in which the first contact 5 is connected to the active layer 3, is electrically connected to the semiconductor device 100 via the wiring layer M3 and the second seal ring 110b, voids do not occur in the conductive film 121 that has already been formed.

[0044] When two or more pairs of first seal rings 110a and second seal rings 110b are provided (two pairs in FIG. 5), the first seal rings 110a and second seal rings 110b are preferably arranged alternately to connect the respective potentials. However, they may also be arranged in the order of first, second, second, first.

[0045] From this viewpoint, it is preferable that the first seal ring 110a and the second seal ring 110b are electrically connected only at the uppermost layer of the conductive film 121.

[0046] In the description of this modification, for convenience, only the first wiring system (the portion consisting of the conductive film 121) is referred to as the seal ring 110 (first seal ring 110a, second seal ring 110b). However, in the seal ring region 101, the second wiring system (the portion consisting of the upper conductive film 122) also functions as a seal ring.

[0047] 5, the first seal ring 110a and the second seal ring 110b are connected by a wiring layer M3 embedded in a low-dielectric-constant interlayer insulating film 20. In contrast, the first seal ring 110a and the second seal ring 110b may not be electrically connected in the interlayer insulating film 20, but may be electrically connected by a second wiring system (including upper via layers VF and upper wiring layers MF) in the upper conductive film 122. In this case, upper via layers VF may be formed independently on the wiring layer M3, which is the top layer in FIG. 1, and the upper via layers VF may be connected to each other by a wide upper wiring layer MF.

[0048] (Modification 2 of the first embodiment) A second modification of the first embodiment will now be described. Fig. 6 shows a schematic cross section of a semiconductor device 100b of this modification.

[0049] In the semiconductor device 100a of the first modification (FIG. 5), the first contact 5 is connected to the active layer 3. In contrast, in the semiconductor device 100b of the present modification (FIG. 6), the second insulating layer 4 is formed over a wider area, and the first contact 5 is connected to the second insulating layer 4.

[0050] This configuration makes it even more difficult for charges to escape from the first seal ring 110a compared to the first modification, and makes it possible to more reliably suppress the occurrence of voids.

[0051] (Modification 3 of the first embodiment) A third modification of the first embodiment will now be described. Fig. 7 shows a schematic cross section of a semiconductor device 100c according to this modification.

[0052] The semiconductor device 100c of this modification includes, in addition to the semiconductor device 100b of modification 2 (FIG. 6), a polysilicon layer 5a provided on the second insulating layer 4. The first seal ring 110a is connected to the polysilicon layer 5a via the first contact 5.

[0053] In this modification, the first seal ring 110a is insulated from the semiconductor substrate 1 by the second insulating layer 4 and the first insulating layer 2A, so that the generation of voids is suppressed.

[0054] The polysilicon layer 5a may be formed on the active layer 3 instead of on the second insulating layer 4. That is, in the configuration of Modification 1 shown in FIG. 5, the polysilicon layer 5a may be formed on the active layer 3, and the first contact 5 may be connected to the polysilicon layer 5a.

[0055] In this case, the first seal ring 110a and the semiconductor substrate 1 are still insulated by the first insulating layer 2A, and the generation of voids is suppressed. Furthermore, if the amount of charge remaining in the polysilicon layer 5a in this modification is smaller than the amount of charge remaining in the active layer 3 in the first embodiment (FIG. 5), the effect of suppressing voids is greater than in the first embodiment. This can be achieved, for example, by making the thickness of the polysilicon layer 5a in this modification smaller than the thickness of the active layer 3 in the first embodiment.

[0056] (Fourth modification of the first embodiment) A fourth modification of the first embodiment will now be described. Fig. 8 shows a schematic cross section of a semiconductor device 100d of this modification.

[0057] The semiconductor device 100d of this modification has a configuration in which the via layer V1 and the via layer V2 in the semiconductor device 100a of the first modification (FIG. 4) are each composed of two line vias. Therefore, the via layer V1 and the via layer V2 each surround the inner region doubly.

[0058] Increasing the number of line vias in this way makes it possible to increase the volume of the metal portion of the seal ring 110. As a result, the strength can be improved. For example, it can be made less susceptible to physical damage during blade dicing and thermal damage during laser grooving. Note that the via layer V1 and the via layer V2 may be configured to have three or more line vias.

[0059] 8 is a schematic view common to the other embodiments and modifications, the line vias of the via layer V1 and the via layer V2 are shown to have a narrower width than the individual via layers V1 and V2 in FIG. 5 and the like. However, this is not limited to this. In the semiconductor device 100d of this modification, the via layers V1 and V2 may be configured to include multiple line vias having the same width as the via layers V1 and V2 in FIG. 5 and the like. In this case, the widths of the wiring layers M1 and M2 are designed to be sufficiently wide.

[0060] Even if the width of a single line via becomes narrower, the strength improves if the total volume of the metal part of multiple line vias increases. Furthermore, narrowing the width of the line via reduces the etching rate during processing, which reduces the time that Cu is exposed to etching and, as a result, has the effect of suppressing the occurrence of voids.

[0061] (Second embodiment) Next, a second embodiment of the present disclosure will be described. Fig. 9 shows a schematic cross section of a semiconductor device 100e of this embodiment.

[0062] While the first embodiment (FIG. 1) has an SOI structure, the semiconductor device 100e of this embodiment is formed using a substrate layer 22 in which a P-type well 2B is provided on a P-type semiconductor substrate 1.

[0063] The upper part of the P-type well 2B is partitioned by a second insulating layer 4, and a P-type impurity region 3A and an N-type impurity region 3B are formed by implanting P-type and N-type impurities, respectively.

[0064] The first seal ring 110a is connected to the N-type impurity region 3B via the first contact 5. The N-type impurity region 3B forms a pn junction with the P-type well 2B, so no current flows between the N-type impurity region 3B and the P-type well 2B. This insulates the first seal ring 110a from the semiconductor substrate 1. Therefore, the generation of voids in the first seal ring 110a is suppressed.

[0065] The second seal ring 110b is connected to the P-type impurity region 3A via the second contact 6. The P-type impurity region 3A is electrically connected to the P-type well 2B and the P-type semiconductor substrate 1. Therefore, the second seal ring 110b is electrically connected to the semiconductor substrate 1. Therefore, the second seal ring 110b can allow the charge buildup to flow to the semiconductor substrate 1.

[0066] As described above, in this embodiment as well, it is possible to suppress the occurrence of voids and to allow charge buildup to flow into the semiconductor substrate 1.

[0067] In this embodiment (including the following modifications), the conductivity types (P type / N type) of the respective parts can be reversed.

[0068] (Modification 1 of the second embodiment) A first modification of the second embodiment will be described below. Fig. 10 shows a schematic cross section of a semiconductor device 100f of this modification.

[0069] The semiconductor device 100f of this modification, like the first modification of the first embodiment (FIG. 5), includes an upper interlayer insulating film 21, which is a general insulating film, on an interlayer insulating film 20 made of a low-k film. A second wiring system made of an upper conductive film 122 and including a via layer VF and a wiring layer MF is formed in the upper interlayer insulating film 21. Furthermore, with respect to the first wiring system in the interlayer insulating film 20, which is a low-k film, the uppermost wiring layer M3 has a width that connects the via layers V2 in the first seal ring 110a and the second seal ring 110b that are adjacent to each other.

[0070] With this configuration, the same effects as those of the first modification of the first embodiment are realized.

[0071] (Modification 2 of the second embodiment) A second modification of the second embodiment will now be described. Fig. 11 shows a schematic cross section of a semiconductor device 100g of this modification.

[0072] In the semiconductor device 100f of the second modification (FIG. 10), the first contact 5 is connected to the P-type impurity region 3 A. In contrast, in the semiconductor device 100g of the present modification (FIG. 11), the second insulating layer 4 is formed over a wider area, and the first contact 5 is connected to the second insulating layer 4.

[0073] This configuration makes it even more difficult for charges to escape from the first seal ring 110a compared to the first modification, and makes it possible to more reliably suppress the occurrence of voids.

[0074] (Modification 3 of the second embodiment) A third modification of the second embodiment will now be described. Fig. 12 shows a schematic cross section of a semiconductor device 100h of this modification.

[0075] The semiconductor device 100h of this modification includes, in addition to the semiconductor device 100g of modification 2 (FIG. 11), a polysilicon layer 5a provided on the second insulating layer 4. The first seal ring 110a is connected to the polysilicon layer 5a via the first contact 5.

[0076] In this modification, the first seal ring 110a is insulated from the semiconductor substrate 1 by the second insulating layer 4 and the first insulating layer 2A, so that the generation of voids is suppressed.

[0077] 5, the polysilicon layer 5a may be formed on the N-type impurity region 3B instead of on the second insulating layer 4. The first contact 5 is connected to the polysilicon layer 5a.

[0078] In this configuration as well, the pn junction between the P-type well 2B and the N-type impurity region 3B insulates the first seal ring 110a from the semiconductor substrate 1. Therefore, the generation of voids in the first seal ring 110a is suppressed.

[0079] The above-described embodiments may be modified in form and detail without departing from the spirit of the claims. Furthermore, the contents of the embodiments may be combined and substituted as appropriate as long as the functions of the subject matter of the present disclosure are not impaired. [Industrial Applicability]

[0080] The present disclosure is useful as a semiconductor device having a seal ring structure that allows charge buildup during the manufacturing process to flow to a semiconductor substrate and ensures moisture resistance. [Explanation of symbols]

[0081] 1. Semiconductor substrate 2A First insulating layer 2B P-type well 3 Active layer 3A P-type impurity region 3B N-type impurity region 4 Second insulating layer 5. First Contact 5a Polysilicon layer 6 Second Contact 20 Interlayer insulating film 21 Upper interlayer insulating film 22 substrate layers 23 Gate electrode 100, 100a~100h Semiconductor equipment 101 Seal ring area 102 Scribe area 103 Element Area 110 Seal ring 110a first seal ring 110b Second seal ring 121 Conductive film 122 Upper conductive film M1~M3 wiring layers V1, V2 via layers VF Upper via layer MF upper wiring layer

Claims

1. a semiconductor substrate; an interlayer insulating film provided on the semiconductor substrate; an element region provided on the semiconductor substrate; a first seal ring embedded in the interlayer insulating film and surrounding the element region, and a second seal ring surrounding the element region on the inside or outside of the first seal ring; the first seal ring and the second seal ring are made of laminated conductive films including at least one line-shaped wiring layer and at least one line-shaped via layer, and are insulated from each other or electrically connected only at the uppermost layer of the conductive films; the first seal ring is electrically insulated from the semiconductor substrate; The semiconductor device is characterized in that the second seal ring is electrically connected to the semiconductor substrate.

2. In claim 1, an upper interlayer insulating film formed on the interlayer insulating film; the first seal ring and the second seal ring are provided above the conductive film and include stacked upper conductive layers including at least one upper wiring layer and at least one upper via layer; the upper wiring layer is thicker than the wiring layer, The semiconductor device is characterized in that the upper conductive layer is buried in the upper interlayer insulating film.

3. In claim 2, the interlayer insulating film is made of a low dielectric constant material, The semiconductor device is characterized in that the dielectric constant of the upper interlayer insulating film is higher than the dielectric constant of the interlayer insulating film.

4. In claim 1, a first insulating layer formed on the semiconductor substrate; an active layer formed on the first insulating layer; a second insulating layer that partitions the active layer, the first seal ring is connected to the active layer via a first contact; The semiconductor device according to claim 1, wherein the second seal ring is connected to the semiconductor substrate via a second contact that penetrates the first insulating layer and the second insulating layer.

5. In claim 1, a first insulating layer formed on the semiconductor substrate; an active layer formed on the first insulating layer; a second insulating layer that partitions the active layer, the first seal ring is connected to the second insulating layer via a first contact; The semiconductor device according to claim 1, wherein the second seal ring is connected to the semiconductor substrate via a second contact that penetrates the first insulating layer and the second insulating layer.

6. In claim 1, a first insulating layer formed on the semiconductor substrate; an active layer formed on the first insulating layer; a second insulating layer that partitions the active layer; a polysilicon layer formed on the active layer or the second insulating layer; the first seal ring is connected to the polysilicon layer through a first contact; The semiconductor device according to claim 1, wherein the second seal ring is connected to the semiconductor substrate via a second contact that penetrates the first insulating layer and the second insulating layer.

7. In claim 1, In the first seal ring and the second seal ring, at least one of the via layers has a plurality of linear vias.

8. In claim 1, Further comprising a first semiconductor region and a second semiconductor region provided on the semiconductor substrate; the first seal ring is electrically connected to the first semiconductor region; the second seal ring is electrically connected to the second semiconductor region; The semiconductor device according to claim 1, wherein the first semiconductor region is insulated from the semiconductor substrate.

9. In claim 8, the semiconductor substrate is a P-type semiconductor substrate, the first semiconductor region is N-type; The semiconductor device is characterized in that the second semiconductor region is of P type.

Images