Photosensitive substrate development method, photomask production method, and electronic device production method

Abstract

A method for producing a photosensitive substrate according to the present invention comprises: a process in which a photosensitive substrate, which has been exposed to light by scanning each one of a plurality of scan fields in the photosensitive substrate through a photomask in a first direction with use of pulsed laser beams that have a plurality of center wavelengths, is heated so that each one of the plurality of scan fields has a temperature distribution that has a temperature gradient in a second direction that intersects with the first direction on the surface of the photosensitive substrate; and a process in which after heating the photosensitive substrate, the photosensitive substrate is developed by suppling a developer liquid to the surface of the photosensitive substrate.

Description

[Technical Field]

[0001] The present disclosure relates to a method for developing a photosensitive substrate, a method for making a photomask, and a method for manufacturing an electronic device. [Background technology]

[0002] In recent years, semiconductor exposure devices have been required to improve their resolution in response to the miniaturization and high integration of semiconductor integrated circuits. To this end, the wavelength of light emitted from exposure light sources has been shortened. For example, KrF excimer laser devices, which output laser light with a wavelength of approximately 248 nm, and ArF excimer laser devices, which output laser light with a wavelength of approximately 193 nm, are used as gas laser devices for exposure.

[0003] The spectral linewidth of the spontaneously oscillating light from KrF excimer laser devices and ArF excimer laser devices is as wide as 350 to 400 pm. Therefore, if a projection lens is constructed using a material that transmits ultraviolet light, such as KrF and ArF laser light, chromatic aberration may occur. As a result, resolution may decrease. Therefore, it is necessary to narrow the spectral linewidth of the laser light output from the gas laser device to a level where chromatic aberration can be ignored. Therefore, a line narrowing module (LNM) containing a line narrowing element (e.g., an etalon or grating) may be installed inside the laser resonator of the gas laser device to narrow the spectral linewidth. A gas laser device that narrows the spectral linewidth is called a line narrowing laser device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Summary of the specification of U.S. Patent No. 5,968,691

[0005] In one aspect of the present disclosure, a method for manufacturing a photosensitive substrate includes: scanning each of a plurality of scan fields included in the photosensitive substrate in a first direction using a pulsed laser beam having a plurality of center wavelengths via a photomask to expose the photosensitive substrate; heating the exposed photosensitive substrate so that a temperature distribution having a temperature gradient in a second direction intersecting the first direction is obtained on the surface of the photosensitive substrate in each of the plurality of scan fields; and, after heating the photosensitive substrate, supplying a developer to the surface of the photosensitive substrate to perform development.

[0006] In one aspect of the present disclosure, a method for creating a photomask for use in photolithography using pulsed laser light having multiple center wavelengths includes: measuring a wafer pattern on a second test wafer that has been exposed by scanning the second test wafer with pulsed laser light through a second test mask in a first direction, and that has been heated to have a temperature distribution on the surface of the second test wafer that has a temperature gradient in a second direction intersecting the first direction in each of multiple scan fields included in the second test wafer, by supplying a developer to the surface of the second test wafer and developing the second test wafer; obtaining a measured wafer pattern that indicates the measurement results in each of multiple divided areas aligned in the second direction; creating a correction mask pattern for creating a photomask based on the test mask pattern formed on the second test mask, the measurement wafer pattern, and a target pattern that is a target wafer pattern on a photosensitive substrate; and creating a photomask based on the correction mask pattern.

[0007] In one aspect of the present disclosure, a method for manufacturing an electronic device includes generating pulsed laser light including multiple center wavelengths using a laser device, outputting the pulsed laser light to an exposure device, scanning and exposing each of multiple scan fields included in a photosensitive substrate in a first direction with the pulsed laser light via a photomask in the exposure device, heating the exposed photosensitive substrate so as to have a temperature distribution in each of the multiple scan fields on the surface of the photosensitive substrate that has a temperature gradient in a second direction intersecting the first direction, and after heating the photosensitive substrate, supplying a developer to the surface of the photosensitive substrate to perform development. [Brief explanation of the drawings]

[0008] Some embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying drawings, in which: [Figure 1] FIG. 1 shows a schematic configuration of an exposure system in a comparative example. [Figure 2] FIG. 2 is a flowchart showing a process for forming a resist pattern on a photosensitive substrate in a comparative example. [Figure 3] FIG. 3 is a flowchart showing the details of the process of post-exposure baking of a photosensitive substrate and supplying a developer. [Figure 4] FIG. 4 shows a schematic configuration of a laser device. [Figure 5] FIG. 5 shows a photosensitive substrate being exposed by an exposure apparatus. [Figure 6] FIG. 6 is a diagram illustrating how the position of the scan field on the photosensitive substrate changes relative to the position of the beam cross section of the pulsed laser light. [Figure 7] FIG. 7 is a diagram illustrating how the position of the scan field on the photosensitive substrate changes relative to the position of the beam cross section of the pulsed laser light. [Figure 8] FIG. 8 is a diagram illustrating how the position of the scan field on the photosensitive substrate changes relative to the position of the beam cross section of the pulsed laser light. [Figure 9] FIG. 9 is a graph showing periodic wavelength changes. [Figure 10] FIG. 10 shows the integrated spectrum of pulsed laser light containing multiple central wavelengths. [Figure 11] FIG. 11 shows an example in which a wafer pattern different from the target pattern is formed due to the optical proximity effect when the target pattern is used as a mask pattern as is. [Figure 12] FIG. 12 shows an example in which a wafer pattern close to a target pattern is formed when a corrected mask pattern that has been subjected to optical proximity effect correction is used. [Figure 13]FIG. 13 is a conceptual diagram of model-based OPC in a comparative example. [Figure 14] FIG. 14 is a flowchart of the model-based OPC. [Figure 15] FIG. 15 shows the data structure of the measurement wafer pattern. [Figure 16] FIG. 16 is a flowchart showing the details of the process of creating a model function group. [Figure 17] FIG. 17 shows the concept of off-axis chromatic aberration that occurs when a photosensitive substrate is exposed with a pulsed laser beam containing a plurality of central wavelengths. [Figure 18] FIG. 18 shows how the contrast of an optical image formed on a photosensitive substrate is reduced by off-axis chromatic aberration. [Figure 19] FIG. 19 shows the measurement points of dimensions for calculating line edge roughness. [Figure 20] FIG. 20 is a flowchart showing a process for forming a resist pattern on a photosensitive substrate in the first embodiment. [Figure 21] FIG. 21 is a flowchart showing the details of the process of post-exposure baking of a photosensitive substrate with a set temperature distribution and supplying a developer. [Figure 22] FIG. 22 is a flowchart showing the details of the process for setting the temperature distribution for post-exposure baking. [Figure 23] FIG. 23 is a flowchart showing the details of the process of post-exposure baking and supplying a developer to each of imax PEB test wafers. [Figure 24] FIG. 24 shows a PEB test wafer and the temperatures set for post-exposure baking the PEB test wafer. [Figure 25] FIG. 25 is a flowchart showing the details of the process for measuring the wafer patterns of imax developed PEB test wafers. [Figure 26] FIG. 26 conceptually shows the area of ​​the scan field where the line edge roughness and critical dimension are measured. [Figure 27]Figure 27 shows a table summarizing the average values. [Figure 28] FIG. 28 is a flowchart showing the details of the process for setting the temperature distribution based on the measurement results. [Figure 29] FIG. 29 shows an example of the temperature distribution in the X-axis direction set in the first embodiment. [Figure 30] FIG. 30 shows an example of the temperature distribution in the Y-axis direction set in the first embodiment. [Figure 31] FIG. 31 shows a first example of the temperature distribution set in the first embodiment. [Figure 32] FIG. 32 shows a second example of the temperature distribution set in the first embodiment. [Figure 33] FIG. 33 is a flowchart showing a process for forming a resist pattern on a photosensitive substrate in the second embodiment. [Figure 34] FIG. 34 is a flowchart showing details of the process of S13 in the second embodiment. [Figure 35] FIG. 35 is a flowchart showing details of the process of S15 in the second embodiment. [Figure 36] FIG. 36 is a conceptual diagram of the division model-based OPC in the second embodiment. [Figure 37] FIG. 37 shows multiple divided regions included in the scan field of the test wafer. [Figure 38] FIG. 38 is a flowchart of the split model-based OPC. [Figure 39] FIG. 39 shows the data structure of the measurement wafer pattern. [Figure 40] FIG. 40 is a flowchart showing the details of the process for creating a model function group. [Figure 41] FIG. 41 shows an example of a set of model functions. Embodiment

[0009] <Contents> 1. Comparative Example 1.1 Exposure system 1.1.1 Configuration 1.1.2 Operation 1.2 Laser device 100 1.2.1 Configuration 1.2.2 Operation 1.3 Band-narrowing module14 1.3.1 Configuration 1.3.2 Operation 1.4 Scanning Exposure 1.5 Periodic wavelength change and integrated spectrum 1.6 Optical Proximity Correction (OPC) 1.6.1 Overview 1.6.2 Model-based OPC 1.7 Issues in the comparative example 2. Control of LER by temperature distribution during post-exposure baking 2.1 Operation 2.1.1 Post-exposure bake 2.1.2 Temperature distribution setting 2.2 Effect 3. Post-exposure bake temperature distribution and combination with OPC 3.1 Operation 3.2 Effect 4.Other

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments described below show some examples of the present disclosure and do not limit the content of the present disclosure. Furthermore, not all of the configurations and operations described in each embodiment are necessarily essential as the configurations and operations of the present disclosure. Note that the same components are given the same reference symbols, and redundant explanations will be omitted.

[0011] 1. Comparative Example 1.1 Exposure system 1 shows a schematic configuration of an exposure system in a comparative example. The comparative example of the present disclosure is a configuration that the applicant recognizes as being known only by the applicant, and is not a publicly known example that the applicant acknowledges. The exposure system includes a laser device 100, an exposure device 200, and a development device 300. In Figure 1, the laser device 100 is shown in a simplified form.

[0012] The laser apparatus 100 includes a laser control processor 130. The laser control processor 130 is a processing device including a memory 132 in which a control program is stored and a CPU (central processing unit) 131 that executes the control program. The laser control processor 130 is specially configured or programmed to execute various processes included in the present disclosure. The laser apparatus 100 is configured to output pulsed laser light toward the exposure apparatus 200.

[0013] 1.1.1 Configuration As shown in FIG. 1, the exposure apparatus 200 includes an illumination optical system 201 , a projection optical system 202 , and an exposure control processor 210 . The illumination optical system 201 illuminates the mask pattern of a photomask (not shown) placed on a mask stage MS with pulsed laser light incident from the laser device 100 .

[0014] The projection optical system 202 reduces and projects the pulsed laser light that has passed through the photomask, forming an image on a workpiece (not shown) placed on a workpiece table WT. The workpiece is a photosensitive substrate such as a semiconductor wafer coated with a resist film.

[0015] The exposure control processor 210 is a processing device that includes a memory 212 that stores a control program, and a CPU 211 that executes the control program. The exposure control processor 210 is specially configured or programmed to execute various processes included in the present disclosure. The exposure control processor 210 manages the overall control of the exposure apparatus 200, and transmits and receives various parameters and signals to and from the laser control processor 130.

[0016] The developing apparatus 300 includes a wafer moving unit 301 , a processing unit 302 , a measurement unit 303 , and a developing control processor 310 . The wafer transfer unit 301 is a device that transfers the photosensitive substrate to and from the exposure device 200 and moves the photosensitive substrate inside the developing device 300 . The processing unit 302 is an apparatus that applies a resist film to a photosensitive substrate, performs post-exposure baking (PEB) of the photosensitive substrate exposed inside the exposure apparatus 200, supplies a developer, cleans, dries, and performs post-development baking (PDB), etc. The post-exposure baking and post-development baking are performed by heating the photosensitive substrate with a hot plate (not shown) included in the processing unit 302. A single developing apparatus 300 may include multiple processing units 302, and processing by each processing unit 302 may be performed in parallel. The measurement unit 303 is a device such as a CD-SEM that measures a pattern formed on a photosensitive substrate by exposure and development. The measurement unit 303 may be included in the developing device 300, or may be provided separately from the developing device 300.

[0017] The development control processor 310 is a processing device that includes a memory 312 that stores a control program and a CPU 311 that executes the control program. The development control processor 310 is specially configured or programmed to execute the various processes included in the present disclosure.

[0018] 1.1.2 Operation The exposure control processor 210 transmits various parameters including the target long wavelength λL, the target short wavelength λS, and the voltage command value, as well as a trigger signal, to the laser control processor 130. The laser control processor 130 controls the laser device 100 in accordance with these parameters and signals.

[0019] The exposure control processor 210 synchronizes the mask stage MS and the workpiece table WT and translates them in opposite directions, thereby exposing the workpiece to pulsed laser light that reflects the mask pattern. This photolithography process transfers a mask pattern onto a photosensitive substrate, which is then subjected to multiple steps to manufacture an electronic device.

[0020] 2 is a flowchart showing a process for forming a resist pattern on a photosensitive substrate in a comparative example. While FIG. 2 mainly shows the process performed by the developing apparatus 300, it also includes a portion of the process performed by the exposure apparatus 200.

[0021] In S3, the development control processor 310 controls the processing unit 302 to form a resist film on the semiconductor wafer to form a photosensitive substrate.

[0022] In S4, the exposure control processor 210 controls each part of the exposure apparatus 200 so that the photosensitive substrate is exposed through a photomask with pulsed laser light having a plurality of center wavelengths.

[0023] In S5, the development control processor 310 controls the processing unit 302 to post-exposure bake the photosensitive substrate and supply a developer to the surface of the photosensitive substrate. For example, acid generated in the exposed portions of the resist film acts as a catalyst during the post-exposure bake, promoting a chemical reaction in the resist film. This chemical reaction changes the positive resist from alkali-insoluble to alkali-soluble, and the negative resist from alkali-soluble to alkali-insoluble. The alkali-soluble portions are then removed by the alkaline developer. Details of S5 will be described later with reference to FIG. 3.

[0024] At S6, the development control processor 310 controls the processing unit 302 to perform cleaning, drying, and post-development baking of the developed photosensitive substrate. In S7, the development control processor 310 controls the measurement unit 303 to measure the photosensitive substrate that has been baked after development, as needed. After S7, the process of this flowchart ends.

[0025] 3 is a flowchart showing the details of the process of post-exposure baking of a photosensitive substrate and supplying a developer, which corresponds to the subroutine of S5 in FIG.

[0026] In S51, the development control processor 310 determines whether or not to change the temperature setting of the hot plate. The temperature of the hot plate is determined by the mask pattern, the type of resist, the exposure conditions, and the like. When the temperature setting of the hot plate is to be changed (S51: YES), the development control processor 310 reads out the new temperature setting in S52 and changes the temperature setting.

[0027] If the temperature setting of the hot plate is not changed (S51: NO), or after the temperature setting of the hot plate is changed (S52), the development control processor 310 controls the processing unit 302 in S53 to bring the temperature of the hot plate close to the set temperature and heat the photosensitive substrate for a predetermined time.

[0028] In S54, the developer control processor 310 controls the processing unit 302 to supply developer to the surface of the photosensitive substrate. After S54, the development control processor 310 ends the processing of this flowchart and returns to the processing shown in FIG.

[0029] 1.2 Laser device 100 1.2.1 Configuration Fig. 4 shows a schematic configuration of the laser device 100. Mutually perpendicular V-axis, H-axis, and Z-axis are shown in Fig. 4. Fig. 4 shows the laser device 100 as seen in the -V direction, the exposure device 200 is shown in a simplified form, and the developing device 300 is not shown.

[0030] In addition to a laser control processor 130, the laser apparatus 100 includes a laser chamber 10, a pulsed power module (PPM) 13, a line narrowing module 14, an output coupling mirror 15, and a monitor module 17. The line narrowing module 14 and the output coupling mirror 15 form an optical resonator.

[0031] The laser chamber 10 is disposed in the optical path of the optical resonator and is provided with windows 10a and 10b. The laser chamber 10 is equipped with a discharge electrode 11a and a paired discharge electrode (not shown) inside. The discharge electrode (not shown) is positioned so as to overlap with the discharge electrode 11a in the direction of the V axis. The laser chamber 10 is filled with a laser gas containing, for example, argon gas or krypton gas as a rare gas, fluorine gas as a halogen gas, and neon gas as a buffer gas.

[0032] The pulse power module 13 includes a switch (not shown) and is connected to a charger (not shown).

[0033] The line narrowing module 14 includes prisms 41 to 43, a grating 53, and a mirror 63. The line narrowing module 14 will be described in detail later. The output coupling mirror 15 is made up of a partial reflection mirror.

[0034] A beam splitter 16 that transmits part of the pulsed laser beam with high transmittance and reflects the other part is disposed in the optical path of the pulsed laser beam output from the output coupling mirror 15. A monitor module 17 is disposed in the optical path of the pulsed laser beam reflected by the beam splitter 16.

[0035] 1.2.2 Operation The laser control processor 130 acquires various parameters, including the target long wavelength λL, the target short wavelength λS, and the voltage command value, from the exposure control processor 210. The laser control processor 130 transmits a control signal to the line narrowing module 14 based on the target long wavelength λL and the target short wavelength λS.

[0036] The laser control processor 130 receives a trigger signal from the exposure control processor 210. The laser control processor 130 transmits an oscillation trigger signal based on the trigger signal to the pulse power module 13. A switch included in the pulse power module 13 turns on when it receives the oscillation trigger signal from the laser control processor 130. When the switch turns on, the pulse power module 13 generates a pulsed high voltage from the electrical energy stored in the charger and applies this high voltage to the discharge electrode 11a.

[0037] When a high voltage is applied to the discharge electrode 11a, a discharge occurs in the discharge space between the discharge electrode 11a and another discharge electrode (not shown). The energy of this discharge excites the laser gas in the laser chamber 10 and causes it to transition to a higher energy level. When the excited laser gas subsequently transitions to a lower energy level, it emits light with a wavelength corresponding to the difference in energy levels.

[0038] Light generated within the laser chamber 10 is emitted to the outside of the laser chamber 10 through windows 10a and 10b. The light emitted from the window 10a enters the line narrowing module 14. Of the light that enters the line narrowing module 14, light having a wavelength near the desired wavelength is returned by the line narrowing module 14 to the laser chamber 10.

[0039] The output coupling mirror 15 transmits and outputs a portion of the light emitted from the window 10 b, and reflects the other portion back into the laser chamber 10 .

[0040] In this way, the light emitted from the laser chamber 10 travels back and forth between the line-narrowing module 14 and the output-coupling mirror 15. This light is amplified each time it passes through the discharge space in the laser chamber 10. In addition, this light is narrowed in line each time it is bent back by the line-narrowing module 14, and becomes light with a steep wavelength distribution centered on a portion of the range of wavelengths selected by the line-narrowing module 14. The light thus oscillates and is line-narrowed, and is output from the output-coupling mirror 15 as pulsed laser light.

[0041] The monitor module 17 measures the central wavelength of the pulsed laser light and transmits the measured wavelength to the laser control processor 130. The laser control processor 130 performs feedback control of the line narrowing module 14 based on the measured wavelength. The pulsed laser light transmitted through the beam splitter 16 enters the exposure device 200 .

[0042] 1.3 Band-narrowing module14 1.3.1 Configuration Prisms 41 to 43 are arranged in the optical path of the light beam emitted from window 10a in ascending order of their numbers. Prisms 41 to 43 are arranged so that the surfaces of prisms 41 to 43 where the light beam enters and exits are all parallel to the V axis. Prism 43 can be rotated around an axis parallel to the V axis by rotation stage 143.

[0043] Mirror 63 is disposed in the optical path of the light beam transmitted through prisms 41 to 43. Mirror 63 is disposed so that the surface that reflects the light beam is parallel to the V axis, and can be rotated around an axis parallel to the V axis by rotation stage 163.

[0044] The grating 53 is disposed in the optical path of the light beam reflected by the mirror 63. The direction of the grooves of the grating 53 is parallel to the V axis.

[0045] 1.3.2 Operation The light beam emitted from the window 10a has its traveling direction changed by each of the prisms 41 to 43 in a plane parallel to the HZ plane, which is a plane perpendicular to the V axis, and its beam width is expanded in the plane parallel to the HZ plane. The light beams transmitted through the prisms 41 to 43 are reflected by the mirror 63 and enter the grating 53 .

[0046] The light beam incident on the grating 53 is reflected by the multiple grooves of the grating 53 and diffracted in a direction according to the wavelength of the light. The grating 53 is in a Littrow configuration so that the angle of incidence of the light beam incident on the grating 53 from the mirror 63 matches the diffraction angle of the diffracted light of the desired wavelength.

[0047] The mirror 63 and the prisms 41 to 43 reduce the beam width of the light beam returned from the grating 53 in a plane parallel to the HZ plane, and return the light beam to the inside of the laser chamber 10 through the window 10a.

[0048] The laser control processor 130 controls the rotation stages 143 and 163 via drivers (not shown). The angle of incidence of the light beam incident on the grating 53 changes depending on the rotation angle of the rotation stages 143 and 163, and the wavelength selected by the line-narrowing module 14 changes. The rotation stage 143 is mainly used for coarse adjustment, and the rotation stage 163 is mainly used for fine adjustment.

[0049] The laser control processor 130 controls the rotation stage 163 so that the attitude of the mirror 63 changes periodically for each set of pulses, based on the target long wavelength λL and target short wavelength λS received from the exposure control processor 210. This causes the central wavelength of the pulsed laser beam to change periodically between the target long wavelength λL and the target short wavelength λS for each set of pulses. In this way, the laser device 100 can perform laser oscillation at multiple wavelengths.

[0050] The focal length in the exposure apparatus 200 depends on the wavelength of the pulsed laser light. The pulsed laser light oscillated at multiple wavelengths and incident on the exposure apparatus 200 can form images at multiple different positions in the direction of the optical path axis of the pulsed laser light, thereby effectively increasing the depth of focus. For example, even when exposing a thick resist film, the imaging performance in the thickness direction of the resist film can be maintained. Alternatively, the resist profile, which indicates the cross-sectional shape of the developed resist film, can be adjusted.

[0051] 1.4 Scanning Exposure FIG. 5 shows a photosensitive substrate exposed by exposure apparatus 200. The photosensitive substrate is, for example, a substantially circular disk-shaped plate of single-crystal silicon. The photosensitive substrate is exposed in sections, such as scan fields SF1 and SF2. Each of scan fields SF1 and SF2 is an area where some of the many semiconductor chips formed on the photosensitive substrate are formed, and corresponds to an area where the reticle pattern of one reticle is transferred in one scan. The numbers included in the symbols SF1 and SF2 indicate the exposure order. When explaining without specifying the exposure order, they are simply referred to as SF without the numbers.

[0052] First, the photosensitive substrate is moved so that the first scan field SF1 is irradiated with the pulsed laser light, and the first scan field SF1 is exposed. Next, the photosensitive substrate is moved so that the second scan field SF2 is irradiated with the pulsed laser light, and the second scan field SF2 is exposed.

[0053] The other scan fields SF are also exposed in sequence, and when the last scan field SFkmax is exposed, the exposure of the photosensitive substrate is completed.

[0054] 6 to 8 show how the position of the scan field SF on the photosensitive substrate changes relative to the position of the beam cross section B of the pulsed laser light. The direction in which the position of the scan field SF changes is defined as the Y-axis direction, and the direction perpendicular to the Y-axis direction is defined as the X-axis direction. The Y-axis direction corresponds to the first direction in this disclosure, and the X-axis direction corresponds to the second direction in this disclosure.

[0055] When exposing one scan field SF, pulsed laser light is output continuously at a predetermined repetition frequency. Continuously outputting pulsed laser light at a predetermined repetition frequency is called burst output. When the exposure position is moved from one scan field SF to another scan field SF, the output of pulsed laser light is paused. Therefore, burst output is repeated multiple times to expose one photosensitive substrate.

[0056] The width of the scan field SF in the X-axis direction corresponds to the width of the beam cross section B of the pulsed laser beam in the X-axis direction at the position of the workpiece table WT (see FIG. 1). The width of the scan field SF in the Y-axis direction is larger than the width W of the beam cross section B of the pulsed laser beam in the Y-axis direction at the position of the workpiece table WT.

[0057] The procedure for scanning and exposing each scan field SF in the Y-axis direction with pulsed laser light is performed in the order shown in FIGS. 6, 7, and 8. First, as shown in FIG. 6, the workpiece table WT is positioned so that the +Y-direction end SFy+ of the scan field SF is located a predetermined distance in the -Y direction relative to the position of the -Y-direction end By- of the beam cross section B. Then, the workpiece table WT is accelerated in the +Y direction to a speed Vy until the +Y-direction end SFy+ of the scan field SF coincides with the position of the -Y-direction end By- of the beam cross section B. As shown in FIG. 7, the scan field SF is exposed while the workpiece table WT is moved in the +Y direction so that the position of the scan field SF moves linearly at a constant speed Vy relative to the position of the beam cross section B. As shown in FIG. 8, the scanning of the scan field SF is completed when the workpiece table WT is moved until the -Y-direction end SFy- of the scan field SF passes the position of the +Y-direction end By+ of the beam cross section B.

[0058] In this way, exposure is performed while the scan field SF moves relative to the position of the beam cross section B. Using the scan field SF as a reference, it can also be said that scanning is performed in the −Y direction with the pulsed laser light.

[0059] The time Ts required for the scan field SF to move a distance equivalent to the width W of the beam cross section B of the pulsed laser light at a speed Vy is given by: Ts=W / Vy The number of irradiation pulses Ns of the pulsed laser light irradiated onto any one location in the scan field SF is the same as the number of pulses of the pulsed laser light generated in the required time Ts, and is given by: Ns=F·Ts Here, F is the repetition frequency of the pulsed laser light. The number of irradiation pulses Ns is also called the number of N slit pulses.

[0060] Here, the scan fields SF included in the photosensitive substrate for manufacturing electronic devices have been described, but the same applies to the scan fields SF included in the PEB test wafer and OPC test wafer described later.

[0061] 1.5 Periodic wavelength change and integrated spectrum Fig. 9 is a graph showing periodic wavelength changes. In Fig. 9, the horizontal axis represents time t and the vertical axis represents wavelength λ. Each small circle shown in Fig. 9 represents the time t when pulsed laser light is output and the center wavelength at that time.

[0062] In the example shown in Figure 9, the center wavelength changes periodically between the target long wavelength λL and the target short wavelength λS. The number of pulses in one cycle of the wavelength change is N. The cycle T of the wavelength change is given by the following equation: T=N / F

[0063] FIG. 10 shows the integrated spectrum of pulsed laser light containing multiple center wavelengths. The integrated spectrum shown in FIG. 10 corresponds to the integrated spectrum for one cycle of the wavelength change shown in FIG. 9. In FIG. 10, the horizontal axis represents wavelength λ, and the vertical axis represents light intensity I. The dashed line represents the spectrum of pulsed laser light for each pulse, and each center wavelength may coincide with the peak wavelength. By changing the center wavelength in multiple steps between the target long wavelength λL and the target short wavelength λS as shown in FIG. 9, the integrated spectrum shown in FIG. 10 can have a flat-top shape with an approximately uniform light intensity I between the target long wavelength λL and the target short wavelength λS.

[0064] The number of irradiation pulses Ns of the pulsed laser light irradiated to any one point in the scan field SF is desirably a multiple of the number of pulses N for one cycle of wavelength change. This ensures that any part of the scan field SF is irradiated with pulsed laser light having the same irradiation pulse number Ns with the same integrated spectrum. This reduces variation in exposure results depending on the irradiation position, enabling the production of high-quality electronic devices.

[0065] 1.6 Optical Proximity Correction (OPC) 1.6.1 Overview In photolithography, if the dimensions of a designed target pattern G are smaller than the wavelength of the exposure light source, even if the target pattern G is directly written on a mask and exposed, it may not be possible to obtain a wafer pattern equivalent to the target pattern G. Therefore, the process of correcting the target pattern G in advance to create a corrected mask pattern F so that a wafer pattern equivalent to the target pattern G can be obtained is called optical proximity correction (OPC).

[0066] 11 shows an example in which, when target pattern G is used as a mask pattern as is, the optical proximity effect results in the formation of a wafer pattern R1 that differs from target pattern G. For example, effects such as corners included in target pattern G being rounded in wafer pattern R1 and convex portions included in target pattern G being recessed in wafer pattern R1 can be observed.

[0067] 12 shows an example in which a wafer pattern R2 similar to the target pattern G is formed using a corrected mask pattern F that has been subjected to optical proximity effect correction. The corrected mask pattern F includes modifications such as adding protruding portions to convex corners of the target pattern G, further recessing concave corners of the target pattern G, and adding an assist pattern SRAF (sub-resolution assist feature). This makes it possible to obtain a wafer pattern R2 with a shape similar to the target pattern G.

[0068] In optical proximity correction, not only the optical proximity effect is corrected, but also differences between mask patterns and wafer patterns that occur during resist film development and other semiconductor processes can be corrected.

[0069] There are two types of optical proximity correction known: model-based OPC and rule-based OPC. Here, we will explain model-based OPC as an example.

[0070] 1.6.2 Model-based OPC In model-based OPC, a model function group M is created based on the results of exposure simulations performed for each characteristic shape included in target pattern G and the actual exposure results. This model function group M is used to create a corrected mask pattern F to obtain a wafer pattern equivalent to target pattern G. Model-based OPC is mainly used in line width generations smaller than 130 nm.

[0071] 13 is a conceptual diagram of model-based OPC in a comparative example. First, an OPC test mask including a test mask pattern E is created based on a target pattern G. An OPC test wafer is exposed using the OPC test mask, and the patterned OPC test wafer is measured to obtain a measurement wafer pattern D.

[0072] A model function group M is created to predict the actual exposure result from the exposure simulation result based on the result of the exposure simulation using the test mask pattern E and the measurement wafer pattern D, which is the actual exposure result. This model function group M is used to create an OPC recipe P, which is a program for creating a corrected mask pattern F from the target pattern G. The corrected mask pattern F is created by executing the OPC recipe P using the target pattern G. A wafer pattern close to the target pattern G can be obtained by exposing a photosensitive substrate using the corrected mask pattern F.

[0073] Figure 14 is a flowchart of model-based OPC. The processing shown in Figure 14 is performed by a processor such as exposure control processor 210. The processor may be included in another device, such as a mask manufacturing device (not shown) or a server (not shown) connected to multiple exposure tools 200, and the configuration of such a processor may be similar to that of exposure control processor 210. When the amount of calculation becomes enormous, it is more advantageous to increase the processing capacity of the processor included in the server than to increase the processing capacity of each of the exposure control processors 210 included in the multiple exposure tools 200.

[0074] In S210, the processor acquires a target pattern G. The target pattern G is a target wafer pattern for a photosensitive substrate designed by a semiconductor chip designer, and is provided in a data format called, for example, GDS (Graphic Data System) or OASIS (Open Artwork System Interchange Standard). The target pattern G may be a pattern after etching if etching of the photosensitive substrate is performed, or may be a pattern of a resist film developed after exposure if etching is not performed.

[0075] In S220, the processor sets exposure conditions based on the target pattern G. The exposure conditions include setting conditions of the exposure apparatus 200, such as the shape of the illumination light source by the illumination optical system 201 (see FIG. 1), the presence or absence of polarized illumination, and the numerical aperture of the projection optical system 202. Further, for example, the exposure conditions include the type of resist film, the presence and type of anti-reflection film, resist stack information, the thickness of the resist film, the application conditions of the resist film, and the development conditions.

[0076] In S230, the processor creates a test mask pattern E based on the target pattern G. Specifically, characteristic shapes included in the target pattern G are extracted, and one or more dimensional conditions are set for each of the shapes to create the test mask pattern E. According to the test mask pattern E, an OPC test mask is created by a mask manufacturing device.

[0077] In S240, exposure apparatus 200 exposes the OPC test wafer by scanning the OPC test wafer through the OPC test mask. The OPC test wafer is a substrate for test exposure on which a resist film is applied under the same conditions as the photosensitive substrate. The OPC test mask corresponds to the second test mask in this disclosure, and the OPC test wafer corresponds to the second test wafer in this disclosure.

[0078] In S242, the processor controls the processing unit 302 to post-expose bake the OPC test wafer in the developer 300 and to supply a developer to the surface of the OPC test wafer. Furthermore, the developed photosensitive substrate is washed, dried, and baked after development, and if etching is to be performed, an etching device (not shown) performs etching to pattern the OPC test wafer.

[0079] In S250, the processor measures the wafer pattern of the OPC test wafer using a measurement device such as a CD-SEM (not shown), and acquires a measurement wafer pattern D indicating the measurement results. 15 shows the data structure of the measurement wafer pattern D. The measurement wafer pattern D includes p dimensions measured for each of m features 1 to m. For example, for feature 1, dimension D 11 ~D 1p is measured, and for shape 2, dimension D 21 ~D 2p is measured, and for shape m, the dimension D m1 ~D mp However, the values ​​of p in shapes 1 to m may be different from each other, and the value of p may be 1 or 2 or more. When multiple scan fields SF included in an OPC test wafer are test exposed using one OPC test mask, the average values ​​for each shape and dimension are calculated from the measurement results for the multiple scan fields SF, and this is used as the measurement wafer pattern D.

[0080] Referring again to FIG. 14, in S260, the processor creates a model function set M based on the test mask pattern E and the measurement wafer pattern D.

[0081] 16 is a flowchart showing the details of the process for creating the model function group M. The process shown in FIG. 16 corresponds to the subroutine of S260 in FIG.

[0082] In S262, the processor performs an exposure simulation with a single wavelength using the test mask pattern E. In the exposure simulation, Fourier's imaging theory is used.

[0083] In S264, the processor initializes a model function group M. The model function group M includes, for example, k functions M1 to M k Functions M1 to M k Each of these functions contains multiple coefficients. For example, the function M1 has i coefficients c 11 ~c 1i contains the function M k has i coefficients c k1 ~c ki However, functions M1 to M k The values ​​of i in may be different from each other.

[0084] In S265, the processor performs a predictive calculation of the wafer pattern by applying the exposure simulation result to the model function group M. The predictive calculation includes the four arithmetic operations and convolution integral.

[0085] In S266, the processor determines whether the result of the predictive calculation matches the measurement wafer pattern D. Even if the result of the predictive calculation does not completely match the measurement wafer pattern D, it can be determined that the result of the predictive calculation matches the measurement wafer pattern D if a predetermined condition is satisfied. If the result of the predictive calculation matches the measurement wafer pattern D (S266: YES), the processor sets the model function set M used in S265 as the created model function set M, ends the processing of this flowchart, and returns to the processing shown in FIG. 14. If the result of the predictive calculation does not match the measurement wafer pattern D (S266: NO), the processor proceeds to S267.

[0086] In S267, the processor updates the model function set M by changing the coefficients included in the model function set M or by making other modifications. The updated model function set M may include, for example, k' functions M1 to M k' Functions M1 to M k'The value of k', which indicates the number of functions M1 to M included in the model function group M used in S265, is k The number of functions M1 to M k' Coefficient c' included in 11 ~c' k'i The coefficient c included in the model function group M used in S265 11 ~c ki may be different from.

[0087] After S267, the processor returns the process to S265 and updates the model function group M until the result of the predictive calculation matches the measured wafer pattern D.

[0088] 14 again, in S270, the processor creates an OPC recipe P based on the model function group M. The OPC recipe P may include, for example, the definition of the model function group M, the dimensions D shown in FIG. 11 ~D mp It includes descriptions of the measurement points and measurement directions, and the correction rules for the mask pattern.

[0089] In S280, the processor executes the OPC recipe P using the target pattern G to create a corrected mask pattern F. The corrected mask pattern F is also provided in the GDS or OASIS data format. In S310, the mask manufacturing equipment creates a photomask based on the corrected mask pattern F, and the process of this flowchart ends.

[0090] 1.7 Issues in the comparative example Figure 17 illustrates the concept of off-axis chromatic aberration CA, which occurs when a photosensitive substrate is exposed with a pulsed laser beam containing multiple center wavelengths. As shown in Figure 17, because the refractive index in the projection optical system 202 differs between the target long wavelength λL and the target short wavelength λS, the portion of the mask pattern of the mask placed on the mask stage MS that is positioned on the optical path axis A of the projection optical system 202 is imaged at a different position in the depth direction of the photosensitive substrate placed on the workpiece table WT. This is called on-axis chromatic aberration. In contrast, the portion of the mask pattern that is positioned away from the optical path axis A is imaged at a different position not only in the depth direction of the photosensitive substrate but also in the plane direction of the photosensitive substrate. This is called off-axis chromatic aberration CA.

[0091] Figure 18 illustrates how off-axis chromatic aberration reduces the contrast of the optical image formed on the photosensitive substrate. The horizontal axis of Figure 18 represents the distance in the X-axis direction from position 0 on the optical path axis A, and the vertical axis represents light intensity I. At position 0 on the optical path axis A, light of multiple wavelengths having the light intensity distribution shown by the dashed line is imaged at the same position in the X-axis direction. However, at positions away from the optical path axis A, light of different wavelengths is imaged at different positions in the X-axis direction. Therefore, the light intensity distribution, shown by the solid line, resulting from the combination of these wavelengths is elongated in the X-axis direction. If the critical dimension is the width of the area exposed to light intensity I equal to or greater than threshold Ith, then critical dimension CD2 at positions away from the optical path axis A is larger than critical dimension CD1 at position 0 on the optical path axis A. Furthermore, at positions away from the optical path axis A, the slope of light intensity I near threshold Ith becomes gentler. As a result, the contrast of the optical image formed on the photosensitive substrate decreases at positions away from the optical path axis A.

[0092] A decrease in contrast may result in a worsening of line edge roughness (LER) in a pattern formed by development after exposure. Figure 19 shows the measurement points for dimensions used to calculate line edge roughness. Line edge roughness is evaluated, for example, by the root mean square (RMS) of the deviation from the ideal center line CL to the edge, and the greater the variation, the larger the value. Therefore, it is desirable for line edge roughness to be small. Line edge roughness may be evaluated by the width of the pattern instead of the deviation from the ideal center line CL to the edge, and may be evaluated by the standard deviation instead of the root mean square. An index evaluated by the width of the pattern is sometimes called line width roughness (LWR), and this is collectively referred to as line edge roughness in this specification.

[0093] The embodiments described below relate to suppressing the deterioration of line edge roughness caused by chromatic aberration of magnification when exposure is performed using multiple wavelengths.

[0094] 2. Control of LER by temperature distribution during post-exposure baking 2.1 Operation 20 is a flowchart showing the process of forming a resist pattern on a photosensitive substrate in Embodiment 1. Fig. 20 mainly shows the process of the developing apparatus 300, but also includes the process of the exposure apparatus 200 in part.

[0095] In S1a, the development control processor 310 sets a temperature distribution for post-exposure baking. The temperature distribution for post-exposure baking is a temperature distribution with a temperature gradient in the X-axis direction in each scan field SF. Details of the processing in S1a will be described later with reference to FIG. 22. S3 and S4 following S1a are similar to those described with reference to FIG.

[0096] In S5a, the development control processor 310 controls the processing unit 302 to post-expose bake the photosensitive substrate with a set temperature distribution and supply a developer to the surface of the photosensitive substrate. Details of S5a will be described later with reference to FIG. S6 and S7 following S5a are similar to those described with reference to FIG.

[0097] 2.1.1 Post-exposure bake Fig. 21 is a flowchart showing the details of the process of post-exposure baking a photosensitive substrate with a set temperature distribution and supplying a developer. The process shown in Fig. 21 corresponds to the subroutine S5a in Fig. 20, and is similar to that described with reference to Fig. 3, except that instead of setting the temperature of the entire hot plate, a temperature distribution with a temperature gradient in the X-axis direction is set.

[0098] 2.1.2 Temperature distribution setting Fig. 22 is a flowchart showing the details of the process for setting the temperature distribution for post-exposure baking. The process shown in Fig. 22 corresponds to the subroutine of S1a in Fig. 20. The temperature distribution for post-exposure baking may be set in advance according to a combination of the mask pattern, resist type, exposure conditions, etc., and the necessary setting data may be read out in S5a.

[0099] Before the development control processor 310 sets the temperature distribution, the exposure control processor 210 controls each component of the exposure apparatus 200 in S11 to expose imax PEB test wafers to pulsed laser light having multiple center wavelengths through a PEB test mask. The PEB test mask may be specially designed for setting the temperature distribution for post-exposure baking, or may be similar to the photomask used in S4 of FIG. 20. Each of the imax PEB test wafers is similar to the photosensitive substrate used in S4 of FIG. 20, and the exposure apparatus 200 scans each of the multiple scan fields SF in the Y-axis direction. The number of imax wafers may be, for example, between 3 and 10. The PEB test mask corresponds to the first test mask in this disclosure, and the PEB test wafer corresponds to the first test wafer in this disclosure.

[0100] In S12, the development control processor 310 controls the processing unit 302 to post-expose bake each of the imax PEB test wafers and supply a developer to the surface of the PEB test wafer. Details of S12 will be described later with reference to FIG.

[0101] In S13, the development control processor 310 controls the measurement unit 303 to measure the wafer patterns of the imax PEB test wafers that have been developed. Details of S13 will be described later with reference to FIG.

[0102] In S15, the development control processor 310 sets the temperature distribution based on the measurement results. Details of S15 will be described later with reference to FIG. After S15, the development control processor 310 ends the processing of this flowchart and returns to the processing shown in FIG.

[0103] 23 is a flowchart showing the details of the process of post-exposure baking and supplying a developer to each of imax PEB test wafers. The process shown in FIG. 23 corresponds to the subroutine of S12 in FIG. In S121, the development control processor 310 sets a counter i to 1 for counting imax PEB test wafers. The imax PEB test wafers are heated at different temperatures T1 to Timax. The temperature of the hot plate for heating the i-th PEB test wafer WFi is the i-th temperature Ti. The temperatures T1 to Timax are set at predetermined temperature intervals centered around a nominal temperature Tnom. The nominal temperature Tnom is the optimal temperature for post-exposure baking derived without consideration of lateral chromatic aberration, and corresponds to the reference temperature in this disclosure. The predetermined temperature interval is, for example, 2°C or more and 10°C or less.

[0104] In S122, the development control processor 310 sets the temperature of the hot plate to the i-th temperature Ti. In S123, the development control processor 310 controls the hot plate to have a uniform temperature distribution of temperature Ti, and controls the processing unit 320 to heat the i-th PEB test wafer WFi for a predetermined time. In S124, the development control processor 310 controls the processing unit 320 to supply the developer to the surface of the i-th PEB test wafer WFi.

[0105] In S125, the development control processor 310 determines whether the value of counter i has reached imax. If the value of counter i has not reached imax (S125: NO), the development control processor 310 adds 1 to the value of counter i in S126 and returns the process to S122. This causes the next PEB test wafer to be post-exposed baked at another temperature Ti and developed. If the value of the counter i reaches imax (S125: YES), the development control processor 310 ends the processing of this flowchart and returns to the processing shown in FIG.

[0106] 24 shows PEB test wafers WF1 to WF4 and temperatures Ti set for post-exposure baking of the PEB test wafers WF1 to WF4. Only one value of temperature Ti is set for each PEB test wafer WFi.

[0107] 25 is a flowchart showing the details of the process for measuring the wafer patterns of imax PEB test wafers that have been developed. The process shown in FIG. 25 corresponds to the subroutine of S13 in FIG.

[0108] In S131, the development control processor 310 sets a counter i to 1 for counting imax PEB test wafers. In S132, the development control processor 310 controls the wafer moving unit 301 to set the ith PEB test wafer WFi in the measurement unit 303.

[0109] In S133, the development control processor 310 sets a counter k to 1 for counting the scan fields SF.

[0110] In S134, the development control processor 310 controls the measurement unit 303 to measure the line edge roughness LERcik and the critical dimension CDcik at the center in the X-axis direction of the kth scan field SFk of the i-th PEB test wafer WFi. In S135, the development control processor 310 controls the measurement unit 303 to measure the line edge roughness LERpik and the critical dimension CDpik of the end portion in the X-axis direction of the kth scan field SFk of the i-th PEB test wafer WFi. The position of the end portion in the X-axis direction of the scan field SFk corresponds to the first position in this disclosure.

[0111] In S136, the development control processor 310 determines whether the value of counter k has reached kmax. If the value of counter k has not reached kmax (S136: NO), the development control processor 310 adds 1 to the value of counter k in S137 and returns the process to S134. If the value of counter k has reached kmax (S136: YES), the development control processor 310 proceeds to the process in S138.

[0112] In S138, the development control processor 310 calculates and stores the average values ​​LERci, CDci, LERpi, and CDpi of the measurement results for each PEB test wafer WFi and for each position within the scan field using the following equations. LERci=Avg(LERcik) CDci=Avg(CDcik) LERpi=Avg(LERpik) CDpi=Avg(CDpik) Here, Avg(Xik) is the average value of kmax Xik values.

[0113] In S139, the development control processor 310 determines whether the value of counter i has reached imax. If the value of counter i has not reached imax (S139: NO), the development control processor 310 adds 1 to the value of counter i in S140 and returns the process to S132. If the value of counter i has reached imax (S139: YES), the development control processor 310 proceeds to the process in S141.

[0114] In S141, the development control processor 310 identifies the average value LERci of the line edge roughness LERcik at the center in the X-axis direction of the scan field SF included in the PEB test wafers baked after exposure at the nominal temperature Tnom among the imax PEB test wafers as the reference LERc. After S141, the development control processor 310 ends the processing of this flowchart and returns to the processing shown in FIG.

[0115] 26 conceptually shows the area in the kth scan field SFk where the line edge roughness LERcik and LERpik and the critical dimensions CDcik and CDpik are measured. The line edge roughness LERcik and the critical dimension CDcik are obtained from the measurement results of the center of the kth scan field SFk in the X-axis direction, and the line edge roughness LERpik and the critical dimension CDpik are obtained from the measurement results of the end of the kth scan field SFk in the X-axis direction.

[0116] 27 shows a table summarizing the average values ​​LERci, CDci, LERpi, and CDpi. A temperature Ti is set for each PEB test wafer WFi. The temperature Ti includes the nominal temperature Tnom. The average values ​​LERci, CDci, LERpi, and CDpi of the measurement results are calculated for each PEB test wafer WFi and for each position within the scan field.

[0117] 28 is a flowchart showing the details of the process for setting the temperature distribution based on the measurement results. The process shown in FIG. 28 corresponds to the subroutine of S15 in FIG. In S151, the development control processor 310 sets a counter i to 1 for counting imax PEB test wafers.

[0118] In S152, the development control processor 310 determines whether the average value LERpi of the line edge roughness LERpik at the end of the i-th PEB test wafer WFi in the X-axis direction is within the allowable range. If the difference between the average value LERpi and the reference LERc is equal to or less than a threshold, the average value LERpi is determined to be within the allowable range. In S153, the development control processor 310 determines whether the average value CDpi of the critical dimensions CDpik at the end in the X-axis direction of the i-th PEB test wafer WFi is within the allowable range.

[0119] If either the average value LERpi or the average value CDpi is outside the allowable range (S152 or S153: NO), the development control processor 310 adds 1 to the value of the counter i in S154 and returns the process to S152. If both the average values ​​LERpi and CDpi are within the allowable ranges (S152 and S153: YES), the development control processor 310 proceeds to S155.

[0120] In S155, the development control processor 310 sets the temperature Tc at the center in the X-axis direction of all scan fields SF to the nominal temperature Tnom. In S156, the development control processor 310 sets the temperature Tp of the X-axis end portions of all scan fields SF to the temperature Ti. After S156, the development control processor 310 ends the processing of this flowchart and returns to the processing shown in FIG.

[0121] 27, when the nominal temperature Tnom is temperature T4, the reference LERc is the average value LERc4. If the difference between the average value LERc4 and the average value LERp2 is equal to or less than the threshold value and the average value CDp2 is within the allowable range, both the average values ​​LERpi and CDpi are determined to be within the allowable range, and the temperature Tp at the end in the X-axis direction is set to temperature T2.

[0122] Figure 29 shows an example of the temperature distribution in the X-axis direction set in the first embodiment. The horizontal axis of Figure 29 represents the position in the X-axis direction within the scan field SF, and the vertical axis represents the temperature. A temperature Tc is set at the center c in the X-axis direction, and a temperature Tp is set at an end p in the X-axis direction, and the temperature distribution in the X-axis direction is set so that there is a gentle temperature gradient between the center c in the X-axis direction and the end p in the X-axis direction.

[0123] The temperature conditions for post-exposure baking change the diffusion length of the catalytic acid and also change the rate of the acid-catalyzed chemical reaction. By setting the temperature conditions so that the average LERpi and average CDpi are within the allowable range, it is possible to adjust the line edge roughness and improve the quality of the pattern formed on the photosensitive substrate.

[0124] Here, the case where the temperature Tc is higher than the temperature Tp is shown, but as a result of setting the optimum temperature by the processing of FIG. 28, the temperature Tc may be lower than the temperature Tp.

[0125] Figure 30 shows an example of the temperature distribution in the Y-axis direction set in the first embodiment. The horizontal axis of Figure 30 represents the position in the Y-axis direction within the scan field SF, and the vertical axis represents the temperature. At the center c of the X-axis direction, a constant temperature Tc is set regardless of the position in the Y-axis direction, and at the end p of the X-axis direction, a constant temperature Tp is set regardless of the position in the Y-axis direction. Note that a constant temperature regardless of the position in the Y-axis direction does not only mean that the temperature distribution in the Y-axis direction of the photosensitive substrate is uniform, but also means that the target temperature is uniform.

[0126] As shown in FIGS. 29 and 30, the temperature distribution in each scan field SF is such that the temperature gradient in the Y-axis direction is smaller than the temperature gradient in the X-axis direction.

[0127] 31 shows a first example of the temperature distribution set in the first embodiment. In this first example, multiple scan fields SF are arranged in a rectangular grid. That is, the boundaries of the scan fields SF intersect at the corners of the scan fields SF in a crisscross pattern. The rectangular grid includes a square grid. In each scan field SF, a temperature Tc at the center in the X-axis direction and a temperature Tp at the end in the X-axis direction are set, and a gentle temperature gradient is created between the center and the end in the X-axis direction.

[0128] 32 shows a second example of the temperature distribution set in the first embodiment. In the second example, multiple scan fields SF are arranged, shifted in the X-axis direction by one row. In each scan field SF, a temperature Tc at the center in the X-axis direction and a temperature Tp at the end in the X-axis direction are set, and a gentle temperature gradient is set between the center and the end in the X-axis direction. In the second example, the temperature gradient at the boundary between adjacent scan fields SF in the Y-axis direction becomes larger.

[0129] In both Figures 31 and 32, the temperature distributions in the multiple scan fields SF are equal to each other. When setting either the temperature distribution of Figure 31 or Figure 32, the development control processor 310 may separately obtain the placement data of the scan field SF on the photosensitive substrate and set the temperature distribution to match the placement data of the scan field SF. Although the temperature distribution in the X-axis direction is shown as being symmetrical about a line parallel to the Y-axis direction, it does not have to be symmetrical. For example, the temperature Tp may be set separately at the end in the +X direction and the end in the -X direction.

[0130] 2.2 Effect (1) A method for developing a photosensitive substrate according to a first embodiment includes the following steps: The photosensitive substrate is exposed by scanning each of multiple scan fields SF contained in the photosensitive substrate in the Y-axis direction with pulsed laser light containing multiple central wavelengths through a photomask, and then heated so that a temperature distribution with a temperature gradient in the X-axis direction that intersects the Y-axis direction on the surface of the photosensitive substrate is obtained in each of the multiple scan fields SF. After the photosensitive substrate is heated, a developer is supplied to the surface of the photosensitive substrate to perform development. According to this, even if chromatic aberration of magnification occurs when exposing using multiple wavelengths, by providing a temperature gradient in the X-axis direction in the temperature distribution of the post-exposure bake, it is possible to adjust the line edge roughness and improve the quality of the pattern formed on the photosensitive substrate.

[0131] (2) In the first embodiment, the photosensitive substrate is heated so that the temperature gradient in the Y-axis direction is smaller than the temperature gradient in the X-axis direction in each of the plurality of scan fields SF. Because the shape of the beam cross section B of the pulsed laser light at the position of the workpiece table WT (see Figure 1) is long in the X-axis direction, the lateral chromatic aberration occurs more significantly in the X-axis direction than in the Y-axis direction. By increasing the temperature gradient in the X-axis direction and performing post-exposure baking with a temperature distribution that corresponds to the position in the X-axis direction, it is possible to appropriately adjust the line edge roughness.

[0132] (3) In the first embodiment, the photosensitive substrate is heated so as to have a uniform temperature distribution in the Y-axis direction in each of the multiple scan fields SF. The chromatic aberration of magnification in the Y-axis direction is not large, and even if there is aberration, it is averaged out by irradiating one location multiple times while scanning in the Y-axis direction. Therefore, by performing post-exposure baking with a uniform temperature distribution in the Y-axis direction, it is possible to appropriately adjust the line edge roughness.

[0133] (4) In the first embodiment, the photosensitive substrate is heated in each of the plurality of scan fields SF so as to have a symmetrical temperature distribution with respect to a straight line parallel to the Y-axis direction as an axis. Since lateral chromatic aberration can occur symmetrically with respect to a line parallel to the Y-axis direction, line edge roughness can be appropriately adjusted by performing post-exposure baking with a symmetric temperature distribution.

[0134] (5) According to the first embodiment, the temperature distributions in the multiple scan fields SF are equal to each other. This makes it possible to appropriately adjust the line edge roughness when the exposure conditions of a plurality of scan fields SF are the same.

[0135] (6) In the first embodiment, multiple scan fields SF are arranged in a rectangular grid. This makes it possible to make the temperature gradient at the boundary with the adjacent scan field SF in the Y-axis direction gentler, and to perform post-exposure baking with an appropriate temperature distribution.

[0136] (7) In the first embodiment, the photosensitive substrate is heated by a hot plate set to have a temperature gradient in the X-axis direction. According to this, by setting the temperature gradient of the hot plate, the temperature distribution of the post-exposure bake can be appropriately controlled.

[0137] (8) The method for developing a photosensitive substrate according to the first embodiment further includes the following. The exposed PEB test wafer WFi is heated by scanning each of the plurality of scan fields SF included in the PEB test wafer WFi in the Y-axis direction with pulsed laser light having a plurality of center wavelengths via a PEB test mask. After the PEB test wafer WFi is heated, a developer is supplied to the surface of the PEB test wafer WFi to perform development. After the PEB test wafer WFi is developed, the wafer pattern of the PEB test wafer WFi is measured. The temperature distribution is set based on the measurement results of the wafer pattern of the PEB test wafer WFi. According to this, by using the measurement results of the wafer pattern, the temperature distribution can be appropriately set.

[0138] (9) In the first embodiment, a plurality of PEB test wafers including the PEB test wafer WFi are heated at temperatures Ti different from each other. This allows an appropriate temperature to be set by using the results of post-exposure baking at different temperatures Ti.

[0139] (10) In the first embodiment, each of the multiple PEB test wafers is heated to have a uniform temperature distribution. This allows for accurate temperature control during post-exposure baking of the PEB test wafer WFi, making the data showing the relationship between the post-exposure baking temperature and the wafer pattern measurement results more accurate, and allowing the temperature distribution to be set appropriately.

[0140] (11) In the first embodiment, the average values ​​LERci, CDci, LERpi, and CDpi of the measurement results of the wafer pattern of the PEB test wafer WFi are calculated for each temperature Ti and for each position in the X-axis direction in each scan field SF, and the temperature distribution in the X-axis direction is set based on the average values ​​LERci, CDci, LERpi, and CDpi. According to this, even if there is a slight variation in the measurement results, accurate measurement data can be obtained by using the average values ​​LERci, CDci, LERpi, or CDpi.

[0141] (12) In the first embodiment, the temperature at which the measurement results of the wafer pattern of the PEB test wafer WFi fall within the allowable range at the end position in the X-axis direction away from the center in the X-axis direction in each scan field SF is identified, and the temperature distribution is set based on the identified temperature. This allows an appropriate temperature distribution to be set according to the position in the X-axis direction in the scan field SF.

[0142] (13) In the first embodiment, the measurement results of the wafer pattern of the PEB test wafer WFi include the average value LERpi of the line edge roughness at the end positions in the X-axis direction, and the temperature distribution is specified so that the average value LERpi is within the allowable range. According to this method, the temperature distribution for post-exposure baking is set after actually measuring the line edge roughness, so that the line edge roughness can be improved with high precision.

[0143] (14) In the first embodiment, when the PEB test wafer WFi is heated and developed at the nominal temperature Tnom, if the difference between the reference LERc at the center in the X-axis direction and the average value LERpi of the line edge roughness at the end positions in the X-axis direction is equal to or less than a threshold value, the average value LERpi at the end positions in the X-axis direction is determined to be within the allowable range. According to this, by determining the difference from the reference LERc, the line edge roughness at the end portion in the X-axis direction can be made closer to that at the center portion in the X-axis direction.

[0144] (15) In the first embodiment, the measurement results of the wafer pattern of the PEB test wafer WFi further include the average value CDpi of the critical dimension at the end position in the X-axis direction, and the temperature distribution is specified so that both the average value LERpi of the line edge roughness at the end position in the X-axis direction and the average value CDpi of the critical dimension are within the allowable range. This makes it possible to improve both line edge roughness and critical dimension. In other respects, the first embodiment is similar to the comparative example.

[0145] 3. Post-exposure bake temperature distribution and combination with OPC 3.1 Operation 33 is a flowchart showing the process of forming a resist pattern on a photosensitive substrate in the second embodiment. Fig. 33 mainly shows the process of the developing apparatus 300, but also includes the process of the exposure apparatus 200 in part.

[0146] The process of setting the temperature distribution in S1a is similar to the process of the first embodiment described with reference to Figures 20 and 22. However, the second embodiment differs from the first embodiment in the following points. (a) In the first embodiment, in S13 of FIG. 22 and S134, S135, and S138 of FIG. 25, the critical dimensions CDcik and CDpik are measured as the wafer pattern and their average values ​​CDci and CDpi are calculated, whereas in the second embodiment, the critical dimensions CDcik and CDpik are not measured and the average values ​​CDci and CDpi are not calculated. (b) In the first embodiment, in S15 of FIG. 22 and S153 of FIG. 28, it is determined whether the average value CDpi of the critical dimension is within the allowable range, whereas in the second embodiment, it is not determined whether the average value CDpi of the critical dimension is within the allowable range.

[0147] Details of the processes of S13 and S15 in the second embodiment are respectively shown in Figures 34 and 35. Figure 34 corresponds to Figure 25 in the first embodiment, and Figure 35 corresponds to Figure 28 in the first embodiment. As shown in FIG. 34, the development control processor 310 measures only the line edge roughness LERcik and LERpik in S134b and S135b, and calculates the average values ​​LERci and LERpi in S138b. As shown in FIG. 35, the development control processor 310 determines in S152 whether the average value LERpi of the line edge roughness is within the allowable range.

[0148] 33 again, in S2b, a photomask is created by OPC. By performing OPC, it is possible to bring the critical dimension within an allowable range. Details of S2b will be described later with reference to FIGS. 36 to 41. The processes from S3 to S7 are the same as those in the first embodiment.

[0149] 36 is a conceptual diagram of the divided model-based OPC in the second embodiment. The divided model-based OPC differs from the model-based OPC in the comparative example in that a target pattern G, a test mask pattern E, a measurement wafer pattern D, a model function group M, an OPC recipe P, and a correction mask pattern F are each created for each of a plurality of divided regions #1 to #n, and the model-based OPC is performed for each of the divided regions #1 to #n.

[0150] 37 shows multiple divided areas #1 to #n included in the scan field SF of the OPC test wafer. n is an integer of 2 or greater, and multiple divided areas #1, #2, ..., and #n are arranged in this order in the X-axis direction on the surface of the OPC test wafer. It is desirable that the widths of divided areas #1 to #n in the X-axis direction are equal to each other. The number of divided areas #1 to #n, i.e., the value of n, is desirable to be 3 or greater and 15 or less.

[0151] Referring again to FIG. 36, the measurement wafer pattern D obtained from the scan field SF of the OPC test wafer is divided into measurement wafer patterns D#1 to D#n corresponding to the division areas #1 to #n.

[0152] One scan field SF included in the OPC test wafer corresponds to an area where a test mask pattern E formed on one OPC test mask is transferred in one scan, and corresponds to the OPC test mask. The test mask pattern E is also divided into test mask patterns E#1 to E#n corresponding to divided areas #1 to #n.

[0153] One scan field SF included in the OPC test wafer corresponds to one scan field SF included in the photosensitive substrate. The target pattern G to be formed on the photosensitive substrate is also divided into target patterns G#1 to G#n corresponding to the divided areas #1 to #n.

[0154] One scan field SF included in the photosensitive substrate corresponds to the area to which the correction mask pattern F of one photomask is transferred in one scan, and corresponds to the photomask. The correction mask pattern F is also divided into correction mask patterns F#1 to F#n corresponding to the divided areas #1 to #n.

[0155] In the divided model-based OPC, model function groups M#1 to M#n corresponding to the divided regions #1 to #n are created, and OPC recipes P#1 to P#n corresponding to the divided regions #1 to #n are created.

[0156] 38 is a flowchart of the division model-based OPC. The processing shown in FIG. 38 is mainly performed by a processor such as the exposure control processor 210.

[0157] In S210a, the processor acquires target patterns G#1 to G#n. For example, the processor acquires target patterns G#1 to G#n by dividing a target pattern G designed by a semiconductor chip designer into divided regions #1 to #n.

[0158] The process of S220 is the same as the process in the model-based OPC described with reference to FIG.

[0159] In S230a, the processor creates test mask patterns E#1-E#n based on target patterns G#1-G#n. For example, test mask pattern E#1 may be created based on the characteristic shape included in target pattern G#1, test mask pattern E#2 may be created based on the characteristic shape included in target pattern G#2, and so on. In this way, different test mask patterns E#1-E#n may be created for divided regions #1-#n. Alternatively, a common test mask pattern, i.e., test mask patterns E#1-E#n including the same pattern shape, may be created based on the characteristic shapes included in target patterns G#1-G#n. An OPC test mask is created by a mask manufacturing device according to the test mask patterns E#1 to E#n.

[0160] In S240a, the OPC test wafer is exposed by scanning it through the OPC test mask by exposure tool 200. The OPC test wafer is exposed to light of multiple wavelengths that is used to expose a photosensitive substrate.

[0161] In S242a, the processor controls the processing unit 302 to post-exposure bake the OPC test wafer with the temperature distribution set in S1a of FIG. 33 and to supply a developer to the surface of the OPC test wafer. Furthermore, the developed photosensitive substrate is washed, dried, and baked after development, and if etching is to be performed, an etching device (not shown) performs etching to pattern the OPC test wafer.

[0162] In S250a, the processor measures the wafer pattern of the OPC test wafer and acquires measurement wafer patterns D#1 to D#n that indicate the measurement results in a plurality of divided areas #1 to #n. The data structure of measurement wafer patterns D#1 to D#n is shown in Fig. 39. Each of measurement wafer patterns D#1 to D#n includes p dimensions measured for each of m shapes 1 to m. When multiple scan fields SF included in an OPC test wafer are test exposed using one OPC test mask, average values ​​are calculated for each divided area, shape, and dimension from the measurement results in the multiple scan fields SF, and these are used as measurement wafer patterns D#1 to D#n.

[0163] 38 again, in S260a, the processor creates model function sets M#1 to M#n based on test mask patterns E#1 to E#n and measurement wafer patterns D#1 to D#n. For example, model function set M#1 is created based on test mask pattern E#1 and measurement wafer pattern D#1, and model function set M#2 is created based on test mask pattern E#2 and measurement wafer pattern D#2.

[0164] 40 is a flowchart showing the details of the process for creating model function groups M#1 to M#n. The process shown in FIG. 40 corresponds to the subroutine of S260a in FIG.

[0165] In S262a, the processor performs an exposure simulation using test mask patterns E#1 to E#n. The exposure simulation may be performed using light with fewer central wavelengths than the pulsed laser light having multiple central wavelengths scanned over the OPC test wafer. It is preferable to perform the exposure simulation using a single wavelength.

[0166] In S263a, the value of counter j is set to an initial value of 1. Counter j identifies one of the model function groups M#1 to M#n, as well as one of the test mask patterns E#1 to E#n and one of the measurement wafer patterns D#1 to D#n.

[0167] The processing of S264a to S267a is the same as the processing of S264 to S267 described with reference to Fig. 16. However, one of the model function groups M#1 to M#n specified by counter j is created using the exposure simulation results using one of the test mask patterns E#1 to E#n specified by counter j and one of the measurement wafer patterns D#1 to D#n specified by counter j. When the determination of S266a is YES and one of the model function groups M#1 to M#n is created, the processor proceeds to S268a.

[0168] In S268a, the processor determines whether the value of counter j is greater than or equal to n. If the value of counter j is less than n (S268a: NO), the processor increments the value of counter j by 1 in S269a, and returns to S264a to set a model function set M#j for another divided region. If the value of counter j is greater than or equal to n, the processor ends the processing of this flowchart and returns to the processing shown in FIG.

[0169] An example of model function groups M#1 to M#n is shown in Fig. 41. When one of the model function groups M#1 to M#n is specified by j, one model function group M#j is made up of k functions M#j1 to M#j. k Contains functions M#j1~M#j k The number of functions, that is, the value of k, may be different among the model function groups M#1 to M#n.

[0170] Referring again to FIG. 38, in S270a, the processor creates OPC recipes P#1 to P#n based on the model function groups M#1 to M#n, respectively.

[0171] In S280a, the processor executes OPC recipes P#1 to P#n using target patterns G#1 to G#n, respectively, to create corrected mask patterns F#1 to F#n, respectively. As a result, for example, corrected mask pattern F#1 is created based on target pattern G#1 and model function group M#1, and corrected mask pattern F#2 is created based on target pattern G#2 and model function group M#2. In S310a, the mask manufacturing equipment creates a photomask based on the corrected mask patterns F#1 to F#n, and the process of this flowchart ends.

[0172] 3.2 Effect

[0173] (16) A method for producing a photomask according to a second embodiment is a method for producing a photomask used in photolithography using a pulsed laser beam having a plurality of center wavelengths, and includes the following steps. The OPC test wafer is exposed by scanning it in the Y-axis direction with pulsed laser light through an OPC test mask, and the surface of the OPC test wafer is heated so as to have a temperature distribution with a temperature gradient in the X-axis direction that intersects with the Y-axis direction on the surface of the OPC test wafer in each of a plurality of scan fields SF included in the OPC test wafer. A developer is supplied to the surface of the OPC test wafer, and the developed wafer pattern on the OPC test wafer is measured, and measurement wafer patterns D#1 to D#n that show the measurement results in each of a plurality of divided areas #1 to #n aligned in the X-axis direction are obtained. Correction mask patterns F#1 to F#n for producing a photomask are created based on test mask patterns E#1 to E#n formed on the OPC test mask, measurement wafer patterns D#1 to D#n, and target patterns G#1 to G#n which are the target wafer patterns for the photosensitive substrate. A photomask is created based on the corrected mask patterns F#1 to F#n. According to this, by using the measurement results for each of the divided regions #1 to #n, OPC that takes off-axis chromatic aberration into consideration can be performed to create corrected mask patterns F#1 to F#n. In the first embodiment, the temperature distribution of the post-exposure bake is set so that both the line edge roughness and the critical dimension are within the allowable range, but it may not be possible to obtain a solution in which both the line edge roughness and the critical dimension are within the allowable range. According to the second embodiment, the line edge roughness is adjusted by the temperature distribution of the post-exposure bake, while the critical dimension can be adjusted by the OPC for each of the divided regions #1 to #n.

[0174] (17) The method for producing a photomask according to the second embodiment further includes the following. The exposed PEB test wafer WFi is heated by scanning each of the plurality of scan fields SF included in the PEB test wafer WFi in the Y-axis direction with pulsed laser light having a plurality of center wavelengths via a PEB test mask. After the PEB test wafer WFi is heated, a developer is supplied to the surface of the PEB test wafer WFi to perform development. After the PEB test wafer WFi is developed, the wafer pattern of the PEB test wafer WFi is measured. The temperature distribution is set based on the measurement results of the wafer pattern of the PEB test wafer WFi. According to this, the temperature distribution for post-exposure baking of the OPC test wafer can be set based on the measurement results of the wafer pattern of the PEB test wafer WFi, so that the OPC test wafer can be created with high accuracy.

[0175] (18) In the second embodiment, the temperature distribution is specified so that the average value of line edge roughness LERpi at the end positions in the X-axis direction away from the center of the X-axis direction in each scan field SF is within the allowable range, and corrected mask patterns F#1 to F#n are created so that the critical dimension at the end positions in the X-axis direction is within the allowable range. This makes it possible to improve both the line edge roughness and the critical dimension at the end positions in the X-axis direction.

[0176] (19) A method for developing a photosensitive substrate according to a second embodiment includes the following steps: A photomask is created using the above-described method including OPC that takes into account off-axis chromatic aberration. The photosensitive substrate is scanned in the Y-axis direction with pulsed laser light containing multiple central wavelengths via a photomask, and the exposed photosensitive substrate is then heated to a set temperature distribution. After the photosensitive substrate is heated, a developer is supplied to the surface of the photosensitive substrate to perform development. This allows a pattern to be formed on a photosensitive substrate with high precision.

[0177] In the second embodiment, a case has been described in which model-based OPC is executed for each of the divided regions #1 to #n, but the present disclosure is not limited to this, and for example, rule-based OPC may be executed for each of the divided regions #1 to #n. In other respects, the second embodiment is similar to the first embodiment.

[0178] 4.Other The above description is intended to be illustrative rather than limiting. Thus, it will be apparent to one skilled in the art that modifications can be made to the disclosed embodiments without departing from the scope of the claims. It will also be apparent to one skilled in the art that the disclosed embodiments can be used in combination.

[0179] Terms used throughout this specification and claims should be construed as "open ended" terms unless expressly stated otherwise. For example, the terms "include" or "including" should be construed as "not limited to what is stated as including." The term "having" should be construed as "not limited to what is stated as having." The indefinite article "a" should be construed as "at least one" or "one or more." The term "at least one of A, B, and C" should be construed as "A," "B," "C," "A+B," "A+C," "B+C," or "A+B+C." It should also be construed to include combinations other than "A," "B," and "C."

Claims

1. heating the photosensitive substrate, which has been exposed by scanning each of a plurality of scan fields included in the photosensitive substrate in a first direction with pulsed laser light having a plurality of center wavelengths via a photomask, so that a temperature distribution having a temperature gradient in a second direction intersecting with the first direction is obtained on the surface of the photosensitive substrate in each of the plurality of scan fields; After heating the photosensitive substrate, a developer is supplied to the surface of the photosensitive substrate to perform development; A method for developing a photosensitive substrate, comprising:

2. 2. The developing method according to claim 1, heating the photosensitive substrate so that the temperature distribution in each of the plurality of scan fields has a temperature gradient in the first direction that is smaller than a temperature gradient in the second direction; Development method.

3. 2. The developing method according to claim 1, heating the photosensitive substrate so as to achieve a uniform temperature distribution in the first direction in each of the plurality of scan fields; Development method.

4. 2. The developing method according to claim 1, heating the photosensitive substrate so that the temperature distribution is symmetrical with respect to a straight line parallel to the first direction in each of the plurality of scan fields; Development method.

5. 2. The developing method according to claim 1, The temperature distributions in the plurality of scan fields are equal to each other. Development method.

6. 2. The developing method according to claim 1, the plurality of scan fields are arranged in a rectangular grid; Development method.

7. 2. The developing method according to claim 1, heating the photosensitive substrate by a hot plate set to have a temperature gradient in the second direction; Development method.

8. 2. The developing method according to claim 1, heating the exposed first test wafer by scanning each of a plurality of scan fields included in the first test wafer in the first direction with pulsed laser light including the plurality of center wavelengths through a first test mask; After heating the first test wafer, supplying a developer to the surface of the first test wafer to perform development; measuring a wafer pattern of the first test wafer after developing the first test wafer; setting the temperature distribution based on a measurement result of a wafer pattern of the first test wafer; The developing method further comprises:

9. 9. The developing method according to claim 8, heating a plurality of first test wafers including the first test wafer at temperatures different from each other; Development method.

10. The developing method according to claim 9, heating each of the plurality of first test wafers to achieve a uniform temperature distribution; Development method.

11. The developing method according to claim 9, calculating an average value of measurement results of the wafer pattern of the first test wafer for each temperature and for each position in the second direction in each of the scan fields, and setting the temperature distribution in the second direction based on the average value; Development method.

12. The developing method according to claim 11, identifying the temperature at which the measurement result of the wafer pattern of the first test wafer falls within an allowable range at a first position away from the center in the second direction in each of the scan fields, and setting the temperature distribution based on the identified temperature; Development method.

13. The developing method according to claim 12, a measurement result of the wafer pattern of the first test wafer includes line edge roughness at the first position, and the temperature distribution is specified so that the line edge roughness at the first position falls within an allowable range. Development method.

14. The developing method according to claim 13, when a difference between the line edge roughness at the center in the second direction when the first test wafer is heated and developed at a reference temperature and the line edge roughness at the first position is equal to or less than a threshold value, the line edge roughness at the first position is determined to be within an acceptable range. Development method.

15. The developing method according to claim 13, the measurement result of the wafer pattern of the first test wafer further includes a critical dimension at the first position, and the temperature distribution is specified so that both the line edge roughness at the first position and the critical dimension are within an allowable range. Development method.

16. A method for producing a photomask used in photolithography using pulsed laser light having a plurality of center wavelengths, comprising: a second test wafer exposed by scanning the second test wafer in a first direction with a pulsed laser beam through a second test mask, the second test wafer heated to have a temperature distribution with a temperature gradient in a second direction intersecting the first direction on the surface of the second test wafer in each of a plurality of scan fields included in the second test wafer, and a developed wafer pattern of the second test wafer measured by supplying a developer to the surface of the second test wafer, and acquiring a measurement wafer pattern showing the measurement results in each of a plurality of divided regions aligned in the second direction; creating a correction mask pattern for producing the photomask based on the test mask pattern formed on the second test mask, the measurement wafer pattern, and a target pattern which is a target wafer pattern on a photosensitive substrate; creating the photomask based on the corrected mask pattern; Including, how to make.

17. 17. The method of claim 16, heating the exposed first test wafer by scanning each of a plurality of scan fields included in the first test wafer in the first direction with pulsed laser light including the plurality of center wavelengths through a first test mask; After heating the first test wafer, supplying a developer to the surface of the first test wafer to perform development; measuring a wafer pattern of the first test wafer after developing the first test wafer; setting the temperature distribution based on a measurement result of a wafer pattern of the first test wafer; The method of making further includes:

18. 17. The method of claim 16, setting the temperature distribution so that line edge roughness at a first position away from a center in the second direction in each of the scan fields falls within an allowable range; creating the corrected mask pattern so that the critical dimension at the first position is within an allowable range; How to create it.

19. creating the photomask by the method of claim 16; scanning the photosensitive substrate in the first direction with pulsed laser light having a plurality of center wavelengths via the photomask, and heating the exposed photosensitive substrate so as to achieve the temperature distribution; After heating the photosensitive substrate, a developer is supplied to the surface of the photosensitive substrate to perform development; A method for developing a photosensitive substrate, comprising:

20. A method for manufacturing an electronic device, comprising: generating pulsed laser light including a plurality of center wavelengths by a laser device; outputting the pulsed laser light to an exposure device; In the exposure device, scanning and exposing each of a plurality of scan fields included in a photosensitive substrate with the pulsed laser light through a photomask in a first direction; heating the exposed photosensitive substrate so as to have a temperature distribution having a temperature gradient in a second direction intersecting with the first direction on the surface of the photosensitive substrate in each of the plurality of scan fields; After heating the photosensitive substrate, a developer is supplied to the surface of the photosensitive substrate to perform development; A method for manufacturing an electronic device, comprising:

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