Semiconductor device and power conversion device

Abstract

To provide a technology that makes it possible to shorten the wiring length of a gate wire connecting a control IC that controls the drive of first and second semiconductor elements connected in parallel and the gate pad of the semiconductor element located far from the control IC.SOLUTION: A first semiconductor element 7 and a second semiconductor element 9 are arranged so that the long side of the first semiconductor element 7 is opposite to the side of the second semiconductor element 9, and the HVIC3 or LVIC2, the first semiconductor element 7, and the second semiconductor element 9 are arranged in this order in a direction orthogonal to the first direction, a gate pad 8 is arranged on one side of the first semiconductor element 7 in the first direction, and gate pad 10 is arranged on the other side of the second semiconductor element 9 in the first direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a power conversion device. [Background technology]

[0002] Conventionally, there is a semiconductor device in which a metal-oxide-semiconductor field-effect transistor (MOSFET) and an insulated gate bipolar transistor (IGBT) are connected in parallel as switching devices and controlled by a single drive signal (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-125806 Summary of the Invention [Problem to be solved by the invention]

[0004] In the technology described in Patent Document 1, both the IGBT and the MOSFET are formed in a rectangular shape having short sides extending in a first direction and long sides perpendicular to the first direction when viewed from above. A gate control circuit (corresponding to a control IC) that controls the driving of the MOSFET and the IGBT, the IGBT, and the MOSFET are arranged in this order in a direction perpendicular to the first direction. This increases the distance between the gate pad of the MOSFET, which is located particularly far from the gate control circuit, and the gate control circuit, and the wiring length of the gate wire connecting them increases, causing various problems.

[0005] Therefore, the present disclosure aims to provide a technology that can shorten the wiring length of the gate wire that connects a control IC that controls the operation of a first semiconductor element and a second semiconductor element that are connected in parallel to the gate pad of a semiconductor element that is located far from the control IC. [Means for solving the problem]

[0006] A semiconductor device according to the present disclosure includes a first semiconductor element and a second semiconductor element connected in parallel, a rectangular control IC that controls the operation of the first semiconductor element and the second semiconductor element and has long sides extending in a first direction in a top view, a first gate pad that is disposed on the first semiconductor element and receives a signal that controls the operation of the first semiconductor element, a second gate pad that is disposed on the second semiconductor element and receives a signal that controls the operation of the second semiconductor element, a first wire that connects the control IC and the first gate pad, and a second wire that connects the control IC and the second gate pad, wherein the first semiconductor element is formed in a rectangular shape having long sides that extend in the first direction in a top view, and the second semiconductor element has sides that extend in the first direction in a top view. square The first semiconductor element and the second semiconductor element are arranged so that the long side of the first semiconductor element faces the side of the second semiconductor element, and the control IC, the first semiconductor element, and the second semiconductor element are arranged in this order in a direction perpendicular to the first direction, with the first gate pad being arranged on one side of the first semiconductor element in the first direction and the second gate pad being arranged on the other side of the second semiconductor element in the first direction. [Effects of the Invention]

[0007] According to the present disclosure, a second gate pad is provided which connects the control IC to a second gate pad of a second semiconductor element disposed at a position far from the control IC. Nowa This allows the wiring length of the earphones to be shortened. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a top view showing an internal configuration of a semiconductor device according to a first embodiment. [Figure 2] 1 is a top view showing a part of the internal configuration of a semiconductor device according to a first embodiment. [Figure 3] 1 is a circuit diagram showing a part of a circuit configuration of a semiconductor device according to a first embodiment. [Figure 4] FIG. 1 is a circuit diagram for explaining the cause of overvoltage breakdown and malfunction caused by dV / dt of a MOSFET. [Figure 5] FIG. 1 is a circuit diagram for explaining parasitic oscillation when a MOSFET and an IGBT are driven in parallel. [Figure 6] FIG. 10 is an explanatory diagram for explaining the allowable current when the SiC-MOS and the Si-IGBT are driven by a single control signal when the chip size of the SiC-MOS is large. [Figure 7] FIG. 10 is an explanatory diagram for explaining the allowable current when the SiC-MOS and the Si-IGBT are driven by a single control signal when the chip size of the SiC-MOS is small. [Figure 8] FIG. 10 is an explanatory diagram for explaining allowable current when a SiC-MOS and a Si-IGBT are driven by individual control signals. [Figure 9] 1 is a top view showing a part of the internal configuration of a semiconductor device according to a first embodiment. [Figure 10] 1 is a side view showing a part of the internal configuration of a semiconductor device according to a first embodiment. [Figure 11] FIG. 10 is a top view showing a part of the internal configuration of a semiconductor device according to a second embodiment. [Figure 12] FIG. 10 is a side view showing a part of the internal configuration of a semiconductor device according to a second embodiment. [Figure 13] FIG. 10 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a third embodiment is applied. DETAILED DESCRIPTION OF THE INVENTION

[0009] <First Embodiment> <Configuration of semiconductor device> The first embodiment will be described below with reference to the drawings. Fig. 1 is a top view showing the internal configuration of a semiconductor device according to the first embodiment. Fig. 2 is a top view showing a part of the internal configuration of the semiconductor device according to the first embodiment. Fig. 3 is a circuit diagram showing a part of the circuit configuration of the semiconductor device according to the first embodiment.

[0010] As shown in FIG. 1, the semiconductor device is configured as a three-phase inverter and includes an LVIC (Low Voltage Integrated Circuit) 2, an HVIC (High Voltage Integrated Circuit) 3, six MOSFETs 7, six IGBTs 9, an IC frame 1, a high-side frame 4, three low-side frames 5, and three low-side terminals 6. The semiconductor device is resin-sealed to form a package, but the sealing resin is omitted in FIG. 1. Here, the HVIC 3 and the LVIC 2 correspond to control ICs. The MOSFETs 7 correspond to a first semiconductor element, and the IGBTs 9 correspond to a second semiconductor element. The number of MOSFETs 7 and IGBTs 9 is not limited to six each.

[0011] Both the HVIC 3 and the LVIC 2 are formed in a rectangular shape with long sides extending in a first direction when viewed from above, and are arranged on the IC frame 1. In Fig. 1, the HVIC 3 is arranged on the right side of the IC frame 1, and the LVIC 2 is arranged on the left side of the IC frame 1. Here, the first direction is the left-right direction in Fig. 1.

[0012] The HVIC 3 controls the driving of three MOSFETs 7 and three IGBTs 9 arranged on the high side. The LVIC 2 controls the driving of three MOSFETs 7 and three IGBTs 9 arranged on the low side. Here, "arranged on the high side" means "arranged on the high side" means "arranged on the high side frame 4," and "arranged on the low side" means "arranged on the low side frame 5."

[0013] As shown in Fig. 3, the HVIC 3 includes two sets of transmission circuits 3a and inverters 3b. The transmission circuits 3a and inverters 3b of each set are connected in series, and the output electrode of one inverter 3b is connected to a gate pad 8 of a MOSFET 7 via a gate wire 13. The output electrode of the other inverter 3b is connected to a gate pad 10 of an IGBT 9 via a gate wire 12. Although Fig. 3 shows that the HVIC 3 is connected to one MOSFET 7 and one IGBT 9, in reality, three MOSFETs are connected to each IGBT 9. Although not shown, the connection relationship between the LVIC 2 and the MOSFET 7 and IGBT 9 is the same as that of the HVIC 3, and therefore will not be described here.

[0014] The high-side frame 4 and the three low-side frames 5 are arranged along a first direction. In FIG. 1 , the high-side frame 4 is arranged on the right side, and the three low-side frames 5 are arranged on the left side. The three low-side terminals 6 are arranged on the left side of the three low-side frames 5.

[0015] As shown in FIGS. 1 and 3, each MOSFET 7 and each IGBT 9 are connected in parallel. As shown in FIGS. 1 and 2, each MOSFET 7 is formed in a rectangular shape having long sides extending in a first direction and short sides extending in a direction perpendicular to the first direction when viewed from above. Three of the six MOSFETs 7 are arranged adjacent to each other on the high-side frame 4 along the first direction. The remaining three MOSFETs 7 are arranged on three low-side frames 5, respectively. Here, the direction perpendicular to the first direction is the up-down direction in FIG. 1.

[0016] Each IGBT 9 has a side extending in a first direction in a top view. squareSpecifically, each IGBT 9 is formed in a rectangular shape having short sides extending in a first direction and long sides extending in a direction perpendicular to the first direction when viewed from above. Three of the six IGBTs 9 are arranged adjacent to each other on the high-side frame 4 along the first direction. The remaining three IGBTs 9 are arranged on three low-side frames 5, respectively.

[0017] Each MOSFET 7 and each IGBT 9 is arranged such that the long side of each MOSFET 7 faces the short side of each IGBT 9. The HVIC 3 (or LVIC 2), each MOSFET 7, and each IGBT 9 are arranged in this order in a direction perpendicular to the first direction. Specifically, the HVIC 3 (or LVIC 2), each MOSFET 7, and each IGBT 9 are arranged in this order from top to bottom in FIG. 1. As a result, on the high side, each MOSFET 7 is arranged between the HVIC 3 and each IGBT 9. On the low side, each MOSFET 7 is arranged between the LVIC 2 and each IGBT 9.

[0018] A gate pad 8 is arranged on each MOSFET 7, to which a signal for controlling the driving of the MOSFET 7 is input from the HVIC 3 (or LVIC 2). The HVIC 3 (or LVIC 2) and the gate pad 8 are connected via a gate wire 13. The angle formed by the gate wire 13 and the first direction is within a range of 80° to 100°. Here, the gate pad 8 corresponds to the first gate pad, and the gate wire 13 corresponds to the first Nowa Equivalent to "no."

[0019] On each IGBT 9, a gate pad 10 is arranged to which a signal for controlling the driving of each IGBT 9 is input from the HVIC 3 (or LVIC 2). The HVIC 3 (or LVIC 2) and the gate pad 10 are connected via a gate wire 12. The angle between the gate wire 12 and the first direction is within a range of 80° to 100°. Here, the gate pad 10 corresponds to a second gate pad, and the gate wire 12 corresponds to a second gate pad. Nowa Equivalent to "no."

[0020] The main current wire 11 electrically connects the emitter electrode on each IGBT 9 to the emitter electrode on each MOSFET 7, and is connected to the low-side terminal 6 (or low-side frame 5).

[0021] Gate pad 8 is arranged on one side of each MOSFET 7 in the first direction, and gate pad 10 is arranged on the other side of each IGBT 9 in the first direction. Specifically, in FIGS. 1 and 2, gate pad 8 is arranged at the left end of each MOSFET 7, and gate pad 10 is arranged at the right end of each IGBT 9. In addition, the output electrode of HVIC3 (or LVIC2) connected to gate pad 8 is arranged at a position facing gate pad 8, and the output electrode of HVIC3 (or LVIC2) connected to gate pad 10 is arranged at a position facing gate pad 10.

[0022] This allows the gate wires 13 and 12 to be wired without crossing each other, and also allows the gate wires 12 connecting the HVIC3 (or LVIC2) and the gate pads 10 located far from the HVIC3 (or LVIC2) to be wired over the shortest distance without having to be routed around, which makes it possible to shorten the wiring length of the gate wires 12.

[0023] If each MOSFET 7 is configured using a semiconductor substrate made of SiC, it is easier to reduce product costs by shrinking each MOSFET 7 to make it smaller. Furthermore, by forming each MOSFET 7 so that the aspect ratio of the long side to the short side of each MOSFET 7 is greater than 2:1, the wiring length of the gate wire 12 between the HVIC 3 (or LVIC 2) and the gate pad 10 can be further shortened. This makes it easier to miniaturize the semiconductor device.

[0024] <Action and effect> Next, the operation and effect of the semiconductor device according to the first embodiment will be described in detail. As shown in Figures 1 to 3, the semiconductor device according to the first embodiment includes: MOSFETs 7 and IGBTs 9 connected in parallel; a rectangular HVIC 3 and LVIC 2 having long sides extending in a first direction in a top view, which control the driving of the MOSFETs 7 and the IGBTs 9; gate pads 8 arranged on the MOSFETs 7 and receiving signals for controlling the driving of the MOSFETs 7; gate pads 10 arranged on the IGBTs 9 and receiving signals for controlling the driving of the IGBTs 9; gate wires 13 connecting the HVIC 3 (or the LVIC 2) to the gate pad 8; and gate wires 12 connecting the HVIC 3 (or the LVIC 2) to the gate pad 10. Each MOSFET 7 is formed in a rectangular shape having long sides extending in the first direction in a top view, and each IGBT 9 has a side extending in the first direction in a top view. square The HVIC 3 (or LVIC 2), the MOSFETs 7, and the IGBTs 9 are arranged in this order in a direction perpendicular to the first direction, with the gate pad 8 being located on one side of each MOSFET 7 in the first direction, and the gate pad 10 being located on the other side of each IGBT 9 in the first direction.

[0025] The angle between the gate wire 13 and the first direction and the angle between the gate wire 12 and the first direction are both within the range of 80° to 100°.

[0026] Therefore, it is possible to shorten the wiring length of the gate wires 12 connecting the HVIC 3 (or LVIC 2) and the gate pads 10 of the IGBTs 9 arranged at positions far from the HVIC 3 (or LVIC 2). This provides the following advantages.

[0027] First, the effect of suppressing overvoltage breakdown and malfunction caused by dV / dt of the MOSFET 7 will be described with reference to Fig. 4. Fig. 4 is a circuit diagram for explaining the cause of overvoltage breakdown and malfunction caused by dV / dt of the MOSFET 7.

[0028] As shown in Figure 4, assume that the high-side IGBT 9 and MOSFET 7 transition from the off state to the on state. When the high-side IGBT 9 and MOSFET 7 transition from the off state to the on state, the parasitic diode of the low-side MOSFET 7, which is the opposing arm, reverse recovers, and the collector-emitter (drain-source) potential of the low-side IGBT 9 and MOSFET 7 rises, generating dV / dt according to the switching time of the high-side IGBT 9 and MOSFET 7.

[0029] MOSFET 7 and IGBT 9 have feedback capacitance Cres, and a displacement current I=Cres×dV / dt is generated through Cres. The wiring impedance of gate wire 12 of IGBT 9 (and gate wire 13 of MOSFET 7) multiplied by the displacement current I causes a temporary rise in the gate-emitter potential of the low-side IGBT 9 and MOSFET 7, resulting in overvoltage breakdown and malfunction.

[0030] The shorter the wiring length of the gate wire 12 of the IGBT 9 (and the gate wire 13 of the MOSFET 7), the more effectively the wiring impedance is reduced, and by suppressing the voltage rise between the gate and emitter of the low-side IGBT 9 and MOSFET 7, it is possible to suppress overvoltage breakdown and malfunction.

[0031] Next, the effect of suppressing parasitic oscillation when the MOSFET 7 and the IGBT 9 are driven in parallel will be described with reference to Fig. 5. Fig. 5 is a circuit diagram for explaining parasitic oscillation when the MOSFET 7 and the IGBT 9 are driven in parallel.

[0032] As shown in FIG. 5, each parasitic inductance component in the main circuit causes oscillation during switching operation when MOSFET 7 and IGBT 9 are driven in parallel, so a design is required to reduce these parasitic inductance components as close to zero as possible.

[0033] In the first embodiment, the gate wire 12 of the IGBT 9 can be designed to be shorter than in the past, and therefore, it is possible to suppress parasitic oscillation by reducing the wiring inductance of the gate wire 12. Note that the parallel driving of the MOSFET 7 and the IGBT 9 may be replaced by the parallel driving of two MOSFETs 7 or the parallel driving of two IGBTs 9.

[0034] Next, we will explain the effect of suppressing wire sweep during the molding resin injection process. As described above, since the gate wire 12 of the IGBT 9 can be designed to be shorter than conventional ones, wire sweep during the molding resin injection process can be suppressed. This makes it possible to improve the assembly efficiency of the product.

[0035] Next, the effect of suppressing breakdown of the MOSFET 7 due to current balance control during current division will be described with reference to Figs. 6 to 8. Fig. 6 is an explanatory diagram for explaining the allowable current when the SiC-MOS and Si-IGBT are driven by a single control signal when the SiC-MOS chip size is large. Fig. 7 is an explanatory diagram for explaining the allowable current when the SiC-MOS and Si-IGBT are driven by a single control signal when the SiC-MOS chip size is small. Fig. 8 is an explanatory diagram for explaining the allowable current when the SiC-MOS and Si-IGBT are driven by individual control signals.

[0036] 6 to 8, the case where the MOSFET 7 is an SiC-MOS and the IGBT 9 is an Si-IGBT will be described.

[0037] Conventionally, two power chips are controlled by a single gate signal, making it impossible to control the current balance. As shown in Figure 6, when the SiC-MOS chip size is large, the SiC-MOS turns on and the I SiC-MOS is flowing, but I SiC-MOS However, as shown in Figure 7, when the SiC-MOS chip size is small, the SiC-MOS turns on first and I SiC-MOS flows, but the allowable current decreases and I SiC-MOS This caused a problem where the SiC-MOS was thermally destroyed when the allowable current of the SiC-MOS exceeded the allowable current.

[0038] In contrast, in the first embodiment, two power chips are driven by separate control signals. As shown in FIG. 8, the Si-IGBT is turned on first, so even if the SiC-MOS chip size is small, the I SiC-MOS is less than the allowable current of the SiC-MOS, making it possible to solve the above problem.

[0039] <Other effects> Next, effects other than those related to the shortening of the wiring length of the gate wire 12 will be described.

[0040] Since the MOSFET 7 contains SiC, it is possible to improve the electrical characteristics of the product.

[0041] Furthermore, since the chip area of ​​the MOSFET 7 is smaller than that of the IGBT 9 when viewed from above, it is possible to reduce the production cost.

[0042] Furthermore, since the aspect ratio of the long side to the short side of the MOSFET 7 is greater than 2:1, the wiring length of the gate wire 12 between the HVIC 3 (or LVIC 2) and the gate pad 10 is further shortened, making it easier to miniaturize the semiconductor device.

[0043] <Embodiment 2> Next, a semiconductor device according to a second embodiment will be described. FIG. 9 is a top view showing a part of the internal configuration of the semiconductor device according to the first embodiment. FIG. 10 is a side view showing a part of the internal configuration of the semiconductor device according to the first embodiment. FIG. 11 is a top view showing a part of the internal configuration of the semiconductor device according to the second embodiment. FIG. 12 is a side view showing a part of the internal configuration of the semiconductor device according to the second embodiment. Although only the low-side side is shown in FIGS. 9 to 12, the positional relationship of each MOSFET 7 and each IGBT 9 is the same on the high-side and low-side sides, so only the low-side side will be described here. In the second embodiment, the same components as those described in the first embodiment are designated by the same reference numerals, and description thereof will be omitted.

[0044] <Configuration of semiconductor device> As shown in FIGS. 9 and 10, in the first embodiment, each MOSFET 7 and each IGBT 9 are both arranged on the low-side frame 5.

[0045] 11 and 12, in the second embodiment, each IGBT 9 is disposed on the low-side frame 5, and each MOSFET 7 is disposed on each IGBT 9 via an insulating material 15. Furthermore, while each MOSFET 7 has a vertical structure in the first embodiment, in the second embodiment it has a horizontal structure in which the drain electrode, source electrode, and gate electrode are formed on the same plane.

[0046] Main current wires 11 electrically connect the emitter electrodes on each IGBT 9 to the emitter electrodes on each MOSFET 7, and are connected to the low-side terminal 6. Meanwhile, main current wires 14 electrically connect the collector electrodes on each MOSFET 7 to the low-side frame 5.

[0047] <Action and effect> The semiconductor device according to the second embodiment includes: MOSFETs 7 and IGBTs 9 connected in parallel; a rectangular HVIC 3 and LVIC 2 that control the driving of the MOSFETs 7 and IGBTs 9 and have long sides extending in a first direction in top view; gate pads 8 that are arranged on the MOSFETs 7 and receive signals that control the driving of the MOSFETs 7; gate pads 10 that are arranged on the IGBTs 9 and receive signals that control the driving of the IGBTs 9; gate wires 13 that connect the HVIC 3 (or the LVIC 2) to the gate pad 8; and gate wires 12 that connect the HVIC 3 (or the LVIC 2) to the gate pad 10. Each MOSFET 7 is formed in a rectangular shape with long sides extending in the first direction in top view, and each IGBT 9 has long sides extending in the first direction in top view. square Each MOSFET 7 is disposed on each IGBT 9 via an insulating material 15, with a gate pad 8 disposed on one side of each MOSFET 7 in the first direction and a gate pad 10 disposed on the other side of each IGBT 9 in the first direction.

[0048] Therefore, similarly to the first embodiment, the wiring length of the gate wires 12 connecting the HVIC 3 (or LVIC 2) and the gate pads 10 of the IGBTs 9 arranged at positions far from the HVIC 3 (or LVIC 2) can be shortened.

[0049] This has the effect of suppressing overvoltage breakdown and malfunction caused by dV / dt of the MOSFET 7, suppressing parasitic oscillation when driving MOSFETs and IGBTs in parallel, suppressing wire sweep during the molding resin injection process, and suppressing breakdown of the MOSFET 7 caused by current balance control during shunting.

[0050] 12, in the second embodiment, the die bond area of ​​the low-side frame 5 where the MOSFETs 7 and the IGBTs 9 are arranged is smaller than in the first embodiment shown in FIG. 10, so that the length B of the portion of the low-side frame 5 excluding the die bond area can be made shorter than the length A shown in FIG. 10. Although not shown, the same effect can be obtained for the high-side frame 4. This makes it possible to make the semiconductor device more compact than in the first embodiment.

[0051] <Third Embodiment> In this embodiment, the semiconductor device according to the above-described first and second embodiments is applied to a power conversion device. Although the application of the semiconductor device according to the first and second embodiments is not limited to a specific power conversion device, a case where the semiconductor device according to the first and second embodiments is applied to a three-phase inverter will be described below as a third embodiment.

[0052] FIG. 13 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to the third embodiment is applied.

[0053] The power conversion system shown in Fig. 13 is composed of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be configured from a variety of sources, such as a DC system, a solar cell, or a storage battery, or it may be configured from a rectifier circuit or an AC / DC converter connected to an AC system. The power supply 100 may also be configured from a DC / DC converter that converts DC power output from a DC system into predetermined power.

[0054] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, and converts DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. As shown in Fig. 13 , the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.

[0055] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0056] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements (not shown) and freewheeling diodes (not shown). By switching the switching elements, DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300. The main conversion circuit 201 can have a variety of specific circuit configurations. However, the main conversion circuit 201 according to this embodiment is a two-level, three-phase full-bridge circuit that can be configured with six switching elements and six freewheeling diodes connected in anti-parallel to each switching element. At least one of the switching elements and freewheeling diodes of the main conversion circuit 201 is configured with a semiconductor module 202 corresponding to either of the first or second embodiment. Two of the six switching elements are connected in series to form upper and lower arms, and each upper and lower arm forms one phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0057] The main conversion circuit 201 also includes a drive circuit (not shown) that drives each switching element, but the drive circuit may be built into the semiconductor module 202, or may be provided separately from the semiconductor module 202. The drive circuit generates drive signals that drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or greater than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or less than the threshold voltage of the switching element.

[0058] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. Then, it outputs a control command (control signal) to a drive circuit provided in the main conversion circuit 201 so that an on signal is output to a switching element that should be in the on state at each time point, and an off signal is output to a switching element that should be in the off state at each time point. In accordance with this control signal, the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0059] The heat dissipation fins 204 dissipate to the outside the heat generated by the operation of the semiconductor module 202. Specifically, joint grease is applied between the heat dissipation fins 204 and the semiconductor module 202, and the heat generated by the semiconductor module 202 is dissipated to the outside by utilizing the thermal conduction of the heat dissipation fins 204 and the joint grease. The heat dissipation fins 204 may be attached to only one side surface of the semiconductor module 202, or may be attached to both sides.

[0060] In the power conversion device according to this embodiment, the semiconductor devices according to the first and second embodiments are applied as the switching elements and free wheel diodes of the main conversion circuit 201, and therefore miniaturization can be achieved.

[0061] In the present embodiment, an example has been described in which the semiconductor device according to the first and second embodiments is applied to a two-level three-phase inverter, but the application of the semiconductor device according to the first and second embodiments is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used, and when power is supplied to a single-phase load, the semiconductor device according to the first and second embodiments may be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the semiconductor device according to the first and second embodiments can also be applied to a DC / DC converter or an AC / DC converter.

[0062] Furthermore, the power conversion device to which the semiconductor device according to the first and second embodiments is applied is not limited to the case where the load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0063] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate.

[0064] Various aspects of the present disclosure are summarized below as appendices.

[0065] (Appendix 1) a first semiconductor element and a second semiconductor element connected in parallel; a control IC that controls driving of the first semiconductor element and the second semiconductor element and has a rectangular shape with long sides extending in a first direction when viewed from above; a first gate pad disposed on the first semiconductor element, to which a signal for controlling the driving of the first semiconductor element is input; a second gate pad disposed on the second semiconductor element, to which a signal for controlling the driving of the second semiconductor element is input; a first wire connecting the control IC and the first gate pad; a second wire connecting the control IC and the second gate pad; the first semiconductor element is formed in a rectangular shape having long sides extending in the first direction in a top view, The second semiconductor element has a side extending in the first direction in a top view. square It is formed in a shape the first semiconductor element and the second semiconductor element are arranged such that the long side of the first semiconductor element faces the side of the second semiconductor element, and the control IC, the first semiconductor element, and the second semiconductor element are arranged in this order in a direction perpendicular to the first direction; the first gate pad is disposed on one side of the first semiconductor element in the first direction; The semiconductor device, wherein the second gate pad is disposed on the other side of the second semiconductor element in the first direction.

[0066] (Appendix 2) The semiconductor device described in Appendix 1, wherein the angle between the first wire and the first direction and the angle between the second wire and the first direction are both within the range of 80° or more and 100° or less.

[0067] (Appendix 3) 3. The semiconductor device according to claim 1, wherein the first semiconductor element includes SiC.

[0068] (Appendix 4) 4. The semiconductor device according to claim 1, wherein the first semiconductor element has a smaller chip area than the second semiconductor element when viewed from above.

[0069] (Appendix 5) 5. The semiconductor device according to claim 1, wherein the aspect ratio of the long side to the short side of the first semiconductor element is greater than 2:1.

[0070] (Appendix 6) a first semiconductor element and a second semiconductor element connected in parallel; a control IC that controls driving of the first semiconductor element and the second semiconductor element and has a rectangular shape with long sides extending in a first direction when viewed from above; a first gate pad disposed on the first semiconductor element, to which a signal for controlling the driving of the first semiconductor element is input; a second gate pad disposed on the second semiconductor element, to which a signal for controlling the driving of the second semiconductor element is input; a first wire connecting the control IC and the first gate pad; a second wire connecting the control IC and the second gate pad; the first semiconductor element is formed in a rectangular shape having long sides extending in the first direction in a top view, The second semiconductor element has a side extending in the first direction in a top view. square It is formed in a shape the first semiconductor element is disposed on the second semiconductor element via an insulating material; the first gate pad is disposed on one side of the first semiconductor element in the first direction; The semiconductor device, wherein the second gate pad is disposed on the other side of the second semiconductor element in the first direction.

[0071] (Appendix 7) 7. The semiconductor device according to claim 1, wherein the first semiconductor element is a MOSFET and the second semiconductor element is an IGBT.

[0072] (Appendix 8) a main conversion circuit including the semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 7, which converts input power and outputs the converted power; a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit; a heat dissipation fin for dissipating heat generated by the operation of the semiconductor device to the outside; A power conversion device comprising: [Explanation of symbols]

[0073] 2 LVIC, 3 HVIC, 7 MOSFET, 8 gate pad, 9 IGBT, 10 gate pad, 12 gate wire, 13 gate wire, 15 insulation material, 200 power converter, 201 main conversion circuit, 202 semiconductor module, 203 control circuit, 204 heat dissipation fin.

Claims

1. a first semiconductor element and a second semiconductor element connected in parallel; a control IC that controls driving of the first semiconductor element and the second semiconductor element and has a rectangular shape with long sides extending in a first direction in a top view; a first gate pad disposed on the first semiconductor element, to which a signal for controlling the driving of the first semiconductor element is input; a second gate pad disposed on the second semiconductor element, to which a signal for controlling driving of the second semiconductor element is input; a first wire connecting the control IC and the first gate pad; a second wire connecting the control IC and the second gate pad; the first semiconductor element is formed in a rectangular shape having long sides extending in the first direction in a top view, the second semiconductor element is formed in a quadrilateral shape having sides extending in the first direction in a top view, the first semiconductor element and the second semiconductor element are arranged such that the long side of the first semiconductor element faces the side of the second semiconductor element, and the control IC, the first semiconductor element, and the second semiconductor element are arranged in this order in a direction perpendicular to the first direction; the first gate pad is disposed on one side of the first semiconductor element in the first direction; The semiconductor device, wherein the second gate pad is disposed on the other side of the second semiconductor element in the first direction.

2. 2. The semiconductor device according to claim 1, wherein an angle formed between said first wire and said first direction and an angle formed between said second wire and said first direction are both within a range of 80 degrees or more and 100 degrees or less.

3. The semiconductor device according to claim 1 , wherein the first semiconductor element comprises SiC.

4. The semiconductor device according to claim 1 , wherein the first semiconductor element has a chip area smaller than that of the second semiconductor element when viewed from above.

5. The semiconductor device according to claim 1 , wherein the aspect ratio of the long side to the short side of the first semiconductor element is greater than 2:

1.

6. 6. The semiconductor device according to claim 1, wherein the first semiconductor element is a MOSFET, and the second semiconductor element is an IGBT.

7. a main conversion circuit having the semiconductor device according to claim 1, which converts input power and outputs the converted power; a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit; a heat dissipation fin for dissipating heat generated by the operation of the semiconductor device to the outside; A power conversion device comprising:

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