Package substrate and semiconductor device

Abstract

To provide a package substrate which can increase the potential difference between wires without increasing the size and increase the reliability in a multilayer substrate.SOLUTION: There is provided a package substrate 120 on which a semiconductor chip 110 in which circuit elements having different operating voltages exist in a mixed manner is mounted on a front surface side thereof, and in which electrical paths extending from the front surface side to a back surface side are formed for each of the operating voltages. A package substrate includes: a base material 121 being a flat insulator; a build-up layer 122 which is formed on at least one of the front and back surfaces thereof and in which a wiring layer 122a and an insulation layer 122b covering the same are stacked alternately; and a via 123 which is formed on the base material 121 and the insulation layer 122b and electrically connects the wiring layers 122a with each other. In the package substrate, the wiring layers 122a having the different operating voltages are arranged so as to be spaced apart by predetermined distances in accordance with the operating voltages, and the wiring layers 122a having the same operating voltage are arranged so as to overlap with each other in a plan view at least in the build-up layer 122.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a package substrate and a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor packages with various structures have been developed with the aim of miniaturizing semiconductor devices.

[0003] For example, there is a semiconductor package in which a semiconductor chip is mounted on a BGA (Ball Grid Array) substrate, which has solder balls arranged in a grid pattern on the backside. Various proposals have been made for this BGA package substrate. Specifically, in order to improve connection reliability and electrical characteristics, a structure has been proposed in which a gold plating layer is formed directly on a copper layer without interposing a nickel plating layer between the copper layer and the gold plating layer on a BGA surface that is larger in area than the semiconductor chip mounting surface (see Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-327940 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of one aspect of the present invention is to provide a package substrate in which the potential difference between wirings can be increased without increasing the size of the multilayer substrate, thereby improving reliability. [Means for solving the problem]

[0006] The package substrate in one embodiment of the present invention includes: A package substrate on which a semiconductor chip having a mixture of circuit elements with different operating voltages is mounted on a front surface side, and which forms electrical paths from the front surface side to a rear surface side for each of the operating voltages, a substrate that is a flat insulator; a build-up layer formed on at least one of the front and rear surfaces of the base material, in which wiring layers and insulating layers covering the wiring layers are alternately stacked; vias formed in the base material and the insulating layer, electrically connecting the wiring layers; and the wiring layers having different operating voltages are spaced apart at predetermined distances corresponding to the operating voltages, The wiring layers having the same operating voltage are arranged so as to overlap each other in plan view at least in the build-up layer. [Effects of the Invention]

[0007] According to one aspect of the present invention, an object is to provide a package substrate in which the potential difference between wirings can be increased without increasing the size of the multilayer substrate, thereby improving reliability. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic cross-sectional view showing a semiconductor device according to this embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view showing a package substrate in this embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view showing a package substrate in this embodiment. [Figure 4A] FIG. 4A is a schematic plan view showing a package substrate in this embodiment. [Figure 4B] FIG. 4B is a schematic plan view showing the package substrate in this embodiment. [Figure 5A] FIG. 5A is an explanatory diagram showing one state in the method for manufacturing a semiconductor device according to this embodiment. [Figure 5B]FIG. 5B is an explanatory diagram showing one state in the method for manufacturing a semiconductor device according to this embodiment. [Figure 5C] FIG. 5C is an explanatory diagram showing one state in the method for manufacturing a semiconductor device according to this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] The semiconductor device according to one embodiment of the present invention is based on the following findings.

[0010] In a BGA (Ball Grid Array) package substrate, such as that described in Patent Document 1, when circuit elements with different operating voltages are mixed, the electric field becomes stronger as the potential difference between the wiring increases, which can lead to migration and reduced reliability. To avoid such a decrease in reliability, it is necessary to determine the degree of migration caused by factors such as the temperature and humidity of the operating environment and the strength of the electric field generated between the wiring, and then separate wiring layers with different operating voltages by a predetermined distance according to the operating voltage. When the voltage difference between the wiring is large, a longer distance between the wiring layers is preferable. However, when wiring layers overlap in a multilayer board, a thicker distance between the wiring layers in the interlayer direction (thickness direction of the board), i.e., a thicker insulating layer, is preferable.

[0011] However, there is an upper limit to the thickness of the insulating layer, and depending on the magnitude of the voltage difference between the wiring, the desired distance between wiring may exceed the upper limit of the insulating layer thickness. In such cases, it becomes impossible to install wiring with different potential differences above and below the wiring, so ensuring sufficient distance between wiring in the in-plane direction would result in an expansion of the package substrate size. As a result, the wiring spacing between each wiring layer becomes wider, reducing the remaining copper ratio, making it difficult to achieve uniform in-plane distribution of wiring. Furthermore, differences in the remaining copper ratio are likely to occur, which can lead to defects such as voids and misalignment of the prepreg during the heating and pressure processing during the manufacturing process.

[0012] In this way, multilayer boards with large potential differences between wiring lines may experience reduced reliability due to migration, and expanding the size in an attempt to avoid this not only makes problems due to the remaining copper ratio more likely to occur, but also goes against the trend toward miniaturization of semiconductor devices.

[0013] Therefore, in the package substrate of one embodiment of the present invention, wiring layers having the same operating voltage are arranged so as to overlap each other when viewed in plan. As a result, the package substrate of this embodiment can increase the potential difference between the wirings without increasing the size, even if it is a multi-layer substrate, and can improve reliability.

[0014] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant explanations may be omitted. In addition, the X-axis, Y-axis, and Z-axis shown in the drawings are perpendicular to one another. The X-axis direction may be referred to as the "width direction," the Y-axis direction as the "depth direction," and the Z-axis direction as the "height direction" or "thickness direction." The surface of each film on the +Z direction side may be referred to as the "front surface" or "top surface," and the surface on the -Z direction side as the "back surface" or "bottom surface." Furthermore, the drawings are schematic, and the ratios of width, depth, and thickness are not as shown. The number, position, shape, structure, size, etc. of the multiple films or layers, or the semiconductor element obtained by structurally combining them, are not limited to the embodiments shown below, and may be any number, position, shape, structure, size, etc. that is preferable for implementing the present invention.

[0015] (Present embodiment) FIG. 1 is a schematic cross-sectional view showing a semiconductor device according to this embodiment. 1, the semiconductor device 100 is a BGA (Ball Grid Array) package. The semiconductor device 100 includes a semiconductor chip 110, a package substrate 120, a conductive adhesive 130, bonding wires 140, a sealing resin 150, and conductive bumps 160.

[0016] The semiconductor chip 110 contains a mixture of circuit elements with different operating voltages. The operating voltage of the semiconductor chip 110 is a mixture of two voltages: a low voltage of 3.3 V for operating the internal circuit of the semiconductor chip 110, and a high voltage of 100 V for operating an external device connected to the semiconductor device 100. As a result, the voltages input and output from the electrode pads provided on the surface of the semiconductor chip 110 to the package substrate 120 via the bonding wires 140 are different, and the potential difference is large.

[0017] The semiconductor chip 110 is mounted on the surface of the package substrate 120, and conductive bumps 160 are formed on electrode pads formed on the back surface. In this package substrate 120, electrical paths for each operating voltage of the semiconductor chip 110 are formed from the electrode pads on the surface to the electrode pads on the back surface on which the multiple conductive bumps 160 are formed. The package substrate 120 will be described in detail later.

[0018] The conductive adhesive 130 is an adhesive that mainly contains a thermosetting epoxy resin and silver flakes. The conductive adhesive 130 is applied to the surface of the package substrate 120, and fixes the semiconductor chip 110 to the surface of the package substrate 120. The material, composition ratio, viscosity, and application amount of the conductive adhesive 130 can be appropriately selected as needed. Furthermore, although a conductive adhesive is used in this embodiment, the present invention is not limited to this and an insulating adhesive may also be used.

[0019] The bonding wires 140 electrically connect the bonding pads provided on the upper surface of the semiconductor chip 110 to the electrode pads on the surface of the package substrate 120 . The material of the bonding wire 140 is not particularly limited and can be appropriately selected, and examples thereof include Au, Cu, Al, Ag, and alloys thereof.

[0020] The sealing resin 150 protects the semiconductor chip 110 , the package substrate 120 , the conductive adhesive 130 and the bonding wires 140 , and also forms the outer shape of the semiconductor device 100 . The sealing resin 150 can be appropriately selected without any particular limitations, and examples thereof include thermosetting epoxy resins.

[0021] The conductive bumps 160 are solder balls and are arranged on the back surface of the package substrate 120. The conductive bumps 160 are melted by the heat of reflow when the semiconductor device 100 is mounted on a mounting substrate, thereby mounting the semiconductor device 100.

[0022] Next, the package substrate 120 will be described in detail with reference to FIGS. 2, 3, 4A, and 4B.

[0023] FIG. 2 is a schematic cross-sectional view showing a package substrate in this embodiment. As shown in FIG. 2, the package substrate 120 has the semiconductor chip 110 mounted on the front surface side and the conductive bumps 160 formed on the back surface side. The package substrate 120 is a multi-layer substrate, and includes a base material 121, a build-up layer 122, a plurality of vias 123, and a resist layer .

[0024] The substrate 121 is a flat insulating plate with a thickness of approximately 100 μm. The material of the base material 121 is formed from BT (Bismaleimide-Triazine) resin. Although BT resin is used in this embodiment, polyimide, polyester, FR-4 (Flame Retardant Type 4), PTFE (polytetrafluoroethylene), CEM (Composite Epoxy Material)-1, CEM-2, CEM-3, metals such as aluminum, etc. may also be used.

[0025] The buildup layers 122 are formed on both the front and back surfaces of the base material 121, and are formed by alternately stacking wiring layers 122a and insulating layers 122b covering the wiring layers 122a. The buildup layers 122 may be formed on at least one of the front and back surfaces of the base material 121, but from the viewpoint of suppressing warpage of the package substrate 120, it is preferable that the number of layers on the front surface and the number of layers on the back surface be the same.

[0026] The wiring layer 122a is a copper foil on which a circuit pattern is formed by etching, and has a thickness of approximately 30 μm. The wiring layers 122a are electrically connected by multiple vias 123, forming a low-voltage electrical path with an operating voltage of 3.3 V and a high-voltage electrical path with an operating voltage of 100 V.

[0027] The insulating layer 122b is made of prepreg, which is a composite material made by impregnating a sheet of fiber with resin. The insulating layer 122b is formed by laminating copper foil of the wiring layer 122a and a semi-cured resin sheet prepreg on the surface of the base material 121 and then performing a heat and pressure treatment, with the cured prepreg becoming the insulating layer 122b. Therefore, the thickness of the insulating layer 122b is approximately 60 μm where the wiring layer 122a is present and approximately 90 μm where the wiring layer 122a is not present. Furthermore, if the copper foil of the wiring layer 122a has a low residual copper ratio during the heat and pressure treatment, the thickness of the insulating layer 122b may decrease. In this regard, in this embodiment, the residual copper ratio can be increased, making it difficult for the thickness of the insulating layer 122b to decrease.

[0028] A plurality of vias 123 are formed in the base material 121 and the insulating layer 122b in order to form electrical paths from the front surface side to the back surface side of the package substrate 120 for each operating voltage.

[0029] The resist layer 124 protects both sides of the package substrate 120 and is formed from solder resist ink. The resist layer 124 is formed by applying solder resist ink to the surface of the wiring layer 122a, which corresponds to the outermost layer of the build-up layer 122, semi-curing it by irradiation with light, and then finally curing it by heat treatment to form the resist layer 124. Therefore, the thickness of the resist layer 124 is about 30 μm where the wiring layer 122a exists, and about 60 μm where the wiring layer 122a does not exist.

[0030] 3 is a schematic cross-sectional view showing a package substrate according to this embodiment, in which a high-voltage region H indicates an area of ​​an electrical path to which a high operating voltage of 100 V is applied, and a low-voltage region L indicates an area of ​​an electrical path to which a low operating voltage of 3.3 V is applied.

[0031] As shown in Figure 3, in the high-voltage region H, the same high-voltage wiring to which 100V is applied is arranged so as to overlap between the outer layer of the M1 layer and the inner layer of the M2 layer. As in the M1 and M2 layers, the same high-voltage wiring to which 100V is applied is also arranged so as to overlap between the inner layer of the M3 layer and the outer layer of the M4 layer. As in the high-voltage region H, the same low-voltage wiring to which a low voltage of 3.3V is applied is also arranged so as to overlap between the outer layer and the inner layer. As described above, the package substrate 120 in this embodiment has a structure in which the outer layer and the inner layer are arranged to overlap each other.

[0032] Furthermore, a predetermined distance is ensured between the wiring layers 122a with different operating voltages on at least one of the front and back surfaces of the substrate 121. In this embodiment, the predetermined distance S1 in the inner layers (M2 and M3 layers) is 100 μm or more, and the predetermined distance S2 from the outer layers (M1 and M4 layers) is 130 μm or more. The predetermined distances S1 and S2 are different because, although the outer layers are coated with the resist layer 124, they tend to have lower surface resistance than the inner layers, and therefore the predetermined distance S2 from the outer layers needs to be wider than the predetermined distance S1 in the inner layers. This predetermined distance can be appropriately selected depending on the magnitude of the operating voltage, etc.

[0033] Therefore, the distance W1 between the inner layers sandwiching the substrate 121 is the thickness of the substrate 121 (100 μm), and therefore satisfies the following formula: S1≦W1. The distance W2 between the same inner layers is 140 μm, and therefore satisfies the following formula: S1≦W2. Furthermore, the distance W3 between the same outer layers is 140 μm, and therefore satisfies the following formula: S2≦W3. The distance W4 between the inner layer and the outer layer is 140 μm, and therefore satisfies the following formula: S2≦W4. Although the interval W4 is the interval when viewed from above in FIG. 3, it may be an interval that takes into consideration the three-dimensional structure (interval in the Z-axis direction).

[0034] In this way, in the package substrate 120 of this embodiment, the wiring layers with different operating voltages are arranged spaced apart at predetermined distances according to the respective operating voltages.

[0035] Therefore, in the package substrate 120 of this embodiment, even if high-voltage regions H and low-voltage regions L are mixed, the high-voltage regions H and low-voltage regions L are arranged at a predetermined distance apart according to the respective operating voltages. As a result, even if the package substrate 120 is a multilayer substrate, the potential difference between the wiring can be increased without expanding the size, thereby improving reliability.

[0036] Furthermore, the thickness of insulating layer 122b of buildup layer 122 on the upper surface of base material 121 is approximately 60 μm where wiring layer 122a is present. For this reason, for example, if the inner layer of wiring layer 122a is set to high-voltage region H, the predetermined distance S1 cannot be ensured, and wiring layer 122a, which will become low-voltage region L, cannot be placed on the outer layer above this high-voltage region H, resulting in a low copper remaining rate.

[0037] Therefore, in this embodiment, the wiring layer 122a that becomes the high-voltage region H is arranged on the M1 layer to increase the remaining copper ratio. Furthermore, when the M2 layer is set to the low-voltage region L, the wiring layer 122a that becomes the low-voltage region L is arranged on the M1 layer above this low-voltage region L to increase the remaining copper ratio. By performing this process not only on the buildup layer 122 on the upper surface side of the base material 121 but also on the buildup layer 122 on the lower surface side, the remaining copper ratio of each wiring layer 122a can be increased overall. This reduces variations in the thickness of the insulating layer 122b during the heat and pressure treatment during manufacturing of the package substrate 120 and also reduces defects such as voids and misalignment of the prepreg. Furthermore, since the difference in the remaining copper ratio of each wiring layer 122a can be reduced, warping of the package substrate 120 can be suppressed.

[0038] In the high-voltage region H, two wiring layers 122a formed on different layers are electrically connected by two or more vias 123. This allows the wiring layer 122a in the high-voltage region H to have a uniform in-plane potential distribution and form a current path that can pass a large current.

[0039] 4A and 4B are schematic plan views showing a package substrate in this embodiment. Fig. 4A is a schematic plan view of the M1 layer, which is an outer layer of the wiring layer 122a shown in Fig. 3. Fig. 4B is a schematic plan view of the M2 layer, which is an inner layer of the wiring layer 122a shown in Fig. 3. As shown in FIGS. 4A and 4B, when comparing the M1 layer and the M2 layer of the wiring layer 122a, the high voltage region H and the low voltage region L are arranged so as to overlap each other.

[0040] In addition, in the overlapping portions of the same regions, the wiring width on the M1 layer is preferably narrower than the wiring width on the M2 layer, from the viewpoint of making the spacing between the wirings on the M1 layer wider than the spacing between the wirings on the M2 layer. In addition, in order to increase the copper remaining ratio, so-called "solid patterns" are provided in the areas other than the high voltage area H and the low voltage area L. The gap between this solid pattern and the area is preferably a gap according to the voltages handled in the high voltage area H and the low voltage area L.

[0041] Next, a method for manufacturing the semiconductor device according to this embodiment will be described with reference to FIGS. 5A to 5C.

[0042] 5A, conductive adhesive 130 is applied to the surface of package substrate 120, and semiconductor chip 110 is mounted and fixed thereon. Electrode pads formed on the surface of semiconductor chip 110 and electrode pads formed on the surface of package substrate 120 are electrically connected by bonding wires 140. Next, as shown in FIG. 5B, the package substrate 120 is sandwiched between two molds, and sealing resin 150 is injected into the molds and solidified to seal them. Then, as shown in FIG. 5C, conductive bumps 160 are formed on the back surface of package substrate 120, and this is separated into individual pieces, thereby manufacturing semiconductor device 100 as shown in FIG. 5C.

[0043] As described above, a package substrate according to one embodiment of the present invention has a semiconductor chip mounted on its front surface, the semiconductor chip including circuit elements with different operating voltages, and electrical paths formed from the front surface to the back surface for each operating voltage. This package substrate includes a base material that is a flat insulator, build-up layers formed on at least one of the front and back surfaces of the base material and in which wiring layers and insulating layers are alternately stacked, and vias formed in the base material and the insulating layer for electrically connecting the wiring layers. The wiring layers with different operating voltages are spaced apart by a predetermined distance corresponding to the respective operating voltages, and the wiring layers with the same operating voltage are arranged so as to overlap at least in the build-up layer when viewed in a plan view. This allows the package substrate to increase the potential difference between the wiring lines in a multi-layer substrate without increasing the size, thereby improving reliability.

[0044] In this embodiment, the two operating voltages are 100V and 3.3V, but they are not limited to this and can be selected appropriately depending on the purpose. [Explanation of symbols]

[0045] 100 Semiconductor device 110 Semiconductor Chips 120 package substrate 121 Base material 122 Build-up layer 122a wiring layer 122b Insulating layer 123 Beer 124 resist layer 130 Conductive adhesive 140 Bonding Wire 150 Sealing resin 160 Conductive Bump H High voltage area L Low voltage area M1, M4 outer layer M2, M3 inner layer

Claims

1. A package substrate on which a semiconductor chip having a mixture of circuit elements with different operating voltages is mounted on a front surface side, and which forms electrical paths from the front surface side to a rear surface side for each of the operating voltages, a substrate that is a flat insulator; a build-up layer formed on at least one of the front and rear surfaces of the base material, in which wiring layers and insulating layers covering the wiring layers are alternately stacked; vias formed in the base material and the insulating layer, electrically connecting the wiring layers; and the wiring layers having different operating voltages are spaced apart at predetermined distances corresponding to the operating voltages, In the build-up layer, in a region where a predetermined wiring pattern is arranged on either the inner layer on the substrate side or the outer layer on the opposite side to the substrate, of two of the wiring layers adjacent to each other in the stacking direction, a wiring pattern to which the same operating voltage as that of the predetermined wiring pattern is applied is arranged on the other layer so as to overlap with the predetermined wiring pattern in a plan view; The predetermined wiring pattern arranged on the inner layer and the wiring pattern arranged on the outer layer are electrically connected by the vias.

2. 2. The package substrate according to claim 1, wherein two or more vias are formed between the wiring layers having the higher operating voltage.

3. the build-up layer is formed on both the front and back surfaces of the base material, The package substrate according to claim 2 , wherein the number of the wiring layers and the insulating layers on the front surface of the base material is the same as the number of the wiring layers and the insulating layers on the back surface of the base material.

4. 4. The package substrate according to claim 3, wherein in a region of the build-up layer where the wiring layers having the same operating voltage are arranged to overlap each other, the wiring width of the outer layer is narrower than the wiring width of the inner layer.

5. A package substrate according to any one of claims 1 to 4; a semiconductor chip mounted on the front surface side of the package substrate; a sealing resin for sealing the semiconductor chip; A semiconductor device having:

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